tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sim/fsl_sim_features.h

   1 /*
   2 ** ###################################################################
   3 **     Version:             rev. 1.0, 2014-05-14
   4 **     Build:               b140515
   5 **
   6 **     Abstract:
   7 **         Chip specific module features.
   8 **
   9 **     Copyright: 2014 Freescale Semiconductor, Inc.
  10 **     All rights reserved.
  11 **
  12 **     Redistribution and use in source and binary forms, with or without modification,
  13 **     are permitted provided that the following conditions are met:
  14 **
  15 **     o Redistributions of source code must retain the above copyright notice, this list
  16 **       of conditions and the following disclaimer.
  17 **
  18 **     o Redistributions in binary form must reproduce the above copyright notice, this
  19 **       list of conditions and the following disclaimer in the documentation and/or
  20 **       other materials provided with the distribution.
  21 **
  22 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  23 **       contributors may be used to endorse or promote products derived from this
  24 **       software without specific prior written permission.
  25 **
  26 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  27 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  28 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  29 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  30 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  31 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  32 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  33 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  35 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36 **
  37 **     http:                 www.freescale.com
  38 **     mail:                 support@freescale.com
  39 **
  40 **     Revisions:
  41 **     - rev. 1.0 (2014-05-14)
  42 **         Customer release.
  43 **
  44 ** ###################################################################
  45 */
  46
  47 #if !defined(__FSL_SIM_FEATURES_H__)
  48 #define __FSL_SIM_FEATURES_H__
  49
  50 #if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \
  51     defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10)
  52     /* @brief Has USB FS divider. */
  53     #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
  54     /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
  55     #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
  56     /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
  57     #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1)
  58     /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
  59     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1)
  60     /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
  61     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
  62     /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
  63     #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
  64     /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
  65     #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0)
  66     /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
  67     #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0)
  68     /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
  69     #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
  70     /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
  71     #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
  72     /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
  73     #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
  74     /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
  75     #define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
  76     /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
  77     #define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
  78     /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
  79     #define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
  80     /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
  81     #define FSL_FEATURE_SIM_OPT_UART_COUNT (2)
  82     /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
  83     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
  84     /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
  85     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
  86     /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
  87     #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
  88     /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
  89     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
  90     /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
  91     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
  92     /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
  93     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
  94     /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
  95     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
  96     /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
  97     #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
  98     /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
  99     #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2)
 100     /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
 101     #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
 102     /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
 103     #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2)
 104     /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
 105     #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
 106     /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
 107     #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
 108     /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
 109     #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2)
 110     /* @brief Has FTM module(s) configuration. */
 111     #define FSL_FEATURE_SIM_OPT_HAS_FTM (1)
 112     /* @brief Number of FTM modules. */
 113     #define FSL_FEATURE_SIM_OPT_FTM_COUNT (3)
 114     /* @brief Number of FTM triggers with selectable source. */
 115     #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2)
 116     /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
 117     #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1)
 118     /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
 119     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0)
 120     /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
 121     #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1)
 122     /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
 123     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1)
 124     /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
 125     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
 126     /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
 127     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1)
 128     /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
 129     #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2)
 130     /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
 131     #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1)
 132     /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
 133     #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1)
 134     /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
 135     #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0)
 136     /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
 137     #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1)
 138     /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
 139     #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1)
 140     /* @brief Has TPM module(s) configuration. */
 141     #define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
 142     /* @brief The highest TPM module index. */
 143     #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
 144     /* @brief Has TPM module with index 0. */
 145     #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
 146     /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
 147     #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
 148     /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
 149     #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
 150     /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
 151     #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
 152     /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
 153     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
 154     /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
 155     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
 156     /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
 157     #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
 158     /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
 159     #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
 160     /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
 161     #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
 162     /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
 163     #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
 164     /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
 165     #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
 166     /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
 167     #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
 168     /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
 169     #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
 170     /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
 171     #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
 172     /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
 173     #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0)
 174     /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
 175     #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
 176     /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
 177     #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
 178     /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
 179     #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
 180     /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
 181     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
 182     /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
 183     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
 184     /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
 185     #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
 186     /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
 187     #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
 188     /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
 189     #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
 190     /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
 191     #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1)
 192     /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
 193     #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1)
 194     /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
 195     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1)
 196     /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
 197     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
 198     /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
 199     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
 200     /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
 201     #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4)
 202     /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
 203     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0)
 204     /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
 205     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
 206     /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
 207     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
 208     /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
 209     #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
 210     /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
 211     #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
 212     /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
 213     #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
 214     /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
 215     #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
 216     /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
 217     #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1)
 218     /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
 219     #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
 220     /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
 221     #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
 222     /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
 223     #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
 224     /* @brief Has device die ID (register bit field SDID[DIEID]). */
 225     #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
 226     /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
 227     #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
 228     /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
 229     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
 230     /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
 231     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
 232     /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
 233     #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
 234     /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
 235     #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
 236     /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
 237     #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
 238     /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
 239     #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
 240     /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
 241     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
 242     /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
 243     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0)
 244     /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
 245     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
 246     /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
 247     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
 248     /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
 249     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
 250     /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
 251     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
 252     /* @brief Has miscellanious control register (register MCR). */
 253     #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
 254     /* @brief Has COP watchdog (registers COPC and SRVCOP). */
 255     #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
 256     /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
 257     #define FSL_FEATURE_SIM_HAS_COP_STOP (0)
 258 #elif defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10)
 259     /* @brief Has USB FS divider. */
 260     #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
 261     /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
 262     #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
 263     /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
 264     #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1)
 265     /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
 266     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1)
 267     /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
 268     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
 269     /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
 270     #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
 271     /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
 272     #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
 273     /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
 274     #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0)
 275     /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
 276     #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
 277     /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
 278     #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
 279     /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
 280     #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
 281     /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
 282     #define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
 283     /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
 284     #define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
 285     /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
 286     #define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
 287     /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
 288     #define FSL_FEATURE_SIM_OPT_UART_COUNT (3)
 289     /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
 290     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
 291     /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
 292     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
 293     /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
 294     #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
 295     /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
 296     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
 297     /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
 298     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1)
 299     /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
 300     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
 301     /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
 302     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
 303     /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
 304     #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
 305     /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
 306     #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2)
 307     /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
 308     #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
 309     /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
 310     #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2)
 311     /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
 312     #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
 313     /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
 314     #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
 315     /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
 316     #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2)
 317     /* @brief Has FTM module(s) configuration. */
 318     #define FSL_FEATURE_SIM_OPT_HAS_FTM (1)
 319     /* @brief Number of FTM modules. */
 320     #define FSL_FEATURE_SIM_OPT_FTM_COUNT (3)
 321     /* @brief Number of FTM triggers with selectable source. */
 322     #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2)
 323     /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
 324     #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1)
 325     /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
 326     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0)
 327     /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
 328     #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1)
 329     /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
 330     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1)
 331     /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
 332     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
 333     /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
 334     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1)
 335     /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
 336     #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2)
 337     /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
 338     #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1)
 339     /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
 340     #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1)
 341     /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
 342     #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0)
 343     /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
 344     #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1)
 345     /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
 346     #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1)
 347     /* @brief Has TPM module(s) configuration. */
 348     #define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
 349     /* @brief The highest TPM module index. */
 350     #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
 351     /* @brief Has TPM module with index 0. */
 352     #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
 353     /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
 354     #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
 355     /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
 356     #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
 357     /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
 358     #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
 359     /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
 360     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
 361     /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
 362     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
 363     /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
 364     #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
 365     /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
 366     #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
 367     /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
 368     #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
 369     /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
 370     #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
 371     /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
 372     #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
 373     /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
 374     #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
 375     /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
 376     #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
 377     /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
 378     #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
 379     /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
 380     #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1)
 381     /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
 382     #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
 383     /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
 384     #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
 385     /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
 386     #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1)
 387     /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
 388     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
 389     /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
 390     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
 391     /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
 392     #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
 393     /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
 394     #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
 395     /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
 396     #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
 397     /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
 398     #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1)
 399     /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
 400     #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2)
 401     /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
 402     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1)
 403     /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
 404     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
 405     /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
 406     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
 407     /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
 408     #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4)
 409     /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
 410     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1)
 411     /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
 412     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
 413     /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
 414     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
 415     /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
 416     #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
 417     /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
 418     #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
 419     /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
 420     #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
 421     /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
 422     #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
 423     /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
 424     #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1)
 425     /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
 426     #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
 427     /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
 428     #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
 429     /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
 430     #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
 431     /* @brief Has device die ID (register bit field SDID[DIEID]). */
 432     #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
 433     /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
 434     #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
 435     /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
 436     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
 437     /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
 438     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
 439     /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
 440     #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
 441     /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
 442     #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
 443     /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
 444     #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
 445     /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
 446     #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
 447     /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
 448     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
 449     /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
 450     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
 451     /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
 452     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
 453     /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
 454     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
 455     /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
 456     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
 457     /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
 458     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
 459     /* @brief Has miscellanious control register (register MCR). */
 460     #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
 461     /* @brief Has COP watchdog (registers COPC and SRVCOP). */
 462     #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
 463     /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
 464     #define FSL_FEATURE_SIM_HAS_COP_STOP (0)
 465 #elif defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12)
 466     /* @brief Has USB FS divider. */
 467     #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
 468     /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
 469     #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
 470     /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
 471     #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1)
 472     /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
 473     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1)
 474     /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
 475     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
 476     /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
 477     #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
 478     /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
 479     #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
 480     /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
 481     #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1)
 482     /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
 483     #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
 484     /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
 485     #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
 486     /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
 487     #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
 488     /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
 489     #define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
 490     /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
 491     #define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
 492     /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
 493     #define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
 494     /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
 495     #define FSL_FEATURE_SIM_OPT_UART_COUNT (3)
 496     /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
 497     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
 498     /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
 499     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
 500     /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
 501     #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
 502     /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
 503     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
 504     /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
 505     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1)
 506     /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
 507     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
 508     /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
 509     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
 510     /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
 511     #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
 512     /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
 513     #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2)
 514     /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
 515     #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
 516     /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
 517     #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2)
 518     /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
 519     #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
 520     /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
 521     #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
 522     /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
 523     #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2)
 524     /* @brief Has FTM module(s) configuration. */
 525     #define FSL_FEATURE_SIM_OPT_HAS_FTM (1)
 526     /* @brief Number of FTM modules. */
 527     #define FSL_FEATURE_SIM_OPT_FTM_COUNT (3)
 528     /* @brief Number of FTM triggers with selectable source. */
 529     #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2)
 530     /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
 531     #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1)
 532     /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
 533     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0)
 534     /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
 535     #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1)
 536     /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
 537     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1)
 538     /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
 539     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
 540     /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
 541     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1)
 542     /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
 543     #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2)
 544     /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
 545     #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1)
 546     /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
 547     #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1)
 548     /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
 549     #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0)
 550     /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
 551     #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1)
 552     /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
 553     #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1)
 554     /* @brief Has TPM module(s) configuration. */
 555     #define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
 556     /* @brief The highest TPM module index. */
 557     #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
 558     /* @brief Has TPM module with index 0. */
 559     #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
 560     /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
 561     #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
 562     /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
 563     #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
 564     /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
 565     #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
 566     /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
 567     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
 568     /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
 569     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
 570     /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
 571     #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
 572     /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
 573     #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
 574     /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
 575     #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
 576     /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
 577     #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
 578     /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
 579     #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
 580     /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
 581     #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
 582     /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
 583     #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
 584     /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
 585     #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
 586     /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
 587     #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1)
 588     /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
 589     #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
 590     /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
 591     #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
 592     /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
 593     #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1)
 594     /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
 595     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
 596     /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
 597     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
 598     /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
 599     #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
 600     /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
 601     #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
 602     /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
 603     #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
 604     /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
 605     #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1)
 606     /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
 607     #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2)
 608     /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
 609     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1)
 610     /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
 611     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
 612     /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
 613     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
 614     /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
 615     #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4)
 616     /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
 617     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1)
 618     /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
 619     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
 620     /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
 621     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
 622     /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
 623     #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
 624     /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
 625     #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
 626     /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
 627     #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
 628     /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
 629     #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
 630     /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
 631     #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1)
 632     /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
 633     #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
 634     /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
 635     #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
 636     /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
 637     #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
 638     /* @brief Has device die ID (register bit field SDID[DIEID]). */
 639     #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
 640     /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
 641     #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
 642     /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
 643     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
 644     /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
 645     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
 646     /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
 647     #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
 648     /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
 649     #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
 650     /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
 651     #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
 652     /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
 653     #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
 654     /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
 655     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
 656     /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
 657     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
 658     /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
 659     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
 660     /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
 661     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
 662     /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
 663     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
 664     /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
 665     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
 666     /* @brief Has miscellanious control register (register MCR). */
 667     #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
 668     /* @brief Has COP watchdog (registers COPC and SRVCOP). */
 669     #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
 670     /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
 671     #define FSL_FEATURE_SIM_HAS_COP_STOP (0)
 672 #elif defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12)
 673     /* @brief Has USB FS divider. */
 674     #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
 675     /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
 676     #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
 677     /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
 678     #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1)
 679     /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
 680     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1)
 681     /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
 682     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
 683     /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
 684     #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
 685     /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
 686     #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
 687     /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
 688     #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1)
 689     /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
 690     #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
 691     /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
 692     #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
 693     /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
 694     #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1)
 695     /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
 696     #define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
 697     /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
 698     #define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
 699     /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
 700     #define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
 701     /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
 702     #define FSL_FEATURE_SIM_OPT_UART_COUNT (3)
 703     /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
 704     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
 705     /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
 706     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
 707     /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
 708     #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
 709     /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
 710     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
 711     /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
 712     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1)
 713     /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
 714     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
 715     /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
 716     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
 717     /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
 718     #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
 719     /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
 720     #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2)
 721     /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
 722     #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
 723     /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
 724     #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2)
 725     /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
 726     #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
 727     /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
 728     #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
 729     /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
 730     #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2)
 731     /* @brief Has FTM module(s) configuration. */
 732     #define FSL_FEATURE_SIM_OPT_HAS_FTM (1)
 733     /* @brief Number of FTM modules. */
 734     #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4)
 735     /* @brief Number of FTM triggers with selectable source. */
 736     #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2)
 737     /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
 738     #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1)
 739     /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
 740     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1)
 741     /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
 742     #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1)
 743     /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
 744     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1)
 745     /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
 746     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
 747     /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
 748     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1)
 749     /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
 750     #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2)
 751     /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
 752     #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1)
 753     /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
 754     #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1)
 755     /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
 756     #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1)
 757     /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
 758     #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1)
 759     /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
 760     #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1)
 761     /* @brief Has TPM module(s) configuration. */
 762     #define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
 763     /* @brief The highest TPM module index. */
 764     #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
 765     /* @brief Has TPM module with index 0. */
 766     #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
 767     /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
 768     #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
 769     /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
 770     #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
 771     /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
 772     #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
 773     /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
 774     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
 775     /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
 776     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
 777     /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
 778     #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
 779     /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
 780     #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
 781     /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
 782     #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
 783     /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
 784     #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
 785     /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
 786     #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
 787     /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
 788     #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
 789     /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
 790     #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
 791     /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
 792     #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
 793     /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
 794     #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1)
 795     /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
 796     #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
 797     /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
 798     #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
 799     /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
 800     #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1)
 801     /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
 802     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
 803     /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
 804     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
 805     /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
 806     #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
 807     /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
 808     #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
 809     /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
 810     #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
 811     /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
 812     #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1)
 813     /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
 814     #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2)
 815     /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
 816     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1)
 817     /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
 818     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1)
 819     /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
 820     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
 821     /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
 822     #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4)
 823     /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
 824     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1)
 825     /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
 826     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
 827     /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
 828     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
 829     /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
 830     #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
 831     /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
 832     #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
 833     /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
 834     #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
 835     /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
 836     #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
 837     /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
 838     #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1)
 839     /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
 840     #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
 841     /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
 842     #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
 843     /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
 844     #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
 845     /* @brief Has device die ID (register bit field SDID[DIEID]). */
 846     #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
 847     /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
 848     #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
 849     /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
 850     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
 851     /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
 852     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
 853     /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
 854     #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
 855     /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
 856     #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
 857     /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
 858     #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
 859     /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
 860     #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
 861     /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
 862     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
 863     /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
 864     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
 865     /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
 866     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
 867     /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
 868     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
 869     /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
 870     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
 871     /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
 872     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
 873     /* @brief Has miscellanious control register (register MCR). */
 874     #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
 875     /* @brief Has COP watchdog (registers COPC and SRVCOP). */
 876     #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
 877     /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
 878     #define FSL_FEATURE_SIM_HAS_COP_STOP (0)
 879 #elif defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12)
 880     /* @brief Has USB FS divider. */
 881     #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
 882     /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
 883     #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
 884     /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
 885     #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1)
 886     /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
 887     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
 888     /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
 889     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
 890     /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
 891     #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
 892     /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
 893     #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
 894     /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
 895     #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1)
 896     /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
 897     #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
 898     /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
 899     #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (1)
 900     /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
 901     #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1)
 902     /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
 903     #define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
 904     /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
 905     #define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
 906     /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
 907     #define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
 908     /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
 909     #define FSL_FEATURE_SIM_OPT_UART_COUNT (4)
 910     /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
 911     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
 912     /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
 913     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
 914     /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
 915     #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
 916     /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
 917     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
 918     /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
 919     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
 920     /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
 921     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
 922     /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
 923     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
 924     /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
 925     #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
 926     /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
 927     #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2)
 928     /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
 929     #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
 930     /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
 931     #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2)
 932     /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
 933     #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
 934     /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
 935     #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
 936     /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
 937     #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2)
 938     /* @brief Has FTM module(s) configuration. */
 939     #define FSL_FEATURE_SIM_OPT_HAS_FTM (1)
 940     /* @brief Number of FTM modules. */
 941     #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4)
 942     /* @brief Number of FTM triggers with selectable source. */
 943     #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2)
 944     /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
 945     #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1)
 946     /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
 947     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1)
 948     /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
 949     #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1)
 950     /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
 951     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1)
 952     /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
 953     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
 954     /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
 955     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
 956     /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
 957     #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (3)
 958     /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
 959     #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1)
 960     /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
 961     #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1)
 962     /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
 963     #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1)
 964     /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
 965     #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
 966     /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
 967     #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
 968     /* @brief Has TPM module(s) configuration. */
 969     #define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
 970     /* @brief The highest TPM module index. */
 971     #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
 972     /* @brief Has TPM module with index 0. */
 973     #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
 974     /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
 975     #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
 976     /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
 977     #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
 978     /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
 979     #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
 980     /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
 981     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
 982     /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
 983     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
 984     /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
 985     #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
 986     /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
 987     #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
 988     /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
 989     #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
 990     /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
 991     #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
 992     /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
 993     #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1)
 994     /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
 995     #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
 996     /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
 997     #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
 998     /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
 999     #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
1000     /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
1001     #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1)
1002     /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
1003     #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
1004     /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
1005     #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
1006     /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
1007     #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
1008     /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
1009     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
1010     /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
1011     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
1012     /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
1013     #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
1014     /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
1015     #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
1016     /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
1017     #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
1018     /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
1019     #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1)
1020     /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
1021     #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2)
1022     /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
1023     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1)
1024     /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
1025     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1)
1026     /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
1027     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
1028     /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
1029     #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4)
1030     /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
1031     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1)
1032     /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
1033     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
1034     /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
1035     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
1036     /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
1037     #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
1038     /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
1039     #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
1040     /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
1041     #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
1042     /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
1043     #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
1044     /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
1045     #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1)
1046     /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
1047     #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
1048     /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
1049     #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
1050     /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
1051     #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
1052     /* @brief Has device die ID (register bit field SDID[DIEID]). */
1053     #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
1054     /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
1055     #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
1056     /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
1057     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
1058     /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
1059     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
1060     /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
1061     #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
1062     /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
1063     #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1)
1064     /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
1065     #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1)
1066     /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
1067     #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1)
1068     /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
1069     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
1070     /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
1071     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
1072     /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
1073     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
1074     /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
1075     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
1076     /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
1077     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1)
1078     /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
1079     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
1080     /* @brief Has miscellanious control register (register MCR). */
1081     #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
1082     /* @brief Has COP watchdog (registers COPC and SRVCOP). */
1083     #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
1084     /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
1085     #define FSL_FEATURE_SIM_HAS_COP_STOP (0)
1086 #elif defined(CPU_MK24FN256VDC12)
1087     /* @brief Has USB FS divider. */
1088     #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
1089     /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
1090     #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
1091     /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
1092     #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1)
1093     /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
1094     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
1095     /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
1096     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
1097     /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
1098     #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
1099     /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
1100     #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
1101     /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
1102     #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1)
1103     /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
1104     #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
1105     /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
1106     #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
1107     /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
1108     #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
1109     /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
1110     #define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
1111     /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
1112     #define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
1113     /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
1114     #define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
1115     /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
1116     #define FSL_FEATURE_SIM_OPT_UART_COUNT (4)
1117     /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
1118     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
1119     /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
1120     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
1121     /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
1122     #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
1123     /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
1124     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
1125     /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
1126     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
1127     /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
1128     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
1129     /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
1130     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
1131     /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
1132     #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
1133     /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
1134     #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2)
1135     /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
1136     #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
1137     /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
1138     #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2)
1139     /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
1140     #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
1141     /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
1142     #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
1143     /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
1144     #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2)
1145     /* @brief Has FTM module(s) configuration. */
1146     #define FSL_FEATURE_SIM_OPT_HAS_FTM (1)
1147     /* @brief Number of FTM modules. */
1148     #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4)
1149     /* @brief Number of FTM triggers with selectable source. */
1150     #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2)
1151     /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
1152     #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1)
1153     /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
1154     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1)
1155     /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
1156     #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1)
1157     /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
1158     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1)
1159     /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
1160     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
1161     /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
1162     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
1163     /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
1164     #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2)
1165     /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
1166     #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1)
1167     /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
1168     #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1)
1169     /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
1170     #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1)
1171     /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
1172     #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
1173     /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
1174     #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
1175     /* @brief Has TPM module(s) configuration. */
1176     #define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
1177     /* @brief The highest TPM module index. */
1178     #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
1179     /* @brief Has TPM module with index 0. */
1180     #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
1181     /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
1182     #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
1183     /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1184     #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
1185     /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1186     #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
1187     /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
1188     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
1189     /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
1190     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
1191     /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
1192     #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
1193     /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
1194     #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
1195     /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
1196     #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
1197     /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
1198     #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
1199     /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
1200     #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
1201     /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
1202     #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
1203     /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
1204     #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
1205     /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
1206     #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
1207     /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
1208     #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1)
1209     /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
1210     #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
1211     /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
1212     #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
1213     /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
1214     #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
1215     /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
1216     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
1217     /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
1218     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
1219     /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
1220     #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
1221     /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
1222     #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
1223     /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
1224     #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
1225     /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
1226     #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1)
1227     /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
1228     #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2)
1229     /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
1230     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1)
1231     /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
1232     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
1233     /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
1234     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
1235     /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
1236     #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4)
1237     /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
1238     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1)
1239     /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
1240     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
1241     /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
1242     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
1243     /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
1244     #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
1245     /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
1246     #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
1247     /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
1248     #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
1249     /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
1250     #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
1251     /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
1252     #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1)
1253     /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
1254     #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
1255     /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
1256     #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
1257     /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
1258     #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
1259     /* @brief Has device die ID (register bit field SDID[DIEID]). */
1260     #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
1261     /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
1262     #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
1263     /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
1264     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
1265     /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
1266     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
1267     /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
1268     #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
1269     /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
1270     #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
1271     /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
1272     #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
1273     /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
1274     #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
1275     /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
1276     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
1277     /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
1278     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
1279     /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
1280     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
1281     /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
1282     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
1283     /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
1284     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
1285     /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
1286     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
1287     /* @brief Has miscellanious control register (register MCR). */
1288     #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
1289     /* @brief Has COP watchdog (registers COPC and SRVCOP). */
1290     #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
1291     /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
1292     #define FSL_FEATURE_SIM_HAS_COP_STOP (0)
1293 #elif defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || \
1294     defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \
1295     defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12)
1296     /* @brief Has USB FS divider. */
1297     #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
1298     /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
1299     #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
1300     /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
1301     #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1)
1302     /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
1303     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
1304     /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
1305     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
1306     /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
1307     #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
1308     /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
1309     #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
1310     /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
1311     #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1)
1312     /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
1313     #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
1314     /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
1315     #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (1)
1316     /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
1317     #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1)
1318     /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
1319     #define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
1320     /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
1321     #define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
1322     /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
1323     #define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
1324     /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
1325     #define FSL_FEATURE_SIM_OPT_UART_COUNT (4)
1326     /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
1327     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
1328     /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
1329     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
1330     /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
1331     #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
1332     /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
1333     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
1334     /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
1335     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
1336     /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
1337     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
1338     /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
1339     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
1340     /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
1341     #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
1342     /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
1343     #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2)
1344     /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
1345     #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
1346     /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
1347     #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2)
1348     /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
1349     #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
1350     /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
1351     #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
1352     /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
1353     #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2)
1354     /* @brief Has FTM module(s) configuration. */
1355     #define FSL_FEATURE_SIM_OPT_HAS_FTM (1)
1356     /* @brief Number of FTM modules. */
1357     #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4)
1358     /* @brief Number of FTM triggers with selectable source. */
1359     #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2)
1360     /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
1361     #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1)
1362     /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
1363     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1)
1364     /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
1365     #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1)
1366     /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
1367     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1)
1368     /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
1369     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
1370     /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
1371     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
1372     /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
1373     #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (3)
1374     /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
1375     #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1)
1376     /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
1377     #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1)
1378     /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
1379     #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1)
1380     /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
1381     #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
1382     /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
1383     #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
1384     /* @brief Has TPM module(s) configuration. */
1385     #define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
1386     /* @brief The highest TPM module index. */
1387     #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
1388     /* @brief Has TPM module with index 0. */
1389     #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
1390     /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
1391     #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
1392     /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1393     #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
1394     /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1395     #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
1396     /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
1397     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
1398     /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
1399     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
1400     /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
1401     #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
1402     /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
1403     #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
1404     /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
1405     #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
1406     /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
1407     #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
1408     /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
1409     #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1)
1410     /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
1411     #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
1412     /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
1413     #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (1)
1414     /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
1415     #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (1)
1416     /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
1417     #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1)
1418     /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
1419     #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
1420     /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
1421     #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
1422     /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
1423     #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
1424     /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
1425     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
1426     /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
1427     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
1428     /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
1429     #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
1430     /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
1431     #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
1432     /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
1433     #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
1434     /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
1435     #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1)
1436     /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
1437     #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2)
1438     /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
1439     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1)
1440     /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
1441     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1)
1442     /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
1443     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
1444     /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
1445     #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4)
1446     /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
1447     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1)
1448     /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
1449     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
1450     /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
1451     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
1452     /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
1453     #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
1454     /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
1455     #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
1456     /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
1457     #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
1458     /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
1459     #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
1460     /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
1461     #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1)
1462     /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
1463     #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
1464     /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
1465     #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
1466     /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
1467     #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
1468     /* @brief Has device die ID (register bit field SDID[DIEID]). */
1469     #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
1470     /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
1471     #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
1472     /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
1473     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
1474     /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
1475     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
1476     /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
1477     #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
1478     /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
1479     #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1)
1480     /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
1481     #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1)
1482     /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
1483     #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1)
1484     /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
1485     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
1486     /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
1487     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
1488     /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
1489     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
1490     /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
1491     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
1492     /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
1493     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1)
1494     /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
1495     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
1496     /* @brief Has miscellanious control register (register MCR). */
1497     #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
1498     /* @brief Has COP watchdog (registers COPC and SRVCOP). */
1499     #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
1500     /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
1501     #define FSL_FEATURE_SIM_HAS_COP_STOP (0)
1502 #elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \
1503     defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18)
1504     /* @brief Has USB FS divider. */
1505     #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
1506     /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
1507     #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
1508     /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
1509     #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1)
1510     /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
1511     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
1512     /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
1513     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
1514     /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
1515     #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
1516     /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
1517     #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
1518     /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
1519     #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1)
1520     /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
1521     #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (1)
1522     /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
1523     #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
1524     /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
1525     #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1)
1526     /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
1527     #define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
1528     /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
1529     #define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
1530     /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
1531     #define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
1532     /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
1533     #define FSL_FEATURE_SIM_OPT_UART_COUNT (4)
1534     /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
1535     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
1536     /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
1537     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
1538     /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
1539     #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
1540     /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
1541     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1)
1542     /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
1543     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1)
1544     /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
1545     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
1546     /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
1547     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
1548     /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
1549     #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
1550     /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
1551     #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2)
1552     /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
1553     #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
1554     /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
1555     #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2)
1556     /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
1557     #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
1558     /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
1559     #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
1560     /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
1561     #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2)
1562     /* @brief Has FTM module(s) configuration. */
1563     #define FSL_FEATURE_SIM_OPT_HAS_FTM (1)
1564     /* @brief Number of FTM modules. */
1565     #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4)
1566     /* @brief Number of FTM triggers with selectable source. */
1567     #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2)
1568     /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
1569     #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1)
1570     /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
1571     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1)
1572     /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
1573     #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1)
1574     /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
1575     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1)
1576     /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
1577     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
1578     /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
1579     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1)
1580     /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
1581     #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (4)
1582     /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
1583     #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1)
1584     /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
1585     #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1)
1586     /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
1587     #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1)
1588     /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
1589     #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1)
1590     /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
1591     #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1)
1592     /* @brief Has TPM module(s) configuration. */
1593     #define FSL_FEATURE_SIM_OPT_HAS_TPM (1)
1594     /* @brief The highest TPM module index. */
1595     #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2)
1596     /* @brief Has TPM module with index 0. */
1597     #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
1598     /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
1599     #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
1600     /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1601     #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1)
1602     /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1603     #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1)
1604     /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
1605     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
1606     /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
1607     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
1608     /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
1609     #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
1610     /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
1611     #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
1612     /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
1613     #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
1614     /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
1615     #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
1616     /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
1617     #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1)
1618     /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
1619     #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
1620     /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
1621     #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (1)
1622     /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
1623     #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (1)
1624     /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
1625     #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1)
1626     /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
1627     #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
1628     /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
1629     #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
1630     /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
1631     #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1)
1632     /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
1633     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
1634     /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
1635     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
1636     /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
1637     #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
1638     /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
1639     #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
1640     /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
1641     #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1)
1642     /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
1643     #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1)
1644     /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
1645     #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2)
1646     /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
1647     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1)
1648     /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
1649     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1)
1650     /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
1651     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
1652     /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
1653     #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4)
1654     /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
1655     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1)
1656     /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
1657     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
1658     /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
1659     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
1660     /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
1661     #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (1)
1662     /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
1663     #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
1664     /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
1665     #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (1)
1666     /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
1667     #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
1668     /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
1669     #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1)
1670     /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
1671     #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
1672     /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
1673     #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
1674     /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
1675     #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
1676     /* @brief Has device die ID (register bit field SDID[DIEID]). */
1677     #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
1678     /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
1679     #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
1680     /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
1681     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
1682     /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
1683     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
1684     /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
1685     #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
1686     /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
1687     #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1)
1688     /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
1689     #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1)
1690     /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
1691     #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1)
1692     /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
1693     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
1694     /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
1695     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
1696     /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
1697     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
1698     /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
1699     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
1700     /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
1701     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1)
1702     /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
1703     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (1)
1704     /* @brief Has miscellanious control register (register MCR). */
1705     #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
1706     /* @brief Has COP watchdog (registers COPC and SRVCOP). */
1707     #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
1708     /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
1709     #define FSL_FEATURE_SIM_HAS_COP_STOP (0)
1710 #elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \
1711     defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)
1712     /* @brief Has USB FS divider. */
1713     #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
1714     /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
1715     #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
1716     /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
1717     #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1)
1718     /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
1719     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
1720     /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
1721     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
1722     /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
1723     #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (1)
1724     /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
1725     #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
1726     /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
1727     #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1)
1728     /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
1729     #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
1730     /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
1731     #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
1732     /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
1733     #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1)
1734     /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
1735     #define FSL_FEATURE_SIM_OPT_HAS_PCR (1)
1736     /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
1737     #define FSL_FEATURE_SIM_OPT_HAS_MCC (1)
1738     /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
1739     #define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
1740     /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
1741     #define FSL_FEATURE_SIM_OPT_UART_COUNT (4)
1742     /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
1743     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
1744     /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
1745     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
1746     /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
1747     #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (1)
1748     /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
1749     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
1750     /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
1751     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
1752     /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
1753     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
1754     /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
1755     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
1756     /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
1757     #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
1758     /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
1759     #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2)
1760     /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
1761     #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
1762     /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
1763     #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2)
1764     /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
1765     #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
1766     /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
1767     #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
1768     /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
1769     #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2)
1770     /* @brief Has FTM module(s) configuration. */
1771     #define FSL_FEATURE_SIM_OPT_HAS_FTM (1)
1772     /* @brief Number of FTM modules. */
1773     #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4)
1774     /* @brief Number of FTM triggers with selectable source. */
1775     #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2)
1776     /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
1777     #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1)
1778     /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
1779     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1)
1780     /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
1781     #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1)
1782     /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
1783     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1)
1784     /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
1785     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
1786     /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
1787     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
1788     /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
1789     #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (4)
1790     /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
1791     #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1)
1792     /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
1793     #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1)
1794     /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
1795     #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1)
1796     /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
1797     #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
1798     /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
1799     #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
1800     /* @brief Has TPM module(s) configuration. */
1801     #define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
1802     /* @brief The highest TPM module index. */
1803     #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
1804     /* @brief Has TPM module with index 0. */
1805     #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
1806     /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
1807     #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
1808     /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1809     #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
1810     /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1811     #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
1812     /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
1813     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
1814     /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
1815     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
1816     /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
1817     #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
1818     /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
1819     #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
1820     /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
1821     #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (1)
1822     /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
1823     #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (1)
1824     /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
1825     #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
1826     /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
1827     #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (1)
1828     /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
1829     #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (1)
1830     /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
1831     #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
1832     /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
1833     #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0)
1834     /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
1835     #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (1)
1836     /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
1837     #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (1)
1838     /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
1839     #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
1840     /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
1841     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
1842     /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
1843     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
1844     /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
1845     #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
1846     /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
1847     #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
1848     /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
1849     #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
1850     /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
1851     #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1)
1852     /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
1853     #define FSL_FEATURE_SIM_OPT_ADC_COUNT (4)
1854     /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
1855     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1)
1856     /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
1857     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1)
1858     /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
1859     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
1860     /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
1861     #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4)
1862     /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
1863     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0)
1864     /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
1865     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (1)
1866     /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
1867     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (1)
1868     /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
1869     #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
1870     /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
1871     #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (1)
1872     /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
1873     #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (1)
1874     /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
1875     #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (1)
1876     /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
1877     #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0)
1878     /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
1879     #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
1880     /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
1881     #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (0)
1882     /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
1883     #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (0)
1884     /* @brief Has device die ID (register bit field SDID[DIEID]). */
1885     #define FSL_FEATURE_SIM_SDID_HAS_DIEID (0)
1886     /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
1887     #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
1888     /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
1889     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (0)
1890     /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
1891     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (0)
1892     /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
1893     #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (1)
1894     /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
1895     #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1)
1896     /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
1897     #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1)
1898     /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
1899     #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1)
1900     /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
1901     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (0)
1902     /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
1903     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0)
1904     /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
1905     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (1)
1906     /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
1907     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (1)
1908     /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
1909     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
1910     /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
1911     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
1912     /* @brief Has miscellanious control register (register MCR). */
1913     #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (1)
1914     /* @brief Has COP watchdog (registers COPC and SRVCOP). */
1915     #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
1916     /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
1917     #define FSL_FEATURE_SIM_HAS_COP_STOP (0)
1918 #elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \
1919     defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4)
1920     /* @brief Has USB FS divider. */
1921     #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
1922     /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
1923     #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
1924     /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
1925     #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0)
1926     /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
1927     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1)
1928     /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
1929     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
1930     /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
1931     #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
1932     /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
1933     #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
1934     /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
1935     #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0)
1936     /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
1937     #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
1938     /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
1939     #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
1940     /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
1941     #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
1942     /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
1943     #define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
1944     /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
1945     #define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
1946     /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
1947     #define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
1948     /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
1949     #define FSL_FEATURE_SIM_OPT_UART_COUNT (0)
1950     /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
1951     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (1)
1952     /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
1953     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
1954     /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
1955     #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
1956     /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
1957     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1)
1958     /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
1959     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1)
1960     /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
1961     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
1962     /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
1963     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
1964     /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
1965     #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0)
1966     /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
1967     #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0)
1968     /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
1969     #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0)
1970     /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
1971     #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0)
1972     /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
1973     #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0)
1974     /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
1975     #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0)
1976     /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
1977     #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0)
1978     /* @brief Has FTM module(s) configuration. */
1979     #define FSL_FEATURE_SIM_OPT_HAS_FTM (0)
1980     /* @brief Number of FTM modules. */
1981     #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0)
1982     /* @brief Number of FTM triggers with selectable source. */
1983     #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0)
1984     /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
1985     #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0)
1986     /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
1987     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0)
1988     /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
1989     #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0)
1990     /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
1991     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0)
1992     /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
1993     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
1994     /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
1995     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
1996     /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
1997     #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0)
1998     /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
1999     #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0)
2000     /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
2001     #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0)
2002     /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
2003     #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0)
2004     /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
2005     #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
2006     /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
2007     #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
2008     /* @brief Has TPM module(s) configuration. */
2009     #define FSL_FEATURE_SIM_OPT_HAS_TPM (1)
2010     /* @brief The highest TPM module index. */
2011     #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (1)
2012     /* @brief Has TPM module with index 0. */
2013     #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1)
2014     /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
2015     #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
2016     /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
2017     #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1)
2018     /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
2019     #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1)
2020     /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
2021     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
2022     /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
2023     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
2024     /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
2025     #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0)
2026     /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
2027     #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0)
2028     /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
2029     #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
2030     /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
2031     #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
2032     /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
2033     #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
2034     /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
2035     #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
2036     /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
2037     #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
2038     /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
2039     #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
2040     /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
2041     #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0)
2042     /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
2043     #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
2044     /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
2045     #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
2046     /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
2047     #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
2048     /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
2049     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (1)
2050     /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
2051     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
2052     /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
2053     #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
2054     /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
2055     #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
2056     /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
2057     #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1)
2058     /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
2059     #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0)
2060     /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
2061     #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1)
2062     /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
2063     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0)
2064     /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
2065     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
2066     /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
2067     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
2068     /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
2069     #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3)
2070     /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
2071     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0)
2072     /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
2073     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
2074     /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
2075     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
2076     /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
2077     #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
2078     /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
2079     #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
2080     /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
2081     #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
2082     /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
2083     #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
2084     /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
2085     #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0)
2086     /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
2087     #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
2088     /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
2089     #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
2090     /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
2091     #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
2092     /* @brief Has device die ID (register bit field SDID[DIEID]). */
2093     #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
2094     /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
2095     #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1)
2096     /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
2097     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
2098     /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
2099     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
2100     /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
2101     #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
2102     /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
2103     #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
2104     /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
2105     #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
2106     /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
2107     #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
2108     /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
2109     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
2110     /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
2111     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0)
2112     /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
2113     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
2114     /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
2115     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
2116     /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
2117     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
2118     /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
2119     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
2120     /* @brief Has miscellanious control register (register MCR). */
2121     #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
2122     /* @brief Has COP watchdog (registers COPC and SRVCOP). */
2123     #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1)
2124     /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
2125     #define FSL_FEATURE_SIM_HAS_COP_STOP (1)
2126 #elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \
2127     defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \
2128     defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4)
2129     /* @brief Has USB FS divider. */
2130     #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
2131     /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
2132     #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
2133     /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
2134     #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0)
2135     /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
2136     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
2137     /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
2138     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
2139     /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
2140     #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
2141     /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
2142     #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
2143     /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
2144     #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0)
2145     /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
2146     #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
2147     /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
2148     #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
2149     /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
2150     #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
2151     /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
2152     #define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
2153     /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
2154     #define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
2155     /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
2156     #define FSL_FEATURE_SIM_OPT_HAS_ODE (1)
2157     /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
2158     #define FSL_FEATURE_SIM_OPT_UART_COUNT (1)
2159     /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
2160     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
2161     /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
2162     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
2163     /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
2164     #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
2165     /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
2166     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
2167     /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
2168     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
2169     /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
2170     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
2171     /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
2172     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
2173     /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
2174     #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
2175     /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
2176     #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (1)
2177     /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
2178     #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
2179     /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
2180     #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (1)
2181     /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
2182     #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0)
2183     /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
2184     #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0)
2185     /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
2186     #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0)
2187     /* @brief Has FTM module(s) configuration. */
2188     #define FSL_FEATURE_SIM_OPT_HAS_FTM (0)
2189     /* @brief Number of FTM modules. */
2190     #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0)
2191     /* @brief Number of FTM triggers with selectable source. */
2192     #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0)
2193     /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
2194     #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0)
2195     /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
2196     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0)
2197     /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
2198     #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0)
2199     /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
2200     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0)
2201     /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
2202     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
2203     /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
2204     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
2205     /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
2206     #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0)
2207     /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
2208     #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0)
2209     /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
2210     #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0)
2211     /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
2212     #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0)
2213     /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
2214     #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
2215     /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
2216     #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
2217     /* @brief Has TPM module(s) configuration. */
2218     #define FSL_FEATURE_SIM_OPT_HAS_TPM (1)
2219     /* @brief The highest TPM module index. */
2220     #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (1)
2221     /* @brief Has TPM module with index 0. */
2222     #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1)
2223     /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
2224     #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
2225     /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
2226     #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1)
2227     /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
2228     #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1)
2229     /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
2230     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
2231     /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
2232     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
2233     /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
2234     #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0)
2235     /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
2236     #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0)
2237     /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
2238     #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
2239     /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
2240     #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
2241     /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
2242     #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
2243     /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
2244     #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
2245     /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
2246     #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
2247     /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
2248     #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
2249     /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
2250     #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0)
2251     /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
2252     #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
2253     /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
2254     #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
2255     /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
2256     #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
2257     /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
2258     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
2259     /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
2260     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
2261     /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
2262     #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
2263     /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
2264     #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (1)
2265     /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
2266     #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1)
2267     /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
2268     #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0)
2269     /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
2270     #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1)
2271     /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
2272     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0)
2273     /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
2274     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
2275     /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
2276     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
2277     /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
2278     #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3)
2279     /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
2280     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0)
2281     /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
2282     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
2283     /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
2284     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
2285     /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
2286     #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
2287     /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
2288     #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
2289     /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
2290     #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
2291     /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
2292     #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
2293     /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
2294     #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0)
2295     /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
2296     #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
2297     /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
2298     #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
2299     /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
2300     #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
2301     /* @brief Has device die ID (register bit field SDID[DIEID]). */
2302     #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
2303     /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
2304     #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1)
2305     /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
2306     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
2307     /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
2308     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
2309     /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
2310     #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
2311     /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
2312     #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
2313     /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
2314     #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
2315     /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
2316     #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
2317     /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
2318     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
2319     /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
2320     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0)
2321     /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
2322     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
2323     /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
2324     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
2325     /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
2326     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
2327     /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
2328     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
2329     /* @brief Has miscellanious control register (register MCR). */
2330     #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
2331     /* @brief Has COP watchdog (registers COPC and SRVCOP). */
2332     #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1)
2333     /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
2334     #define FSL_FEATURE_SIM_HAS_COP_STOP (0)
2335 #elif defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || \
2336     defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || \
2337     defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || \
2338     defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || \
2339     defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || \
2340     defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || \
2341     defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \
2342     defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \
2343     defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4)
2344     /* @brief Has USB FS divider. */
2345     #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
2346     /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
2347     #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
2348     /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
2349     #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0)
2350     /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
2351     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1)
2352     /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
2353     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
2354     /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
2355     #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
2356     /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
2357     #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
2358     /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
2359     #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1)
2360     /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
2361     #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
2362     /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
2363     #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
2364     /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
2365     #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
2366     /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
2367     #define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
2368     /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
2369     #define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
2370     /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
2371     #define FSL_FEATURE_SIM_OPT_HAS_ODE (1)
2372     /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
2373     #define FSL_FEATURE_SIM_OPT_UART_COUNT (1)
2374     /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
2375     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (1)
2376     /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
2377     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (1)
2378     /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
2379     #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
2380     /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
2381     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1)
2382     /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
2383     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1)
2384     /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
2385     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (1)
2386     /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
2387     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (1)
2388     /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
2389     #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0)
2390     /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
2391     #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0)
2392     /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
2393     #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0)
2394     /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
2395     #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0)
2396     /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
2397     #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0)
2398     /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
2399     #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0)
2400     /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
2401     #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0)
2402     /* @brief Has FTM module(s) configuration. */
2403     #define FSL_FEATURE_SIM_OPT_HAS_FTM (0)
2404     /* @brief Number of FTM modules. */
2405     #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0)
2406     /* @brief Number of FTM triggers with selectable source. */
2407     #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0)
2408     /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
2409     #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0)
2410     /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
2411     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0)
2412     /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
2413     #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0)
2414     /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
2415     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0)
2416     /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
2417     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
2418     /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
2419     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
2420     /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
2421     #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0)
2422     /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
2423     #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0)
2424     /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
2425     #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0)
2426     /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
2427     #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0)
2428     /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
2429     #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
2430     /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
2431     #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
2432     /* @brief Has TPM module(s) configuration. */
2433     #define FSL_FEATURE_SIM_OPT_HAS_TPM (1)
2434     /* @brief The highest TPM module index. */
2435     #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2)
2436     /* @brief Has TPM module with index 0. */
2437     #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1)
2438     /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
2439     #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
2440     /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
2441     #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1)
2442     /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
2443     #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (2)
2444     /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
2445     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1)
2446     /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
2447     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1)
2448     /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
2449     #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0)
2450     /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
2451     #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0)
2452     /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
2453     #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
2454     /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
2455     #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
2456     /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
2457     #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
2458     /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
2459     #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
2460     /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
2461     #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
2462     /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
2463     #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
2464     /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
2465     #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1)
2466     /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
2467     #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
2468     /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
2469     #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
2470     /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
2471     #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
2472     /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
2473     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (1)
2474     /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
2475     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (1)
2476     /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
2477     #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (1)
2478     /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
2479     #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
2480     /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
2481     #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1)
2482     /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
2483     #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0)
2484     /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
2485     #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1)
2486     /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
2487     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0)
2488     /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
2489     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
2490     /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
2491     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
2492     /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
2493     #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3)
2494     /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
2495     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0)
2496     /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
2497     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
2498     /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
2499     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
2500     /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
2501     #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
2502     /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
2503     #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
2504     /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
2505     #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
2506     /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
2507     #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
2508     /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
2509     #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0)
2510     /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
2511     #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
2512     /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
2513     #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
2514     /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
2515     #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
2516     /* @brief Has device die ID (register bit field SDID[DIEID]). */
2517     #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
2518     /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
2519     #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1)
2520     /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
2521     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
2522     /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
2523     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
2524     /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
2525     #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
2526     /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
2527     #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
2528     /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
2529     #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
2530     /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
2531     #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
2532     /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
2533     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
2534     /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
2535     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
2536     /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
2537     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
2538     /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
2539     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
2540     /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
2541     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
2542     /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
2543     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
2544     /* @brief Has miscellanious control register (register MCR). */
2545     #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
2546     /* @brief Has COP watchdog (registers COPC and SRVCOP). */
2547     #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1)
2548     /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
2549     #define FSL_FEATURE_SIM_HAS_COP_STOP (1)
2550 #elif defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || \
2551     defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || \
2552     defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4)
2553     /* @brief Has USB FS divider. */
2554     #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
2555     /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
2556     #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (1)
2557     /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
2558     #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0)
2559     /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
2560     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
2561     /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
2562     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
2563     /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
2564     #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
2565     /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
2566     #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
2567     /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
2568     #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1)
2569     /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
2570     #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
2571     /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
2572     #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
2573     /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
2574     #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
2575     /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
2576     #define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
2577     /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
2578     #define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
2579     /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
2580     #define FSL_FEATURE_SIM_OPT_HAS_ODE (1)
2581     /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
2582     #define FSL_FEATURE_SIM_OPT_UART_COUNT (3)
2583     /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
2584     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
2585     /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
2586     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
2587     /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
2588     #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
2589     /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
2590     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
2591     /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
2592     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
2593     /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
2594     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
2595     /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
2596     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
2597     /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
2598     #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
2599     /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
2600     #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2)
2601     /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
2602     #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
2603     /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
2604     #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (1)
2605     /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
2606     #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
2607     /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
2608     #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
2609     /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
2610     #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (1)
2611     /* @brief Has FTM module(s) configuration. */
2612     #define FSL_FEATURE_SIM_OPT_HAS_FTM (0)
2613     /* @brief Number of FTM modules. */
2614     #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0)
2615     /* @brief Number of FTM triggers with selectable source. */
2616     #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0)
2617     /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
2618     #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0)
2619     /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
2620     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0)
2621     /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
2622     #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0)
2623     /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
2624     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0)
2625     /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
2626     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
2627     /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
2628     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
2629     /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
2630     #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0)
2631     /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
2632     #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0)
2633     /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
2634     #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0)
2635     /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
2636     #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0)
2637     /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
2638     #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
2639     /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
2640     #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
2641     /* @brief Has TPM module(s) configuration. */
2642     #define FSL_FEATURE_SIM_OPT_HAS_TPM (1)
2643     /* @brief The highest TPM module index. */
2644     #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2)
2645     /* @brief Has TPM module with index 0. */
2646     #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1)
2647     /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
2648     #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
2649     /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
2650     #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1)
2651     /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
2652     #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1)
2653     /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
2654     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1)
2655     /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
2656     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1)
2657     /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
2658     #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
2659     /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
2660     #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
2661     /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
2662     #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
2663     /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
2664     #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
2665     /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
2666     #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
2667     /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
2668     #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
2669     /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
2670     #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
2671     /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
2672     #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
2673     /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
2674     #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1)
2675     /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
2676     #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
2677     /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
2678     #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
2679     /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
2680     #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
2681     /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
2682     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
2683     /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
2684     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
2685     /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
2686     #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
2687     /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
2688     #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (1)
2689     /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
2690     #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1)
2691     /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
2692     #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0)
2693     /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
2694     #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1)
2695     /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
2696     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0)
2697     /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
2698     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
2699     /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
2700     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
2701     /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
2702     #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3)
2703     /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
2704     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0)
2705     /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
2706     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
2707     /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
2708     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
2709     /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
2710     #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
2711     /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
2712     #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
2713     /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
2714     #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
2715     /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
2716     #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
2717     /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
2718     #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0)
2719     /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
2720     #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
2721     /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
2722     #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
2723     /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
2724     #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
2725     /* @brief Has device die ID (register bit field SDID[DIEID]). */
2726     #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
2727     /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
2728     #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1)
2729     /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
2730     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
2731     /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
2732     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
2733     /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
2734     #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
2735     /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
2736     #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
2737     /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
2738     #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
2739     /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
2740     #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
2741     /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
2742     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
2743     /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
2744     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0)
2745     /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
2746     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
2747     /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
2748     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
2749     /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
2750     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
2751     /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
2752     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
2753     /* @brief Has miscellanious control register (register MCR). */
2754     #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
2755     /* @brief Has COP watchdog (registers COPC and SRVCOP). */
2756     #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1)
2757     /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
2758     #define FSL_FEATURE_SIM_HAS_COP_STOP (0)
2759 #elif defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || \
2760     defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \
2761     defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4)
2762     /* @brief Has USB FS divider. */
2763     #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
2764     /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
2765     #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (1)
2766     /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
2767     #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0)
2768     /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
2769     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
2770     /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
2771     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
2772     /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
2773     #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
2774     /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
2775     #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
2776     /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
2777     #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1)
2778     /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
2779     #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
2780     /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
2781     #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
2782     /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
2783     #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
2784     /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
2785     #define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
2786     /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
2787     #define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
2788     /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
2789     #define FSL_FEATURE_SIM_OPT_HAS_ODE (1)
2790     /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
2791     #define FSL_FEATURE_SIM_OPT_UART_COUNT (3)
2792     /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
2793     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
2794     /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
2795     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
2796     /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
2797     #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
2798     /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
2799     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
2800     /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
2801     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
2802     /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
2803     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
2804     /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
2805     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
2806     /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
2807     #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
2808     /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
2809     #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2)
2810     /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
2811     #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
2812     /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
2813     #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (1)
2814     /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
2815     #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
2816     /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
2817     #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
2818     /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
2819     #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (1)
2820     /* @brief Has FTM module(s) configuration. */
2821     #define FSL_FEATURE_SIM_OPT_HAS_FTM (0)
2822     /* @brief Number of FTM modules. */
2823     #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0)
2824     /* @brief Number of FTM triggers with selectable source. */
2825     #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0)
2826     /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
2827     #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0)
2828     /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
2829     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0)
2830     /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
2831     #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0)
2832     /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
2833     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0)
2834     /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
2835     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
2836     /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
2837     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
2838     /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
2839     #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0)
2840     /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
2841     #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0)
2842     /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
2843     #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0)
2844     /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
2845     #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0)
2846     /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
2847     #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
2848     /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
2849     #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
2850     /* @brief Has TPM module(s) configuration. */
2851     #define FSL_FEATURE_SIM_OPT_HAS_TPM (1)
2852     /* @brief The highest TPM module index. */
2853     #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2)
2854     /* @brief Has TPM module with index 0. */
2855     #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1)
2856     /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
2857     #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
2858     /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
2859     #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1)
2860     /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
2861     #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (2)
2862     /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
2863     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1)
2864     /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
2865     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1)
2866     /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
2867     #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
2868     /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
2869     #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
2870     /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
2871     #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
2872     /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
2873     #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
2874     /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
2875     #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
2876     /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
2877     #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
2878     /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
2879     #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
2880     /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
2881     #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
2882     /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
2883     #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1)
2884     /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
2885     #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
2886     /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
2887     #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
2888     /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
2889     #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
2890     /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
2891     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
2892     /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
2893     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
2894     /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
2895     #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
2896     /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
2897     #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (1)
2898     /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
2899     #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1)
2900     /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
2901     #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0)
2902     /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
2903     #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1)
2904     /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
2905     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0)
2906     /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
2907     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
2908     /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
2909     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
2910     /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
2911     #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3)
2912     /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
2913     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0)
2914     /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
2915     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
2916     /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
2917     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
2918     /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
2919     #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
2920     /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
2921     #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
2922     /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
2923     #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
2924     /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
2925     #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
2926     /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
2927     #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0)
2928     /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
2929     #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
2930     /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
2931     #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
2932     /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
2933     #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
2934     /* @brief Has device die ID (register bit field SDID[DIEID]). */
2935     #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
2936     /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
2937     #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1)
2938     /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
2939     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
2940     /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
2941     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
2942     /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
2943     #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
2944     /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
2945     #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
2946     /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
2947     #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
2948     /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
2949     #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
2950     /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
2951     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
2952     /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
2953     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
2954     /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
2955     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
2956     /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
2957     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
2958     /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
2959     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
2960     /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
2961     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
2962     /* @brief Has miscellanious control register (register MCR). */
2963     #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
2964     /* @brief Has COP watchdog (registers COPC and SRVCOP). */
2965     #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1)
2966     /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
2967     #define FSL_FEATURE_SIM_HAS_COP_STOP (0)
2968 #elif defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || \
2969     defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10)
2970     /* @brief Has USB FS divider. */
2971     #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
2972     /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
2973     #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
2974     /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
2975     #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1)
2976     /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
2977     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1)
2978     /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
2979     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
2980     /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
2981     #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
2982     /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
2983     #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0)
2984     /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
2985     #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0)
2986     /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
2987     #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
2988     /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
2989     #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
2990     /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
2991     #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
2992     /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
2993     #define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
2994     /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
2995     #define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
2996     /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
2997     #define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
2998     /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
2999     #define FSL_FEATURE_SIM_OPT_UART_COUNT (2)
3000     /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
3001     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
3002     /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
3003     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
3004     /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
3005     #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
3006     /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
3007     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
3008     /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
3009     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
3010     /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
3011     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
3012     /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
3013     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
3014     /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
3015     #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
3016     /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
3017     #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2)
3018     /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
3019     #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
3020     /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
3021     #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2)
3022     /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
3023     #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
3024     /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
3025     #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
3026     /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
3027     #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2)
3028     /* @brief Has FTM module(s) configuration. */
3029     #define FSL_FEATURE_SIM_OPT_HAS_FTM (1)
3030     /* @brief Number of FTM modules. */
3031     #define FSL_FEATURE_SIM_OPT_FTM_COUNT (3)
3032     /* @brief Number of FTM triggers with selectable source. */
3033     #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2)
3034     /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
3035     #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1)
3036     /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
3037     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0)
3038     /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
3039     #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1)
3040     /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
3041     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1)
3042     /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
3043     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
3044     /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
3045     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1)
3046     /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
3047     #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2)
3048     /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
3049     #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1)
3050     /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
3051     #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1)
3052     /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
3053     #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0)
3054     /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
3055     #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1)
3056     /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
3057     #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1)
3058     /* @brief Has TPM module(s) configuration. */
3059     #define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
3060     /* @brief The highest TPM module index. */
3061     #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
3062     /* @brief Has TPM module with index 0. */
3063     #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
3064     /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
3065     #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
3066     /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
3067     #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
3068     /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
3069     #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
3070     /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
3071     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
3072     /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
3073     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
3074     /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
3075     #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
3076     /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
3077     #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
3078     /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
3079     #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
3080     /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
3081     #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
3082     /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
3083     #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
3084     /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
3085     #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
3086     /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
3087     #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
3088     /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
3089     #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
3090     /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
3091     #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0)
3092     /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
3093     #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
3094     /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
3095     #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
3096     /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
3097     #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
3098     /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
3099     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
3100     /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
3101     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
3102     /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
3103     #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
3104     /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
3105     #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
3106     /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
3107     #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
3108     /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
3109     #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1)
3110     /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
3111     #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2)
3112     /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
3113     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1)
3114     /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
3115     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
3116     /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
3117     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
3118     /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
3119     #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4)
3120     /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
3121     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0)
3122     /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
3123     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
3124     /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
3125     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
3126     /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
3127     #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
3128     /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
3129     #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
3130     /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
3131     #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
3132     /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
3133     #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
3134     /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
3135     #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1)
3136     /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
3137     #define FSL_FEATURE_SIM_SDID_HAS_FAMID (0)
3138     /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
3139     #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
3140     /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
3141     #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
3142     /* @brief Has device die ID (register bit field SDID[DIEID]). */
3143     #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
3144     /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
3145     #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
3146     /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
3147     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
3148     /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
3149     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
3150     /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
3151     #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
3152     /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
3153     #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
3154     /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
3155     #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
3156     /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
3157     #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
3158     /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
3159     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
3160     /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
3161     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0)
3162     /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
3163     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
3164     /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
3165     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
3166     /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
3167     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
3168     /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
3169     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
3170     /* @brief Has miscellanious control register (register MCR). */
3171     #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
3172     /* @brief Has COP watchdog (registers COPC and SRVCOP). */
3173     #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
3174     /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
3175     #define FSL_FEATURE_SIM_HAS_COP_STOP (0)
3176 #elif defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12)
3177     /* @brief Has USB FS divider. */
3178     #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
3179     /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
3180     #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
3181     /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
3182     #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1)
3183     /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
3184     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1)
3185     /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
3186     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
3187     /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
3188     #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
3189     /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
3190     #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0)
3191     /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
3192     #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0)
3193     /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
3194     #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
3195     /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
3196     #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
3197     /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
3198     #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
3199     /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
3200     #define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
3201     /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
3202     #define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
3203     /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
3204     #define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
3205     /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
3206     #define FSL_FEATURE_SIM_OPT_UART_COUNT (3)
3207     /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
3208     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
3209     /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
3210     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
3211     /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
3212     #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
3213     /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
3214     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
3215     /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
3216     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1)
3217     /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
3218     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
3219     /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
3220     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
3221     /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
3222     #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
3223     /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
3224     #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2)
3225     /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
3226     #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
3227     /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
3228     #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2)
3229     /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
3230     #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
3231     /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
3232     #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
3233     /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
3234     #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2)
3235     /* @brief Has FTM module(s) configuration. */
3236     #define FSL_FEATURE_SIM_OPT_HAS_FTM (1)
3237     /* @brief Number of FTM modules. */
3238     #define FSL_FEATURE_SIM_OPT_FTM_COUNT (3)
3239     /* @brief Number of FTM triggers with selectable source. */
3240     #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2)
3241     /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
3242     #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1)
3243     /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
3244     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0)
3245     /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
3246     #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1)
3247     /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
3248     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1)
3249     /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
3250     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
3251     /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
3252     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1)
3253     /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
3254     #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2)
3255     /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
3256     #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1)
3257     /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
3258     #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1)
3259     /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
3260     #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0)
3261     /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
3262     #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1)
3263     /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
3264     #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1)
3265     /* @brief Has TPM module(s) configuration. */
3266     #define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
3267     /* @brief The highest TPM module index. */
3268     #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
3269     /* @brief Has TPM module with index 0. */
3270     #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
3271     /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
3272     #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
3273     /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
3274     #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
3275     /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
3276     #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
3277     /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
3278     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
3279     /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
3280     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
3281     /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
3282     #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
3283     /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
3284     #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
3285     /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
3286     #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
3287     /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
3288     #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
3289     /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
3290     #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
3291     /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
3292     #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
3293     /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
3294     #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
3295     /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
3296     #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
3297     /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
3298     #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0)
3299     /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
3300     #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
3301     /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
3302     #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
3303     /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
3304     #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1)
3305     /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
3306     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
3307     /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
3308     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
3309     /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
3310     #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
3311     /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
3312     #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
3313     /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
3314     #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
3315     /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
3316     #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1)
3317     /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
3318     #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2)
3319     /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
3320     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1)
3321     /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
3322     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
3323     /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
3324     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
3325     /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
3326     #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4)
3327     /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
3328     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0)
3329     /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
3330     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
3331     /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
3332     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
3333     /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
3334     #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
3335     /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
3336     #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
3337     /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
3338     #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
3339     /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
3340     #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
3341     /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
3342     #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1)
3343     /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
3344     #define FSL_FEATURE_SIM_SDID_HAS_FAMID (0)
3345     /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
3346     #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
3347     /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
3348     #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
3349     /* @brief Has device die ID (register bit field SDID[DIEID]). */
3350     #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
3351     /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
3352     #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
3353     /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
3354     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
3355     /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
3356     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
3357     /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
3358     #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
3359     /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
3360     #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
3361     /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
3362     #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
3363     /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
3364     #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
3365     /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
3366     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
3367     /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
3368     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
3369     /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
3370     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
3371     /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
3372     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
3373     /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
3374     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
3375     /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
3376     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
3377     /* @brief Has miscellanious control register (register MCR). */
3378     #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
3379     /* @brief Has COP watchdog (registers COPC and SRVCOP). */
3380     #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
3381     /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
3382     #define FSL_FEATURE_SIM_HAS_COP_STOP (0)
3383 #elif defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12)
3384     /* @brief Has USB FS divider. */
3385     #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
3386     /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
3387     #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
3388     /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
3389     #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1)
3390     /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
3391     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1)
3392     /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
3393     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
3394     /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
3395     #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
3396     /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
3397     #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0)
3398     /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
3399     #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0)
3400     /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
3401     #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
3402     /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
3403     #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
3404     /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
3405     #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1)
3406     /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
3407     #define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
3408     /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
3409     #define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
3410     /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
3411     #define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
3412     /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
3413     #define FSL_FEATURE_SIM_OPT_UART_COUNT (3)
3414     /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
3415     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
3416     /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
3417     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
3418     /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
3419     #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
3420     /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
3421     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
3422     /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
3423     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1)
3424     /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
3425     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
3426     /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
3427     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
3428     /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
3429     #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
3430     /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
3431     #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2)
3432     /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
3433     #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
3434     /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
3435     #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2)
3436     /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
3437     #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
3438     /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
3439     #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
3440     /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
3441     #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2)
3442     /* @brief Has FTM module(s) configuration. */
3443     #define FSL_FEATURE_SIM_OPT_HAS_FTM (1)
3444     /* @brief Number of FTM modules. */
3445     #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4)
3446     /* @brief Number of FTM triggers with selectable source. */
3447     #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2)
3448     /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
3449     #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1)
3450     /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
3451     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1)
3452     /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
3453     #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1)
3454     /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
3455     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1)
3456     /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
3457     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
3458     /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
3459     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1)
3460     /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
3461     #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2)
3462     /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
3463     #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1)
3464     /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
3465     #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1)
3466     /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
3467     #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1)
3468     /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
3469     #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1)
3470     /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
3471     #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1)
3472     /* @brief Has TPM module(s) configuration. */
3473     #define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
3474     /* @brief The highest TPM module index. */
3475     #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
3476     /* @brief Has TPM module with index 0. */
3477     #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
3478     /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
3479     #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
3480     /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
3481     #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
3482     /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
3483     #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
3484     /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
3485     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
3486     /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
3487     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
3488     /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
3489     #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
3490     /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
3491     #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
3492     /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
3493     #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
3494     /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
3495     #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
3496     /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
3497     #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
3498     /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
3499     #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
3500     /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
3501     #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
3502     /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
3503     #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
3504     /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
3505     #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0)
3506     /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
3507     #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
3508     /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
3509     #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
3510     /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
3511     #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1)
3512     /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
3513     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
3514     /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
3515     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
3516     /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
3517     #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
3518     /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
3519     #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
3520     /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
3521     #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
3522     /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
3523     #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1)
3524     /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
3525     #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2)
3526     /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
3527     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1)
3528     /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
3529     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1)
3530     /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
3531     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
3532     /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
3533     #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4)
3534     /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
3535     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0)
3536     /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
3537     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
3538     /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
3539     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
3540     /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
3541     #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
3542     /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
3543     #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
3544     /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
3545     #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
3546     /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
3547     #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
3548     /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
3549     #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1)
3550     /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
3551     #define FSL_FEATURE_SIM_SDID_HAS_FAMID (0)
3552     /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
3553     #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
3554     /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
3555     #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
3556     /* @brief Has device die ID (register bit field SDID[DIEID]). */
3557     #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
3558     /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
3559     #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
3560     /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
3561     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
3562     /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
3563     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
3564     /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
3565     #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
3566     /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
3567     #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
3568     /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
3569     #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
3570     /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
3571     #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
3572     /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
3573     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
3574     /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
3575     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
3576     /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
3577     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
3578     /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
3579     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
3580     /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
3581     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
3582     /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
3583     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
3584     /* @brief Has miscellanious control register (register MCR). */
3585     #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
3586     /* @brief Has COP watchdog (registers COPC and SRVCOP). */
3587     #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
3588     /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
3589     #define FSL_FEATURE_SIM_HAS_COP_STOP (0)
3590 #elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F64VLH15) || defined(CPU_MKV45F128VLH15) || \
3591     defined(CPU_MKV45F256VLH15) || defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F256VLH15)
3592     /* @brief Has USB FS divider. */
3593     #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
3594     /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
3595     #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
3596     /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
3597     #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1)
3598     /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
3599     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
3600     /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
3601     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
3602     /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
3603     #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
3604     /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
3605     #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0)
3606     /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
3607     #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0)
3608     /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
3609     #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
3610     /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
3611     #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
3612     /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
3613     #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
3614     /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
3615     #define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
3616     /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
3617     #define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
3618     /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
3619     #define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
3620     /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
3621     #define FSL_FEATURE_SIM_OPT_UART_COUNT (2)
3622     /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
3623     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
3624     /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
3625     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
3626     /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
3627     #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
3628     /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
3629     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
3630     /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
3631     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
3632     /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
3633     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
3634     /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
3635     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
3636     /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
3637     #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
3638     /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
3639     #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (1)
3640     /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
3641     #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
3642     /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
3643     #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2)
3644     /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
3645     #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
3646     /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
3647     #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
3648     /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
3649     #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2)
3650     /* @brief Has FTM module(s) configuration. */
3651     #define FSL_FEATURE_SIM_OPT_HAS_FTM (1)
3652     /* @brief Number of FTM modules. */
3653     #define FSL_FEATURE_SIM_OPT_FTM_COUNT (2)
3654     /* @brief Number of FTM triggers with selectable source. */
3655     #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2)
3656     /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
3657     #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1)
3658     /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
3659     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1)
3660     /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
3661     #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0)
3662     /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
3663     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0)
3664     /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
3665     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
3666     /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
3667     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
3668     /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
3669     #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (4)
3670     /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
3671     #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1)
3672     /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
3673     #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0)
3674     /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
3675     #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1)
3676     /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
3677     #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1)
3678     /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
3679     #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1)
3680     /* @brief Has TPM module(s) configuration. */
3681     #define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
3682     /* @brief The highest TPM module index. */
3683     #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
3684     /* @brief Has TPM module with index 0. */
3685     #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
3686     /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
3687     #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
3688     /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
3689     #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
3690     /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
3691     #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
3692     /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
3693     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
3694     /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
3695     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
3696     /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
3697     #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0)
3698     /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
3699     #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0)
3700     /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
3701     #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
3702     /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
3703     #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
3704     /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
3705     #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
3706     /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
3707     #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
3708     /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
3709     #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
3710     /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
3711     #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
3712     /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
3713     #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0)
3714     /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
3715     #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
3716     /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
3717     #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
3718     /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
3719     #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
3720     /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
3721     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
3722     /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
3723     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
3724     /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
3725     #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
3726     /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
3727     #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
3728     /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
3729     #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
3730     /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
3731     #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1)
3732     /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
3733     #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1)
3734     /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
3735     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1)
3736     /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
3737     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
3738     /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
3739     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
3740     /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
3741     #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4)
3742     /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
3743     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0)
3744     /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
3745     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
3746     /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
3747     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
3748     /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
3749     #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
3750     /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
3751     #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
3752     /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
3753     #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (1)
3754     /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
3755     #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
3756     /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
3757     #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1)
3758     /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
3759     #define FSL_FEATURE_SIM_SDID_HAS_FAMID (0)
3760     /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
3761     #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
3762     /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
3763     #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
3764     /* @brief Has device die ID (register bit field SDID[DIEID]). */
3765     #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
3766     /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
3767     #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
3768     /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
3769     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
3770     /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
3771     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
3772     /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
3773     #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
3774     /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
3775     #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
3776     /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
3777     #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
3778     /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
3779     #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
3780     /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
3781     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
3782     /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
3783     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0)
3784     /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
3785     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
3786     /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
3787     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
3788     /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
3789     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
3790     /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
3791     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
3792     /* @brief Has miscellanious control register (register MCR). */
3793     #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
3794     /* @brief Has COP watchdog (registers COPC and SRVCOP). */
3795     #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
3796     /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
3797     #define FSL_FEATURE_SIM_HAS_COP_STOP (0)
3798 #elif defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLL15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLL15) || \
3799     defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLL15)
3800     /* @brief Has USB FS divider. */
3801     #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
3802     /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
3803     #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
3804     /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
3805     #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1)
3806     /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
3807     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
3808     /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
3809     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
3810     /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
3811     #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
3812     /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
3813     #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0)
3814     /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
3815     #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0)
3816     /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
3817     #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
3818     /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
3819     #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
3820     /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
3821     #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
3822     /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
3823     #define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
3824     /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
3825     #define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
3826     /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
3827     #define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
3828     /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
3829     #define FSL_FEATURE_SIM_OPT_UART_COUNT (2)
3830     /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
3831     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
3832     /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
3833     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
3834     /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
3835     #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
3836     /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
3837     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
3838     /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
3839     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
3840     /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
3841     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
3842     /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
3843     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
3844     /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
3845     #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
3846     /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
3847     #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (1)
3848     /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
3849     #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
3850     /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
3851     #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2)
3852     /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
3853     #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
3854     /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
3855     #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
3856     /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
3857     #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2)
3858     /* @brief Has FTM module(s) configuration. */
3859     #define FSL_FEATURE_SIM_OPT_HAS_FTM (1)
3860     /* @brief Number of FTM modules. */
3861     #define FSL_FEATURE_SIM_OPT_FTM_COUNT (3)
3862     /* @brief Number of FTM triggers with selectable source. */
3863     #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2)
3864     /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
3865     #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1)
3866     /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
3867     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1)
3868     /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
3869     #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0)
3870     /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
3871     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0)
3872     /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
3873     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
3874     /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
3875     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
3876     /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
3877     #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (4)
3878     /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
3879     #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1)
3880     /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
3881     #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0)
3882     /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
3883     #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1)
3884     /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
3885     #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1)
3886     /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
3887     #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1)
3888     /* @brief Has TPM module(s) configuration. */
3889     #define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
3890     /* @brief The highest TPM module index. */
3891     #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
3892     /* @brief Has TPM module with index 0. */
3893     #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
3894     /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
3895     #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
3896     /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
3897     #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
3898     /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
3899     #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
3900     /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
3901     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
3902     /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
3903     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
3904     /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
3905     #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0)
3906     /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
3907     #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0)
3908     /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
3909     #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
3910     /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
3911     #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
3912     /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
3913     #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
3914     /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
3915     #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
3916     /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
3917     #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
3918     /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
3919     #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
3920     /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
3921     #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0)
3922     /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
3923     #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
3924     /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
3925     #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
3926     /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
3927     #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
3928     /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
3929     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
3930     /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
3931     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
3932     /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
3933     #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
3934     /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
3935     #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
3936     /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
3937     #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
3938     /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
3939     #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1)
3940     /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
3941     #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1)
3942     /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
3943     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1)
3944     /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
3945     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
3946     /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
3947     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
3948     /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
3949     #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4)
3950     /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
3951     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0)
3952     /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
3953     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
3954     /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
3955     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
3956     /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
3957     #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
3958     /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
3959     #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
3960     /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
3961     #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (1)
3962     /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
3963     #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
3964     /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
3965     #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1)
3966     /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
3967     #define FSL_FEATURE_SIM_SDID_HAS_FAMID (0)
3968     /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
3969     #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
3970     /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
3971     #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
3972     /* @brief Has device die ID (register bit field SDID[DIEID]). */
3973     #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
3974     /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
3975     #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
3976     /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
3977     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
3978     /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
3979     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
3980     /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
3981     #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
3982     /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
3983     #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
3984     /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
3985     #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
3986     /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
3987     #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
3988     /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
3989     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
3990     /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
3991     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0)
3992     /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
3993     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
3994     /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
3995     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
3996     /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
3997     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
3998     /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
3999     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
4000     /* @brief Has miscellanious control register (register MCR). */
4001     #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
4002     /* @brief Has COP watchdog (registers COPC and SRVCOP). */
4003     #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
4004     /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
4005     #define FSL_FEATURE_SIM_HAS_COP_STOP (0)
4006 #elif defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || \
4007     defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15)
4008     /* @brief Has USB FS divider. */
4009     #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
4010     /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
4011     #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
4012     /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
4013     #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1)
4014     /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
4015     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
4016     /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
4017     #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
4018     /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
4019     #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
4020     /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
4021     #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0)
4022     /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
4023     #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0)
4024     /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
4025     #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
4026     /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
4027     #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
4028     /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
4029     #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
4030     /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
4031     #define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
4032     /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
4033     #define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
4034     /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
4035     #define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
4036     /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
4037     #define FSL_FEATURE_SIM_OPT_UART_COUNT (2)
4038     /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
4039     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
4040     /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
4041     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
4042     /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
4043     #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
4044     /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
4045     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
4046     /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
4047     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
4048     /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
4049     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
4050     /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
4051     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
4052     /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
4053     #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
4054     /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
4055     #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (1)
4056     /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
4057     #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
4058     /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
4059     #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2)
4060     /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
4061     #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
4062     /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
4063     #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
4064     /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
4065     #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2)
4066     /* @brief Has FTM module(s) configuration. */
4067     #define FSL_FEATURE_SIM_OPT_HAS_FTM (1)
4068     /* @brief Number of FTM modules. */
4069     #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0)
4070     /* @brief Number of FTM triggers with selectable source. */
4071     #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2)
4072     /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
4073     #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1)
4074     /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
4075     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1)
4076     /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
4077     #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0)
4078     /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
4079     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0)
4080     /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
4081     #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
4082     /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
4083     #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
4084     /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
4085     #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (4)
4086     /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
4087     #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1)
4088     /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
4089     #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0)
4090     /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
4091     #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1)
4092     /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
4093     #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1)
4094     /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
4095     #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1)
4096     /* @brief Has TPM module(s) configuration. */
4097     #define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
4098     /* @brief The highest TPM module index. */
4099     #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
4100     /* @brief Has TPM module with index 0. */
4101     #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
4102     /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
4103     #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
4104     /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
4105     #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
4106     /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
4107     #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
4108     /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
4109     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
4110     /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
4111     #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
4112     /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
4113     #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0)
4114     /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
4115     #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0)
4116     /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
4117     #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
4118     /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
4119     #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
4120     /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
4121     #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
4122     /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
4123     #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
4124     /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
4125     #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
4126     /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
4127     #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
4128     /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
4129     #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0)
4130     /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
4131     #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
4132     /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
4133     #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
4134     /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
4135     #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
4136     /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
4137     #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
4138     /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
4139     #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
4140     /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
4141     #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
4142     /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
4143     #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
4144     /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
4145     #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
4146     /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
4147     #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1)
4148     /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
4149     #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1)
4150     /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
4151     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1)
4152     /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
4153     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
4154     /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
4155     #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
4156     /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
4157     #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4)
4158     /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
4159     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0)
4160     /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
4161     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
4162     /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
4163     #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
4164     /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
4165     #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
4166     /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
4167     #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
4168     /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
4169     #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (1)
4170     /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
4171     #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
4172     /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
4173     #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1)
4174     /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
4175     #define FSL_FEATURE_SIM_SDID_HAS_FAMID (0)
4176     /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
4177     #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
4178     /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
4179     #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
4180     /* @brief Has device die ID (register bit field SDID[DIEID]). */
4181     #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
4182     /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
4183     #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
4184     /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
4185     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
4186     /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
4187     #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
4188     /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
4189     #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
4190     /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
4191     #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
4192     /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
4193     #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
4194     /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
4195     #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
4196     /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
4197     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
4198     /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
4199     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0)
4200     /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
4201     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
4202     /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
4203     #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
4204     /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
4205     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
4206     /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
4207     #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
4208     /* @brief Has miscellanious control register (register MCR). */
4209     #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
4210     /* @brief Has COP watchdog (registers COPC and SRVCOP). */
4211     #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
4212     /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
4213     #define FSL_FEATURE_SIM_HAS_COP_STOP (0)
4214 #else
4215     #error "No valid CPU defined!"
4216 #endif
4217
4218 #endif /* __FSL_SIM_FEATURES_H__ */
4219
4220 /*******************************************************************************
4221  * EOF
4222  ******************************************************************************/