tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/smc/fsl_smc_features.h

   1 /*
   2 ** ###################################################################
   3 **     Version:             rev. 1.0, 2014-05-14
   4 **     Build:               b140515
   5 **
   6 **     Abstract:
   7 **         Chip specific module features.
   8 **
   9 **     Copyright: 2014 Freescale Semiconductor, Inc.
  10 **     All rights reserved.
  11 **
  12 **     Redistribution and use in source and binary forms, with or without modification,
  13 **     are permitted provided that the following conditions are met:
  14 **
  15 **     o Redistributions of source code must retain the above copyright notice, this list
  16 **       of conditions and the following disclaimer.
  17 **
  18 **     o Redistributions in binary form must reproduce the above copyright notice, this
  19 **       list of conditions and the following disclaimer in the documentation and/or
  20 **       other materials provided with the distribution.
  21 **
  22 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  23 **       contributors may be used to endorse or promote products derived from this
  24 **       software without specific prior written permission.
  25 **
  26 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  27 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  28 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  29 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  30 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  31 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  32 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  33 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  35 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36 **
  37 **     http:                 www.freescale.com
  38 **     mail:                 support@freescale.com
  39 **
  40 **     Revisions:
  41 **     - rev. 1.0 (2014-05-14)
  42 **         Customer release.
  43 **
  44 ** ###################################################################
  45 */
  46
  47 #if !defined(__FSL_SMC_FEATURES_H__)
  48 #define __FSL_SMC_FEATURES_H__
  49
  50 #if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \
  51     defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || \
  52     defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || \
  53     defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \
  54     defined(CPU_MK22FN512VLL12) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || \
  55     defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || defined(CPU_MKV31F128VLH10) || \
  56     defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || \
  57     defined(CPU_MKV31F512VLL12)
  58     /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
  59     #define FSL_FEATURE_SMC_HAS_PSTOPO (1)
  60     /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
  61     #define FSL_FEATURE_SMC_HAS_LPOPO (0)
  62     /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
  63     #define FSL_FEATURE_SMC_HAS_PORPO (1)
  64     /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
  65     #define FSL_FEATURE_SMC_HAS_LPWUI (0)
  66     /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
  67     #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1)
  68     /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
  69     #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0)
  70     /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
  71     #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0)
  72     /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
  73     #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
  74     /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
  75     #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1)
  76     /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
  77     #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
  78 #elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \
  79     defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \
  80     defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
  81     defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \
  82     defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \
  83     defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \
  84     defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \
  85     defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || \
  86     defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || \
  87     defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || \
  88     defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12)
  89     /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
  90     #define FSL_FEATURE_SMC_HAS_PSTOPO (0)
  91     /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
  92     #define FSL_FEATURE_SMC_HAS_LPOPO (0)
  93     /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
  94     #define FSL_FEATURE_SMC_HAS_PORPO (1)
  95     /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
  96     #define FSL_FEATURE_SMC_HAS_LPWUI (1)
  97     /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
  98     #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0)
  99     /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
 100     #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (1)
 101     /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
 102     #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0)
 103     /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
 104     #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
 105     /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
 106     #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0)
 107     /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
 108     #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
 109 #elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \
 110     defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18)
 111     /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
 112     #define FSL_FEATURE_SMC_HAS_PSTOPO (1)
 113     /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
 114     #define FSL_FEATURE_SMC_HAS_LPOPO (0)
 115     /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
 116     #define FSL_FEATURE_SMC_HAS_PORPO (1)
 117     /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
 118     #define FSL_FEATURE_SMC_HAS_LPWUI (0)
 119     /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
 120     #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1)
 121     /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
 122     #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0)
 123     /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
 124     #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0)
 125     /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
 126     #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (1)
 127     /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
 128     #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1)
 129     /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
 130     #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
 131 #elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \
 132     defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)
 133     /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
 134     #define FSL_FEATURE_SMC_HAS_PSTOPO (0)
 135     /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
 136     #define FSL_FEATURE_SMC_HAS_LPOPO (0)
 137     /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
 138     #define FSL_FEATURE_SMC_HAS_PORPO (0)
 139     /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
 140     #define FSL_FEATURE_SMC_HAS_LPWUI (1)
 141     /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
 142     #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0)
 143     /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
 144     #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (1)
 145     /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
 146     #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0)
 147     /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
 148     #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
 149     /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
 150     #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0)
 151     /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
 152     #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
 153 #elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \
 154     defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4)
 155     /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
 156     #define FSL_FEATURE_SMC_HAS_PSTOPO (1)
 157     /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
 158     #define FSL_FEATURE_SMC_HAS_LPOPO (1)
 159     /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
 160     #define FSL_FEATURE_SMC_HAS_PORPO (1)
 161     /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
 162     #define FSL_FEATURE_SMC_HAS_LPWUI (0)
 163     /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
 164     #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0)
 165     /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
 166     #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0)
 167     /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
 168     #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (1)
 169     /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
 170     #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
 171     /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
 172     #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0)
 173     /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
 174     #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (0)
 175 #elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \
 176     defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \
 177     defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL13Z64VFM4) || \
 178     defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || \
 179     defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || \
 180     defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || defined(CPU_MKL23Z64VFM4) || \
 181     defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || \
 182     defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || \
 183     defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || defined(CPU_MKL25Z32VFM4) || \
 184     defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || \
 185     defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \
 186     defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL26Z256VLK4) || \
 187     defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || \
 188     defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \
 189     defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \
 190     defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || \
 191     defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4)
 192     /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
 193     #define FSL_FEATURE_SMC_HAS_PSTOPO (1)
 194     /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
 195     #define FSL_FEATURE_SMC_HAS_LPOPO (0)
 196     /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
 197     #define FSL_FEATURE_SMC_HAS_PORPO (1)
 198     /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
 199     #define FSL_FEATURE_SMC_HAS_LPWUI (0)
 200     /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
 201     #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0)
 202     /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
 203     #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0)
 204     /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
 205     #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (1)
 206     /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
 207     #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
 208     /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
 209     #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0)
 210     /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
 211     #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
 212 #elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || \
 213     defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || \
 214     defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || \
 215     defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || \
 216     defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15)
 217     /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
 218     #define FSL_FEATURE_SMC_HAS_PSTOPO (1)
 219     /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
 220     #define FSL_FEATURE_SMC_HAS_LPOPO (1)
 221     /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
 222     #define FSL_FEATURE_SMC_HAS_PORPO (1)
 223     /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
 224     #define FSL_FEATURE_SMC_HAS_LPWUI (0)
 225     /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
 226     #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0)
 227     /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
 228     #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0)
 229     /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
 230     #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (1)
 231     /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
 232     #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
 233     /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
 234     #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1)
 235     /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
 236     #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (0)
 237 #else
 238     #error "No valid CPU defined!"
 239 #endif
 240
 241 #endif /* __FSL_SMC_FEATURES_H__ */
 242
 243 /*******************************************************************************
 244  * EOF
 245  ******************************************************************************/