tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/fsl_bitaccess.h

   1 /*
   2 ** ###################################################################
   3 **     Version:             rev. 2.5, 2014-02-10
   4 **     Build:               b140604
   5 **
   6 **     Abstract:
   7 **         Register bit field access macros.
   8 **
   9 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  10 **     All rights reserved.
  11 **
  12 **     Redistribution and use in source and binary forms, with or without modification,
  13 **     are permitted provided that the following conditions are met:
  14 **
  15 **     o Redistributions of source code must retain the above copyright notice, this list
  16 **       of conditions and the following disclaimer.
  17 **
  18 **     o Redistributions in binary form must reproduce the above copyright notice, this
  19 **       list of conditions and the following disclaimer in the documentation and/or
  20 **       other materials provided with the distribution.
  21 **
  22 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  23 **       contributors may be used to endorse or promote products derived from this
  24 **       software without specific prior written permission.
  25 **
  26 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  27 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  28 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  29 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  30 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  31 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  32 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  33 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  35 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36 **
  37 **     http:                 www.freescale.com
  38 **     mail:                 support@freescale.com
  39 **
  40 **     Revisions:
  41 **     - rev. 1.0 (2013-08-12)
  42 **         Initial version.
  43 **     - rev. 2.0 (2013-10-29)
  44 **         Register accessor macros added to the memory map.
  45 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  46 **         Startup file for gcc has been updated according to CMSIS 3.2.
  47 **         System initialization updated.
  48 **         MCG - registers updated.
  49 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
  50 **     - rev. 2.1 (2013-10-30)
  51 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  52 **     - rev. 2.2 (2013-12-09)
  53 **         DMA - EARS register removed.
  54 **         AIPS0, AIPS1 - MPRA register updated.
  55 **     - rev. 2.3 (2014-01-24)
  56 **         Update according to reference manual rev. 2
  57 **         ENET, MCG, MCM, SIM, USB - registers updated
  58 **     - rev. 2.4 (2014-02-10)
  59 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  60 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  61 **     - rev. 2.5 (2014-02-10)
  62 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  63 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  64 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  65 **
  66 ** ###################################################################
  67 */
  68
  69
  70 #ifndef _FSL_BITACCESS_H
  71 #define _FSL_BITACCESS_H  1
  72
  73 #include <stdint.h>
  74 #include <stdlib.h>
  75
  76 /**
  77  * @brief Macro to access a single bit of a 32-bit peripheral register (bit band region
  78  *        0x40000000 to 0x400FFFFF) using the bit-band alias region access.
  79  * @param Reg Register to access.
  80  * @param Bit Bit number to access.
  81  * @return Value of the targeted bit in the bit band region.
  82  */
  83 #define BITBAND_ACCESS32(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
  84
  85 /**
  86  * @brief Macro to access a single bit of a 16-bit peripheral register (bit band region
  87  *        0x40000000 to 0x400FFFFF) using the bit-band alias region access.
  88  * @param Reg Register to access.
  89  * @param Bit Bit number to access.
  90  * @return Value of the targeted bit in the bit band region.
  91  */
  92 #define BITBAND_ACCESS16(Reg,Bit) (*((uint16_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
  93
  94 /**
  95  * @brief Macro to access a single bit of an 8-bit peripheral register (bit band region
  96  *        0x40000000 to 0x400FFFFF) using the bit-band alias region access.
  97  * @param Reg Register to access.
  98  * @param Bit Bit number to access.
  99  * @return Value of the targeted bit in the bit band region.
 100  */
 101 #define BITBAND_ACCESS8(Reg,Bit) (*((uint8_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
 102
 103 /*
 104  * Macros for single instance registers
 105  */
 106
 107 #define BF_SET(reg, field)       HW_##reg##_SET(BM_##reg##_##field)
 108 #define BF_CLR(reg, field)       HW_##reg##_CLR(BM_##reg##_##field)
 109 #define BF_TOG(reg, field)       HW_##reg##_TOG(BM_##reg##_##field)
 110
 111 #define BF_SETV(reg, field, v)   HW_##reg##_SET(BF_##reg##_##field(v))
 112 #define BF_CLRV(reg, field, v)   HW_##reg##_CLR(BF_##reg##_##field(v))
 113 #define BF_TOGV(reg, field, v)   HW_##reg##_TOG(BF_##reg##_##field(v))
 114
 115 #define BV_FLD(reg, field, sym)  BF_##reg##_##field(BV_##reg##_##field##__##sym)
 116 #define BV_VAL(reg, field, sym)  BV_##reg##_##field##__##sym
 117
 118 #define BF_RD(reg, field)        HW_##reg.B.field
 119 #define BF_WR(reg, field, v)     BW_##reg##_##field(v)
 120
 121 #define BF_CS1(reg, f1, v1)  \
 122         (HW_##reg##_CLR(BM_##reg##_##f1),      \
 123          HW_##reg##_SET(BF_##reg##_##f1(v1)))
 124
 125 #define BF_CS2(reg, f1, v1, f2, v2)  \
 126         (HW_##reg##_CLR(BM_##reg##_##f1 |      \
 127                         BM_##reg##_##f2),      \
 128          HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
 129                         BF_##reg##_##f2(v2)))
 130
 131 #define BF_CS3(reg, f1, v1, f2, v2, f3, v3)  \
 132         (HW_##reg##_CLR(BM_##reg##_##f1 |      \
 133                         BM_##reg##_##f2 |      \
 134                         BM_##reg##_##f3),      \
 135          HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
 136                         BF_##reg##_##f2(v2) |  \
 137                         BF_##reg##_##f3(v3)))
 138
 139 #define BF_CS4(reg, f1, v1, f2, v2, f3, v3, f4, v4)  \
 140         (HW_##reg##_CLR(BM_##reg##_##f1 |      \
 141                         BM_##reg##_##f2 |      \
 142                         BM_##reg##_##f3 |      \
 143                         BM_##reg##_##f4),      \
 144          HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
 145                         BF_##reg##_##f2(v2) |  \
 146                         BF_##reg##_##f3(v3) |  \
 147                         BF_##reg##_##f4(v4)))
 148
 149 #define BF_CS5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5)  \
 150         (HW_##reg##_CLR(BM_##reg##_##f1 |      \
 151                         BM_##reg##_##f2 |      \
 152                         BM_##reg##_##f3 |      \
 153                         BM_##reg##_##f4 |      \
 154                         BM_##reg##_##f5),      \
 155          HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
 156                         BF_##reg##_##f2(v2) |  \
 157                         BF_##reg##_##f3(v3) |  \
 158                         BF_##reg##_##f4(v4) |  \
 159                         BF_##reg##_##f5(v5)))
 160
 161 #define BF_CS6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6)  \
 162         (HW_##reg##_CLR(BM_##reg##_##f1 |      \
 163                         BM_##reg##_##f2 |      \
 164                         BM_##reg##_##f3 |      \
 165                         BM_##reg##_##f4 |      \
 166                         BM_##reg##_##f5 |      \
 167                         BM_##reg##_##f6),      \
 168          HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
 169                         BF_##reg##_##f2(v2) |  \
 170                         BF_##reg##_##f3(v3) |  \
 171                         BF_##reg##_##f4(v4) |  \
 172                         BF_##reg##_##f5(v5) |  \
 173                         BF_##reg##_##f6(v6)))
 174
 175 #define BF_CS7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7)  \
 176         (HW_##reg##_CLR(BM_##reg##_##f1 |      \
 177                         BM_##reg##_##f2 |      \
 178                         BM_##reg##_##f3 |      \
 179                         BM_##reg##_##f4 |      \
 180                         BM_##reg##_##f5 |      \
 181                         BM_##reg##_##f6 |      \
 182                         BM_##reg##_##f7),      \
 183          HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
 184                         BF_##reg##_##f2(v2) |  \
 185                         BF_##reg##_##f3(v3) |  \
 186                         BF_##reg##_##f4(v4) |  \
 187                         BF_##reg##_##f5(v5) |  \
 188                         BF_##reg##_##f6(v6) |  \
 189                         BF_##reg##_##f7(v7)))
 190
 191 #define BF_CS8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8)  \
 192         (HW_##reg##_CLR(BM_##reg##_##f1 |      \
 193                         BM_##reg##_##f2 |      \
 194                         BM_##reg##_##f3 |      \
 195                         BM_##reg##_##f4 |      \
 196                         BM_##reg##_##f5 |      \
 197                         BM_##reg##_##f6 |      \
 198                         BM_##reg##_##f7 |      \
 199                         BM_##reg##_##f8),      \
 200          HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
 201                         BF_##reg##_##f2(v2) |  \
 202                         BF_##reg##_##f3(v3) |  \
 203                         BF_##reg##_##f4(v4) |  \
 204                         BF_##reg##_##f5(v5) |  \
 205                         BF_##reg##_##f6(v6) |  \
 206                         BF_##reg##_##f7(v7) |  \
 207                         BF_##reg##_##f8(v8)))
 208
 209 /*
 210  * Macros for multiple instance registers
 211  */
 212
 213 #define BF_SETn(reg, n, field)       HW_##reg##_SET(n, BM_##reg##_##field)
 214 #define BF_CLRn(reg, n, field)       HW_##reg##_CLR(n, BM_##reg##_##field)
 215 #define BF_TOGn(reg, n, field)       HW_##reg##_TOG(n, BM_##reg##_##field)
 216
 217 #define BF_SETVn(reg, n, field, v)   HW_##reg##_SET(n, BF_##reg##_##field(v))
 218 #define BF_CLRVn(reg, n, field, v)   HW_##reg##_CLR(n, BF_##reg##_##field(v))
 219 #define BF_TOGVn(reg, n, field, v)   HW_##reg##_TOG(n, BF_##reg##_##field(v))
 220
 221 #define BV_FLDn(reg, n, field, sym)  BF_##reg##_##field(BV_##reg##_##field##__##sym)
 222 #define BV_VALn(reg, n, field, sym)  BV_##reg##_##field##__##sym
 223
 224 #define BF_RDn(reg, n, field)        HW_##reg(n).B.field
 225 #define BF_WRn(reg, n, field, v)     BW_##reg##_##field(n, v)
 226
 227 #define BF_CS1n(reg, n, f1, v1)  \
 228         (HW_##reg##_CLR(n, (BM_##reg##_##f1)),      \
 229          HW_##reg##_SET(n, (BF_##reg##_##f1(v1))))
 230
 231 #define BF_CS2n(reg, n, f1, v1, f2, v2)  \
 232         (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
 233                             BM_##reg##_##f2)),      \
 234          HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
 235                             BF_##reg##_##f2(v2))))
 236
 237 #define BF_CS3n(reg, n, f1, v1, f2, v2, f3, v3)  \
 238         (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
 239                             BM_##reg##_##f2 |       \
 240                             BM_##reg##_##f3)),      \
 241          HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
 242                             BF_##reg##_##f2(v2) |   \
 243                             BF_##reg##_##f3(v3))))
 244
 245 #define BF_CS4n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4)  \
 246         (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
 247                             BM_##reg##_##f2 |       \
 248                             BM_##reg##_##f3 |       \
 249                             BM_##reg##_##f4)),      \
 250          HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
 251                             BF_##reg##_##f2(v2) |   \
 252                             BF_##reg##_##f3(v3) |   \
 253                             BF_##reg##_##f4(v4))))
 254
 255 #define BF_CS5n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5)  \
 256         (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
 257                             BM_##reg##_##f2 |       \
 258                             BM_##reg##_##f3 |       \
 259                             BM_##reg##_##f4 |       \
 260                             BM_##reg##_##f5)),      \
 261          HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
 262                             BF_##reg##_##f2(v2) |   \
 263                             BF_##reg##_##f3(v3) |   \
 264                             BF_##reg##_##f4(v4) |   \
 265                             BF_##reg##_##f5(v5))))
 266
 267 #define BF_CS6n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6)  \
 268         (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
 269                             BM_##reg##_##f2 |       \
 270                             BM_##reg##_##f3 |       \
 271                             BM_##reg##_##f4 |       \
 272                             BM_##reg##_##f5 |       \
 273                             BM_##reg##_##f6)),      \
 274          HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
 275                             BF_##reg##_##f2(v2) |   \
 276                             BF_##reg##_##f3(v3) |   \
 277                             BF_##reg##_##f4(v4) |   \
 278                             BF_##reg##_##f5(v5) |   \
 279                             BF_##reg##_##f6(v6))))
 280
 281 #define BF_CS7n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7)  \
 282         (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
 283                             BM_##reg##_##f2 |       \
 284                             BM_##reg##_##f3 |       \
 285                             BM_##reg##_##f4 |       \
 286                             BM_##reg##_##f5 |       \
 287                             BM_##reg##_##f6 |       \
 288                             BM_##reg##_##f7)),      \
 289          HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
 290                             BF_##reg##_##f2(v2) |   \
 291                             BF_##reg##_##f3(v3) |   \
 292                             BF_##reg##_##f4(v4) |   \
 293                             BF_##reg##_##f5(v5) |   \
 294                             BF_##reg##_##f6(v6) |   \
 295                             BF_##reg##_##f7(v7))))
 296
 297 #define BF_CS8n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8)  \
 298         (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
 299                             BM_##reg##_##f2 |       \
 300                             BM_##reg##_##f3 |       \
 301                             BM_##reg##_##f4 |       \
 302                             BM_##reg##_##f5 |       \
 303                             BM_##reg##_##f6 |       \
 304                             BM_##reg##_##f7 |       \
 305                             BM_##reg##_##f8)),      \
 306          HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
 307                             BF_##reg##_##f2(v2) |   \
 308                             BF_##reg##_##f3(v3) |   \
 309                             BF_##reg##_##f4(v4) |   \
 310                             BF_##reg##_##f5(v5) |   \
 311                             BF_##reg##_##f6(v6) |   \
 312                             BF_##reg##_##f7(v7) |   \
 313                             BF_##reg##_##f8(v8))))
 314
 315 /*
 316  * Macros for single instance MULTI-BLOCK registers
 317  */
 318
 319 #define BFn_SET(reg, blk, field)       HW_##reg##_SET(blk, BM_##reg##_##field)
 320 #define BFn_CLR(reg, blk, field)       HW_##reg##_CLR(blk, BM_##reg##_##field)
 321 #define BFn_TOG(reg, blk, field)       HW_##reg##_TOG(blk, BM_##reg##_##field)
 322
 323 #define BFn_SETV(reg, blk, field, v)   HW_##reg##_SET(blk, BF_##reg##_##field(v))
 324 #define BFn_CLRV(reg, blk, field, v)   HW_##reg##_CLR(blk, BF_##reg##_##field(v))
 325 #define BFn_TOGV(reg, blk, field, v)   HW_##reg##_TOG(blk, BF_##reg##_##field(v))
 326
 327 #define BVn_FLD(reg, field, sym)  BF_##reg##_##field(BV_##reg##_##field##__##sym)
 328 #define BVn_VAL(reg, field, sym)  BV_##reg##_##field##__##sym
 329
 330 #define BFn_RD(reg, blk, field)        HW_##reg(blk).B.field
 331 #define BFn_WR(reg, blk, field, v)     BW_##reg##_##field(blk, v)
 332
 333 #define BFn_CS1(reg, blk, f1, v1)  \
 334         (HW_##reg##_CLR(blk, BM_##reg##_##f1),      \
 335          HW_##reg##_SET(blk, BF_##reg##_##f1(v1)))
 336
 337 #define BFn_CS2(reg, blk, f1, v1, f2, v2)  \
 338         (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
 339                         BM_##reg##_##f2),      \
 340          HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
 341                         BF_##reg##_##f2(v2)))
 342
 343 #define BFn_CS3(reg, blk, f1, v1, f2, v2, f3, v3)  \
 344         (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
 345                         BM_##reg##_##f2 |      \
 346                         BM_##reg##_##f3),      \
 347          HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
 348                         BF_##reg##_##f2(v2) |  \
 349                         BF_##reg##_##f3(v3)))
 350
 351 #define BFn_CS4(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4)  \
 352         (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
 353                         BM_##reg##_##f2 |      \
 354                         BM_##reg##_##f3 |      \
 355                         BM_##reg##_##f4),      \
 356          HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
 357                         BF_##reg##_##f2(v2) |  \
 358                         BF_##reg##_##f3(v3) |  \
 359                         BF_##reg##_##f4(v4)))
 360
 361 #define BFn_CS5(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5)  \
 362         (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
 363                         BM_##reg##_##f2 |      \
 364                         BM_##reg##_##f3 |      \
 365                         BM_##reg##_##f4 |      \
 366                         BM_##reg##_##f5),      \
 367          HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
 368                         BF_##reg##_##f2(v2) |  \
 369                         BF_##reg##_##f3(v3) |  \
 370                         BF_##reg##_##f4(v4) |  \
 371                         BF_##reg##_##f5(v5)))
 372
 373 #define BFn_CS6(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6)  \
 374         (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
 375                         BM_##reg##_##f2 |      \
 376                         BM_##reg##_##f3 |      \
 377                         BM_##reg##_##f4 |      \
 378                         BM_##reg##_##f5 |      \
 379                         BM_##reg##_##f6),      \
 380          HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
 381                         BF_##reg##_##f2(v2) |  \
 382                         BF_##reg##_##f3(v3) |  \
 383                         BF_##reg##_##f4(v4) |  \
 384                         BF_##reg##_##f5(v5) |  \
 385                         BF_##reg##_##f6(v6)))
 386
 387 #define BFn_CS7(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7)  \
 388         (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
 389                         BM_##reg##_##f2 |      \
 390                         BM_##reg##_##f3 |      \
 391                         BM_##reg##_##f4 |      \
 392                         BM_##reg##_##f5 |      \
 393                         BM_##reg##_##f6 |      \
 394                         BM_##reg##_##f7),      \
 395          HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
 396                         BF_##reg##_##f2(v2) |  \
 397                         BF_##reg##_##f3(v3) |  \
 398                         BF_##reg##_##f4(v4) |  \
 399                         BF_##reg##_##f5(v5) |  \
 400                         BF_##reg##_##f6(v6) |  \
 401                         BF_##reg##_##f7(v7)))
 402
 403 #define BFn_CS8(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8)  \
 404         (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
 405                         BM_##reg##_##f2 |      \
 406                         BM_##reg##_##f3 |      \
 407                         BM_##reg##_##f4 |      \
 408                         BM_##reg##_##f5 |      \
 409                         BM_##reg##_##f6 |      \
 410                         BM_##reg##_##f7 |      \
 411                         BM_##reg##_##f8),      \
 412          HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
 413                         BF_##reg##_##f2(v2) |  \
 414                         BF_##reg##_##f3(v3) |  \
 415                         BF_##reg##_##f4(v4) |  \
 416                         BF_##reg##_##f5(v5) |  \
 417                         BF_##reg##_##f6(v6) |  \
 418                         BF_##reg##_##f7(v7) |  \
 419                         BF_##reg##_##f8(v8)))
 420
 421 /*
 422  * Macros for MULTI-BLOCK multiple instance registers
 423  */
 424
 425 #define BFn_SETn(reg, blk, n, field)       HW_##reg##_SET(blk, n, BM_##reg##_##field)
 426 #define BFn_CLRn(reg, blk, n, field)       HW_##reg##_CLR(blk, n, BM_##reg##_##field)
 427 #define BFn_TOGn(reg, blk, n, field)       HW_##reg##_TOG(blk, n, BM_##reg##_##field)
 428
 429 #define BFn_SETVn(reg, blk, n, field, v)   HW_##reg##_SET(blk, n, BF_##reg##_##field(v))
 430 #define BFn_CLRVn(reg, blk, n, field, v)   HW_##reg##_CLR(blk, n, BF_##reg##_##field(v))
 431 #define BFn_TOGVn(reg, blk, n, field, v)   HW_##reg##_TOG(blk, n, BF_##reg##_##field(v))
 432
 433 #define BVn_FLDn(reg, blk, n, field, sym)  BF_##reg##_##field(BV_##reg##_##field##__##sym)
 434 #define BVn_VALn(reg, blk, n, field, sym)  BV_##reg##_##field##__##sym
 435
 436 #define BFn_RDn(reg, blk, n, field)        HW_##reg(n).B.field
 437 #define BFn_WRn(reg, blk, n, field, v)     BW_##reg##_##field(n, v)
 438
 439 #define BFn_CS1n(reg, blk, n, f1, v1)  \
 440         (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1)),      \
 441          HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1))))
 442
 443 #define BFn_CS2n(reg, blk, n, f1, v1, f2, v2)  \
 444         (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
 445                             BM_##reg##_##f2)),      \
 446          HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
 447                             BF_##reg##_##f2(v2))))
 448
 449 #define BFn_CS3n(reg, blk, n, f1, v1, f2, v2, f3, v3)  \
 450         (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
 451                             BM_##reg##_##f2 |       \
 452                             BM_##reg##_##f3)),      \
 453          HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
 454                             BF_##reg##_##f2(v2) |   \
 455                             BF_##reg##_##f3(v3))))
 456
 457 #define BFn_CS4n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4)  \
 458         (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
 459                             BM_##reg##_##f2 |       \
 460                             BM_##reg##_##f3 |       \
 461                             BM_##reg##_##f4)),      \
 462          HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
 463                             BF_##reg##_##f2(v2) |   \
 464                             BF_##reg##_##f3(v3) |   \
 465                             BF_##reg##_##f4(v4))))
 466
 467 #define BFn_CS5n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5)  \
 468         (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
 469                             BM_##reg##_##f2 |       \
 470                             BM_##reg##_##f3 |       \
 471                             BM_##reg##_##f4 |       \
 472                             BM_##reg##_##f5)),      \
 473          HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
 474                             BF_##reg##_##f2(v2) |   \
 475                             BF_##reg##_##f3(v3) |   \
 476                             BF_##reg##_##f4(v4) |   \
 477                             BF_##reg##_##f5(v5))))
 478
 479 #define BFn_CS6n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6)  \
 480         (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
 481                             BM_##reg##_##f2 |       \
 482                             BM_##reg##_##f3 |       \
 483                             BM_##reg##_##f4 |       \
 484                             BM_##reg##_##f5 |       \
 485                             BM_##reg##_##f6)),      \
 486          HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
 487                             BF_##reg##_##f2(v2) |   \
 488                             BF_##reg##_##f3(v3) |   \
 489                             BF_##reg##_##f4(v4) |   \
 490                             BF_##reg##_##f5(v5) |   \
 491                             BF_##reg##_##f6(v6))))
 492
 493 #define BFn_CS7n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7)  \
 494         (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
 495                             BM_##reg##_##f2 |       \
 496                             BM_##reg##_##f3 |       \
 497                             BM_##reg##_##f4 |       \
 498                             BM_##reg##_##f5 |       \
 499                             BM_##reg##_##f6 |       \
 500                             BM_##reg##_##f7)),      \
 501          HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
 502                             BF_##reg##_##f2(v2) |   \
 503                             BF_##reg##_##f3(v3) |   \
 504                             BF_##reg##_##f4(v4) |   \
 505                             BF_##reg##_##f5(v5) |   \
 506                             BF_##reg##_##f6(v6) |   \
 507                             BF_##reg##_##f7(v7))))
 508
 509 #define BFn_CS8n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8)  \
 510         (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
 511                             BM_##reg##_##f2 |       \
 512                             BM_##reg##_##f3 |       \
 513                             BM_##reg##_##f4 |       \
 514                             BM_##reg##_##f5 |       \
 515                             BM_##reg##_##f6 |       \
 516                             BM_##reg##_##f7 |       \
 517                             BM_##reg##_##f8)),      \
 518          HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
 519                             BF_##reg##_##f2(v2) |   \
 520                             BF_##reg##_##f3(v3) |   \
 521                             BF_##reg##_##f4(v4) |   \
 522                             BF_##reg##_##f5(v5) |   \
 523                             BF_##reg##_##f6(v6) |   \
 524                             BF_##reg##_##f7(v7) |   \
 525                             BF_##reg##_##f8(v8))))
 526
 527 #endif /* _FSL_BITACCESS_H */
 528
 529 /******************************************************************************/