]>
git.gir.st - tmk_keyboard.git/blob - tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_adc.h
2 ** ###################################################################
3 ** Compilers: Keil ARM C/C++ Compiler
4 ** Freescale C/C++ for Embedded ARM
6 ** IAR ANSI C/C++ Compiler for ARM
8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
9 ** Version: rev. 2.5, 2014-02-10
13 ** Extension to the CMSIS register access layer header.
15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
16 ** All rights reserved.
18 ** Redistribution and use in source and binary forms, with or without modification,
19 ** are permitted provided that the following conditions are met:
21 ** o Redistributions of source code must retain the above copyright notice, this list
22 ** of conditions and the following disclaimer.
24 ** o Redistributions in binary form must reproduce the above copyright notice, this
25 ** list of conditions and the following disclaimer in the documentation and/or
26 ** other materials provided with the distribution.
28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
29 ** contributors may be used to endorse or promote products derived from this
30 ** software without specific prior written permission.
32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ** http: www.freescale.com
44 ** mail: support@freescale.com
47 ** - rev. 1.0 (2013-08-12)
49 ** - rev. 2.0 (2013-10-29)
50 ** Register accessor macros added to the memory map.
51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
52 ** Startup file for gcc has been updated according to CMSIS 3.2.
53 ** System initialization updated.
54 ** MCG - registers updated.
55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
56 ** - rev. 2.1 (2013-10-30)
57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
58 ** - rev. 2.2 (2013-12-09)
59 ** DMA - EARS register removed.
60 ** AIPS0, AIPS1 - MPRA register updated.
61 ** - rev. 2.3 (2014-01-24)
62 ** Update according to reference manual rev. 2
63 ** ENET, MCG, MCM, SIM, USB - registers updated
64 ** - rev. 2.4 (2014-02-10)
65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
67 ** - rev. 2.5 (2014-02-10)
68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
72 ** ###################################################################
76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
78 * This file was generated automatically and any changes may be lost.
80 #ifndef __HW_ADC_REGISTERS_H__
81 #define __HW_ADC_REGISTERS_H__
84 #include "fsl_bitaccess.h"
89 * Analog-to-Digital Converter
91 * Registers defined in this header file:
92 * - HW_ADC_SC1n - ADC Status and Control Registers 1
93 * - HW_ADC_CFG1 - ADC Configuration Register 1
94 * - HW_ADC_CFG2 - ADC Configuration Register 2
95 * - HW_ADC_Rn - ADC Data Result Register
96 * - HW_ADC_CV1 - Compare Value Registers
97 * - HW_ADC_CV2 - Compare Value Registers
98 * - HW_ADC_SC2 - Status and Control Register 2
99 * - HW_ADC_SC3 - Status and Control Register 3
100 * - HW_ADC_OFS - ADC Offset Correction Register
101 * - HW_ADC_PG - ADC Plus-Side Gain Register
102 * - HW_ADC_MG - ADC Minus-Side Gain Register
103 * - HW_ADC_CLPD - ADC Plus-Side General Calibration Value Register
104 * - HW_ADC_CLPS - ADC Plus-Side General Calibration Value Register
105 * - HW_ADC_CLP4 - ADC Plus-Side General Calibration Value Register
106 * - HW_ADC_CLP3 - ADC Plus-Side General Calibration Value Register
107 * - HW_ADC_CLP2 - ADC Plus-Side General Calibration Value Register
108 * - HW_ADC_CLP1 - ADC Plus-Side General Calibration Value Register
109 * - HW_ADC_CLP0 - ADC Plus-Side General Calibration Value Register
110 * - HW_ADC_CLMD - ADC Minus-Side General Calibration Value Register
111 * - HW_ADC_CLMS - ADC Minus-Side General Calibration Value Register
112 * - HW_ADC_CLM4 - ADC Minus-Side General Calibration Value Register
113 * - HW_ADC_CLM3 - ADC Minus-Side General Calibration Value Register
114 * - HW_ADC_CLM2 - ADC Minus-Side General Calibration Value Register
115 * - HW_ADC_CLM1 - ADC Minus-Side General Calibration Value Register
116 * - HW_ADC_CLM0 - ADC Minus-Side General Calibration Value Register
118 * - hw_adc_t - Struct containing all module registers.
121 #define HW_ADC_INSTANCE_COUNT (2U) /*!< Number of instances of the ADC module. */
122 #define HW_ADC0 (0U) /*!< Instance number for ADC0. */
123 #define HW_ADC1 (1U) /*!< Instance number for ADC1. */
125 /*******************************************************************************
126 * HW_ADC_SC1n - ADC Status and Control Registers 1
127 ******************************************************************************/
130 * @brief HW_ADC_SC1n - ADC Status and Control Registers 1 (RW)
132 * Reset value: 0x0000001FU
134 * SC1A is used for both software and hardware trigger modes of operation. To
135 * allow sequential conversions of the ADC to be triggered by internal peripherals,
136 * the ADC can have more than one status and control register: one for each
137 * conversion. The SC1B-SC1n registers indicate potentially multiple SC1 registers
138 * for use only in hardware trigger mode. See the chip configuration information
139 * about the number of SC1n registers specific to this device. The SC1n registers
140 * have identical fields, and are used in a "ping-pong" approach to control ADC
141 * operation. At any one point in time, only one of the SC1n registers is actively
142 * controlling ADC conversions. Updating SC1A while SC1n is actively controlling
143 * a conversion is allowed, and vice-versa for any of the SC1n registers specific
144 * to this MCU. Writing SC1A while SC1A is actively controlling a conversion
145 * aborts the current conversion. In Software Trigger mode, when SC2[ADTRG]=0,
146 * writes to SC1A subsequently initiate a new conversion, if SC1[ADCH] contains a
147 * value other than all 1s. Writing any of the SC1n registers while that specific
148 * SC1n register is actively controlling a conversion aborts the current conversion.
149 * None of the SC1B-SC1n registers are used for software trigger operation and
150 * therefore writes to the SC1B-SC1n registers do not initiate a new conversion.
152 typedef union _hw_adc_sc1n
155 struct _hw_adc_sc1n_bitfields
157 uint32_t ADCH
: 5; /*!< [4:0] Input channel select */
158 uint32_t DIFF
: 1; /*!< [5] Differential Mode Enable */
159 uint32_t AIEN
: 1; /*!< [6] Interrupt Enable */
160 uint32_t COCO
: 1; /*!< [7] Conversion Complete Flag */
161 uint32_t RESERVED0
: 24; /*!< [31:8] */
166 * @name Constants and macros for entire ADC_SC1n register
169 #define HW_ADC_SC1n_COUNT (2U)
171 #define HW_ADC_SC1n_ADDR(x, n) ((x) + 0x0U + (0x4U * (n)))
173 #define HW_ADC_SC1n(x, n) (*(__IO hw_adc_sc1n_t *) HW_ADC_SC1n_ADDR(x, n))
174 #define HW_ADC_SC1n_RD(x, n) (HW_ADC_SC1n(x, n).U)
175 #define HW_ADC_SC1n_WR(x, n, v) (HW_ADC_SC1n(x, n).U = (v))
176 #define HW_ADC_SC1n_SET(x, n, v) (HW_ADC_SC1n_WR(x, n, HW_ADC_SC1n_RD(x, n) | (v)))
177 #define HW_ADC_SC1n_CLR(x, n, v) (HW_ADC_SC1n_WR(x, n, HW_ADC_SC1n_RD(x, n) & ~(v)))
178 #define HW_ADC_SC1n_TOG(x, n, v) (HW_ADC_SC1n_WR(x, n, HW_ADC_SC1n_RD(x, n) ^ (v)))
182 * Constants & macros for individual ADC_SC1n bitfields
186 * @name Register ADC_SC1n, field ADCH[4:0] (RW)
188 * Selects one of the input channels. The input channel decode depends on the
189 * value of DIFF. DAD0-DAD3 are associated with the input pin pairs DADPx and
190 * DADMx. Some of the input channel options in the bitfield-setting descriptions might
191 * not be available for your device. For the actual ADC channel assignments for
192 * your device, see the Chip Configuration details. The successive approximation
193 * converter subsystem is turned off when the channel select bits are all set,
194 * that is, ADCH = 11111. This feature allows explicit disabling of the ADC and
195 * isolation of the input channel from all sources. Terminating continuous
196 * conversions this way prevents an additional single conversion from being performed. It
197 * is not necessary to set ADCH to all 1s to place the ADC in a low-power state
198 * when continuous conversions are not enabled because the module automatically
199 * enters a low-power state when a conversion completes.
202 * - 00000 - When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is
204 * - 00001 - When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is
206 * - 00010 - When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is
208 * - 00011 - When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is
210 * - 00100 - When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
211 * - 00101 - When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
212 * - 00110 - When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
213 * - 00111 - When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
214 * - 01000 - When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
215 * - 01001 - When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
216 * - 01010 - When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
217 * - 01011 - When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
218 * - 01100 - When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
219 * - 01101 - When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
220 * - 01110 - When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
221 * - 01111 - When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
222 * - 10000 - When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
223 * - 10001 - When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
224 * - 10010 - When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
225 * - 10011 - When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
226 * - 10100 - When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
227 * - 10101 - When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
228 * - 10110 - When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
229 * - 10111 - When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
230 * - 11000 - Reserved.
231 * - 11001 - Reserved.
232 * - 11010 - When DIFF=0, Temp Sensor (single-ended) is selected as input; when
233 * DIFF=1, Temp Sensor (differential) is selected as input.
234 * - 11011 - When DIFF=0, Bandgap (single-ended) is selected as input; when
235 * DIFF=1, Bandgap (differential) is selected as input.
236 * - 11100 - Reserved.
237 * - 11101 - When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH
238 * (differential) is selected as input. Voltage reference selected is determined
240 * - 11110 - When DIFF=0,VREFSL is selected as input; when DIFF=1, it is
241 * reserved. Voltage reference selected is determined by SC2[REFSEL].
242 * - 11111 - Module is disabled.
245 #define BP_ADC_SC1n_ADCH (0U) /*!< Bit position for ADC_SC1n_ADCH. */
246 #define BM_ADC_SC1n_ADCH (0x0000001FU) /*!< Bit mask for ADC_SC1n_ADCH. */
247 #define BS_ADC_SC1n_ADCH (5U) /*!< Bit field size in bits for ADC_SC1n_ADCH. */
249 /*! @brief Read current value of the ADC_SC1n_ADCH field. */
250 #define BR_ADC_SC1n_ADCH(x, n) (HW_ADC_SC1n(x, n).B.ADCH)
252 /*! @brief Format value for bitfield ADC_SC1n_ADCH. */
253 #define BF_ADC_SC1n_ADCH(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC1n_ADCH) & BM_ADC_SC1n_ADCH)
255 /*! @brief Set the ADCH field to a new value. */
256 #define BW_ADC_SC1n_ADCH(x, n, v) (HW_ADC_SC1n_WR(x, n, (HW_ADC_SC1n_RD(x, n) & ~BM_ADC_SC1n_ADCH) | BF_ADC_SC1n_ADCH(v)))
260 * @name Register ADC_SC1n, field DIFF[5] (RW)
262 * Configures the ADC to operate in differential mode. When enabled, this mode
263 * automatically selects from the differential channels, and changes the
264 * conversion algorithm and the number of cycles to complete a conversion.
267 * - 0 - Single-ended conversions and input channels are selected.
268 * - 1 - Differential conversions and input channels are selected.
271 #define BP_ADC_SC1n_DIFF (5U) /*!< Bit position for ADC_SC1n_DIFF. */
272 #define BM_ADC_SC1n_DIFF (0x00000020U) /*!< Bit mask for ADC_SC1n_DIFF. */
273 #define BS_ADC_SC1n_DIFF (1U) /*!< Bit field size in bits for ADC_SC1n_DIFF. */
275 /*! @brief Read current value of the ADC_SC1n_DIFF field. */
276 #define BR_ADC_SC1n_DIFF(x, n) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_DIFF))
278 /*! @brief Format value for bitfield ADC_SC1n_DIFF. */
279 #define BF_ADC_SC1n_DIFF(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC1n_DIFF) & BM_ADC_SC1n_DIFF)
281 /*! @brief Set the DIFF field to a new value. */
282 #define BW_ADC_SC1n_DIFF(x, n, v) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_DIFF) = (v))
286 * @name Register ADC_SC1n, field AIEN[6] (RW)
288 * Enables conversion complete interrupts. When COCO becomes set while the
289 * respective AIEN is high, an interrupt is asserted.
292 * - 0 - Conversion complete interrupt is disabled.
293 * - 1 - Conversion complete interrupt is enabled.
296 #define BP_ADC_SC1n_AIEN (6U) /*!< Bit position for ADC_SC1n_AIEN. */
297 #define BM_ADC_SC1n_AIEN (0x00000040U) /*!< Bit mask for ADC_SC1n_AIEN. */
298 #define BS_ADC_SC1n_AIEN (1U) /*!< Bit field size in bits for ADC_SC1n_AIEN. */
300 /*! @brief Read current value of the ADC_SC1n_AIEN field. */
301 #define BR_ADC_SC1n_AIEN(x, n) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_AIEN))
303 /*! @brief Format value for bitfield ADC_SC1n_AIEN. */
304 #define BF_ADC_SC1n_AIEN(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC1n_AIEN) & BM_ADC_SC1n_AIEN)
306 /*! @brief Set the AIEN field to a new value. */
307 #define BW_ADC_SC1n_AIEN(x, n, v) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_AIEN) = (v))
311 * @name Register ADC_SC1n, field COCO[7] (RO)
313 * This is a read-only field that is set each time a conversion is completed
314 * when the compare function is disabled, or SC2[ACFE]=0 and the hardware average
315 * function is disabled, or SC3[AVGE]=0. When the compare function is enabled, or
316 * SC2[ACFE]=1, COCO is set upon completion of a conversion only if the compare
317 * result is true. When the hardware average function is enabled, or SC3[AVGE]=1,
318 * COCO is set upon completion of the selected number of conversions (determined
319 * by AVGS). COCO in SC1A is also set at the completion of a calibration sequence.
320 * COCO is cleared when the respective SC1n register is written or when the
321 * respective Rn register is read.
324 * - 0 - Conversion is not completed.
325 * - 1 - Conversion is completed.
328 #define BP_ADC_SC1n_COCO (7U) /*!< Bit position for ADC_SC1n_COCO. */
329 #define BM_ADC_SC1n_COCO (0x00000080U) /*!< Bit mask for ADC_SC1n_COCO. */
330 #define BS_ADC_SC1n_COCO (1U) /*!< Bit field size in bits for ADC_SC1n_COCO. */
332 /*! @brief Read current value of the ADC_SC1n_COCO field. */
333 #define BR_ADC_SC1n_COCO(x, n) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_COCO))
336 /*******************************************************************************
337 * HW_ADC_CFG1 - ADC Configuration Register 1
338 ******************************************************************************/
341 * @brief HW_ADC_CFG1 - ADC Configuration Register 1 (RW)
343 * Reset value: 0x00000000U
345 * The configuration Register 1 (CFG1) selects the mode of operation, clock
346 * source, clock divide, and configuration for low power or long sample time.
348 typedef union _hw_adc_cfg1
351 struct _hw_adc_cfg1_bitfields
353 uint32_t ADICLK
: 2; /*!< [1:0] Input Clock Select */
354 uint32_t MODE
: 2; /*!< [3:2] Conversion mode selection */
355 uint32_t ADLSMP
: 1; /*!< [4] Sample Time Configuration */
356 uint32_t ADIV
: 2; /*!< [6:5] Clock Divide Select */
357 uint32_t ADLPC
: 1; /*!< [7] Low-Power Configuration */
358 uint32_t RESERVED0
: 24; /*!< [31:8] */
363 * @name Constants and macros for entire ADC_CFG1 register
366 #define HW_ADC_CFG1_ADDR(x) ((x) + 0x8U)
368 #define HW_ADC_CFG1(x) (*(__IO hw_adc_cfg1_t *) HW_ADC_CFG1_ADDR(x))
369 #define HW_ADC_CFG1_RD(x) (HW_ADC_CFG1(x).U)
370 #define HW_ADC_CFG1_WR(x, v) (HW_ADC_CFG1(x).U = (v))
371 #define HW_ADC_CFG1_SET(x, v) (HW_ADC_CFG1_WR(x, HW_ADC_CFG1_RD(x) | (v)))
372 #define HW_ADC_CFG1_CLR(x, v) (HW_ADC_CFG1_WR(x, HW_ADC_CFG1_RD(x) & ~(v)))
373 #define HW_ADC_CFG1_TOG(x, v) (HW_ADC_CFG1_WR(x, HW_ADC_CFG1_RD(x) ^ (v)))
377 * Constants & macros for individual ADC_CFG1 bitfields
381 * @name Register ADC_CFG1, field ADICLK[1:0] (RW)
383 * Selects the input clock source to generate the internal clock, ADCK. Note
384 * that when the ADACK clock source is selected, it is not required to be active
385 * prior to conversion start. When it is selected and it is not active prior to a
386 * conversion start, when CFG2[ADACKEN]=0, the asynchronous clock is activated at
387 * the start of a conversion and deactivated when conversions are terminated. In
388 * this case, there is an associated clock startup delay each time the clock
389 * source is re-activated.
393 * - 01 - Alternate clock 2 (ALTCLK2)
394 * - 10 - Alternate clock (ALTCLK)
395 * - 11 - Asynchronous clock (ADACK)
398 #define BP_ADC_CFG1_ADICLK (0U) /*!< Bit position for ADC_CFG1_ADICLK. */
399 #define BM_ADC_CFG1_ADICLK (0x00000003U) /*!< Bit mask for ADC_CFG1_ADICLK. */
400 #define BS_ADC_CFG1_ADICLK (2U) /*!< Bit field size in bits for ADC_CFG1_ADICLK. */
402 /*! @brief Read current value of the ADC_CFG1_ADICLK field. */
403 #define BR_ADC_CFG1_ADICLK(x) (HW_ADC_CFG1(x).B.ADICLK)
405 /*! @brief Format value for bitfield ADC_CFG1_ADICLK. */
406 #define BF_ADC_CFG1_ADICLK(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG1_ADICLK) & BM_ADC_CFG1_ADICLK)
408 /*! @brief Set the ADICLK field to a new value. */
409 #define BW_ADC_CFG1_ADICLK(x, v) (HW_ADC_CFG1_WR(x, (HW_ADC_CFG1_RD(x) & ~BM_ADC_CFG1_ADICLK) | BF_ADC_CFG1_ADICLK(v)))
413 * @name Register ADC_CFG1, field MODE[3:2] (RW)
415 * Selects the ADC resolution mode.
418 * - 00 - When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is
419 * differential 9-bit conversion with 2's complement output.
420 * - 01 - When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is
421 * differential 13-bit conversion with 2's complement output.
422 * - 10 - When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is
423 * differential 11-bit conversion with 2's complement output
424 * - 11 - When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is
425 * differential 16-bit conversion with 2's complement output
428 #define BP_ADC_CFG1_MODE (2U) /*!< Bit position for ADC_CFG1_MODE. */
429 #define BM_ADC_CFG1_MODE (0x0000000CU) /*!< Bit mask for ADC_CFG1_MODE. */
430 #define BS_ADC_CFG1_MODE (2U) /*!< Bit field size in bits for ADC_CFG1_MODE. */
432 /*! @brief Read current value of the ADC_CFG1_MODE field. */
433 #define BR_ADC_CFG1_MODE(x) (HW_ADC_CFG1(x).B.MODE)
435 /*! @brief Format value for bitfield ADC_CFG1_MODE. */
436 #define BF_ADC_CFG1_MODE(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG1_MODE) & BM_ADC_CFG1_MODE)
438 /*! @brief Set the MODE field to a new value. */
439 #define BW_ADC_CFG1_MODE(x, v) (HW_ADC_CFG1_WR(x, (HW_ADC_CFG1_RD(x) & ~BM_ADC_CFG1_MODE) | BF_ADC_CFG1_MODE(v)))
443 * @name Register ADC_CFG1, field ADLSMP[4] (RW)
445 * Selects between different sample times based on the conversion mode selected.
446 * This field adjusts the sample period to allow higher impedance inputs to be
447 * accurately sampled or to maximize conversion speed for lower impedance inputs.
448 * Longer sample times can also be used to lower overall power consumption if
449 * continuous conversions are enabled and high conversion rates are not required.
450 * When ADLSMP=1, the long sample time select bits, (ADLSTS[1:0]), can select the
451 * extent of the long sample time.
454 * - 0 - Short sample time.
455 * - 1 - Long sample time.
458 #define BP_ADC_CFG1_ADLSMP (4U) /*!< Bit position for ADC_CFG1_ADLSMP. */
459 #define BM_ADC_CFG1_ADLSMP (0x00000010U) /*!< Bit mask for ADC_CFG1_ADLSMP. */
460 #define BS_ADC_CFG1_ADLSMP (1U) /*!< Bit field size in bits for ADC_CFG1_ADLSMP. */
462 /*! @brief Read current value of the ADC_CFG1_ADLSMP field. */
463 #define BR_ADC_CFG1_ADLSMP(x) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLSMP))
465 /*! @brief Format value for bitfield ADC_CFG1_ADLSMP. */
466 #define BF_ADC_CFG1_ADLSMP(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG1_ADLSMP) & BM_ADC_CFG1_ADLSMP)
468 /*! @brief Set the ADLSMP field to a new value. */
469 #define BW_ADC_CFG1_ADLSMP(x, v) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLSMP) = (v))
473 * @name Register ADC_CFG1, field ADIV[6:5] (RW)
475 * Selects the divide ratio used by the ADC to generate the internal clock ADCK.
478 * - 00 - The divide ratio is 1 and the clock rate is input clock.
479 * - 01 - The divide ratio is 2 and the clock rate is (input clock)/2.
480 * - 10 - The divide ratio is 4 and the clock rate is (input clock)/4.
481 * - 11 - The divide ratio is 8 and the clock rate is (input clock)/8.
484 #define BP_ADC_CFG1_ADIV (5U) /*!< Bit position for ADC_CFG1_ADIV. */
485 #define BM_ADC_CFG1_ADIV (0x00000060U) /*!< Bit mask for ADC_CFG1_ADIV. */
486 #define BS_ADC_CFG1_ADIV (2U) /*!< Bit field size in bits for ADC_CFG1_ADIV. */
488 /*! @brief Read current value of the ADC_CFG1_ADIV field. */
489 #define BR_ADC_CFG1_ADIV(x) (HW_ADC_CFG1(x).B.ADIV)
491 /*! @brief Format value for bitfield ADC_CFG1_ADIV. */
492 #define BF_ADC_CFG1_ADIV(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG1_ADIV) & BM_ADC_CFG1_ADIV)
494 /*! @brief Set the ADIV field to a new value. */
495 #define BW_ADC_CFG1_ADIV(x, v) (HW_ADC_CFG1_WR(x, (HW_ADC_CFG1_RD(x) & ~BM_ADC_CFG1_ADIV) | BF_ADC_CFG1_ADIV(v)))
499 * @name Register ADC_CFG1, field ADLPC[7] (RW)
501 * Controls the power configuration of the successive approximation converter.
502 * This optimizes power consumption when higher sample rates are not required.
505 * - 0 - Normal power configuration.
506 * - 1 - Low-power configuration. The power is reduced at the expense of maximum
510 #define BP_ADC_CFG1_ADLPC (7U) /*!< Bit position for ADC_CFG1_ADLPC. */
511 #define BM_ADC_CFG1_ADLPC (0x00000080U) /*!< Bit mask for ADC_CFG1_ADLPC. */
512 #define BS_ADC_CFG1_ADLPC (1U) /*!< Bit field size in bits for ADC_CFG1_ADLPC. */
514 /*! @brief Read current value of the ADC_CFG1_ADLPC field. */
515 #define BR_ADC_CFG1_ADLPC(x) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLPC))
517 /*! @brief Format value for bitfield ADC_CFG1_ADLPC. */
518 #define BF_ADC_CFG1_ADLPC(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG1_ADLPC) & BM_ADC_CFG1_ADLPC)
520 /*! @brief Set the ADLPC field to a new value. */
521 #define BW_ADC_CFG1_ADLPC(x, v) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLPC) = (v))
524 /*******************************************************************************
525 * HW_ADC_CFG2 - ADC Configuration Register 2
526 ******************************************************************************/
529 * @brief HW_ADC_CFG2 - ADC Configuration Register 2 (RW)
531 * Reset value: 0x00000000U
533 * Configuration Register 2 (CFG2) selects the special high-speed configuration
534 * for very high speed conversions and selects the long sample time duration
535 * during long sample mode.
537 typedef union _hw_adc_cfg2
540 struct _hw_adc_cfg2_bitfields
542 uint32_t ADLSTS
: 2; /*!< [1:0] Long Sample Time Select */
543 uint32_t ADHSC
: 1; /*!< [2] High-Speed Configuration */
544 uint32_t ADACKEN
: 1; /*!< [3] Asynchronous Clock Output Enable */
545 uint32_t MUXSEL
: 1; /*!< [4] ADC Mux Select */
546 uint32_t RESERVED0
: 27; /*!< [31:5] */
551 * @name Constants and macros for entire ADC_CFG2 register
554 #define HW_ADC_CFG2_ADDR(x) ((x) + 0xCU)
556 #define HW_ADC_CFG2(x) (*(__IO hw_adc_cfg2_t *) HW_ADC_CFG2_ADDR(x))
557 #define HW_ADC_CFG2_RD(x) (HW_ADC_CFG2(x).U)
558 #define HW_ADC_CFG2_WR(x, v) (HW_ADC_CFG2(x).U = (v))
559 #define HW_ADC_CFG2_SET(x, v) (HW_ADC_CFG2_WR(x, HW_ADC_CFG2_RD(x) | (v)))
560 #define HW_ADC_CFG2_CLR(x, v) (HW_ADC_CFG2_WR(x, HW_ADC_CFG2_RD(x) & ~(v)))
561 #define HW_ADC_CFG2_TOG(x, v) (HW_ADC_CFG2_WR(x, HW_ADC_CFG2_RD(x) ^ (v)))
565 * Constants & macros for individual ADC_CFG2 bitfields
569 * @name Register ADC_CFG2, field ADLSTS[1:0] (RW)
571 * Selects between the extended sample times when long sample time is selected,
572 * that is, when CFG1[ADLSMP]=1. This allows higher impedance inputs to be
573 * accurately sampled or to maximize conversion speed for lower impedance inputs.
574 * Longer sample times can also be used to lower overall power consumption when
575 * continuous conversions are enabled if high conversion rates are not required.
578 * - 00 - Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles
580 * - 01 - 12 extra ADCK cycles; 16 ADCK cycles total sample time.
581 * - 10 - 6 extra ADCK cycles; 10 ADCK cycles total sample time.
582 * - 11 - 2 extra ADCK cycles; 6 ADCK cycles total sample time.
585 #define BP_ADC_CFG2_ADLSTS (0U) /*!< Bit position for ADC_CFG2_ADLSTS. */
586 #define BM_ADC_CFG2_ADLSTS (0x00000003U) /*!< Bit mask for ADC_CFG2_ADLSTS. */
587 #define BS_ADC_CFG2_ADLSTS (2U) /*!< Bit field size in bits for ADC_CFG2_ADLSTS. */
589 /*! @brief Read current value of the ADC_CFG2_ADLSTS field. */
590 #define BR_ADC_CFG2_ADLSTS(x) (HW_ADC_CFG2(x).B.ADLSTS)
592 /*! @brief Format value for bitfield ADC_CFG2_ADLSTS. */
593 #define BF_ADC_CFG2_ADLSTS(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG2_ADLSTS) & BM_ADC_CFG2_ADLSTS)
595 /*! @brief Set the ADLSTS field to a new value. */
596 #define BW_ADC_CFG2_ADLSTS(x, v) (HW_ADC_CFG2_WR(x, (HW_ADC_CFG2_RD(x) & ~BM_ADC_CFG2_ADLSTS) | BF_ADC_CFG2_ADLSTS(v)))
600 * @name Register ADC_CFG2, field ADHSC[2] (RW)
602 * Configures the ADC for very high-speed operation. The conversion sequence is
603 * altered with 2 ADCK cycles added to the conversion time to allow higher speed
607 * - 0 - Normal conversion sequence selected.
608 * - 1 - High-speed conversion sequence selected with 2 additional ADCK cycles
609 * to total conversion time.
612 #define BP_ADC_CFG2_ADHSC (2U) /*!< Bit position for ADC_CFG2_ADHSC. */
613 #define BM_ADC_CFG2_ADHSC (0x00000004U) /*!< Bit mask for ADC_CFG2_ADHSC. */
614 #define BS_ADC_CFG2_ADHSC (1U) /*!< Bit field size in bits for ADC_CFG2_ADHSC. */
616 /*! @brief Read current value of the ADC_CFG2_ADHSC field. */
617 #define BR_ADC_CFG2_ADHSC(x) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADHSC))
619 /*! @brief Format value for bitfield ADC_CFG2_ADHSC. */
620 #define BF_ADC_CFG2_ADHSC(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG2_ADHSC) & BM_ADC_CFG2_ADHSC)
622 /*! @brief Set the ADHSC field to a new value. */
623 #define BW_ADC_CFG2_ADHSC(x, v) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADHSC) = (v))
627 * @name Register ADC_CFG2, field ADACKEN[3] (RW)
629 * Enables the asynchronous clock source and the clock source output regardless
630 * of the conversion and status of CFG1[ADICLK]. Based on MCU configuration, the
631 * asynchronous clock may be used by other modules. See chip configuration
632 * information. Setting this field allows the clock to be used even while the ADC is
633 * idle or operating from a different clock source. Also, latency of initiating a
634 * single or first-continuous conversion with the asynchronous clock selected is
635 * reduced because the ADACK clock is already operational.
638 * - 0 - Asynchronous clock output disabled; Asynchronous clock is enabled only
639 * if selected by ADICLK and a conversion is active.
640 * - 1 - Asynchronous clock and clock output is enabled regardless of the state
644 #define BP_ADC_CFG2_ADACKEN (3U) /*!< Bit position for ADC_CFG2_ADACKEN. */
645 #define BM_ADC_CFG2_ADACKEN (0x00000008U) /*!< Bit mask for ADC_CFG2_ADACKEN. */
646 #define BS_ADC_CFG2_ADACKEN (1U) /*!< Bit field size in bits for ADC_CFG2_ADACKEN. */
648 /*! @brief Read current value of the ADC_CFG2_ADACKEN field. */
649 #define BR_ADC_CFG2_ADACKEN(x) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADACKEN))
651 /*! @brief Format value for bitfield ADC_CFG2_ADACKEN. */
652 #define BF_ADC_CFG2_ADACKEN(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG2_ADACKEN) & BM_ADC_CFG2_ADACKEN)
654 /*! @brief Set the ADACKEN field to a new value. */
655 #define BW_ADC_CFG2_ADACKEN(x, v) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADACKEN) = (v))
659 * @name Register ADC_CFG2, field MUXSEL[4] (RW)
661 * Changes the ADC mux setting to select between alternate sets of ADC channels.
664 * - 0 - ADxxa channels are selected.
665 * - 1 - ADxxb channels are selected.
668 #define BP_ADC_CFG2_MUXSEL (4U) /*!< Bit position for ADC_CFG2_MUXSEL. */
669 #define BM_ADC_CFG2_MUXSEL (0x00000010U) /*!< Bit mask for ADC_CFG2_MUXSEL. */
670 #define BS_ADC_CFG2_MUXSEL (1U) /*!< Bit field size in bits for ADC_CFG2_MUXSEL. */
672 /*! @brief Read current value of the ADC_CFG2_MUXSEL field. */
673 #define BR_ADC_CFG2_MUXSEL(x) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_MUXSEL))
675 /*! @brief Format value for bitfield ADC_CFG2_MUXSEL. */
676 #define BF_ADC_CFG2_MUXSEL(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG2_MUXSEL) & BM_ADC_CFG2_MUXSEL)
678 /*! @brief Set the MUXSEL field to a new value. */
679 #define BW_ADC_CFG2_MUXSEL(x, v) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_MUXSEL) = (v))
682 /*******************************************************************************
683 * HW_ADC_Rn - ADC Data Result Register
684 ******************************************************************************/
687 * @brief HW_ADC_Rn - ADC Data Result Register (RO)
689 * Reset value: 0x00000000U
691 * The data result registers (Rn) contain the result of an ADC conversion of the
692 * channel selected by the corresponding status and channel control register
693 * (SC1A:SC1n). For every status and channel control register, there is a
694 * corresponding data result register. Unused bits in R n are cleared in unsigned
695 * right-aligned modes and carry the sign bit (MSB) in sign-extended 2's complement modes.
696 * For example, when configured for 10-bit single-ended mode, D[15:10] are
697 * cleared. When configured for 11-bit differential mode, D[15:10] carry the sign bit,
698 * that is, bit 10 extended through bit 15. The following table describes the
699 * behavior of the data result registers in the different modes of operation. Data
700 * result register description Conversion mode D15 D14 D13 D12 D11 D10 D9 D8 D7
701 * D6 D5 D4 D3 D2 D1 D0 Format 16-bit differential S D D D D D D D D D D D D D D D
702 * Signed 2's complement 16-bit single-ended D D D D D D D D D D D D D D D D
703 * Unsigned right justified 13-bit differential S S S S D D D D D D D D D D D D
704 * Sign-extended 2's complement 12-bit single-ended 0 0 0 0 D D D D D D D D D D D D
705 * Unsigned right-justified 11-bit differential S S S S S S D D D D D D D D D D
706 * Sign-extended 2's complement 10-bit single-ended 0 0 0 0 0 0 D D D D D D D D D D
707 * Unsigned right-justified 9-bit differential S S S S S S S S D D D D D D D D
708 * Sign-extended 2's complement 8-bit single-ended 0 0 0 0 0 0 0 0 D D D D D D D D
709 * Unsigned right-justified S: Sign bit or sign bit extension; D: Data, which is
710 * 2's complement data if indicated
712 typedef union _hw_adc_rn
715 struct _hw_adc_rn_bitfields
717 uint32_t D
: 16; /*!< [15:0] Data result */
718 uint32_t RESERVED0
: 16; /*!< [31:16] */
723 * @name Constants and macros for entire ADC_Rn register
726 #define HW_ADC_Rn_COUNT (2U)
728 #define HW_ADC_Rn_ADDR(x, n) ((x) + 0x10U + (0x4U * (n)))
730 #define HW_ADC_Rn(x, n) (*(__I hw_adc_rn_t *) HW_ADC_Rn_ADDR(x, n))
731 #define HW_ADC_Rn_RD(x, n) (HW_ADC_Rn(x, n).U)
735 * Constants & macros for individual ADC_Rn bitfields
739 * @name Register ADC_Rn, field D[15:0] (RO)
742 #define BP_ADC_Rn_D (0U) /*!< Bit position for ADC_Rn_D. */
743 #define BM_ADC_Rn_D (0x0000FFFFU) /*!< Bit mask for ADC_Rn_D. */
744 #define BS_ADC_Rn_D (16U) /*!< Bit field size in bits for ADC_Rn_D. */
746 /*! @brief Read current value of the ADC_Rn_D field. */
747 #define BR_ADC_Rn_D(x, n) (HW_ADC_Rn(x, n).B.D)
750 /*******************************************************************************
751 * HW_ADC_CV1 - Compare Value Registers
752 ******************************************************************************/
755 * @brief HW_ADC_CV1 - Compare Value Registers (RW)
757 * Reset value: 0x00000000U
759 * The Compare Value Registers (CV1 and CV2) contain a compare value used to
760 * compare the conversion result when the compare function is enabled, that is,
761 * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
762 * different modes of operation for both bit position definition and value format
763 * using unsigned or sign-extended 2's complement. Therefore, the compare function
764 * uses only the CVn fields that are related to the ADC mode of operation. The
765 * compare value 2 register (CV2) is used only when the compare range function is
766 * enabled, that is, SC2[ACREN]=1.
768 typedef union _hw_adc_cv1
771 struct _hw_adc_cv1_bitfields
773 uint32_t CV
: 16; /*!< [15:0] Compare Value. */
774 uint32_t RESERVED0
: 16; /*!< [31:16] */
779 * @name Constants and macros for entire ADC_CV1 register
782 #define HW_ADC_CV1_ADDR(x) ((x) + 0x18U)
784 #define HW_ADC_CV1(x) (*(__IO hw_adc_cv1_t *) HW_ADC_CV1_ADDR(x))
785 #define HW_ADC_CV1_RD(x) (HW_ADC_CV1(x).U)
786 #define HW_ADC_CV1_WR(x, v) (HW_ADC_CV1(x).U = (v))
787 #define HW_ADC_CV1_SET(x, v) (HW_ADC_CV1_WR(x, HW_ADC_CV1_RD(x) | (v)))
788 #define HW_ADC_CV1_CLR(x, v) (HW_ADC_CV1_WR(x, HW_ADC_CV1_RD(x) & ~(v)))
789 #define HW_ADC_CV1_TOG(x, v) (HW_ADC_CV1_WR(x, HW_ADC_CV1_RD(x) ^ (v)))
793 * Constants & macros for individual ADC_CV1 bitfields
797 * @name Register ADC_CV1, field CV[15:0] (RW)
800 #define BP_ADC_CV1_CV (0U) /*!< Bit position for ADC_CV1_CV. */
801 #define BM_ADC_CV1_CV (0x0000FFFFU) /*!< Bit mask for ADC_CV1_CV. */
802 #define BS_ADC_CV1_CV (16U) /*!< Bit field size in bits for ADC_CV1_CV. */
804 /*! @brief Read current value of the ADC_CV1_CV field. */
805 #define BR_ADC_CV1_CV(x) (HW_ADC_CV1(x).B.CV)
807 /*! @brief Format value for bitfield ADC_CV1_CV. */
808 #define BF_ADC_CV1_CV(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CV1_CV) & BM_ADC_CV1_CV)
810 /*! @brief Set the CV field to a new value. */
811 #define BW_ADC_CV1_CV(x, v) (HW_ADC_CV1_WR(x, (HW_ADC_CV1_RD(x) & ~BM_ADC_CV1_CV) | BF_ADC_CV1_CV(v)))
814 /*******************************************************************************
815 * HW_ADC_CV2 - Compare Value Registers
816 ******************************************************************************/
819 * @brief HW_ADC_CV2 - Compare Value Registers (RW)
821 * Reset value: 0x00000000U
823 * The Compare Value Registers (CV1 and CV2) contain a compare value used to
824 * compare the conversion result when the compare function is enabled, that is,
825 * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
826 * different modes of operation for both bit position definition and value format
827 * using unsigned or sign-extended 2's complement. Therefore, the compare function
828 * uses only the CVn fields that are related to the ADC mode of operation. The
829 * compare value 2 register (CV2) is used only when the compare range function is
830 * enabled, that is, SC2[ACREN]=1.
832 typedef union _hw_adc_cv2
835 struct _hw_adc_cv2_bitfields
837 uint32_t CV
: 16; /*!< [15:0] Compare Value. */
838 uint32_t RESERVED0
: 16; /*!< [31:16] */
843 * @name Constants and macros for entire ADC_CV2 register
846 #define HW_ADC_CV2_ADDR(x) ((x) + 0x1CU)
848 #define HW_ADC_CV2(x) (*(__IO hw_adc_cv2_t *) HW_ADC_CV2_ADDR(x))
849 #define HW_ADC_CV2_RD(x) (HW_ADC_CV2(x).U)
850 #define HW_ADC_CV2_WR(x, v) (HW_ADC_CV2(x).U = (v))
851 #define HW_ADC_CV2_SET(x, v) (HW_ADC_CV2_WR(x, HW_ADC_CV2_RD(x) | (v)))
852 #define HW_ADC_CV2_CLR(x, v) (HW_ADC_CV2_WR(x, HW_ADC_CV2_RD(x) & ~(v)))
853 #define HW_ADC_CV2_TOG(x, v) (HW_ADC_CV2_WR(x, HW_ADC_CV2_RD(x) ^ (v)))
857 * Constants & macros for individual ADC_CV2 bitfields
861 * @name Register ADC_CV2, field CV[15:0] (RW)
864 #define BP_ADC_CV2_CV (0U) /*!< Bit position for ADC_CV2_CV. */
865 #define BM_ADC_CV2_CV (0x0000FFFFU) /*!< Bit mask for ADC_CV2_CV. */
866 #define BS_ADC_CV2_CV (16U) /*!< Bit field size in bits for ADC_CV2_CV. */
868 /*! @brief Read current value of the ADC_CV2_CV field. */
869 #define BR_ADC_CV2_CV(x) (HW_ADC_CV2(x).B.CV)
871 /*! @brief Format value for bitfield ADC_CV2_CV. */
872 #define BF_ADC_CV2_CV(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CV2_CV) & BM_ADC_CV2_CV)
874 /*! @brief Set the CV field to a new value. */
875 #define BW_ADC_CV2_CV(x, v) (HW_ADC_CV2_WR(x, (HW_ADC_CV2_RD(x) & ~BM_ADC_CV2_CV) | BF_ADC_CV2_CV(v)))
878 /*******************************************************************************
879 * HW_ADC_SC2 - Status and Control Register 2
880 ******************************************************************************/
883 * @brief HW_ADC_SC2 - Status and Control Register 2 (RW)
885 * Reset value: 0x00000000U
887 * The status and control register 2 (SC2) contains the conversion active,
888 * hardware/software trigger select, compare function, and voltage reference select of
891 typedef union _hw_adc_sc2
894 struct _hw_adc_sc2_bitfields
896 uint32_t REFSEL
: 2; /*!< [1:0] Voltage Reference Selection */
897 uint32_t DMAEN
: 1; /*!< [2] DMA Enable */
898 uint32_t ACREN
: 1; /*!< [3] Compare Function Range Enable */
899 uint32_t ACFGT
: 1; /*!< [4] Compare Function Greater Than Enable */
900 uint32_t ACFE
: 1; /*!< [5] Compare Function Enable */
901 uint32_t ADTRG
: 1; /*!< [6] Conversion Trigger Select */
902 uint32_t ADACT
: 1; /*!< [7] Conversion Active */
903 uint32_t RESERVED0
: 24; /*!< [31:8] */
908 * @name Constants and macros for entire ADC_SC2 register
911 #define HW_ADC_SC2_ADDR(x) ((x) + 0x20U)
913 #define HW_ADC_SC2(x) (*(__IO hw_adc_sc2_t *) HW_ADC_SC2_ADDR(x))
914 #define HW_ADC_SC2_RD(x) (HW_ADC_SC2(x).U)
915 #define HW_ADC_SC2_WR(x, v) (HW_ADC_SC2(x).U = (v))
916 #define HW_ADC_SC2_SET(x, v) (HW_ADC_SC2_WR(x, HW_ADC_SC2_RD(x) | (v)))
917 #define HW_ADC_SC2_CLR(x, v) (HW_ADC_SC2_WR(x, HW_ADC_SC2_RD(x) & ~(v)))
918 #define HW_ADC_SC2_TOG(x, v) (HW_ADC_SC2_WR(x, HW_ADC_SC2_RD(x) ^ (v)))
922 * Constants & macros for individual ADC_SC2 bitfields
926 * @name Register ADC_SC2, field REFSEL[1:0] (RW)
928 * Selects the voltage reference source used for conversions.
931 * - 00 - Default voltage reference pin pair, that is, external pins VREFH and
933 * - 01 - Alternate reference pair, that is, VALTH and VALTL . This pair may be
934 * additional external pins or internal sources depending on the MCU
935 * configuration. See the chip configuration information for details specific to this
941 #define BP_ADC_SC2_REFSEL (0U) /*!< Bit position for ADC_SC2_REFSEL. */
942 #define BM_ADC_SC2_REFSEL (0x00000003U) /*!< Bit mask for ADC_SC2_REFSEL. */
943 #define BS_ADC_SC2_REFSEL (2U) /*!< Bit field size in bits for ADC_SC2_REFSEL. */
945 /*! @brief Read current value of the ADC_SC2_REFSEL field. */
946 #define BR_ADC_SC2_REFSEL(x) (HW_ADC_SC2(x).B.REFSEL)
948 /*! @brief Format value for bitfield ADC_SC2_REFSEL. */
949 #define BF_ADC_SC2_REFSEL(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_REFSEL) & BM_ADC_SC2_REFSEL)
951 /*! @brief Set the REFSEL field to a new value. */
952 #define BW_ADC_SC2_REFSEL(x, v) (HW_ADC_SC2_WR(x, (HW_ADC_SC2_RD(x) & ~BM_ADC_SC2_REFSEL) | BF_ADC_SC2_REFSEL(v)))
956 * @name Register ADC_SC2, field DMAEN[2] (RW)
959 * - 0 - DMA is disabled.
960 * - 1 - DMA is enabled and will assert the ADC DMA request during an ADC
961 * conversion complete event noted when any of the SC1n[COCO] flags is asserted.
964 #define BP_ADC_SC2_DMAEN (2U) /*!< Bit position for ADC_SC2_DMAEN. */
965 #define BM_ADC_SC2_DMAEN (0x00000004U) /*!< Bit mask for ADC_SC2_DMAEN. */
966 #define BS_ADC_SC2_DMAEN (1U) /*!< Bit field size in bits for ADC_SC2_DMAEN. */
968 /*! @brief Read current value of the ADC_SC2_DMAEN field. */
969 #define BR_ADC_SC2_DMAEN(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_DMAEN))
971 /*! @brief Format value for bitfield ADC_SC2_DMAEN. */
972 #define BF_ADC_SC2_DMAEN(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_DMAEN) & BM_ADC_SC2_DMAEN)
974 /*! @brief Set the DMAEN field to a new value. */
975 #define BW_ADC_SC2_DMAEN(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_DMAEN) = (v))
979 * @name Register ADC_SC2, field ACREN[3] (RW)
981 * Configures the compare function to check if the conversion result of the
982 * input being monitored is either between or outside the range formed by CV1 and CV2
983 * determined by the value of ACFGT. ACFE must be set for ACFGT to have any
987 * - 0 - Range function disabled. Only CV1 is compared.
988 * - 1 - Range function enabled. Both CV1 and CV2 are compared.
991 #define BP_ADC_SC2_ACREN (3U) /*!< Bit position for ADC_SC2_ACREN. */
992 #define BM_ADC_SC2_ACREN (0x00000008U) /*!< Bit mask for ADC_SC2_ACREN. */
993 #define BS_ADC_SC2_ACREN (1U) /*!< Bit field size in bits for ADC_SC2_ACREN. */
995 /*! @brief Read current value of the ADC_SC2_ACREN field. */
996 #define BR_ADC_SC2_ACREN(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACREN))
998 /*! @brief Format value for bitfield ADC_SC2_ACREN. */
999 #define BF_ADC_SC2_ACREN(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_ACREN) & BM_ADC_SC2_ACREN)
1001 /*! @brief Set the ACREN field to a new value. */
1002 #define BW_ADC_SC2_ACREN(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACREN) = (v))
1006 * @name Register ADC_SC2, field ACFGT[4] (RW)
1008 * Configures the compare function to check the conversion result relative to
1009 * the CV1 and CV2 based upon the value of ACREN. ACFE must be set for ACFGT to
1013 * - 0 - Configures less than threshold, outside range not inclusive and inside
1014 * range not inclusive; functionality based on the values placed in CV1 and
1016 * - 1 - Configures greater than or equal to threshold, outside and inside
1017 * ranges inclusive; functionality based on the values placed in CV1 and CV2.
1020 #define BP_ADC_SC2_ACFGT (4U) /*!< Bit position for ADC_SC2_ACFGT. */
1021 #define BM_ADC_SC2_ACFGT (0x00000010U) /*!< Bit mask for ADC_SC2_ACFGT. */
1022 #define BS_ADC_SC2_ACFGT (1U) /*!< Bit field size in bits for ADC_SC2_ACFGT. */
1024 /*! @brief Read current value of the ADC_SC2_ACFGT field. */
1025 #define BR_ADC_SC2_ACFGT(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFGT))
1027 /*! @brief Format value for bitfield ADC_SC2_ACFGT. */
1028 #define BF_ADC_SC2_ACFGT(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_ACFGT) & BM_ADC_SC2_ACFGT)
1030 /*! @brief Set the ACFGT field to a new value. */
1031 #define BW_ADC_SC2_ACFGT(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFGT) = (v))
1035 * @name Register ADC_SC2, field ACFE[5] (RW)
1037 * Enables the compare function.
1040 * - 0 - Compare function disabled.
1041 * - 1 - Compare function enabled.
1044 #define BP_ADC_SC2_ACFE (5U) /*!< Bit position for ADC_SC2_ACFE. */
1045 #define BM_ADC_SC2_ACFE (0x00000020U) /*!< Bit mask for ADC_SC2_ACFE. */
1046 #define BS_ADC_SC2_ACFE (1U) /*!< Bit field size in bits for ADC_SC2_ACFE. */
1048 /*! @brief Read current value of the ADC_SC2_ACFE field. */
1049 #define BR_ADC_SC2_ACFE(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFE))
1051 /*! @brief Format value for bitfield ADC_SC2_ACFE. */
1052 #define BF_ADC_SC2_ACFE(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_ACFE) & BM_ADC_SC2_ACFE)
1054 /*! @brief Set the ACFE field to a new value. */
1055 #define BW_ADC_SC2_ACFE(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFE) = (v))
1059 * @name Register ADC_SC2, field ADTRG[6] (RW)
1061 * Selects the type of trigger used for initiating a conversion. Two types of
1062 * trigger are selectable: Software trigger: When software trigger is selected, a
1063 * conversion is initiated following a write to SC1A. Hardware trigger: When
1064 * hardware trigger is selected, a conversion is initiated following the assertion of
1065 * the ADHWT input after a pulse of the ADHWTSn input.
1068 * - 0 - Software trigger selected.
1069 * - 1 - Hardware trigger selected.
1072 #define BP_ADC_SC2_ADTRG (6U) /*!< Bit position for ADC_SC2_ADTRG. */
1073 #define BM_ADC_SC2_ADTRG (0x00000040U) /*!< Bit mask for ADC_SC2_ADTRG. */
1074 #define BS_ADC_SC2_ADTRG (1U) /*!< Bit field size in bits for ADC_SC2_ADTRG. */
1076 /*! @brief Read current value of the ADC_SC2_ADTRG field. */
1077 #define BR_ADC_SC2_ADTRG(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ADTRG))
1079 /*! @brief Format value for bitfield ADC_SC2_ADTRG. */
1080 #define BF_ADC_SC2_ADTRG(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_ADTRG) & BM_ADC_SC2_ADTRG)
1082 /*! @brief Set the ADTRG field to a new value. */
1083 #define BW_ADC_SC2_ADTRG(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ADTRG) = (v))
1087 * @name Register ADC_SC2, field ADACT[7] (RO)
1089 * Indicates that a conversion or hardware averaging is in progress. ADACT is
1090 * set when a conversion is initiated and cleared when a conversion is completed or
1094 * - 0 - Conversion not in progress.
1095 * - 1 - Conversion in progress.
1098 #define BP_ADC_SC2_ADACT (7U) /*!< Bit position for ADC_SC2_ADACT. */
1099 #define BM_ADC_SC2_ADACT (0x00000080U) /*!< Bit mask for ADC_SC2_ADACT. */
1100 #define BS_ADC_SC2_ADACT (1U) /*!< Bit field size in bits for ADC_SC2_ADACT. */
1102 /*! @brief Read current value of the ADC_SC2_ADACT field. */
1103 #define BR_ADC_SC2_ADACT(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ADACT))
1106 /*******************************************************************************
1107 * HW_ADC_SC3 - Status and Control Register 3
1108 ******************************************************************************/
1111 * @brief HW_ADC_SC3 - Status and Control Register 3 (RW)
1113 * Reset value: 0x00000000U
1115 * The Status and Control Register 3 (SC3) controls the calibration, continuous
1116 * convert, and hardware averaging functions of the ADC module.
1118 typedef union _hw_adc_sc3
1121 struct _hw_adc_sc3_bitfields
1123 uint32_t AVGS
: 2; /*!< [1:0] Hardware Average Select */
1124 uint32_t AVGE
: 1; /*!< [2] Hardware Average Enable */
1125 uint32_t ADCO
: 1; /*!< [3] Continuous Conversion Enable */
1126 uint32_t RESERVED0
: 2; /*!< [5:4] */
1127 uint32_t CALF
: 1; /*!< [6] Calibration Failed Flag */
1128 uint32_t CAL
: 1; /*!< [7] Calibration */
1129 uint32_t RESERVED1
: 24; /*!< [31:8] */
1134 * @name Constants and macros for entire ADC_SC3 register
1137 #define HW_ADC_SC3_ADDR(x) ((x) + 0x24U)
1139 #define HW_ADC_SC3(x) (*(__IO hw_adc_sc3_t *) HW_ADC_SC3_ADDR(x))
1140 #define HW_ADC_SC3_RD(x) (HW_ADC_SC3(x).U)
1141 #define HW_ADC_SC3_WR(x, v) (HW_ADC_SC3(x).U = (v))
1142 #define HW_ADC_SC3_SET(x, v) (HW_ADC_SC3_WR(x, HW_ADC_SC3_RD(x) | (v)))
1143 #define HW_ADC_SC3_CLR(x, v) (HW_ADC_SC3_WR(x, HW_ADC_SC3_RD(x) & ~(v)))
1144 #define HW_ADC_SC3_TOG(x, v) (HW_ADC_SC3_WR(x, HW_ADC_SC3_RD(x) ^ (v)))
1148 * Constants & macros for individual ADC_SC3 bitfields
1152 * @name Register ADC_SC3, field AVGS[1:0] (RW)
1154 * Determines how many ADC conversions will be averaged to create the ADC
1158 * - 00 - 4 samples averaged.
1159 * - 01 - 8 samples averaged.
1160 * - 10 - 16 samples averaged.
1161 * - 11 - 32 samples averaged.
1164 #define BP_ADC_SC3_AVGS (0U) /*!< Bit position for ADC_SC3_AVGS. */
1165 #define BM_ADC_SC3_AVGS (0x00000003U) /*!< Bit mask for ADC_SC3_AVGS. */
1166 #define BS_ADC_SC3_AVGS (2U) /*!< Bit field size in bits for ADC_SC3_AVGS. */
1168 /*! @brief Read current value of the ADC_SC3_AVGS field. */
1169 #define BR_ADC_SC3_AVGS(x) (HW_ADC_SC3(x).B.AVGS)
1171 /*! @brief Format value for bitfield ADC_SC3_AVGS. */
1172 #define BF_ADC_SC3_AVGS(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC3_AVGS) & BM_ADC_SC3_AVGS)
1174 /*! @brief Set the AVGS field to a new value. */
1175 #define BW_ADC_SC3_AVGS(x, v) (HW_ADC_SC3_WR(x, (HW_ADC_SC3_RD(x) & ~BM_ADC_SC3_AVGS) | BF_ADC_SC3_AVGS(v)))
1179 * @name Register ADC_SC3, field AVGE[2] (RW)
1181 * Enables the hardware average function of the ADC.
1184 * - 0 - Hardware average function disabled.
1185 * - 1 - Hardware average function enabled.
1188 #define BP_ADC_SC3_AVGE (2U) /*!< Bit position for ADC_SC3_AVGE. */
1189 #define BM_ADC_SC3_AVGE (0x00000004U) /*!< Bit mask for ADC_SC3_AVGE. */
1190 #define BS_ADC_SC3_AVGE (1U) /*!< Bit field size in bits for ADC_SC3_AVGE. */
1192 /*! @brief Read current value of the ADC_SC3_AVGE field. */
1193 #define BR_ADC_SC3_AVGE(x) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_AVGE))
1195 /*! @brief Format value for bitfield ADC_SC3_AVGE. */
1196 #define BF_ADC_SC3_AVGE(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC3_AVGE) & BM_ADC_SC3_AVGE)
1198 /*! @brief Set the AVGE field to a new value. */
1199 #define BW_ADC_SC3_AVGE(x, v) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_AVGE) = (v))
1203 * @name Register ADC_SC3, field ADCO[3] (RW)
1205 * Enables continuous conversions.
1208 * - 0 - One conversion or one set of conversions if the hardware average
1209 * function is enabled, that is, AVGE=1, after initiating a conversion.
1210 * - 1 - Continuous conversions or sets of conversions if the hardware average
1211 * function is enabled, that is, AVGE=1, after initiating a conversion.
1214 #define BP_ADC_SC3_ADCO (3U) /*!< Bit position for ADC_SC3_ADCO. */
1215 #define BM_ADC_SC3_ADCO (0x00000008U) /*!< Bit mask for ADC_SC3_ADCO. */
1216 #define BS_ADC_SC3_ADCO (1U) /*!< Bit field size in bits for ADC_SC3_ADCO. */
1218 /*! @brief Read current value of the ADC_SC3_ADCO field. */
1219 #define BR_ADC_SC3_ADCO(x) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_ADCO))
1221 /*! @brief Format value for bitfield ADC_SC3_ADCO. */
1222 #define BF_ADC_SC3_ADCO(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC3_ADCO) & BM_ADC_SC3_ADCO)
1224 /*! @brief Set the ADCO field to a new value. */
1225 #define BW_ADC_SC3_ADCO(x, v) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_ADCO) = (v))
1229 * @name Register ADC_SC3, field CALF[6] (RO)
1231 * Displays the result of the calibration sequence. The calibration sequence
1232 * will fail if SC2[ADTRG] = 1, any ADC register is written, or any stop mode is
1233 * entered before the calibration sequence completes. Writing 1 to CALF clears it.
1236 * - 0 - Calibration completed normally.
1237 * - 1 - Calibration failed. ADC accuracy specifications are not guaranteed.
1240 #define BP_ADC_SC3_CALF (6U) /*!< Bit position for ADC_SC3_CALF. */
1241 #define BM_ADC_SC3_CALF (0x00000040U) /*!< Bit mask for ADC_SC3_CALF. */
1242 #define BS_ADC_SC3_CALF (1U) /*!< Bit field size in bits for ADC_SC3_CALF. */
1244 /*! @brief Read current value of the ADC_SC3_CALF field. */
1245 #define BR_ADC_SC3_CALF(x) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_CALF))
1249 * @name Register ADC_SC3, field CAL[7] (RW)
1251 * Begins the calibration sequence when set. This field stays set while the
1252 * calibration is in progress and is cleared when the calibration sequence is
1253 * completed. CALF must be checked to determine the result of the calibration sequence.
1254 * Once started, the calibration routine cannot be interrupted by writes to the
1255 * ADC registers or the results will be invalid and CALF will set. Setting CAL
1256 * will abort any current conversion.
1259 #define BP_ADC_SC3_CAL (7U) /*!< Bit position for ADC_SC3_CAL. */
1260 #define BM_ADC_SC3_CAL (0x00000080U) /*!< Bit mask for ADC_SC3_CAL. */
1261 #define BS_ADC_SC3_CAL (1U) /*!< Bit field size in bits for ADC_SC3_CAL. */
1263 /*! @brief Read current value of the ADC_SC3_CAL field. */
1264 #define BR_ADC_SC3_CAL(x) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_CAL))
1266 /*! @brief Format value for bitfield ADC_SC3_CAL. */
1267 #define BF_ADC_SC3_CAL(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC3_CAL) & BM_ADC_SC3_CAL)
1269 /*! @brief Set the CAL field to a new value. */
1270 #define BW_ADC_SC3_CAL(x, v) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_CAL) = (v))
1273 /*******************************************************************************
1274 * HW_ADC_OFS - ADC Offset Correction Register
1275 ******************************************************************************/
1278 * @brief HW_ADC_OFS - ADC Offset Correction Register (RW)
1280 * Reset value: 0x00000004U
1282 * The ADC Offset Correction Register (OFS) contains the user-selected or
1283 * calibration-generated offset error correction value. This register is a 2's
1284 * complement, left-justified, 16-bit value . The value in OFS is subtracted from the
1285 * conversion and the result is transferred into the result registers, Rn. If the
1286 * result is greater than the maximum or less than the minimum result value, it is
1287 * forced to the appropriate limit for the current mode of operation.
1289 typedef union _hw_adc_ofs
1292 struct _hw_adc_ofs_bitfields
1294 uint32_t OFS
: 16; /*!< [15:0] Offset Error Correction Value */
1295 uint32_t RESERVED0
: 16; /*!< [31:16] */
1300 * @name Constants and macros for entire ADC_OFS register
1303 #define HW_ADC_OFS_ADDR(x) ((x) + 0x28U)
1305 #define HW_ADC_OFS(x) (*(__IO hw_adc_ofs_t *) HW_ADC_OFS_ADDR(x))
1306 #define HW_ADC_OFS_RD(x) (HW_ADC_OFS(x).U)
1307 #define HW_ADC_OFS_WR(x, v) (HW_ADC_OFS(x).U = (v))
1308 #define HW_ADC_OFS_SET(x, v) (HW_ADC_OFS_WR(x, HW_ADC_OFS_RD(x) | (v)))
1309 #define HW_ADC_OFS_CLR(x, v) (HW_ADC_OFS_WR(x, HW_ADC_OFS_RD(x) & ~(v)))
1310 #define HW_ADC_OFS_TOG(x, v) (HW_ADC_OFS_WR(x, HW_ADC_OFS_RD(x) ^ (v)))
1314 * Constants & macros for individual ADC_OFS bitfields
1318 * @name Register ADC_OFS, field OFS[15:0] (RW)
1321 #define BP_ADC_OFS_OFS (0U) /*!< Bit position for ADC_OFS_OFS. */
1322 #define BM_ADC_OFS_OFS (0x0000FFFFU) /*!< Bit mask for ADC_OFS_OFS. */
1323 #define BS_ADC_OFS_OFS (16U) /*!< Bit field size in bits for ADC_OFS_OFS. */
1325 /*! @brief Read current value of the ADC_OFS_OFS field. */
1326 #define BR_ADC_OFS_OFS(x) (HW_ADC_OFS(x).B.OFS)
1328 /*! @brief Format value for bitfield ADC_OFS_OFS. */
1329 #define BF_ADC_OFS_OFS(v) ((uint32_t)((uint32_t)(v) << BP_ADC_OFS_OFS) & BM_ADC_OFS_OFS)
1331 /*! @brief Set the OFS field to a new value. */
1332 #define BW_ADC_OFS_OFS(x, v) (HW_ADC_OFS_WR(x, (HW_ADC_OFS_RD(x) & ~BM_ADC_OFS_OFS) | BF_ADC_OFS_OFS(v)))
1335 /*******************************************************************************
1336 * HW_ADC_PG - ADC Plus-Side Gain Register
1337 ******************************************************************************/
1340 * @brief HW_ADC_PG - ADC Plus-Side Gain Register (RW)
1342 * Reset value: 0x00008200U
1344 * The Plus-Side Gain Register (PG) contains the gain error correction for the
1345 * plus-side input in differential mode or the overall conversion in single-ended
1346 * mode. PG, a 16-bit real number in binary format, is the gain adjustment
1347 * factor, with the radix point fixed between ADPG15 and ADPG14. This register must be
1348 * written by the user with the value described in the calibration procedure.
1349 * Otherwise, the gain error specifications may not be met.
1351 typedef union _hw_adc_pg
1354 struct _hw_adc_pg_bitfields
1356 uint32_t PG
: 16; /*!< [15:0] Plus-Side Gain */
1357 uint32_t RESERVED0
: 16; /*!< [31:16] */
1362 * @name Constants and macros for entire ADC_PG register
1365 #define HW_ADC_PG_ADDR(x) ((x) + 0x2CU)
1367 #define HW_ADC_PG(x) (*(__IO hw_adc_pg_t *) HW_ADC_PG_ADDR(x))
1368 #define HW_ADC_PG_RD(x) (HW_ADC_PG(x).U)
1369 #define HW_ADC_PG_WR(x, v) (HW_ADC_PG(x).U = (v))
1370 #define HW_ADC_PG_SET(x, v) (HW_ADC_PG_WR(x, HW_ADC_PG_RD(x) | (v)))
1371 #define HW_ADC_PG_CLR(x, v) (HW_ADC_PG_WR(x, HW_ADC_PG_RD(x) & ~(v)))
1372 #define HW_ADC_PG_TOG(x, v) (HW_ADC_PG_WR(x, HW_ADC_PG_RD(x) ^ (v)))
1376 * Constants & macros for individual ADC_PG bitfields
1380 * @name Register ADC_PG, field PG[15:0] (RW)
1383 #define BP_ADC_PG_PG (0U) /*!< Bit position for ADC_PG_PG. */
1384 #define BM_ADC_PG_PG (0x0000FFFFU) /*!< Bit mask for ADC_PG_PG. */
1385 #define BS_ADC_PG_PG (16U) /*!< Bit field size in bits for ADC_PG_PG. */
1387 /*! @brief Read current value of the ADC_PG_PG field. */
1388 #define BR_ADC_PG_PG(x) (HW_ADC_PG(x).B.PG)
1390 /*! @brief Format value for bitfield ADC_PG_PG. */
1391 #define BF_ADC_PG_PG(v) ((uint32_t)((uint32_t)(v) << BP_ADC_PG_PG) & BM_ADC_PG_PG)
1393 /*! @brief Set the PG field to a new value. */
1394 #define BW_ADC_PG_PG(x, v) (HW_ADC_PG_WR(x, (HW_ADC_PG_RD(x) & ~BM_ADC_PG_PG) | BF_ADC_PG_PG(v)))
1397 /*******************************************************************************
1398 * HW_ADC_MG - ADC Minus-Side Gain Register
1399 ******************************************************************************/
1402 * @brief HW_ADC_MG - ADC Minus-Side Gain Register (RW)
1404 * Reset value: 0x00008200U
1406 * The Minus-Side Gain Register (MG) contains the gain error correction for the
1407 * minus-side input in differential mode. This register is ignored in
1408 * single-ended mode. MG, a 16-bit real number in binary format, is the gain adjustment
1409 * factor, with the radix point fixed between ADMG15 and ADMG14. This register must
1410 * be written by the user with the value described in the calibration procedure.
1411 * Otherwise, the gain error specifications may not be met.
1413 typedef union _hw_adc_mg
1416 struct _hw_adc_mg_bitfields
1418 uint32_t MG
: 16; /*!< [15:0] Minus-Side Gain */
1419 uint32_t RESERVED0
: 16; /*!< [31:16] */
1424 * @name Constants and macros for entire ADC_MG register
1427 #define HW_ADC_MG_ADDR(x) ((x) + 0x30U)
1429 #define HW_ADC_MG(x) (*(__IO hw_adc_mg_t *) HW_ADC_MG_ADDR(x))
1430 #define HW_ADC_MG_RD(x) (HW_ADC_MG(x).U)
1431 #define HW_ADC_MG_WR(x, v) (HW_ADC_MG(x).U = (v))
1432 #define HW_ADC_MG_SET(x, v) (HW_ADC_MG_WR(x, HW_ADC_MG_RD(x) | (v)))
1433 #define HW_ADC_MG_CLR(x, v) (HW_ADC_MG_WR(x, HW_ADC_MG_RD(x) & ~(v)))
1434 #define HW_ADC_MG_TOG(x, v) (HW_ADC_MG_WR(x, HW_ADC_MG_RD(x) ^ (v)))
1438 * Constants & macros for individual ADC_MG bitfields
1442 * @name Register ADC_MG, field MG[15:0] (RW)
1445 #define BP_ADC_MG_MG (0U) /*!< Bit position for ADC_MG_MG. */
1446 #define BM_ADC_MG_MG (0x0000FFFFU) /*!< Bit mask for ADC_MG_MG. */
1447 #define BS_ADC_MG_MG (16U) /*!< Bit field size in bits for ADC_MG_MG. */
1449 /*! @brief Read current value of the ADC_MG_MG field. */
1450 #define BR_ADC_MG_MG(x) (HW_ADC_MG(x).B.MG)
1452 /*! @brief Format value for bitfield ADC_MG_MG. */
1453 #define BF_ADC_MG_MG(v) ((uint32_t)((uint32_t)(v) << BP_ADC_MG_MG) & BM_ADC_MG_MG)
1455 /*! @brief Set the MG field to a new value. */
1456 #define BW_ADC_MG_MG(x, v) (HW_ADC_MG_WR(x, (HW_ADC_MG_RD(x) & ~BM_ADC_MG_MG) | BF_ADC_MG_MG(v)))
1459 /*******************************************************************************
1460 * HW_ADC_CLPD - ADC Plus-Side General Calibration Value Register
1461 ******************************************************************************/
1464 * @brief HW_ADC_CLPD - ADC Plus-Side General Calibration Value Register (RW)
1466 * Reset value: 0x0000000AU
1468 * The Plus-Side General Calibration Value Registers (CLPx) contain calibration
1469 * information that is generated by the calibration function. These registers
1470 * contain seven calibration values of varying widths: CLP0[5:0], CLP1[6:0],
1471 * CLP2[7:0], CLP3[8:0], CLP4[9:0], CLPS[5:0], and CLPD[5:0]. CLPx are automatically set
1472 * when the self-calibration sequence is done, that is, CAL is cleared. If these
1473 * registers are written by the user after calibration, the linearity error
1474 * specifications may not be met.
1476 typedef union _hw_adc_clpd
1479 struct _hw_adc_clpd_bitfields
1481 uint32_t CLPD
: 6; /*!< [5:0] */
1482 uint32_t RESERVED0
: 26; /*!< [31:6] */
1487 * @name Constants and macros for entire ADC_CLPD register
1490 #define HW_ADC_CLPD_ADDR(x) ((x) + 0x34U)
1492 #define HW_ADC_CLPD(x) (*(__IO hw_adc_clpd_t *) HW_ADC_CLPD_ADDR(x))
1493 #define HW_ADC_CLPD_RD(x) (HW_ADC_CLPD(x).U)
1494 #define HW_ADC_CLPD_WR(x, v) (HW_ADC_CLPD(x).U = (v))
1495 #define HW_ADC_CLPD_SET(x, v) (HW_ADC_CLPD_WR(x, HW_ADC_CLPD_RD(x) | (v)))
1496 #define HW_ADC_CLPD_CLR(x, v) (HW_ADC_CLPD_WR(x, HW_ADC_CLPD_RD(x) & ~(v)))
1497 #define HW_ADC_CLPD_TOG(x, v) (HW_ADC_CLPD_WR(x, HW_ADC_CLPD_RD(x) ^ (v)))
1501 * Constants & macros for individual ADC_CLPD bitfields
1505 * @name Register ADC_CLPD, field CLPD[5:0] (RW)
1510 #define BP_ADC_CLPD_CLPD (0U) /*!< Bit position for ADC_CLPD_CLPD. */
1511 #define BM_ADC_CLPD_CLPD (0x0000003FU) /*!< Bit mask for ADC_CLPD_CLPD. */
1512 #define BS_ADC_CLPD_CLPD (6U) /*!< Bit field size in bits for ADC_CLPD_CLPD. */
1514 /*! @brief Read current value of the ADC_CLPD_CLPD field. */
1515 #define BR_ADC_CLPD_CLPD(x) (HW_ADC_CLPD(x).B.CLPD)
1517 /*! @brief Format value for bitfield ADC_CLPD_CLPD. */
1518 #define BF_ADC_CLPD_CLPD(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLPD_CLPD) & BM_ADC_CLPD_CLPD)
1520 /*! @brief Set the CLPD field to a new value. */
1521 #define BW_ADC_CLPD_CLPD(x, v) (HW_ADC_CLPD_WR(x, (HW_ADC_CLPD_RD(x) & ~BM_ADC_CLPD_CLPD) | BF_ADC_CLPD_CLPD(v)))
1524 /*******************************************************************************
1525 * HW_ADC_CLPS - ADC Plus-Side General Calibration Value Register
1526 ******************************************************************************/
1529 * @brief HW_ADC_CLPS - ADC Plus-Side General Calibration Value Register (RW)
1531 * Reset value: 0x00000020U
1533 * For more information, see CLPD register description.
1535 typedef union _hw_adc_clps
1538 struct _hw_adc_clps_bitfields
1540 uint32_t CLPS
: 6; /*!< [5:0] */
1541 uint32_t RESERVED0
: 26; /*!< [31:6] */
1546 * @name Constants and macros for entire ADC_CLPS register
1549 #define HW_ADC_CLPS_ADDR(x) ((x) + 0x38U)
1551 #define HW_ADC_CLPS(x) (*(__IO hw_adc_clps_t *) HW_ADC_CLPS_ADDR(x))
1552 #define HW_ADC_CLPS_RD(x) (HW_ADC_CLPS(x).U)
1553 #define HW_ADC_CLPS_WR(x, v) (HW_ADC_CLPS(x).U = (v))
1554 #define HW_ADC_CLPS_SET(x, v) (HW_ADC_CLPS_WR(x, HW_ADC_CLPS_RD(x) | (v)))
1555 #define HW_ADC_CLPS_CLR(x, v) (HW_ADC_CLPS_WR(x, HW_ADC_CLPS_RD(x) & ~(v)))
1556 #define HW_ADC_CLPS_TOG(x, v) (HW_ADC_CLPS_WR(x, HW_ADC_CLPS_RD(x) ^ (v)))
1560 * Constants & macros for individual ADC_CLPS bitfields
1564 * @name Register ADC_CLPS, field CLPS[5:0] (RW)
1569 #define BP_ADC_CLPS_CLPS (0U) /*!< Bit position for ADC_CLPS_CLPS. */
1570 #define BM_ADC_CLPS_CLPS (0x0000003FU) /*!< Bit mask for ADC_CLPS_CLPS. */
1571 #define BS_ADC_CLPS_CLPS (6U) /*!< Bit field size in bits for ADC_CLPS_CLPS. */
1573 /*! @brief Read current value of the ADC_CLPS_CLPS field. */
1574 #define BR_ADC_CLPS_CLPS(x) (HW_ADC_CLPS(x).B.CLPS)
1576 /*! @brief Format value for bitfield ADC_CLPS_CLPS. */
1577 #define BF_ADC_CLPS_CLPS(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLPS_CLPS) & BM_ADC_CLPS_CLPS)
1579 /*! @brief Set the CLPS field to a new value. */
1580 #define BW_ADC_CLPS_CLPS(x, v) (HW_ADC_CLPS_WR(x, (HW_ADC_CLPS_RD(x) & ~BM_ADC_CLPS_CLPS) | BF_ADC_CLPS_CLPS(v)))
1583 /*******************************************************************************
1584 * HW_ADC_CLP4 - ADC Plus-Side General Calibration Value Register
1585 ******************************************************************************/
1588 * @brief HW_ADC_CLP4 - ADC Plus-Side General Calibration Value Register (RW)
1590 * Reset value: 0x00000200U
1592 * For more information, see CLPD register description.
1594 typedef union _hw_adc_clp4
1597 struct _hw_adc_clp4_bitfields
1599 uint32_t CLP4
: 10; /*!< [9:0] */
1600 uint32_t RESERVED0
: 22; /*!< [31:10] */
1605 * @name Constants and macros for entire ADC_CLP4 register
1608 #define HW_ADC_CLP4_ADDR(x) ((x) + 0x3CU)
1610 #define HW_ADC_CLP4(x) (*(__IO hw_adc_clp4_t *) HW_ADC_CLP4_ADDR(x))
1611 #define HW_ADC_CLP4_RD(x) (HW_ADC_CLP4(x).U)
1612 #define HW_ADC_CLP4_WR(x, v) (HW_ADC_CLP4(x).U = (v))
1613 #define HW_ADC_CLP4_SET(x, v) (HW_ADC_CLP4_WR(x, HW_ADC_CLP4_RD(x) | (v)))
1614 #define HW_ADC_CLP4_CLR(x, v) (HW_ADC_CLP4_WR(x, HW_ADC_CLP4_RD(x) & ~(v)))
1615 #define HW_ADC_CLP4_TOG(x, v) (HW_ADC_CLP4_WR(x, HW_ADC_CLP4_RD(x) ^ (v)))
1619 * Constants & macros for individual ADC_CLP4 bitfields
1623 * @name Register ADC_CLP4, field CLP4[9:0] (RW)
1628 #define BP_ADC_CLP4_CLP4 (0U) /*!< Bit position for ADC_CLP4_CLP4. */
1629 #define BM_ADC_CLP4_CLP4 (0x000003FFU) /*!< Bit mask for ADC_CLP4_CLP4. */
1630 #define BS_ADC_CLP4_CLP4 (10U) /*!< Bit field size in bits for ADC_CLP4_CLP4. */
1632 /*! @brief Read current value of the ADC_CLP4_CLP4 field. */
1633 #define BR_ADC_CLP4_CLP4(x) (HW_ADC_CLP4(x).B.CLP4)
1635 /*! @brief Format value for bitfield ADC_CLP4_CLP4. */
1636 #define BF_ADC_CLP4_CLP4(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLP4_CLP4) & BM_ADC_CLP4_CLP4)
1638 /*! @brief Set the CLP4 field to a new value. */
1639 #define BW_ADC_CLP4_CLP4(x, v) (HW_ADC_CLP4_WR(x, (HW_ADC_CLP4_RD(x) & ~BM_ADC_CLP4_CLP4) | BF_ADC_CLP4_CLP4(v)))
1642 /*******************************************************************************
1643 * HW_ADC_CLP3 - ADC Plus-Side General Calibration Value Register
1644 ******************************************************************************/
1647 * @brief HW_ADC_CLP3 - ADC Plus-Side General Calibration Value Register (RW)
1649 * Reset value: 0x00000100U
1651 * For more information, see CLPD register description.
1653 typedef union _hw_adc_clp3
1656 struct _hw_adc_clp3_bitfields
1658 uint32_t CLP3
: 9; /*!< [8:0] */
1659 uint32_t RESERVED0
: 23; /*!< [31:9] */
1664 * @name Constants and macros for entire ADC_CLP3 register
1667 #define HW_ADC_CLP3_ADDR(x) ((x) + 0x40U)
1669 #define HW_ADC_CLP3(x) (*(__IO hw_adc_clp3_t *) HW_ADC_CLP3_ADDR(x))
1670 #define HW_ADC_CLP3_RD(x) (HW_ADC_CLP3(x).U)
1671 #define HW_ADC_CLP3_WR(x, v) (HW_ADC_CLP3(x).U = (v))
1672 #define HW_ADC_CLP3_SET(x, v) (HW_ADC_CLP3_WR(x, HW_ADC_CLP3_RD(x) | (v)))
1673 #define HW_ADC_CLP3_CLR(x, v) (HW_ADC_CLP3_WR(x, HW_ADC_CLP3_RD(x) & ~(v)))
1674 #define HW_ADC_CLP3_TOG(x, v) (HW_ADC_CLP3_WR(x, HW_ADC_CLP3_RD(x) ^ (v)))
1678 * Constants & macros for individual ADC_CLP3 bitfields
1682 * @name Register ADC_CLP3, field CLP3[8:0] (RW)
1687 #define BP_ADC_CLP3_CLP3 (0U) /*!< Bit position for ADC_CLP3_CLP3. */
1688 #define BM_ADC_CLP3_CLP3 (0x000001FFU) /*!< Bit mask for ADC_CLP3_CLP3. */
1689 #define BS_ADC_CLP3_CLP3 (9U) /*!< Bit field size in bits for ADC_CLP3_CLP3. */
1691 /*! @brief Read current value of the ADC_CLP3_CLP3 field. */
1692 #define BR_ADC_CLP3_CLP3(x) (HW_ADC_CLP3(x).B.CLP3)
1694 /*! @brief Format value for bitfield ADC_CLP3_CLP3. */
1695 #define BF_ADC_CLP3_CLP3(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLP3_CLP3) & BM_ADC_CLP3_CLP3)
1697 /*! @brief Set the CLP3 field to a new value. */
1698 #define BW_ADC_CLP3_CLP3(x, v) (HW_ADC_CLP3_WR(x, (HW_ADC_CLP3_RD(x) & ~BM_ADC_CLP3_CLP3) | BF_ADC_CLP3_CLP3(v)))
1701 /*******************************************************************************
1702 * HW_ADC_CLP2 - ADC Plus-Side General Calibration Value Register
1703 ******************************************************************************/
1706 * @brief HW_ADC_CLP2 - ADC Plus-Side General Calibration Value Register (RW)
1708 * Reset value: 0x00000080U
1710 * For more information, see CLPD register description.
1712 typedef union _hw_adc_clp2
1715 struct _hw_adc_clp2_bitfields
1717 uint32_t CLP2
: 8; /*!< [7:0] */
1718 uint32_t RESERVED0
: 24; /*!< [31:8] */
1723 * @name Constants and macros for entire ADC_CLP2 register
1726 #define HW_ADC_CLP2_ADDR(x) ((x) + 0x44U)
1728 #define HW_ADC_CLP2(x) (*(__IO hw_adc_clp2_t *) HW_ADC_CLP2_ADDR(x))
1729 #define HW_ADC_CLP2_RD(x) (HW_ADC_CLP2(x).U)
1730 #define HW_ADC_CLP2_WR(x, v) (HW_ADC_CLP2(x).U = (v))
1731 #define HW_ADC_CLP2_SET(x, v) (HW_ADC_CLP2_WR(x, HW_ADC_CLP2_RD(x) | (v)))
1732 #define HW_ADC_CLP2_CLR(x, v) (HW_ADC_CLP2_WR(x, HW_ADC_CLP2_RD(x) & ~(v)))
1733 #define HW_ADC_CLP2_TOG(x, v) (HW_ADC_CLP2_WR(x, HW_ADC_CLP2_RD(x) ^ (v)))
1737 * Constants & macros for individual ADC_CLP2 bitfields
1741 * @name Register ADC_CLP2, field CLP2[7:0] (RW)
1746 #define BP_ADC_CLP2_CLP2 (0U) /*!< Bit position for ADC_CLP2_CLP2. */
1747 #define BM_ADC_CLP2_CLP2 (0x000000FFU) /*!< Bit mask for ADC_CLP2_CLP2. */
1748 #define BS_ADC_CLP2_CLP2 (8U) /*!< Bit field size in bits for ADC_CLP2_CLP2. */
1750 /*! @brief Read current value of the ADC_CLP2_CLP2 field. */
1751 #define BR_ADC_CLP2_CLP2(x) (HW_ADC_CLP2(x).B.CLP2)
1753 /*! @brief Format value for bitfield ADC_CLP2_CLP2. */
1754 #define BF_ADC_CLP2_CLP2(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLP2_CLP2) & BM_ADC_CLP2_CLP2)
1756 /*! @brief Set the CLP2 field to a new value. */
1757 #define BW_ADC_CLP2_CLP2(x, v) (HW_ADC_CLP2_WR(x, (HW_ADC_CLP2_RD(x) & ~BM_ADC_CLP2_CLP2) | BF_ADC_CLP2_CLP2(v)))
1760 /*******************************************************************************
1761 * HW_ADC_CLP1 - ADC Plus-Side General Calibration Value Register
1762 ******************************************************************************/
1765 * @brief HW_ADC_CLP1 - ADC Plus-Side General Calibration Value Register (RW)
1767 * Reset value: 0x00000040U
1769 * For more information, see CLPD register description.
1771 typedef union _hw_adc_clp1
1774 struct _hw_adc_clp1_bitfields
1776 uint32_t CLP1
: 7; /*!< [6:0] */
1777 uint32_t RESERVED0
: 25; /*!< [31:7] */
1782 * @name Constants and macros for entire ADC_CLP1 register
1785 #define HW_ADC_CLP1_ADDR(x) ((x) + 0x48U)
1787 #define HW_ADC_CLP1(x) (*(__IO hw_adc_clp1_t *) HW_ADC_CLP1_ADDR(x))
1788 #define HW_ADC_CLP1_RD(x) (HW_ADC_CLP1(x).U)
1789 #define HW_ADC_CLP1_WR(x, v) (HW_ADC_CLP1(x).U = (v))
1790 #define HW_ADC_CLP1_SET(x, v) (HW_ADC_CLP1_WR(x, HW_ADC_CLP1_RD(x) | (v)))
1791 #define HW_ADC_CLP1_CLR(x, v) (HW_ADC_CLP1_WR(x, HW_ADC_CLP1_RD(x) & ~(v)))
1792 #define HW_ADC_CLP1_TOG(x, v) (HW_ADC_CLP1_WR(x, HW_ADC_CLP1_RD(x) ^ (v)))
1796 * Constants & macros for individual ADC_CLP1 bitfields
1800 * @name Register ADC_CLP1, field CLP1[6:0] (RW)
1805 #define BP_ADC_CLP1_CLP1 (0U) /*!< Bit position for ADC_CLP1_CLP1. */
1806 #define BM_ADC_CLP1_CLP1 (0x0000007FU) /*!< Bit mask for ADC_CLP1_CLP1. */
1807 #define BS_ADC_CLP1_CLP1 (7U) /*!< Bit field size in bits for ADC_CLP1_CLP1. */
1809 /*! @brief Read current value of the ADC_CLP1_CLP1 field. */
1810 #define BR_ADC_CLP1_CLP1(x) (HW_ADC_CLP1(x).B.CLP1)
1812 /*! @brief Format value for bitfield ADC_CLP1_CLP1. */
1813 #define BF_ADC_CLP1_CLP1(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLP1_CLP1) & BM_ADC_CLP1_CLP1)
1815 /*! @brief Set the CLP1 field to a new value. */
1816 #define BW_ADC_CLP1_CLP1(x, v) (HW_ADC_CLP1_WR(x, (HW_ADC_CLP1_RD(x) & ~BM_ADC_CLP1_CLP1) | BF_ADC_CLP1_CLP1(v)))
1819 /*******************************************************************************
1820 * HW_ADC_CLP0 - ADC Plus-Side General Calibration Value Register
1821 ******************************************************************************/
1824 * @brief HW_ADC_CLP0 - ADC Plus-Side General Calibration Value Register (RW)
1826 * Reset value: 0x00000020U
1828 * For more information, see CLPD register description.
1830 typedef union _hw_adc_clp0
1833 struct _hw_adc_clp0_bitfields
1835 uint32_t CLP0
: 6; /*!< [5:0] */
1836 uint32_t RESERVED0
: 26; /*!< [31:6] */
1841 * @name Constants and macros for entire ADC_CLP0 register
1844 #define HW_ADC_CLP0_ADDR(x) ((x) + 0x4CU)
1846 #define HW_ADC_CLP0(x) (*(__IO hw_adc_clp0_t *) HW_ADC_CLP0_ADDR(x))
1847 #define HW_ADC_CLP0_RD(x) (HW_ADC_CLP0(x).U)
1848 #define HW_ADC_CLP0_WR(x, v) (HW_ADC_CLP0(x).U = (v))
1849 #define HW_ADC_CLP0_SET(x, v) (HW_ADC_CLP0_WR(x, HW_ADC_CLP0_RD(x) | (v)))
1850 #define HW_ADC_CLP0_CLR(x, v) (HW_ADC_CLP0_WR(x, HW_ADC_CLP0_RD(x) & ~(v)))
1851 #define HW_ADC_CLP0_TOG(x, v) (HW_ADC_CLP0_WR(x, HW_ADC_CLP0_RD(x) ^ (v)))
1855 * Constants & macros for individual ADC_CLP0 bitfields
1859 * @name Register ADC_CLP0, field CLP0[5:0] (RW)
1864 #define BP_ADC_CLP0_CLP0 (0U) /*!< Bit position for ADC_CLP0_CLP0. */
1865 #define BM_ADC_CLP0_CLP0 (0x0000003FU) /*!< Bit mask for ADC_CLP0_CLP0. */
1866 #define BS_ADC_CLP0_CLP0 (6U) /*!< Bit field size in bits for ADC_CLP0_CLP0. */
1868 /*! @brief Read current value of the ADC_CLP0_CLP0 field. */
1869 #define BR_ADC_CLP0_CLP0(x) (HW_ADC_CLP0(x).B.CLP0)
1871 /*! @brief Format value for bitfield ADC_CLP0_CLP0. */
1872 #define BF_ADC_CLP0_CLP0(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLP0_CLP0) & BM_ADC_CLP0_CLP0)
1874 /*! @brief Set the CLP0 field to a new value. */
1875 #define BW_ADC_CLP0_CLP0(x, v) (HW_ADC_CLP0_WR(x, (HW_ADC_CLP0_RD(x) & ~BM_ADC_CLP0_CLP0) | BF_ADC_CLP0_CLP0(v)))
1878 /*******************************************************************************
1879 * HW_ADC_CLMD - ADC Minus-Side General Calibration Value Register
1880 ******************************************************************************/
1883 * @brief HW_ADC_CLMD - ADC Minus-Side General Calibration Value Register (RW)
1885 * Reset value: 0x0000000AU
1887 * The Minus-Side General Calibration Value (CLMx) registers contain calibration
1888 * information that is generated by the calibration function. These registers
1889 * contain seven calibration values of varying widths: CLM0[5:0], CLM1[6:0],
1890 * CLM2[7:0], CLM3[8:0], CLM4[9:0], CLMS[5:0], and CLMD[5:0]. CLMx are automatically
1891 * set when the self-calibration sequence is done, that is, CAL is cleared. If
1892 * these registers are written by the user after calibration, the linearity error
1893 * specifications may not be met.
1895 typedef union _hw_adc_clmd
1898 struct _hw_adc_clmd_bitfields
1900 uint32_t CLMD
: 6; /*!< [5:0] */
1901 uint32_t RESERVED0
: 26; /*!< [31:6] */
1906 * @name Constants and macros for entire ADC_CLMD register
1909 #define HW_ADC_CLMD_ADDR(x) ((x) + 0x54U)
1911 #define HW_ADC_CLMD(x) (*(__IO hw_adc_clmd_t *) HW_ADC_CLMD_ADDR(x))
1912 #define HW_ADC_CLMD_RD(x) (HW_ADC_CLMD(x).U)
1913 #define HW_ADC_CLMD_WR(x, v) (HW_ADC_CLMD(x).U = (v))
1914 #define HW_ADC_CLMD_SET(x, v) (HW_ADC_CLMD_WR(x, HW_ADC_CLMD_RD(x) | (v)))
1915 #define HW_ADC_CLMD_CLR(x, v) (HW_ADC_CLMD_WR(x, HW_ADC_CLMD_RD(x) & ~(v)))
1916 #define HW_ADC_CLMD_TOG(x, v) (HW_ADC_CLMD_WR(x, HW_ADC_CLMD_RD(x) ^ (v)))
1920 * Constants & macros for individual ADC_CLMD bitfields
1924 * @name Register ADC_CLMD, field CLMD[5:0] (RW)
1929 #define BP_ADC_CLMD_CLMD (0U) /*!< Bit position for ADC_CLMD_CLMD. */
1930 #define BM_ADC_CLMD_CLMD (0x0000003FU) /*!< Bit mask for ADC_CLMD_CLMD. */
1931 #define BS_ADC_CLMD_CLMD (6U) /*!< Bit field size in bits for ADC_CLMD_CLMD. */
1933 /*! @brief Read current value of the ADC_CLMD_CLMD field. */
1934 #define BR_ADC_CLMD_CLMD(x) (HW_ADC_CLMD(x).B.CLMD)
1936 /*! @brief Format value for bitfield ADC_CLMD_CLMD. */
1937 #define BF_ADC_CLMD_CLMD(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLMD_CLMD) & BM_ADC_CLMD_CLMD)
1939 /*! @brief Set the CLMD field to a new value. */
1940 #define BW_ADC_CLMD_CLMD(x, v) (HW_ADC_CLMD_WR(x, (HW_ADC_CLMD_RD(x) & ~BM_ADC_CLMD_CLMD) | BF_ADC_CLMD_CLMD(v)))
1943 /*******************************************************************************
1944 * HW_ADC_CLMS - ADC Minus-Side General Calibration Value Register
1945 ******************************************************************************/
1948 * @brief HW_ADC_CLMS - ADC Minus-Side General Calibration Value Register (RW)
1950 * Reset value: 0x00000020U
1952 * For more information, see CLMD register description.
1954 typedef union _hw_adc_clms
1957 struct _hw_adc_clms_bitfields
1959 uint32_t CLMS
: 6; /*!< [5:0] */
1960 uint32_t RESERVED0
: 26; /*!< [31:6] */
1965 * @name Constants and macros for entire ADC_CLMS register
1968 #define HW_ADC_CLMS_ADDR(x) ((x) + 0x58U)
1970 #define HW_ADC_CLMS(x) (*(__IO hw_adc_clms_t *) HW_ADC_CLMS_ADDR(x))
1971 #define HW_ADC_CLMS_RD(x) (HW_ADC_CLMS(x).U)
1972 #define HW_ADC_CLMS_WR(x, v) (HW_ADC_CLMS(x).U = (v))
1973 #define HW_ADC_CLMS_SET(x, v) (HW_ADC_CLMS_WR(x, HW_ADC_CLMS_RD(x) | (v)))
1974 #define HW_ADC_CLMS_CLR(x, v) (HW_ADC_CLMS_WR(x, HW_ADC_CLMS_RD(x) & ~(v)))
1975 #define HW_ADC_CLMS_TOG(x, v) (HW_ADC_CLMS_WR(x, HW_ADC_CLMS_RD(x) ^ (v)))
1979 * Constants & macros for individual ADC_CLMS bitfields
1983 * @name Register ADC_CLMS, field CLMS[5:0] (RW)
1988 #define BP_ADC_CLMS_CLMS (0U) /*!< Bit position for ADC_CLMS_CLMS. */
1989 #define BM_ADC_CLMS_CLMS (0x0000003FU) /*!< Bit mask for ADC_CLMS_CLMS. */
1990 #define BS_ADC_CLMS_CLMS (6U) /*!< Bit field size in bits for ADC_CLMS_CLMS. */
1992 /*! @brief Read current value of the ADC_CLMS_CLMS field. */
1993 #define BR_ADC_CLMS_CLMS(x) (HW_ADC_CLMS(x).B.CLMS)
1995 /*! @brief Format value for bitfield ADC_CLMS_CLMS. */
1996 #define BF_ADC_CLMS_CLMS(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLMS_CLMS) & BM_ADC_CLMS_CLMS)
1998 /*! @brief Set the CLMS field to a new value. */
1999 #define BW_ADC_CLMS_CLMS(x, v) (HW_ADC_CLMS_WR(x, (HW_ADC_CLMS_RD(x) & ~BM_ADC_CLMS_CLMS) | BF_ADC_CLMS_CLMS(v)))
2002 /*******************************************************************************
2003 * HW_ADC_CLM4 - ADC Minus-Side General Calibration Value Register
2004 ******************************************************************************/
2007 * @brief HW_ADC_CLM4 - ADC Minus-Side General Calibration Value Register (RW)
2009 * Reset value: 0x00000200U
2011 * For more information, see CLMD register description.
2013 typedef union _hw_adc_clm4
2016 struct _hw_adc_clm4_bitfields
2018 uint32_t CLM4
: 10; /*!< [9:0] */
2019 uint32_t RESERVED0
: 22; /*!< [31:10] */
2024 * @name Constants and macros for entire ADC_CLM4 register
2027 #define HW_ADC_CLM4_ADDR(x) ((x) + 0x5CU)
2029 #define HW_ADC_CLM4(x) (*(__IO hw_adc_clm4_t *) HW_ADC_CLM4_ADDR(x))
2030 #define HW_ADC_CLM4_RD(x) (HW_ADC_CLM4(x).U)
2031 #define HW_ADC_CLM4_WR(x, v) (HW_ADC_CLM4(x).U = (v))
2032 #define HW_ADC_CLM4_SET(x, v) (HW_ADC_CLM4_WR(x, HW_ADC_CLM4_RD(x) | (v)))
2033 #define HW_ADC_CLM4_CLR(x, v) (HW_ADC_CLM4_WR(x, HW_ADC_CLM4_RD(x) & ~(v)))
2034 #define HW_ADC_CLM4_TOG(x, v) (HW_ADC_CLM4_WR(x, HW_ADC_CLM4_RD(x) ^ (v)))
2038 * Constants & macros for individual ADC_CLM4 bitfields
2042 * @name Register ADC_CLM4, field CLM4[9:0] (RW)
2047 #define BP_ADC_CLM4_CLM4 (0U) /*!< Bit position for ADC_CLM4_CLM4. */
2048 #define BM_ADC_CLM4_CLM4 (0x000003FFU) /*!< Bit mask for ADC_CLM4_CLM4. */
2049 #define BS_ADC_CLM4_CLM4 (10U) /*!< Bit field size in bits for ADC_CLM4_CLM4. */
2051 /*! @brief Read current value of the ADC_CLM4_CLM4 field. */
2052 #define BR_ADC_CLM4_CLM4(x) (HW_ADC_CLM4(x).B.CLM4)
2054 /*! @brief Format value for bitfield ADC_CLM4_CLM4. */
2055 #define BF_ADC_CLM4_CLM4(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLM4_CLM4) & BM_ADC_CLM4_CLM4)
2057 /*! @brief Set the CLM4 field to a new value. */
2058 #define BW_ADC_CLM4_CLM4(x, v) (HW_ADC_CLM4_WR(x, (HW_ADC_CLM4_RD(x) & ~BM_ADC_CLM4_CLM4) | BF_ADC_CLM4_CLM4(v)))
2061 /*******************************************************************************
2062 * HW_ADC_CLM3 - ADC Minus-Side General Calibration Value Register
2063 ******************************************************************************/
2066 * @brief HW_ADC_CLM3 - ADC Minus-Side General Calibration Value Register (RW)
2068 * Reset value: 0x00000100U
2070 * For more information, see CLMD register description.
2072 typedef union _hw_adc_clm3
2075 struct _hw_adc_clm3_bitfields
2077 uint32_t CLM3
: 9; /*!< [8:0] */
2078 uint32_t RESERVED0
: 23; /*!< [31:9] */
2083 * @name Constants and macros for entire ADC_CLM3 register
2086 #define HW_ADC_CLM3_ADDR(x) ((x) + 0x60U)
2088 #define HW_ADC_CLM3(x) (*(__IO hw_adc_clm3_t *) HW_ADC_CLM3_ADDR(x))
2089 #define HW_ADC_CLM3_RD(x) (HW_ADC_CLM3(x).U)
2090 #define HW_ADC_CLM3_WR(x, v) (HW_ADC_CLM3(x).U = (v))
2091 #define HW_ADC_CLM3_SET(x, v) (HW_ADC_CLM3_WR(x, HW_ADC_CLM3_RD(x) | (v)))
2092 #define HW_ADC_CLM3_CLR(x, v) (HW_ADC_CLM3_WR(x, HW_ADC_CLM3_RD(x) & ~(v)))
2093 #define HW_ADC_CLM3_TOG(x, v) (HW_ADC_CLM3_WR(x, HW_ADC_CLM3_RD(x) ^ (v)))
2097 * Constants & macros for individual ADC_CLM3 bitfields
2101 * @name Register ADC_CLM3, field CLM3[8:0] (RW)
2106 #define BP_ADC_CLM3_CLM3 (0U) /*!< Bit position for ADC_CLM3_CLM3. */
2107 #define BM_ADC_CLM3_CLM3 (0x000001FFU) /*!< Bit mask for ADC_CLM3_CLM3. */
2108 #define BS_ADC_CLM3_CLM3 (9U) /*!< Bit field size in bits for ADC_CLM3_CLM3. */
2110 /*! @brief Read current value of the ADC_CLM3_CLM3 field. */
2111 #define BR_ADC_CLM3_CLM3(x) (HW_ADC_CLM3(x).B.CLM3)
2113 /*! @brief Format value for bitfield ADC_CLM3_CLM3. */
2114 #define BF_ADC_CLM3_CLM3(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLM3_CLM3) & BM_ADC_CLM3_CLM3)
2116 /*! @brief Set the CLM3 field to a new value. */
2117 #define BW_ADC_CLM3_CLM3(x, v) (HW_ADC_CLM3_WR(x, (HW_ADC_CLM3_RD(x) & ~BM_ADC_CLM3_CLM3) | BF_ADC_CLM3_CLM3(v)))
2120 /*******************************************************************************
2121 * HW_ADC_CLM2 - ADC Minus-Side General Calibration Value Register
2122 ******************************************************************************/
2125 * @brief HW_ADC_CLM2 - ADC Minus-Side General Calibration Value Register (RW)
2127 * Reset value: 0x00000080U
2129 * For more information, see CLMD register description.
2131 typedef union _hw_adc_clm2
2134 struct _hw_adc_clm2_bitfields
2136 uint32_t CLM2
: 8; /*!< [7:0] */
2137 uint32_t RESERVED0
: 24; /*!< [31:8] */
2142 * @name Constants and macros for entire ADC_CLM2 register
2145 #define HW_ADC_CLM2_ADDR(x) ((x) + 0x64U)
2147 #define HW_ADC_CLM2(x) (*(__IO hw_adc_clm2_t *) HW_ADC_CLM2_ADDR(x))
2148 #define HW_ADC_CLM2_RD(x) (HW_ADC_CLM2(x).U)
2149 #define HW_ADC_CLM2_WR(x, v) (HW_ADC_CLM2(x).U = (v))
2150 #define HW_ADC_CLM2_SET(x, v) (HW_ADC_CLM2_WR(x, HW_ADC_CLM2_RD(x) | (v)))
2151 #define HW_ADC_CLM2_CLR(x, v) (HW_ADC_CLM2_WR(x, HW_ADC_CLM2_RD(x) & ~(v)))
2152 #define HW_ADC_CLM2_TOG(x, v) (HW_ADC_CLM2_WR(x, HW_ADC_CLM2_RD(x) ^ (v)))
2156 * Constants & macros for individual ADC_CLM2 bitfields
2160 * @name Register ADC_CLM2, field CLM2[7:0] (RW)
2165 #define BP_ADC_CLM2_CLM2 (0U) /*!< Bit position for ADC_CLM2_CLM2. */
2166 #define BM_ADC_CLM2_CLM2 (0x000000FFU) /*!< Bit mask for ADC_CLM2_CLM2. */
2167 #define BS_ADC_CLM2_CLM2 (8U) /*!< Bit field size in bits for ADC_CLM2_CLM2. */
2169 /*! @brief Read current value of the ADC_CLM2_CLM2 field. */
2170 #define BR_ADC_CLM2_CLM2(x) (HW_ADC_CLM2(x).B.CLM2)
2172 /*! @brief Format value for bitfield ADC_CLM2_CLM2. */
2173 #define BF_ADC_CLM2_CLM2(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLM2_CLM2) & BM_ADC_CLM2_CLM2)
2175 /*! @brief Set the CLM2 field to a new value. */
2176 #define BW_ADC_CLM2_CLM2(x, v) (HW_ADC_CLM2_WR(x, (HW_ADC_CLM2_RD(x) & ~BM_ADC_CLM2_CLM2) | BF_ADC_CLM2_CLM2(v)))
2179 /*******************************************************************************
2180 * HW_ADC_CLM1 - ADC Minus-Side General Calibration Value Register
2181 ******************************************************************************/
2184 * @brief HW_ADC_CLM1 - ADC Minus-Side General Calibration Value Register (RW)
2186 * Reset value: 0x00000040U
2188 * For more information, see CLMD register description.
2190 typedef union _hw_adc_clm1
2193 struct _hw_adc_clm1_bitfields
2195 uint32_t CLM1
: 7; /*!< [6:0] */
2196 uint32_t RESERVED0
: 25; /*!< [31:7] */
2201 * @name Constants and macros for entire ADC_CLM1 register
2204 #define HW_ADC_CLM1_ADDR(x) ((x) + 0x68U)
2206 #define HW_ADC_CLM1(x) (*(__IO hw_adc_clm1_t *) HW_ADC_CLM1_ADDR(x))
2207 #define HW_ADC_CLM1_RD(x) (HW_ADC_CLM1(x).U)
2208 #define HW_ADC_CLM1_WR(x, v) (HW_ADC_CLM1(x).U = (v))
2209 #define HW_ADC_CLM1_SET(x, v) (HW_ADC_CLM1_WR(x, HW_ADC_CLM1_RD(x) | (v)))
2210 #define HW_ADC_CLM1_CLR(x, v) (HW_ADC_CLM1_WR(x, HW_ADC_CLM1_RD(x) & ~(v)))
2211 #define HW_ADC_CLM1_TOG(x, v) (HW_ADC_CLM1_WR(x, HW_ADC_CLM1_RD(x) ^ (v)))
2215 * Constants & macros for individual ADC_CLM1 bitfields
2219 * @name Register ADC_CLM1, field CLM1[6:0] (RW)
2224 #define BP_ADC_CLM1_CLM1 (0U) /*!< Bit position for ADC_CLM1_CLM1. */
2225 #define BM_ADC_CLM1_CLM1 (0x0000007FU) /*!< Bit mask for ADC_CLM1_CLM1. */
2226 #define BS_ADC_CLM1_CLM1 (7U) /*!< Bit field size in bits for ADC_CLM1_CLM1. */
2228 /*! @brief Read current value of the ADC_CLM1_CLM1 field. */
2229 #define BR_ADC_CLM1_CLM1(x) (HW_ADC_CLM1(x).B.CLM1)
2231 /*! @brief Format value for bitfield ADC_CLM1_CLM1. */
2232 #define BF_ADC_CLM1_CLM1(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLM1_CLM1) & BM_ADC_CLM1_CLM1)
2234 /*! @brief Set the CLM1 field to a new value. */
2235 #define BW_ADC_CLM1_CLM1(x, v) (HW_ADC_CLM1_WR(x, (HW_ADC_CLM1_RD(x) & ~BM_ADC_CLM1_CLM1) | BF_ADC_CLM1_CLM1(v)))
2238 /*******************************************************************************
2239 * HW_ADC_CLM0 - ADC Minus-Side General Calibration Value Register
2240 ******************************************************************************/
2243 * @brief HW_ADC_CLM0 - ADC Minus-Side General Calibration Value Register (RW)
2245 * Reset value: 0x00000020U
2247 * For more information, see CLMD register description.
2249 typedef union _hw_adc_clm0
2252 struct _hw_adc_clm0_bitfields
2254 uint32_t CLM0
: 6; /*!< [5:0] */
2255 uint32_t RESERVED0
: 26; /*!< [31:6] */
2260 * @name Constants and macros for entire ADC_CLM0 register
2263 #define HW_ADC_CLM0_ADDR(x) ((x) + 0x6CU)
2265 #define HW_ADC_CLM0(x) (*(__IO hw_adc_clm0_t *) HW_ADC_CLM0_ADDR(x))
2266 #define HW_ADC_CLM0_RD(x) (HW_ADC_CLM0(x).U)
2267 #define HW_ADC_CLM0_WR(x, v) (HW_ADC_CLM0(x).U = (v))
2268 #define HW_ADC_CLM0_SET(x, v) (HW_ADC_CLM0_WR(x, HW_ADC_CLM0_RD(x) | (v)))
2269 #define HW_ADC_CLM0_CLR(x, v) (HW_ADC_CLM0_WR(x, HW_ADC_CLM0_RD(x) & ~(v)))
2270 #define HW_ADC_CLM0_TOG(x, v) (HW_ADC_CLM0_WR(x, HW_ADC_CLM0_RD(x) ^ (v)))
2274 * Constants & macros for individual ADC_CLM0 bitfields
2278 * @name Register ADC_CLM0, field CLM0[5:0] (RW)
2283 #define BP_ADC_CLM0_CLM0 (0U) /*!< Bit position for ADC_CLM0_CLM0. */
2284 #define BM_ADC_CLM0_CLM0 (0x0000003FU) /*!< Bit mask for ADC_CLM0_CLM0. */
2285 #define BS_ADC_CLM0_CLM0 (6U) /*!< Bit field size in bits for ADC_CLM0_CLM0. */
2287 /*! @brief Read current value of the ADC_CLM0_CLM0 field. */
2288 #define BR_ADC_CLM0_CLM0(x) (HW_ADC_CLM0(x).B.CLM0)
2290 /*! @brief Format value for bitfield ADC_CLM0_CLM0. */
2291 #define BF_ADC_CLM0_CLM0(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLM0_CLM0) & BM_ADC_CLM0_CLM0)
2293 /*! @brief Set the CLM0 field to a new value. */
2294 #define BW_ADC_CLM0_CLM0(x, v) (HW_ADC_CLM0_WR(x, (HW_ADC_CLM0_RD(x) & ~BM_ADC_CLM0_CLM0) | BF_ADC_CLM0_CLM0(v)))
2297 /*******************************************************************************
2298 * hw_adc_t - module struct
2299 ******************************************************************************/
2301 * @brief All ADC module registers.
2304 typedef struct _hw_adc
2306 __IO hw_adc_sc1n_t SC1n
[2]; /*!< [0x0] ADC Status and Control Registers 1 */
2307 __IO hw_adc_cfg1_t CFG1
; /*!< [0x8] ADC Configuration Register 1 */
2308 __IO hw_adc_cfg2_t CFG2
; /*!< [0xC] ADC Configuration Register 2 */
2309 __I hw_adc_rn_t Rn
[2]; /*!< [0x10] ADC Data Result Register */
2310 __IO hw_adc_cv1_t CV1
; /*!< [0x18] Compare Value Registers */
2311 __IO hw_adc_cv2_t CV2
; /*!< [0x1C] Compare Value Registers */
2312 __IO hw_adc_sc2_t SC2
; /*!< [0x20] Status and Control Register 2 */
2313 __IO hw_adc_sc3_t SC3
; /*!< [0x24] Status and Control Register 3 */
2314 __IO hw_adc_ofs_t OFS
; /*!< [0x28] ADC Offset Correction Register */
2315 __IO hw_adc_pg_t PG
; /*!< [0x2C] ADC Plus-Side Gain Register */
2316 __IO hw_adc_mg_t MG
; /*!< [0x30] ADC Minus-Side Gain Register */
2317 __IO hw_adc_clpd_t CLPD
; /*!< [0x34] ADC Plus-Side General Calibration Value Register */
2318 __IO hw_adc_clps_t CLPS
; /*!< [0x38] ADC Plus-Side General Calibration Value Register */
2319 __IO hw_adc_clp4_t CLP4
; /*!< [0x3C] ADC Plus-Side General Calibration Value Register */
2320 __IO hw_adc_clp3_t CLP3
; /*!< [0x40] ADC Plus-Side General Calibration Value Register */
2321 __IO hw_adc_clp2_t CLP2
; /*!< [0x44] ADC Plus-Side General Calibration Value Register */
2322 __IO hw_adc_clp1_t CLP1
; /*!< [0x48] ADC Plus-Side General Calibration Value Register */
2323 __IO hw_adc_clp0_t CLP0
; /*!< [0x4C] ADC Plus-Side General Calibration Value Register */
2324 uint8_t _reserved0
[4];
2325 __IO hw_adc_clmd_t CLMD
; /*!< [0x54] ADC Minus-Side General Calibration Value Register */
2326 __IO hw_adc_clms_t CLMS
; /*!< [0x58] ADC Minus-Side General Calibration Value Register */
2327 __IO hw_adc_clm4_t CLM4
; /*!< [0x5C] ADC Minus-Side General Calibration Value Register */
2328 __IO hw_adc_clm3_t CLM3
; /*!< [0x60] ADC Minus-Side General Calibration Value Register */
2329 __IO hw_adc_clm2_t CLM2
; /*!< [0x64] ADC Minus-Side General Calibration Value Register */
2330 __IO hw_adc_clm1_t CLM1
; /*!< [0x68] ADC Minus-Side General Calibration Value Register */
2331 __IO hw_adc_clm0_t CLM0
; /*!< [0x6C] ADC Minus-Side General Calibration Value Register */
2335 /*! @brief Macro to access all ADC registers. */
2336 /*! @param x ADC module instance base address. */
2337 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
2338 * use the '&' operator, like <code>&HW_ADC(ADC0_BASE)</code>. */
2339 #define HW_ADC(x) (*(hw_adc_t *)(x))
2341 #endif /* __HW_ADC_REGISTERS_H__ */