2 ** ###################################################################
3 ** Compilers: Keil ARM C/C++ Compiler
4 ** Freescale C/C++ for Embedded ARM
6 ** IAR ANSI C/C++ Compiler for ARM
8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
9 ** Version: rev. 2.5, 2014-02-10
13 ** Extension to the CMSIS register access layer header.
15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
16 ** All rights reserved.
18 ** Redistribution and use in source and binary forms, with or without modification,
19 ** are permitted provided that the following conditions are met:
21 ** o Redistributions of source code must retain the above copyright notice, this list
22 ** of conditions and the following disclaimer.
24 ** o Redistributions in binary form must reproduce the above copyright notice, this
25 ** list of conditions and the following disclaimer in the documentation and/or
26 ** other materials provided with the distribution.
28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
29 ** contributors may be used to endorse or promote products derived from this
30 ** software without specific prior written permission.
32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ** http: www.freescale.com
44 ** mail: support@freescale.com
47 ** - rev. 1.0 (2013-08-12)
49 ** - rev. 2.0 (2013-10-29)
50 ** Register accessor macros added to the memory map.
51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
52 ** Startup file for gcc has been updated according to CMSIS 3.2.
53 ** System initialization updated.
54 ** MCG - registers updated.
55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
56 ** - rev. 2.1 (2013-10-30)
57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
58 ** - rev. 2.2 (2013-12-09)
59 ** DMA - EARS register removed.
60 ** AIPS0, AIPS1 - MPRA register updated.
61 ** - rev. 2.3 (2014-01-24)
62 ** Update according to reference manual rev. 2
63 ** ENET, MCG, MCM, SIM, USB - registers updated
64 ** - rev. 2.4 (2014-02-10)
65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
67 ** - rev. 2.5 (2014-02-10)
68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
72 ** ###################################################################
76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
78 * This file was generated automatically and any changes may be lost.
80 #ifndef __HW_AIPS_REGISTERS_H__
81 #define __HW_AIPS_REGISTERS_H__
84 #include "fsl_bitaccess.h"
91 * Registers defined in this header file:
92 * - HW_AIPS_MPRA - Master Privilege Register A
93 * - HW_AIPS_PACRA - Peripheral Access Control Register
94 * - HW_AIPS_PACRB - Peripheral Access Control Register
95 * - HW_AIPS_PACRC - Peripheral Access Control Register
96 * - HW_AIPS_PACRD - Peripheral Access Control Register
97 * - HW_AIPS_PACRE - Peripheral Access Control Register
98 * - HW_AIPS_PACRF - Peripheral Access Control Register
99 * - HW_AIPS_PACRG - Peripheral Access Control Register
100 * - HW_AIPS_PACRH - Peripheral Access Control Register
101 * - HW_AIPS_PACRI - Peripheral Access Control Register
102 * - HW_AIPS_PACRJ - Peripheral Access Control Register
103 * - HW_AIPS_PACRK - Peripheral Access Control Register
104 * - HW_AIPS_PACRL - Peripheral Access Control Register
105 * - HW_AIPS_PACRM - Peripheral Access Control Register
106 * - HW_AIPS_PACRN - Peripheral Access Control Register
107 * - HW_AIPS_PACRO - Peripheral Access Control Register
108 * - HW_AIPS_PACRP - Peripheral Access Control Register
109 * - HW_AIPS_PACRU - Peripheral Access Control Register
111 * - hw_aips_t - Struct containing all module registers.
114 #define HW_AIPS_INSTANCE_COUNT (2U) /*!< Number of instances of the AIPS module. */
115 #define HW_AIPS0 (0U) /*!< Instance number for AIPS0. */
116 #define HW_AIPS1 (1U) /*!< Instance number for AIPS1. */
118 /*******************************************************************************
119 * HW_AIPS_MPRA - Master Privilege Register A
120 ******************************************************************************/
123 * @brief HW_AIPS_MPRA - Master Privilege Register A (RW)
125 * Reset value: 0x77700000U
127 * The MPRA specifies identical 4-bit fields defining the access-privilege level
128 * associated with a bus master to various peripherals on the chip. The register
129 * provides one field per bus master. At reset, the default value loaded into
130 * the MPRA fields is chip-specific. See the chip configuration details for the
131 * value of a particular device. A register field that maps to an unimplemented
132 * master or peripheral behaves as read-only-zero. Each master is assigned a logical
133 * ID from 0 to 15. See the master logical ID assignment table in the
134 * chip-specific AIPS information.
136 typedef union _hw_aips_mpra
139 struct _hw_aips_mpra_bitfields
141 uint32_t RESERVED0
: 8; /*!< [7:0] */
142 uint32_t MPL5
: 1; /*!< [8] Master 5 Privilege Level */
143 uint32_t MTW5
: 1; /*!< [9] Master 5 Trusted For Writes */
144 uint32_t MTR5
: 1; /*!< [10] Master 5 Trusted For Read */
145 uint32_t RESERVED1
: 1; /*!< [11] */
146 uint32_t MPL4
: 1; /*!< [12] Master 4 Privilege Level */
147 uint32_t MTW4
: 1; /*!< [13] Master 4 Trusted For Writes */
148 uint32_t MTR4
: 1; /*!< [14] Master 4 Trusted For Read */
149 uint32_t RESERVED2
: 1; /*!< [15] */
150 uint32_t MPL3
: 1; /*!< [16] Master 3 Privilege Level */
151 uint32_t MTW3
: 1; /*!< [17] Master 3 Trusted For Writes */
152 uint32_t MTR3
: 1; /*!< [18] Master 3 Trusted For Read */
153 uint32_t RESERVED3
: 1; /*!< [19] */
154 uint32_t MPL2
: 1; /*!< [20] Master 2 Privilege Level */
155 uint32_t MTW2
: 1; /*!< [21] Master 2 Trusted For Writes */
156 uint32_t MTR2
: 1; /*!< [22] Master 2 Trusted For Read */
157 uint32_t RESERVED4
: 1; /*!< [23] */
158 uint32_t MPL1
: 1; /*!< [24] Master 1 Privilege Level */
159 uint32_t MTW1
: 1; /*!< [25] Master 1 Trusted for Writes */
160 uint32_t MTR1
: 1; /*!< [26] Master 1 Trusted for Read */
161 uint32_t RESERVED5
: 1; /*!< [27] */
162 uint32_t MPL0
: 1; /*!< [28] Master 0 Privilege Level */
163 uint32_t MTW0
: 1; /*!< [29] Master 0 Trusted For Writes */
164 uint32_t MTR0
: 1; /*!< [30] Master 0 Trusted For Read */
165 uint32_t RESERVED6
: 1; /*!< [31] */
170 * @name Constants and macros for entire AIPS_MPRA register
173 #define HW_AIPS_MPRA_ADDR(x) ((x) + 0x0U)
175 #define HW_AIPS_MPRA(x) (*(__IO hw_aips_mpra_t *) HW_AIPS_MPRA_ADDR(x))
176 #define HW_AIPS_MPRA_RD(x) (HW_AIPS_MPRA(x).U)
177 #define HW_AIPS_MPRA_WR(x, v) (HW_AIPS_MPRA(x).U = (v))
178 #define HW_AIPS_MPRA_SET(x, v) (HW_AIPS_MPRA_WR(x, HW_AIPS_MPRA_RD(x) | (v)))
179 #define HW_AIPS_MPRA_CLR(x, v) (HW_AIPS_MPRA_WR(x, HW_AIPS_MPRA_RD(x) & ~(v)))
180 #define HW_AIPS_MPRA_TOG(x, v) (HW_AIPS_MPRA_WR(x, HW_AIPS_MPRA_RD(x) ^ (v)))
184 * Constants & macros for individual AIPS_MPRA bitfields
188 * @name Register AIPS_MPRA, field MPL5[8] (RW)
190 * Specifies how the privilege level of the master is determined.
193 * - 0 - Accesses from this master are forced to user-mode.
194 * - 1 - Accesses from this master are not forced to user-mode.
197 #define BP_AIPS_MPRA_MPL5 (8U) /*!< Bit position for AIPS_MPRA_MPL5. */
198 #define BM_AIPS_MPRA_MPL5 (0x00000100U) /*!< Bit mask for AIPS_MPRA_MPL5. */
199 #define BS_AIPS_MPRA_MPL5 (1U) /*!< Bit field size in bits for AIPS_MPRA_MPL5. */
201 /*! @brief Read current value of the AIPS_MPRA_MPL5 field. */
202 #define BR_AIPS_MPRA_MPL5(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL5))
204 /*! @brief Format value for bitfield AIPS_MPRA_MPL5. */
205 #define BF_AIPS_MPRA_MPL5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MPL5) & BM_AIPS_MPRA_MPL5)
207 /*! @brief Set the MPL5 field to a new value. */
208 #define BW_AIPS_MPRA_MPL5(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL5) = (v))
212 * @name Register AIPS_MPRA, field MTW5[9] (RW)
214 * Determines whether the master is trusted for write accesses.
217 * - 0 - This master is not trusted for write accesses.
218 * - 1 - This master is trusted for write accesses.
221 #define BP_AIPS_MPRA_MTW5 (9U) /*!< Bit position for AIPS_MPRA_MTW5. */
222 #define BM_AIPS_MPRA_MTW5 (0x00000200U) /*!< Bit mask for AIPS_MPRA_MTW5. */
223 #define BS_AIPS_MPRA_MTW5 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTW5. */
225 /*! @brief Read current value of the AIPS_MPRA_MTW5 field. */
226 #define BR_AIPS_MPRA_MTW5(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW5))
228 /*! @brief Format value for bitfield AIPS_MPRA_MTW5. */
229 #define BF_AIPS_MPRA_MTW5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTW5) & BM_AIPS_MPRA_MTW5)
231 /*! @brief Set the MTW5 field to a new value. */
232 #define BW_AIPS_MPRA_MTW5(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW5) = (v))
236 * @name Register AIPS_MPRA, field MTR5[10] (RW)
238 * Determines whether the master is trusted for read accesses.
241 * - 0 - This master is not trusted for read accesses.
242 * - 1 - This master is trusted for read accesses.
245 #define BP_AIPS_MPRA_MTR5 (10U) /*!< Bit position for AIPS_MPRA_MTR5. */
246 #define BM_AIPS_MPRA_MTR5 (0x00000400U) /*!< Bit mask for AIPS_MPRA_MTR5. */
247 #define BS_AIPS_MPRA_MTR5 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTR5. */
249 /*! @brief Read current value of the AIPS_MPRA_MTR5 field. */
250 #define BR_AIPS_MPRA_MTR5(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR5))
252 /*! @brief Format value for bitfield AIPS_MPRA_MTR5. */
253 #define BF_AIPS_MPRA_MTR5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTR5) & BM_AIPS_MPRA_MTR5)
255 /*! @brief Set the MTR5 field to a new value. */
256 #define BW_AIPS_MPRA_MTR5(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR5) = (v))
260 * @name Register AIPS_MPRA, field MPL4[12] (RW)
262 * Specifies how the privilege level of the master is determined.
265 * - 0 - Accesses from this master are forced to user-mode.
266 * - 1 - Accesses from this master are not forced to user-mode.
269 #define BP_AIPS_MPRA_MPL4 (12U) /*!< Bit position for AIPS_MPRA_MPL4. */
270 #define BM_AIPS_MPRA_MPL4 (0x00001000U) /*!< Bit mask for AIPS_MPRA_MPL4. */
271 #define BS_AIPS_MPRA_MPL4 (1U) /*!< Bit field size in bits for AIPS_MPRA_MPL4. */
273 /*! @brief Read current value of the AIPS_MPRA_MPL4 field. */
274 #define BR_AIPS_MPRA_MPL4(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL4))
276 /*! @brief Format value for bitfield AIPS_MPRA_MPL4. */
277 #define BF_AIPS_MPRA_MPL4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MPL4) & BM_AIPS_MPRA_MPL4)
279 /*! @brief Set the MPL4 field to a new value. */
280 #define BW_AIPS_MPRA_MPL4(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL4) = (v))
284 * @name Register AIPS_MPRA, field MTW4[13] (RW)
286 * Determines whether the master is trusted for write accesses.
289 * - 0 - This master is not trusted for write accesses.
290 * - 1 - This master is trusted for write accesses.
293 #define BP_AIPS_MPRA_MTW4 (13U) /*!< Bit position for AIPS_MPRA_MTW4. */
294 #define BM_AIPS_MPRA_MTW4 (0x00002000U) /*!< Bit mask for AIPS_MPRA_MTW4. */
295 #define BS_AIPS_MPRA_MTW4 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTW4. */
297 /*! @brief Read current value of the AIPS_MPRA_MTW4 field. */
298 #define BR_AIPS_MPRA_MTW4(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW4))
300 /*! @brief Format value for bitfield AIPS_MPRA_MTW4. */
301 #define BF_AIPS_MPRA_MTW4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTW4) & BM_AIPS_MPRA_MTW4)
303 /*! @brief Set the MTW4 field to a new value. */
304 #define BW_AIPS_MPRA_MTW4(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW4) = (v))
308 * @name Register AIPS_MPRA, field MTR4[14] (RW)
310 * Determines whether the master is trusted for read accesses.
313 * - 0 - This master is not trusted for read accesses.
314 * - 1 - This master is trusted for read accesses.
317 #define BP_AIPS_MPRA_MTR4 (14U) /*!< Bit position for AIPS_MPRA_MTR4. */
318 #define BM_AIPS_MPRA_MTR4 (0x00004000U) /*!< Bit mask for AIPS_MPRA_MTR4. */
319 #define BS_AIPS_MPRA_MTR4 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTR4. */
321 /*! @brief Read current value of the AIPS_MPRA_MTR4 field. */
322 #define BR_AIPS_MPRA_MTR4(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR4))
324 /*! @brief Format value for bitfield AIPS_MPRA_MTR4. */
325 #define BF_AIPS_MPRA_MTR4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTR4) & BM_AIPS_MPRA_MTR4)
327 /*! @brief Set the MTR4 field to a new value. */
328 #define BW_AIPS_MPRA_MTR4(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR4) = (v))
332 * @name Register AIPS_MPRA, field MPL3[16] (RW)
334 * Specifies how the privilege level of the master is determined.
337 * - 0 - Accesses from this master are forced to user-mode.
338 * - 1 - Accesses from this master are not forced to user-mode.
341 #define BP_AIPS_MPRA_MPL3 (16U) /*!< Bit position for AIPS_MPRA_MPL3. */
342 #define BM_AIPS_MPRA_MPL3 (0x00010000U) /*!< Bit mask for AIPS_MPRA_MPL3. */
343 #define BS_AIPS_MPRA_MPL3 (1U) /*!< Bit field size in bits for AIPS_MPRA_MPL3. */
345 /*! @brief Read current value of the AIPS_MPRA_MPL3 field. */
346 #define BR_AIPS_MPRA_MPL3(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL3))
348 /*! @brief Format value for bitfield AIPS_MPRA_MPL3. */
349 #define BF_AIPS_MPRA_MPL3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MPL3) & BM_AIPS_MPRA_MPL3)
351 /*! @brief Set the MPL3 field to a new value. */
352 #define BW_AIPS_MPRA_MPL3(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL3) = (v))
356 * @name Register AIPS_MPRA, field MTW3[17] (RW)
358 * Determines whether the master is trusted for write accesses.
361 * - 0 - This master is not trusted for write accesses.
362 * - 1 - This master is trusted for write accesses.
365 #define BP_AIPS_MPRA_MTW3 (17U) /*!< Bit position for AIPS_MPRA_MTW3. */
366 #define BM_AIPS_MPRA_MTW3 (0x00020000U) /*!< Bit mask for AIPS_MPRA_MTW3. */
367 #define BS_AIPS_MPRA_MTW3 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTW3. */
369 /*! @brief Read current value of the AIPS_MPRA_MTW3 field. */
370 #define BR_AIPS_MPRA_MTW3(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW3))
372 /*! @brief Format value for bitfield AIPS_MPRA_MTW3. */
373 #define BF_AIPS_MPRA_MTW3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTW3) & BM_AIPS_MPRA_MTW3)
375 /*! @brief Set the MTW3 field to a new value. */
376 #define BW_AIPS_MPRA_MTW3(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW3) = (v))
380 * @name Register AIPS_MPRA, field MTR3[18] (RW)
382 * Determines whether the master is trusted for read accesses.
385 * - 0 - This master is not trusted for read accesses.
386 * - 1 - This master is trusted for read accesses.
389 #define BP_AIPS_MPRA_MTR3 (18U) /*!< Bit position for AIPS_MPRA_MTR3. */
390 #define BM_AIPS_MPRA_MTR3 (0x00040000U) /*!< Bit mask for AIPS_MPRA_MTR3. */
391 #define BS_AIPS_MPRA_MTR3 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTR3. */
393 /*! @brief Read current value of the AIPS_MPRA_MTR3 field. */
394 #define BR_AIPS_MPRA_MTR3(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR3))
396 /*! @brief Format value for bitfield AIPS_MPRA_MTR3. */
397 #define BF_AIPS_MPRA_MTR3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTR3) & BM_AIPS_MPRA_MTR3)
399 /*! @brief Set the MTR3 field to a new value. */
400 #define BW_AIPS_MPRA_MTR3(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR3) = (v))
404 * @name Register AIPS_MPRA, field MPL2[20] (RW)
406 * Specifies how the privilege level of the master is determined.
409 * - 0 - Accesses from this master are forced to user-mode.
410 * - 1 - Accesses from this master are not forced to user-mode.
413 #define BP_AIPS_MPRA_MPL2 (20U) /*!< Bit position for AIPS_MPRA_MPL2. */
414 #define BM_AIPS_MPRA_MPL2 (0x00100000U) /*!< Bit mask for AIPS_MPRA_MPL2. */
415 #define BS_AIPS_MPRA_MPL2 (1U) /*!< Bit field size in bits for AIPS_MPRA_MPL2. */
417 /*! @brief Read current value of the AIPS_MPRA_MPL2 field. */
418 #define BR_AIPS_MPRA_MPL2(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL2))
420 /*! @brief Format value for bitfield AIPS_MPRA_MPL2. */
421 #define BF_AIPS_MPRA_MPL2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MPL2) & BM_AIPS_MPRA_MPL2)
423 /*! @brief Set the MPL2 field to a new value. */
424 #define BW_AIPS_MPRA_MPL2(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL2) = (v))
428 * @name Register AIPS_MPRA, field MTW2[21] (RW)
430 * Determines whether the master is trusted for write accesses.
433 * - 0 - This master is not trusted for write accesses.
434 * - 1 - This master is trusted for write accesses.
437 #define BP_AIPS_MPRA_MTW2 (21U) /*!< Bit position for AIPS_MPRA_MTW2. */
438 #define BM_AIPS_MPRA_MTW2 (0x00200000U) /*!< Bit mask for AIPS_MPRA_MTW2. */
439 #define BS_AIPS_MPRA_MTW2 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTW2. */
441 /*! @brief Read current value of the AIPS_MPRA_MTW2 field. */
442 #define BR_AIPS_MPRA_MTW2(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW2))
444 /*! @brief Format value for bitfield AIPS_MPRA_MTW2. */
445 #define BF_AIPS_MPRA_MTW2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTW2) & BM_AIPS_MPRA_MTW2)
447 /*! @brief Set the MTW2 field to a new value. */
448 #define BW_AIPS_MPRA_MTW2(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW2) = (v))
452 * @name Register AIPS_MPRA, field MTR2[22] (RW)
454 * Determines whether the master is trusted for read accesses.
457 * - 0 - This master is not trusted for read accesses.
458 * - 1 - This master is trusted for read accesses.
461 #define BP_AIPS_MPRA_MTR2 (22U) /*!< Bit position for AIPS_MPRA_MTR2. */
462 #define BM_AIPS_MPRA_MTR2 (0x00400000U) /*!< Bit mask for AIPS_MPRA_MTR2. */
463 #define BS_AIPS_MPRA_MTR2 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTR2. */
465 /*! @brief Read current value of the AIPS_MPRA_MTR2 field. */
466 #define BR_AIPS_MPRA_MTR2(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR2))
468 /*! @brief Format value for bitfield AIPS_MPRA_MTR2. */
469 #define BF_AIPS_MPRA_MTR2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTR2) & BM_AIPS_MPRA_MTR2)
471 /*! @brief Set the MTR2 field to a new value. */
472 #define BW_AIPS_MPRA_MTR2(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR2) = (v))
476 * @name Register AIPS_MPRA, field MPL1[24] (RW)
478 * Specifies how the privilege level of the master is determined.
481 * - 0 - Accesses from this master are forced to user-mode.
482 * - 1 - Accesses from this master are not forced to user-mode.
485 #define BP_AIPS_MPRA_MPL1 (24U) /*!< Bit position for AIPS_MPRA_MPL1. */
486 #define BM_AIPS_MPRA_MPL1 (0x01000000U) /*!< Bit mask for AIPS_MPRA_MPL1. */
487 #define BS_AIPS_MPRA_MPL1 (1U) /*!< Bit field size in bits for AIPS_MPRA_MPL1. */
489 /*! @brief Read current value of the AIPS_MPRA_MPL1 field. */
490 #define BR_AIPS_MPRA_MPL1(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL1))
492 /*! @brief Format value for bitfield AIPS_MPRA_MPL1. */
493 #define BF_AIPS_MPRA_MPL1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MPL1) & BM_AIPS_MPRA_MPL1)
495 /*! @brief Set the MPL1 field to a new value. */
496 #define BW_AIPS_MPRA_MPL1(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL1) = (v))
500 * @name Register AIPS_MPRA, field MTW1[25] (RW)
502 * Determines whether the master is trusted for write accesses.
505 * - 0 - This master is not trusted for write accesses.
506 * - 1 - This master is trusted for write accesses.
509 #define BP_AIPS_MPRA_MTW1 (25U) /*!< Bit position for AIPS_MPRA_MTW1. */
510 #define BM_AIPS_MPRA_MTW1 (0x02000000U) /*!< Bit mask for AIPS_MPRA_MTW1. */
511 #define BS_AIPS_MPRA_MTW1 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTW1. */
513 /*! @brief Read current value of the AIPS_MPRA_MTW1 field. */
514 #define BR_AIPS_MPRA_MTW1(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW1))
516 /*! @brief Format value for bitfield AIPS_MPRA_MTW1. */
517 #define BF_AIPS_MPRA_MTW1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTW1) & BM_AIPS_MPRA_MTW1)
519 /*! @brief Set the MTW1 field to a new value. */
520 #define BW_AIPS_MPRA_MTW1(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW1) = (v))
524 * @name Register AIPS_MPRA, field MTR1[26] (RW)
526 * Determines whether the master is trusted for read accesses.
529 * - 0 - This master is not trusted for read accesses.
530 * - 1 - This master is trusted for read accesses.
533 #define BP_AIPS_MPRA_MTR1 (26U) /*!< Bit position for AIPS_MPRA_MTR1. */
534 #define BM_AIPS_MPRA_MTR1 (0x04000000U) /*!< Bit mask for AIPS_MPRA_MTR1. */
535 #define BS_AIPS_MPRA_MTR1 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTR1. */
537 /*! @brief Read current value of the AIPS_MPRA_MTR1 field. */
538 #define BR_AIPS_MPRA_MTR1(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR1))
540 /*! @brief Format value for bitfield AIPS_MPRA_MTR1. */
541 #define BF_AIPS_MPRA_MTR1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTR1) & BM_AIPS_MPRA_MTR1)
543 /*! @brief Set the MTR1 field to a new value. */
544 #define BW_AIPS_MPRA_MTR1(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR1) = (v))
548 * @name Register AIPS_MPRA, field MPL0[28] (RW)
550 * Specifies how the privilege level of the master is determined.
553 * - 0 - Accesses from this master are forced to user-mode.
554 * - 1 - Accesses from this master are not forced to user-mode.
557 #define BP_AIPS_MPRA_MPL0 (28U) /*!< Bit position for AIPS_MPRA_MPL0. */
558 #define BM_AIPS_MPRA_MPL0 (0x10000000U) /*!< Bit mask for AIPS_MPRA_MPL0. */
559 #define BS_AIPS_MPRA_MPL0 (1U) /*!< Bit field size in bits for AIPS_MPRA_MPL0. */
561 /*! @brief Read current value of the AIPS_MPRA_MPL0 field. */
562 #define BR_AIPS_MPRA_MPL0(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL0))
564 /*! @brief Format value for bitfield AIPS_MPRA_MPL0. */
565 #define BF_AIPS_MPRA_MPL0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MPL0) & BM_AIPS_MPRA_MPL0)
567 /*! @brief Set the MPL0 field to a new value. */
568 #define BW_AIPS_MPRA_MPL0(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL0) = (v))
572 * @name Register AIPS_MPRA, field MTW0[29] (RW)
574 * Determines whether the master is trusted for write accesses.
577 * - 0 - This master is not trusted for write accesses.
578 * - 1 - This master is trusted for write accesses.
581 #define BP_AIPS_MPRA_MTW0 (29U) /*!< Bit position for AIPS_MPRA_MTW0. */
582 #define BM_AIPS_MPRA_MTW0 (0x20000000U) /*!< Bit mask for AIPS_MPRA_MTW0. */
583 #define BS_AIPS_MPRA_MTW0 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTW0. */
585 /*! @brief Read current value of the AIPS_MPRA_MTW0 field. */
586 #define BR_AIPS_MPRA_MTW0(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW0))
588 /*! @brief Format value for bitfield AIPS_MPRA_MTW0. */
589 #define BF_AIPS_MPRA_MTW0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTW0) & BM_AIPS_MPRA_MTW0)
591 /*! @brief Set the MTW0 field to a new value. */
592 #define BW_AIPS_MPRA_MTW0(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW0) = (v))
596 * @name Register AIPS_MPRA, field MTR0[30] (RW)
598 * Determines whether the master is trusted for read accesses.
601 * - 0 - This master is not trusted for read accesses.
602 * - 1 - This master is trusted for read accesses.
605 #define BP_AIPS_MPRA_MTR0 (30U) /*!< Bit position for AIPS_MPRA_MTR0. */
606 #define BM_AIPS_MPRA_MTR0 (0x40000000U) /*!< Bit mask for AIPS_MPRA_MTR0. */
607 #define BS_AIPS_MPRA_MTR0 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTR0. */
609 /*! @brief Read current value of the AIPS_MPRA_MTR0 field. */
610 #define BR_AIPS_MPRA_MTR0(x) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR0))
612 /*! @brief Format value for bitfield AIPS_MPRA_MTR0. */
613 #define BF_AIPS_MPRA_MTR0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTR0) & BM_AIPS_MPRA_MTR0)
615 /*! @brief Set the MTR0 field to a new value. */
616 #define BW_AIPS_MPRA_MTR0(x, v) (BITBAND_ACCESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR0) = (v))
619 /*******************************************************************************
620 * HW_AIPS_PACRA - Peripheral Access Control Register
621 ******************************************************************************/
624 * @brief HW_AIPS_PACRA - Peripheral Access Control Register (RW)
626 * Reset value: 0x50004000U
628 * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
629 * defines the access levels for a particular peripheral. The mapping between a
630 * peripheral and its PACR field is shown in the table below. The peripheral assignment
631 * to each PACR is defined by the memory map slot that the peripheral is
632 * assigned to. See this chip's memory map for the assignment of a particular
633 * peripheral. The following table shows the location of each peripheral slot's PACR field
634 * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
635 * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
636 * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
637 * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
638 * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
639 * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
640 * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
641 * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
642 * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
643 * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
644 * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
645 * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
646 * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
647 * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
648 * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
649 * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
650 * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
651 * A-D, which control peripheral slots 0-31, are shown below. The following
652 * section, PACRPeripheral Access Control Register , shows the register field
653 * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
654 * sections because they occupy two non-contiguous address spaces.
656 typedef union _hw_aips_pacra
659 struct _hw_aips_pacra_bitfields
661 uint32_t TP7
: 1; /*!< [0] Trusted Protect */
662 uint32_t WP7
: 1; /*!< [1] Write Protect */
663 uint32_t SP7
: 1; /*!< [2] Supervisor Protect */
664 uint32_t RESERVED0
: 1; /*!< [3] */
665 uint32_t TP6
: 1; /*!< [4] Trusted Protect */
666 uint32_t WP6
: 1; /*!< [5] Write Protect */
667 uint32_t SP6
: 1; /*!< [6] Supervisor Protect */
668 uint32_t RESERVED1
: 1; /*!< [7] */
669 uint32_t TP5
: 1; /*!< [8] Trusted Protect */
670 uint32_t WP5
: 1; /*!< [9] Write Protect */
671 uint32_t SP5
: 1; /*!< [10] Supervisor Protect */
672 uint32_t RESERVED2
: 1; /*!< [11] */
673 uint32_t TP4
: 1; /*!< [12] Trusted Protect */
674 uint32_t WP4
: 1; /*!< [13] Write Protect */
675 uint32_t SP4
: 1; /*!< [14] Supervisor Protect */
676 uint32_t RESERVED3
: 1; /*!< [15] */
677 uint32_t TP3
: 1; /*!< [16] Trusted Protect */
678 uint32_t WP3
: 1; /*!< [17] Write Protect */
679 uint32_t SP3
: 1; /*!< [18] Supervisor Protect */
680 uint32_t RESERVED4
: 1; /*!< [19] */
681 uint32_t TP2
: 1; /*!< [20] Trusted Protect */
682 uint32_t WP2
: 1; /*!< [21] Write Protect */
683 uint32_t SP2
: 1; /*!< [22] Supervisor Protect */
684 uint32_t RESERVED5
: 1; /*!< [23] */
685 uint32_t TP1
: 1; /*!< [24] Trusted Protect */
686 uint32_t WP1
: 1; /*!< [25] Write Protect */
687 uint32_t SP1
: 1; /*!< [26] Supervisor Protect */
688 uint32_t RESERVED6
: 1; /*!< [27] */
689 uint32_t TP0
: 1; /*!< [28] Trusted Protect */
690 uint32_t WP0
: 1; /*!< [29] Write Protect */
691 uint32_t SP0
: 1; /*!< [30] Supervisor Protect */
692 uint32_t RESERVED7
: 1; /*!< [31] */
697 * @name Constants and macros for entire AIPS_PACRA register
700 #define HW_AIPS_PACRA_ADDR(x) ((x) + 0x20U)
702 #define HW_AIPS_PACRA(x) (*(__IO hw_aips_pacra_t *) HW_AIPS_PACRA_ADDR(x))
703 #define HW_AIPS_PACRA_RD(x) (HW_AIPS_PACRA(x).U)
704 #define HW_AIPS_PACRA_WR(x, v) (HW_AIPS_PACRA(x).U = (v))
705 #define HW_AIPS_PACRA_SET(x, v) (HW_AIPS_PACRA_WR(x, HW_AIPS_PACRA_RD(x) | (v)))
706 #define HW_AIPS_PACRA_CLR(x, v) (HW_AIPS_PACRA_WR(x, HW_AIPS_PACRA_RD(x) & ~(v)))
707 #define HW_AIPS_PACRA_TOG(x, v) (HW_AIPS_PACRA_WR(x, HW_AIPS_PACRA_RD(x) ^ (v)))
711 * Constants & macros for individual AIPS_PACRA bitfields
715 * @name Register AIPS_PACRA, field TP7[0] (RW)
717 * Determines whether the peripheral allows accesses from an untrusted master.
718 * When this field is set and an access is attempted by an untrusted master, the
719 * access terminates with an error response and no peripheral access initiates.
722 * - 0 - Accesses from an untrusted master are allowed.
723 * - 1 - Accesses from an untrusted master are not allowed.
726 #define BP_AIPS_PACRA_TP7 (0U) /*!< Bit position for AIPS_PACRA_TP7. */
727 #define BM_AIPS_PACRA_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRA_TP7. */
728 #define BS_AIPS_PACRA_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRA_TP7. */
730 /*! @brief Read current value of the AIPS_PACRA_TP7 field. */
731 #define BR_AIPS_PACRA_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP7))
733 /*! @brief Format value for bitfield AIPS_PACRA_TP7. */
734 #define BF_AIPS_PACRA_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_TP7) & BM_AIPS_PACRA_TP7)
736 /*! @brief Set the TP7 field to a new value. */
737 #define BW_AIPS_PACRA_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP7) = (v))
741 * @name Register AIPS_PACRA, field WP7[1] (RW)
743 * Determines whether the peripheral allows write accesses. When this field is
744 * set and a write access is attempted, access terminates with an error response
745 * and no peripheral access initiates.
748 * - 0 - This peripheral allows write accesses.
749 * - 1 - This peripheral is write protected.
752 #define BP_AIPS_PACRA_WP7 (1U) /*!< Bit position for AIPS_PACRA_WP7. */
753 #define BM_AIPS_PACRA_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRA_WP7. */
754 #define BS_AIPS_PACRA_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRA_WP7. */
756 /*! @brief Read current value of the AIPS_PACRA_WP7 field. */
757 #define BR_AIPS_PACRA_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP7))
759 /*! @brief Format value for bitfield AIPS_PACRA_WP7. */
760 #define BF_AIPS_PACRA_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_WP7) & BM_AIPS_PACRA_WP7)
762 /*! @brief Set the WP7 field to a new value. */
763 #define BW_AIPS_PACRA_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP7) = (v))
767 * @name Register AIPS_PACRA, field SP7[2] (RW)
769 * Determines whether the peripheral requires supervisor privilege level for
770 * accesses. When this field is set, the master privilege level must indicate the
771 * supervisor access attribute, and the MPRx[MPLn] control field for the master
772 * must be set. If not, access terminates with an error response and no peripheral
776 * - 0 - This peripheral does not require supervisor privilege level for
778 * - 1 - This peripheral requires supervisor privilege level for accesses.
781 #define BP_AIPS_PACRA_SP7 (2U) /*!< Bit position for AIPS_PACRA_SP7. */
782 #define BM_AIPS_PACRA_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRA_SP7. */
783 #define BS_AIPS_PACRA_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRA_SP7. */
785 /*! @brief Read current value of the AIPS_PACRA_SP7 field. */
786 #define BR_AIPS_PACRA_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP7))
788 /*! @brief Format value for bitfield AIPS_PACRA_SP7. */
789 #define BF_AIPS_PACRA_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_SP7) & BM_AIPS_PACRA_SP7)
791 /*! @brief Set the SP7 field to a new value. */
792 #define BW_AIPS_PACRA_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP7) = (v))
796 * @name Register AIPS_PACRA, field TP6[4] (RW)
798 * Determines whether the peripheral allows accesses from an untrusted master.
799 * When this field is set and an access is attempted by an untrusted master, the
800 * access terminates with an error response and no peripheral access initiates.
803 * - 0 - Accesses from an untrusted master are allowed.
804 * - 1 - Accesses from an untrusted master are not allowed.
807 #define BP_AIPS_PACRA_TP6 (4U) /*!< Bit position for AIPS_PACRA_TP6. */
808 #define BM_AIPS_PACRA_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRA_TP6. */
809 #define BS_AIPS_PACRA_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRA_TP6. */
811 /*! @brief Read current value of the AIPS_PACRA_TP6 field. */
812 #define BR_AIPS_PACRA_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP6))
814 /*! @brief Format value for bitfield AIPS_PACRA_TP6. */
815 #define BF_AIPS_PACRA_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_TP6) & BM_AIPS_PACRA_TP6)
817 /*! @brief Set the TP6 field to a new value. */
818 #define BW_AIPS_PACRA_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP6) = (v))
822 * @name Register AIPS_PACRA, field WP6[5] (RW)
824 * Determines whether the peripheral allows write accesses. When this field is
825 * set and a write access is attempted, access terminates with an error response
826 * and no peripheral access initiates.
829 * - 0 - This peripheral allows write accesses.
830 * - 1 - This peripheral is write protected.
833 #define BP_AIPS_PACRA_WP6 (5U) /*!< Bit position for AIPS_PACRA_WP6. */
834 #define BM_AIPS_PACRA_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRA_WP6. */
835 #define BS_AIPS_PACRA_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRA_WP6. */
837 /*! @brief Read current value of the AIPS_PACRA_WP6 field. */
838 #define BR_AIPS_PACRA_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP6))
840 /*! @brief Format value for bitfield AIPS_PACRA_WP6. */
841 #define BF_AIPS_PACRA_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_WP6) & BM_AIPS_PACRA_WP6)
843 /*! @brief Set the WP6 field to a new value. */
844 #define BW_AIPS_PACRA_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP6) = (v))
848 * @name Register AIPS_PACRA, field SP6[6] (RW)
850 * Determines whether the peripheral requires supervisor privilege level for
851 * accesses. When this field is set, the master privilege level must indicate the
852 * supervisor access attribute, and the MPRx[MPLn] control field for the master
853 * must be set. If not, access terminates with an error response and no peripheral
857 * - 0 - This peripheral does not require supervisor privilege level for
859 * - 1 - This peripheral requires supervisor privilege level for accesses.
862 #define BP_AIPS_PACRA_SP6 (6U) /*!< Bit position for AIPS_PACRA_SP6. */
863 #define BM_AIPS_PACRA_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRA_SP6. */
864 #define BS_AIPS_PACRA_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRA_SP6. */
866 /*! @brief Read current value of the AIPS_PACRA_SP6 field. */
867 #define BR_AIPS_PACRA_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP6))
869 /*! @brief Format value for bitfield AIPS_PACRA_SP6. */
870 #define BF_AIPS_PACRA_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_SP6) & BM_AIPS_PACRA_SP6)
872 /*! @brief Set the SP6 field to a new value. */
873 #define BW_AIPS_PACRA_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP6) = (v))
877 * @name Register AIPS_PACRA, field TP5[8] (RW)
879 * Determines whether the peripheral allows accesses from an untrusted master.
880 * When this field is set and an access is attempted by an untrusted master, the
881 * access terminates with an error response and no peripheral access initiates.
884 * - 0 - Accesses from an untrusted master are allowed.
885 * - 1 - Accesses from an untrusted master are not allowed.
888 #define BP_AIPS_PACRA_TP5 (8U) /*!< Bit position for AIPS_PACRA_TP5. */
889 #define BM_AIPS_PACRA_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRA_TP5. */
890 #define BS_AIPS_PACRA_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRA_TP5. */
892 /*! @brief Read current value of the AIPS_PACRA_TP5 field. */
893 #define BR_AIPS_PACRA_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP5))
895 /*! @brief Format value for bitfield AIPS_PACRA_TP5. */
896 #define BF_AIPS_PACRA_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_TP5) & BM_AIPS_PACRA_TP5)
898 /*! @brief Set the TP5 field to a new value. */
899 #define BW_AIPS_PACRA_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP5) = (v))
903 * @name Register AIPS_PACRA, field WP5[9] (RW)
905 * Determines whether the peripheral allows write accesses. When this field is
906 * set and a write access is attempted, access terminates with an error response
907 * and no peripheral access initiates.
910 * - 0 - This peripheral allows write accesses.
911 * - 1 - This peripheral is write protected.
914 #define BP_AIPS_PACRA_WP5 (9U) /*!< Bit position for AIPS_PACRA_WP5. */
915 #define BM_AIPS_PACRA_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRA_WP5. */
916 #define BS_AIPS_PACRA_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRA_WP5. */
918 /*! @brief Read current value of the AIPS_PACRA_WP5 field. */
919 #define BR_AIPS_PACRA_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP5))
921 /*! @brief Format value for bitfield AIPS_PACRA_WP5. */
922 #define BF_AIPS_PACRA_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_WP5) & BM_AIPS_PACRA_WP5)
924 /*! @brief Set the WP5 field to a new value. */
925 #define BW_AIPS_PACRA_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP5) = (v))
929 * @name Register AIPS_PACRA, field SP5[10] (RW)
931 * Determines whether the peripheral requires supervisor privilege level for
932 * accesses. When this field is set, the master privilege level must indicate the
933 * supervisor access attribute, and the MPRx[MPLn] control field for the master
934 * must be set. If not, access terminates with an error response and no peripheral
938 * - 0 - This peripheral does not require supervisor privilege level for
940 * - 1 - This peripheral requires supervisor privilege level for accesses.
943 #define BP_AIPS_PACRA_SP5 (10U) /*!< Bit position for AIPS_PACRA_SP5. */
944 #define BM_AIPS_PACRA_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRA_SP5. */
945 #define BS_AIPS_PACRA_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRA_SP5. */
947 /*! @brief Read current value of the AIPS_PACRA_SP5 field. */
948 #define BR_AIPS_PACRA_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP5))
950 /*! @brief Format value for bitfield AIPS_PACRA_SP5. */
951 #define BF_AIPS_PACRA_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_SP5) & BM_AIPS_PACRA_SP5)
953 /*! @brief Set the SP5 field to a new value. */
954 #define BW_AIPS_PACRA_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP5) = (v))
958 * @name Register AIPS_PACRA, field TP4[12] (RW)
960 * Determines whether the peripheral allows accesses from an untrusted master.
961 * When this field is set and an access is attempted by an untrusted master, the
962 * access terminates with an error response and no peripheral access initiates.
965 * - 0 - Accesses from an untrusted master are allowed.
966 * - 1 - Accesses from an untrusted master are not allowed.
969 #define BP_AIPS_PACRA_TP4 (12U) /*!< Bit position for AIPS_PACRA_TP4. */
970 #define BM_AIPS_PACRA_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRA_TP4. */
971 #define BS_AIPS_PACRA_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRA_TP4. */
973 /*! @brief Read current value of the AIPS_PACRA_TP4 field. */
974 #define BR_AIPS_PACRA_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP4))
976 /*! @brief Format value for bitfield AIPS_PACRA_TP4. */
977 #define BF_AIPS_PACRA_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_TP4) & BM_AIPS_PACRA_TP4)
979 /*! @brief Set the TP4 field to a new value. */
980 #define BW_AIPS_PACRA_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP4) = (v))
984 * @name Register AIPS_PACRA, field WP4[13] (RW)
986 * Determines whether the peripheral allows write accesss. When this bit is set
987 * and a write access is attempted, access terminates with an error response and
988 * no peripheral access initiates.
991 * - 0 - This peripheral allows write accesses.
992 * - 1 - This peripheral is write protected.
995 #define BP_AIPS_PACRA_WP4 (13U) /*!< Bit position for AIPS_PACRA_WP4. */
996 #define BM_AIPS_PACRA_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRA_WP4. */
997 #define BS_AIPS_PACRA_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRA_WP4. */
999 /*! @brief Read current value of the AIPS_PACRA_WP4 field. */
1000 #define BR_AIPS_PACRA_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP4))
1002 /*! @brief Format value for bitfield AIPS_PACRA_WP4. */
1003 #define BF_AIPS_PACRA_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_WP4) & BM_AIPS_PACRA_WP4)
1005 /*! @brief Set the WP4 field to a new value. */
1006 #define BW_AIPS_PACRA_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP4) = (v))
1010 * @name Register AIPS_PACRA, field SP4[14] (RW)
1012 * Determines whether the peripheral requires supervisor privilege level for
1013 * accesses. When this field is set, the master privilege level must indicate the
1014 * supervisor access attribute, and the MPRx[MPLn] control field for the master
1015 * must be set. If not, access terminates with an error response and no peripheral
1019 * - 0 - This peripheral does not require supervisor privilege level for
1021 * - 1 - This peripheral requires supervisor privilege level for accesses.
1024 #define BP_AIPS_PACRA_SP4 (14U) /*!< Bit position for AIPS_PACRA_SP4. */
1025 #define BM_AIPS_PACRA_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRA_SP4. */
1026 #define BS_AIPS_PACRA_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRA_SP4. */
1028 /*! @brief Read current value of the AIPS_PACRA_SP4 field. */
1029 #define BR_AIPS_PACRA_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP4))
1031 /*! @brief Format value for bitfield AIPS_PACRA_SP4. */
1032 #define BF_AIPS_PACRA_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_SP4) & BM_AIPS_PACRA_SP4)
1034 /*! @brief Set the SP4 field to a new value. */
1035 #define BW_AIPS_PACRA_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP4) = (v))
1039 * @name Register AIPS_PACRA, field TP3[16] (RW)
1041 * Determines whether the peripheral allows accesses from an untrusted master.
1042 * When this bit is set and an access is attempted by an untrusted master, the
1043 * access terminates with an error response and no peripheral access initiates.
1046 * - 0 - Accesses from an untrusted master are allowed.
1047 * - 1 - Accesses from an untrusted master are not allowed.
1050 #define BP_AIPS_PACRA_TP3 (16U) /*!< Bit position for AIPS_PACRA_TP3. */
1051 #define BM_AIPS_PACRA_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRA_TP3. */
1052 #define BS_AIPS_PACRA_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRA_TP3. */
1054 /*! @brief Read current value of the AIPS_PACRA_TP3 field. */
1055 #define BR_AIPS_PACRA_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP3))
1057 /*! @brief Format value for bitfield AIPS_PACRA_TP3. */
1058 #define BF_AIPS_PACRA_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_TP3) & BM_AIPS_PACRA_TP3)
1060 /*! @brief Set the TP3 field to a new value. */
1061 #define BW_AIPS_PACRA_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP3) = (v))
1065 * @name Register AIPS_PACRA, field WP3[17] (RW)
1067 * Determines whether the peripheral allows write accesses. When this field is
1068 * set and a write access is attempted, access terminates with an error response
1069 * and no peripheral access initiates.
1072 * - 0 - This peripheral allows write accesses.
1073 * - 1 - This peripheral is write protected.
1076 #define BP_AIPS_PACRA_WP3 (17U) /*!< Bit position for AIPS_PACRA_WP3. */
1077 #define BM_AIPS_PACRA_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRA_WP3. */
1078 #define BS_AIPS_PACRA_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRA_WP3. */
1080 /*! @brief Read current value of the AIPS_PACRA_WP3 field. */
1081 #define BR_AIPS_PACRA_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP3))
1083 /*! @brief Format value for bitfield AIPS_PACRA_WP3. */
1084 #define BF_AIPS_PACRA_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_WP3) & BM_AIPS_PACRA_WP3)
1086 /*! @brief Set the WP3 field to a new value. */
1087 #define BW_AIPS_PACRA_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP3) = (v))
1091 * @name Register AIPS_PACRA, field SP3[18] (RW)
1093 * Determines whether the peripheral requires supervisor privilege level for
1094 * access. When this bit is set, the master privilege level must indicate the
1095 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
1096 * set. If not, access terminates with an error response and no peripheral access
1100 * - 0 - This peripheral does not require supervisor privilege level for
1102 * - 1 - This peripheral requires supervisor privilege level for accesses.
1105 #define BP_AIPS_PACRA_SP3 (18U) /*!< Bit position for AIPS_PACRA_SP3. */
1106 #define BM_AIPS_PACRA_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRA_SP3. */
1107 #define BS_AIPS_PACRA_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRA_SP3. */
1109 /*! @brief Read current value of the AIPS_PACRA_SP3 field. */
1110 #define BR_AIPS_PACRA_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP3))
1112 /*! @brief Format value for bitfield AIPS_PACRA_SP3. */
1113 #define BF_AIPS_PACRA_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_SP3) & BM_AIPS_PACRA_SP3)
1115 /*! @brief Set the SP3 field to a new value. */
1116 #define BW_AIPS_PACRA_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP3) = (v))
1120 * @name Register AIPS_PACRA, field TP2[20] (RW)
1122 * Determines whether the peripheral allows accesses from an untrusted master.
1123 * When this field is set and an access is attempted by an untrusted master, the
1124 * access terminates with an error response and no peripheral access initiates.
1127 * - 0 - Accesses from an untrusted master are allowed.
1128 * - 1 - Accesses from an untrusted master are not allowed.
1131 #define BP_AIPS_PACRA_TP2 (20U) /*!< Bit position for AIPS_PACRA_TP2. */
1132 #define BM_AIPS_PACRA_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRA_TP2. */
1133 #define BS_AIPS_PACRA_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRA_TP2. */
1135 /*! @brief Read current value of the AIPS_PACRA_TP2 field. */
1136 #define BR_AIPS_PACRA_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP2))
1138 /*! @brief Format value for bitfield AIPS_PACRA_TP2. */
1139 #define BF_AIPS_PACRA_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_TP2) & BM_AIPS_PACRA_TP2)
1141 /*! @brief Set the TP2 field to a new value. */
1142 #define BW_AIPS_PACRA_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP2) = (v))
1146 * @name Register AIPS_PACRA, field WP2[21] (RW)
1148 * Determines whether the peripheral allows write accesss. When this bit is set
1149 * and a write access is attempted, access terminates with an error response and
1150 * no peripheral access initiates.
1153 * - 0 - This peripheral allows write accesses.
1154 * - 1 - This peripheral is write protected.
1157 #define BP_AIPS_PACRA_WP2 (21U) /*!< Bit position for AIPS_PACRA_WP2. */
1158 #define BM_AIPS_PACRA_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRA_WP2. */
1159 #define BS_AIPS_PACRA_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRA_WP2. */
1161 /*! @brief Read current value of the AIPS_PACRA_WP2 field. */
1162 #define BR_AIPS_PACRA_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP2))
1164 /*! @brief Format value for bitfield AIPS_PACRA_WP2. */
1165 #define BF_AIPS_PACRA_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_WP2) & BM_AIPS_PACRA_WP2)
1167 /*! @brief Set the WP2 field to a new value. */
1168 #define BW_AIPS_PACRA_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP2) = (v))
1172 * @name Register AIPS_PACRA, field SP2[22] (RW)
1174 * Determines whether the peripheral requires supervisor privilege level for
1175 * accesses. When this field is set, the master privilege level must indicate the
1176 * supervisor access attribute, and the MPRx[MPLn] control field for the master
1177 * must be set. If not, access terminates with an error response and no peripheral
1181 * - 0 - This peripheral does not require supervisor privilege level for
1183 * - 1 - This peripheral requires supervisor privilege level for accesses.
1186 #define BP_AIPS_PACRA_SP2 (22U) /*!< Bit position for AIPS_PACRA_SP2. */
1187 #define BM_AIPS_PACRA_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRA_SP2. */
1188 #define BS_AIPS_PACRA_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRA_SP2. */
1190 /*! @brief Read current value of the AIPS_PACRA_SP2 field. */
1191 #define BR_AIPS_PACRA_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP2))
1193 /*! @brief Format value for bitfield AIPS_PACRA_SP2. */
1194 #define BF_AIPS_PACRA_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_SP2) & BM_AIPS_PACRA_SP2)
1196 /*! @brief Set the SP2 field to a new value. */
1197 #define BW_AIPS_PACRA_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP2) = (v))
1201 * @name Register AIPS_PACRA, field TP1[24] (RW)
1203 * Determines whether the peripheral allows accesses from an untrusted master.
1204 * When this bit is set and an access is attempted by an untrusted master, the
1205 * access terminates with an error response and no peripheral access initiates.
1208 * - 0 - Accesses from an untrusted master are allowed.
1209 * - 1 - Accesses from an untrusted master are not allowed.
1212 #define BP_AIPS_PACRA_TP1 (24U) /*!< Bit position for AIPS_PACRA_TP1. */
1213 #define BM_AIPS_PACRA_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRA_TP1. */
1214 #define BS_AIPS_PACRA_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRA_TP1. */
1216 /*! @brief Read current value of the AIPS_PACRA_TP1 field. */
1217 #define BR_AIPS_PACRA_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP1))
1219 /*! @brief Format value for bitfield AIPS_PACRA_TP1. */
1220 #define BF_AIPS_PACRA_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_TP1) & BM_AIPS_PACRA_TP1)
1222 /*! @brief Set the TP1 field to a new value. */
1223 #define BW_AIPS_PACRA_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP1) = (v))
1227 * @name Register AIPS_PACRA, field WP1[25] (RW)
1229 * Determines whether the peripheral allows write accesses. When this field is
1230 * set and a write access is attempted, access terminates with an error response
1231 * and no peripheral access initiates.
1234 * - 0 - This peripheral allows write accesses.
1235 * - 1 - This peripheral is write protected.
1238 #define BP_AIPS_PACRA_WP1 (25U) /*!< Bit position for AIPS_PACRA_WP1. */
1239 #define BM_AIPS_PACRA_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRA_WP1. */
1240 #define BS_AIPS_PACRA_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRA_WP1. */
1242 /*! @brief Read current value of the AIPS_PACRA_WP1 field. */
1243 #define BR_AIPS_PACRA_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP1))
1245 /*! @brief Format value for bitfield AIPS_PACRA_WP1. */
1246 #define BF_AIPS_PACRA_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_WP1) & BM_AIPS_PACRA_WP1)
1248 /*! @brief Set the WP1 field to a new value. */
1249 #define BW_AIPS_PACRA_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP1) = (v))
1253 * @name Register AIPS_PACRA, field SP1[26] (RW)
1255 * Determines whether the peripheral requires supervisor privilege level for
1256 * accesses. When this field is set, the master privilege level must indicate the
1257 * supervisor access attribute, and the MPRx[MPLn] control field for the master
1258 * must be set. If not, access terminates with an error response and no peripheral
1262 * - 0 - This peripheral does not require supervisor privilege level for
1264 * - 1 - This peripheral requires supervisor privilege level for accesses.
1267 #define BP_AIPS_PACRA_SP1 (26U) /*!< Bit position for AIPS_PACRA_SP1. */
1268 #define BM_AIPS_PACRA_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRA_SP1. */
1269 #define BS_AIPS_PACRA_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRA_SP1. */
1271 /*! @brief Read current value of the AIPS_PACRA_SP1 field. */
1272 #define BR_AIPS_PACRA_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP1))
1274 /*! @brief Format value for bitfield AIPS_PACRA_SP1. */
1275 #define BF_AIPS_PACRA_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_SP1) & BM_AIPS_PACRA_SP1)
1277 /*! @brief Set the SP1 field to a new value. */
1278 #define BW_AIPS_PACRA_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP1) = (v))
1282 * @name Register AIPS_PACRA, field TP0[28] (RW)
1284 * Determines whether the peripheral allows accesses from an untrusted master.
1285 * When this field is set and an access is attempted by an untrusted master, the
1286 * access terminates with an error response and no peripheral access initiates.
1289 * - 0 - Accesses from an untrusted master are allowed.
1290 * - 1 - Accesses from an untrusted master are not allowed.
1293 #define BP_AIPS_PACRA_TP0 (28U) /*!< Bit position for AIPS_PACRA_TP0. */
1294 #define BM_AIPS_PACRA_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRA_TP0. */
1295 #define BS_AIPS_PACRA_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRA_TP0. */
1297 /*! @brief Read current value of the AIPS_PACRA_TP0 field. */
1298 #define BR_AIPS_PACRA_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP0))
1300 /*! @brief Format value for bitfield AIPS_PACRA_TP0. */
1301 #define BF_AIPS_PACRA_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_TP0) & BM_AIPS_PACRA_TP0)
1303 /*! @brief Set the TP0 field to a new value. */
1304 #define BW_AIPS_PACRA_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP0) = (v))
1308 * @name Register AIPS_PACRA, field WP0[29] (RW)
1310 * Determines whether the peripheral allows write accesss. When this bit is set
1311 * and a write access is attempted, access terminates with an error response and
1312 * no peripheral access initiates.
1315 * - 0 - This peripheral allows write accesses.
1316 * - 1 - This peripheral is write protected.
1319 #define BP_AIPS_PACRA_WP0 (29U) /*!< Bit position for AIPS_PACRA_WP0. */
1320 #define BM_AIPS_PACRA_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRA_WP0. */
1321 #define BS_AIPS_PACRA_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRA_WP0. */
1323 /*! @brief Read current value of the AIPS_PACRA_WP0 field. */
1324 #define BR_AIPS_PACRA_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP0))
1326 /*! @brief Format value for bitfield AIPS_PACRA_WP0. */
1327 #define BF_AIPS_PACRA_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_WP0) & BM_AIPS_PACRA_WP0)
1329 /*! @brief Set the WP0 field to a new value. */
1330 #define BW_AIPS_PACRA_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP0) = (v))
1334 * @name Register AIPS_PACRA, field SP0[30] (RW)
1336 * Determines whether the peripheral requires supervisor privilege level for
1337 * accesses. When this field is set, the master privilege level must indicate the
1338 * supervisor access attribute, and the MPRx[MPLn] control field for the master
1339 * must be set. If not, access terminates with an error response and no peripheral
1343 * - 0 - This peripheral does not require supervisor privilege level for
1345 * - 1 - This peripheral requires supervisor privilege level for accesses.
1348 #define BP_AIPS_PACRA_SP0 (30U) /*!< Bit position for AIPS_PACRA_SP0. */
1349 #define BM_AIPS_PACRA_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRA_SP0. */
1350 #define BS_AIPS_PACRA_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRA_SP0. */
1352 /*! @brief Read current value of the AIPS_PACRA_SP0 field. */
1353 #define BR_AIPS_PACRA_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP0))
1355 /*! @brief Format value for bitfield AIPS_PACRA_SP0. */
1356 #define BF_AIPS_PACRA_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_SP0) & BM_AIPS_PACRA_SP0)
1358 /*! @brief Set the SP0 field to a new value. */
1359 #define BW_AIPS_PACRA_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP0) = (v))
1362 /*******************************************************************************
1363 * HW_AIPS_PACRB - Peripheral Access Control Register
1364 ******************************************************************************/
1367 * @brief HW_AIPS_PACRB - Peripheral Access Control Register (RW)
1369 * Reset value: 0x44004400U
1371 * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
1372 * defines the access levels for a particular peripheral. The mapping between a
1373 * peripheral and its PACR field is shown in the table below. The peripheral assignment
1374 * to each PACR is defined by the memory map slot that the peripheral is
1375 * assigned to. See this chip's memory map for the assignment of a particular
1376 * peripheral. The following table shows the location of each peripheral slot's PACR field
1377 * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
1378 * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
1379 * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
1380 * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
1381 * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
1382 * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
1383 * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
1384 * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
1385 * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
1386 * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
1387 * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
1388 * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
1389 * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
1390 * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
1391 * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
1392 * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
1393 * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
1394 * A-D, which control peripheral slots 0-31, are shown below. The following
1395 * section, PACRPeripheral Access Control Register , shows the register field
1396 * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
1397 * sections because they occupy two non-contiguous address spaces.
1399 typedef union _hw_aips_pacrb
1402 struct _hw_aips_pacrb_bitfields
1404 uint32_t TP7
: 1; /*!< [0] Trusted Protect */
1405 uint32_t WP7
: 1; /*!< [1] Write Protect */
1406 uint32_t SP7
: 1; /*!< [2] Supervisor Protect */
1407 uint32_t RESERVED0
: 1; /*!< [3] */
1408 uint32_t TP6
: 1; /*!< [4] Trusted Protect */
1409 uint32_t WP6
: 1; /*!< [5] Write Protect */
1410 uint32_t SP6
: 1; /*!< [6] Supervisor Protect */
1411 uint32_t RESERVED1
: 1; /*!< [7] */
1412 uint32_t TP5
: 1; /*!< [8] Trusted Protect */
1413 uint32_t WP5
: 1; /*!< [9] Write Protect */
1414 uint32_t SP5
: 1; /*!< [10] Supervisor Protect */
1415 uint32_t RESERVED2
: 1; /*!< [11] */
1416 uint32_t TP4
: 1; /*!< [12] Trusted Protect */
1417 uint32_t WP4
: 1; /*!< [13] Write Protect */
1418 uint32_t SP4
: 1; /*!< [14] Supervisor Protect */
1419 uint32_t RESERVED3
: 1; /*!< [15] */
1420 uint32_t TP3
: 1; /*!< [16] Trusted Protect */
1421 uint32_t WP3
: 1; /*!< [17] Write Protect */
1422 uint32_t SP3
: 1; /*!< [18] Supervisor Protect */
1423 uint32_t RESERVED4
: 1; /*!< [19] */
1424 uint32_t TP2
: 1; /*!< [20] Trusted Protect */
1425 uint32_t WP2
: 1; /*!< [21] Write Protect */
1426 uint32_t SP2
: 1; /*!< [22] Supervisor Protect */
1427 uint32_t RESERVED5
: 1; /*!< [23] */
1428 uint32_t TP1
: 1; /*!< [24] Trusted Protect */
1429 uint32_t WP1
: 1; /*!< [25] Write Protect */
1430 uint32_t SP1
: 1; /*!< [26] Supervisor Protect */
1431 uint32_t RESERVED6
: 1; /*!< [27] */
1432 uint32_t TP0
: 1; /*!< [28] Trusted Protect */
1433 uint32_t WP0
: 1; /*!< [29] Write Protect */
1434 uint32_t SP0
: 1; /*!< [30] Supervisor Protect */
1435 uint32_t RESERVED7
: 1; /*!< [31] */
1440 * @name Constants and macros for entire AIPS_PACRB register
1443 #define HW_AIPS_PACRB_ADDR(x) ((x) + 0x24U)
1445 #define HW_AIPS_PACRB(x) (*(__IO hw_aips_pacrb_t *) HW_AIPS_PACRB_ADDR(x))
1446 #define HW_AIPS_PACRB_RD(x) (HW_AIPS_PACRB(x).U)
1447 #define HW_AIPS_PACRB_WR(x, v) (HW_AIPS_PACRB(x).U = (v))
1448 #define HW_AIPS_PACRB_SET(x, v) (HW_AIPS_PACRB_WR(x, HW_AIPS_PACRB_RD(x) | (v)))
1449 #define HW_AIPS_PACRB_CLR(x, v) (HW_AIPS_PACRB_WR(x, HW_AIPS_PACRB_RD(x) & ~(v)))
1450 #define HW_AIPS_PACRB_TOG(x, v) (HW_AIPS_PACRB_WR(x, HW_AIPS_PACRB_RD(x) ^ (v)))
1454 * Constants & macros for individual AIPS_PACRB bitfields
1458 * @name Register AIPS_PACRB, field TP7[0] (RW)
1460 * Determines whether the peripheral allows accesses from an untrusted master.
1461 * When this field is set and an access is attempted by an untrusted master, the
1462 * access terminates with an error response and no peripheral access initiates.
1465 * - 0 - Accesses from an untrusted master are allowed.
1466 * - 1 - Accesses from an untrusted master are not allowed.
1469 #define BP_AIPS_PACRB_TP7 (0U) /*!< Bit position for AIPS_PACRB_TP7. */
1470 #define BM_AIPS_PACRB_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRB_TP7. */
1471 #define BS_AIPS_PACRB_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRB_TP7. */
1473 /*! @brief Read current value of the AIPS_PACRB_TP7 field. */
1474 #define BR_AIPS_PACRB_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP7))
1476 /*! @brief Format value for bitfield AIPS_PACRB_TP7. */
1477 #define BF_AIPS_PACRB_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_TP7) & BM_AIPS_PACRB_TP7)
1479 /*! @brief Set the TP7 field to a new value. */
1480 #define BW_AIPS_PACRB_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP7) = (v))
1484 * @name Register AIPS_PACRB, field WP7[1] (RW)
1486 * Determines whether the peripheral allows write accesses. When this field is
1487 * set and a write access is attempted, access terminates with an error response
1488 * and no peripheral access initiates.
1491 * - 0 - This peripheral allows write accesses.
1492 * - 1 - This peripheral is write protected.
1495 #define BP_AIPS_PACRB_WP7 (1U) /*!< Bit position for AIPS_PACRB_WP7. */
1496 #define BM_AIPS_PACRB_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRB_WP7. */
1497 #define BS_AIPS_PACRB_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRB_WP7. */
1499 /*! @brief Read current value of the AIPS_PACRB_WP7 field. */
1500 #define BR_AIPS_PACRB_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP7))
1502 /*! @brief Format value for bitfield AIPS_PACRB_WP7. */
1503 #define BF_AIPS_PACRB_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_WP7) & BM_AIPS_PACRB_WP7)
1505 /*! @brief Set the WP7 field to a new value. */
1506 #define BW_AIPS_PACRB_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP7) = (v))
1510 * @name Register AIPS_PACRB, field SP7[2] (RW)
1512 * Determines whether the peripheral requires supervisor privilege level for
1513 * accesses. When this field is set, the master privilege level must indicate the
1514 * supervisor access attribute, and the MPRx[MPLn] control field for the master
1515 * must be set. If not, access terminates with an error response and no peripheral
1519 * - 0 - This peripheral does not require supervisor privilege level for
1521 * - 1 - This peripheral requires supervisor privilege level for accesses.
1524 #define BP_AIPS_PACRB_SP7 (2U) /*!< Bit position for AIPS_PACRB_SP7. */
1525 #define BM_AIPS_PACRB_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRB_SP7. */
1526 #define BS_AIPS_PACRB_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRB_SP7. */
1528 /*! @brief Read current value of the AIPS_PACRB_SP7 field. */
1529 #define BR_AIPS_PACRB_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP7))
1531 /*! @brief Format value for bitfield AIPS_PACRB_SP7. */
1532 #define BF_AIPS_PACRB_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_SP7) & BM_AIPS_PACRB_SP7)
1534 /*! @brief Set the SP7 field to a new value. */
1535 #define BW_AIPS_PACRB_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP7) = (v))
1539 * @name Register AIPS_PACRB, field TP6[4] (RW)
1541 * Determines whether the peripheral allows accesses from an untrusted master.
1542 * When this field is set and an access is attempted by an untrusted master, the
1543 * access terminates with an error response and no peripheral access initiates.
1546 * - 0 - Accesses from an untrusted master are allowed.
1547 * - 1 - Accesses from an untrusted master are not allowed.
1550 #define BP_AIPS_PACRB_TP6 (4U) /*!< Bit position for AIPS_PACRB_TP6. */
1551 #define BM_AIPS_PACRB_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRB_TP6. */
1552 #define BS_AIPS_PACRB_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRB_TP6. */
1554 /*! @brief Read current value of the AIPS_PACRB_TP6 field. */
1555 #define BR_AIPS_PACRB_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP6))
1557 /*! @brief Format value for bitfield AIPS_PACRB_TP6. */
1558 #define BF_AIPS_PACRB_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_TP6) & BM_AIPS_PACRB_TP6)
1560 /*! @brief Set the TP6 field to a new value. */
1561 #define BW_AIPS_PACRB_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP6) = (v))
1565 * @name Register AIPS_PACRB, field WP6[5] (RW)
1567 * Determines whether the peripheral allows write accesses. When this field is
1568 * set and a write access is attempted, access terminates with an error response
1569 * and no peripheral access initiates.
1572 * - 0 - This peripheral allows write accesses.
1573 * - 1 - This peripheral is write protected.
1576 #define BP_AIPS_PACRB_WP6 (5U) /*!< Bit position for AIPS_PACRB_WP6. */
1577 #define BM_AIPS_PACRB_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRB_WP6. */
1578 #define BS_AIPS_PACRB_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRB_WP6. */
1580 /*! @brief Read current value of the AIPS_PACRB_WP6 field. */
1581 #define BR_AIPS_PACRB_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP6))
1583 /*! @brief Format value for bitfield AIPS_PACRB_WP6. */
1584 #define BF_AIPS_PACRB_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_WP6) & BM_AIPS_PACRB_WP6)
1586 /*! @brief Set the WP6 field to a new value. */
1587 #define BW_AIPS_PACRB_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP6) = (v))
1591 * @name Register AIPS_PACRB, field SP6[6] (RW)
1593 * Determines whether the peripheral requires supervisor privilege level for
1594 * accesses. When this field is set, the master privilege level must indicate the
1595 * supervisor access attribute, and the MPRx[MPLn] control field for the master
1596 * must be set. If not, access terminates with an error response and no peripheral
1600 * - 0 - This peripheral does not require supervisor privilege level for
1602 * - 1 - This peripheral requires supervisor privilege level for accesses.
1605 #define BP_AIPS_PACRB_SP6 (6U) /*!< Bit position for AIPS_PACRB_SP6. */
1606 #define BM_AIPS_PACRB_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRB_SP6. */
1607 #define BS_AIPS_PACRB_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRB_SP6. */
1609 /*! @brief Read current value of the AIPS_PACRB_SP6 field. */
1610 #define BR_AIPS_PACRB_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP6))
1612 /*! @brief Format value for bitfield AIPS_PACRB_SP6. */
1613 #define BF_AIPS_PACRB_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_SP6) & BM_AIPS_PACRB_SP6)
1615 /*! @brief Set the SP6 field to a new value. */
1616 #define BW_AIPS_PACRB_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP6) = (v))
1620 * @name Register AIPS_PACRB, field TP5[8] (RW)
1622 * Determines whether the peripheral allows accesses from an untrusted master.
1623 * When this field is set and an access is attempted by an untrusted master, the
1624 * access terminates with an error response and no peripheral access initiates.
1627 * - 0 - Accesses from an untrusted master are allowed.
1628 * - 1 - Accesses from an untrusted master are not allowed.
1631 #define BP_AIPS_PACRB_TP5 (8U) /*!< Bit position for AIPS_PACRB_TP5. */
1632 #define BM_AIPS_PACRB_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRB_TP5. */
1633 #define BS_AIPS_PACRB_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRB_TP5. */
1635 /*! @brief Read current value of the AIPS_PACRB_TP5 field. */
1636 #define BR_AIPS_PACRB_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP5))
1638 /*! @brief Format value for bitfield AIPS_PACRB_TP5. */
1639 #define BF_AIPS_PACRB_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_TP5) & BM_AIPS_PACRB_TP5)
1641 /*! @brief Set the TP5 field to a new value. */
1642 #define BW_AIPS_PACRB_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP5) = (v))
1646 * @name Register AIPS_PACRB, field WP5[9] (RW)
1648 * Determines whether the peripheral allows write accesses. When this field is
1649 * set and a write access is attempted, access terminates with an error response
1650 * and no peripheral access initiates.
1653 * - 0 - This peripheral allows write accesses.
1654 * - 1 - This peripheral is write protected.
1657 #define BP_AIPS_PACRB_WP5 (9U) /*!< Bit position for AIPS_PACRB_WP5. */
1658 #define BM_AIPS_PACRB_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRB_WP5. */
1659 #define BS_AIPS_PACRB_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRB_WP5. */
1661 /*! @brief Read current value of the AIPS_PACRB_WP5 field. */
1662 #define BR_AIPS_PACRB_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP5))
1664 /*! @brief Format value for bitfield AIPS_PACRB_WP5. */
1665 #define BF_AIPS_PACRB_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_WP5) & BM_AIPS_PACRB_WP5)
1667 /*! @brief Set the WP5 field to a new value. */
1668 #define BW_AIPS_PACRB_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP5) = (v))
1672 * @name Register AIPS_PACRB, field SP5[10] (RW)
1674 * Determines whether the peripheral requires supervisor privilege level for
1675 * accesses. When this field is set, the master privilege level must indicate the
1676 * supervisor access attribute, and the MPRx[MPLn] control field for the master
1677 * must be set. If not, access terminates with an error response and no peripheral
1681 * - 0 - This peripheral does not require supervisor privilege level for
1683 * - 1 - This peripheral requires supervisor privilege level for accesses.
1686 #define BP_AIPS_PACRB_SP5 (10U) /*!< Bit position for AIPS_PACRB_SP5. */
1687 #define BM_AIPS_PACRB_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRB_SP5. */
1688 #define BS_AIPS_PACRB_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRB_SP5. */
1690 /*! @brief Read current value of the AIPS_PACRB_SP5 field. */
1691 #define BR_AIPS_PACRB_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP5))
1693 /*! @brief Format value for bitfield AIPS_PACRB_SP5. */
1694 #define BF_AIPS_PACRB_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_SP5) & BM_AIPS_PACRB_SP5)
1696 /*! @brief Set the SP5 field to a new value. */
1697 #define BW_AIPS_PACRB_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP5) = (v))
1701 * @name Register AIPS_PACRB, field TP4[12] (RW)
1703 * Determines whether the peripheral allows accesses from an untrusted master.
1704 * When this field is set and an access is attempted by an untrusted master, the
1705 * access terminates with an error response and no peripheral access initiates.
1708 * - 0 - Accesses from an untrusted master are allowed.
1709 * - 1 - Accesses from an untrusted master are not allowed.
1712 #define BP_AIPS_PACRB_TP4 (12U) /*!< Bit position for AIPS_PACRB_TP4. */
1713 #define BM_AIPS_PACRB_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRB_TP4. */
1714 #define BS_AIPS_PACRB_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRB_TP4. */
1716 /*! @brief Read current value of the AIPS_PACRB_TP4 field. */
1717 #define BR_AIPS_PACRB_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP4))
1719 /*! @brief Format value for bitfield AIPS_PACRB_TP4. */
1720 #define BF_AIPS_PACRB_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_TP4) & BM_AIPS_PACRB_TP4)
1722 /*! @brief Set the TP4 field to a new value. */
1723 #define BW_AIPS_PACRB_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP4) = (v))
1727 * @name Register AIPS_PACRB, field WP4[13] (RW)
1729 * Determines whether the peripheral allows write accesss. When this bit is set
1730 * and a write access is attempted, access terminates with an error response and
1731 * no peripheral access initiates.
1734 * - 0 - This peripheral allows write accesses.
1735 * - 1 - This peripheral is write protected.
1738 #define BP_AIPS_PACRB_WP4 (13U) /*!< Bit position for AIPS_PACRB_WP4. */
1739 #define BM_AIPS_PACRB_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRB_WP4. */
1740 #define BS_AIPS_PACRB_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRB_WP4. */
1742 /*! @brief Read current value of the AIPS_PACRB_WP4 field. */
1743 #define BR_AIPS_PACRB_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP4))
1745 /*! @brief Format value for bitfield AIPS_PACRB_WP4. */
1746 #define BF_AIPS_PACRB_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_WP4) & BM_AIPS_PACRB_WP4)
1748 /*! @brief Set the WP4 field to a new value. */
1749 #define BW_AIPS_PACRB_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP4) = (v))
1753 * @name Register AIPS_PACRB, field SP4[14] (RW)
1755 * Determines whether the peripheral requires supervisor privilege level for
1756 * accesses. When this field is set, the master privilege level must indicate the
1757 * supervisor access attribute, and the MPRx[MPLn] control field for the master
1758 * must be set. If not, access terminates with an error response and no peripheral
1762 * - 0 - This peripheral does not require supervisor privilege level for
1764 * - 1 - This peripheral requires supervisor privilege level for accesses.
1767 #define BP_AIPS_PACRB_SP4 (14U) /*!< Bit position for AIPS_PACRB_SP4. */
1768 #define BM_AIPS_PACRB_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRB_SP4. */
1769 #define BS_AIPS_PACRB_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRB_SP4. */
1771 /*! @brief Read current value of the AIPS_PACRB_SP4 field. */
1772 #define BR_AIPS_PACRB_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP4))
1774 /*! @brief Format value for bitfield AIPS_PACRB_SP4. */
1775 #define BF_AIPS_PACRB_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_SP4) & BM_AIPS_PACRB_SP4)
1777 /*! @brief Set the SP4 field to a new value. */
1778 #define BW_AIPS_PACRB_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP4) = (v))
1782 * @name Register AIPS_PACRB, field TP3[16] (RW)
1784 * Determines whether the peripheral allows accesses from an untrusted master.
1785 * When this bit is set and an access is attempted by an untrusted master, the
1786 * access terminates with an error response and no peripheral access initiates.
1789 * - 0 - Accesses from an untrusted master are allowed.
1790 * - 1 - Accesses from an untrusted master are not allowed.
1793 #define BP_AIPS_PACRB_TP3 (16U) /*!< Bit position for AIPS_PACRB_TP3. */
1794 #define BM_AIPS_PACRB_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRB_TP3. */
1795 #define BS_AIPS_PACRB_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRB_TP3. */
1797 /*! @brief Read current value of the AIPS_PACRB_TP3 field. */
1798 #define BR_AIPS_PACRB_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP3))
1800 /*! @brief Format value for bitfield AIPS_PACRB_TP3. */
1801 #define BF_AIPS_PACRB_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_TP3) & BM_AIPS_PACRB_TP3)
1803 /*! @brief Set the TP3 field to a new value. */
1804 #define BW_AIPS_PACRB_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP3) = (v))
1808 * @name Register AIPS_PACRB, field WP3[17] (RW)
1810 * Determines whether the peripheral allows write accesses. When this field is
1811 * set and a write access is attempted, access terminates with an error response
1812 * and no peripheral access initiates.
1815 * - 0 - This peripheral allows write accesses.
1816 * - 1 - This peripheral is write protected.
1819 #define BP_AIPS_PACRB_WP3 (17U) /*!< Bit position for AIPS_PACRB_WP3. */
1820 #define BM_AIPS_PACRB_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRB_WP3. */
1821 #define BS_AIPS_PACRB_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRB_WP3. */
1823 /*! @brief Read current value of the AIPS_PACRB_WP3 field. */
1824 #define BR_AIPS_PACRB_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP3))
1826 /*! @brief Format value for bitfield AIPS_PACRB_WP3. */
1827 #define BF_AIPS_PACRB_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_WP3) & BM_AIPS_PACRB_WP3)
1829 /*! @brief Set the WP3 field to a new value. */
1830 #define BW_AIPS_PACRB_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP3) = (v))
1834 * @name Register AIPS_PACRB, field SP3[18] (RW)
1836 * Determines whether the peripheral requires supervisor privilege level for
1837 * access. When this bit is set, the master privilege level must indicate the
1838 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
1839 * set. If not, access terminates with an error response and no peripheral access
1843 * - 0 - This peripheral does not require supervisor privilege level for
1845 * - 1 - This peripheral requires supervisor privilege level for accesses.
1848 #define BP_AIPS_PACRB_SP3 (18U) /*!< Bit position for AIPS_PACRB_SP3. */
1849 #define BM_AIPS_PACRB_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRB_SP3. */
1850 #define BS_AIPS_PACRB_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRB_SP3. */
1852 /*! @brief Read current value of the AIPS_PACRB_SP3 field. */
1853 #define BR_AIPS_PACRB_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP3))
1855 /*! @brief Format value for bitfield AIPS_PACRB_SP3. */
1856 #define BF_AIPS_PACRB_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_SP3) & BM_AIPS_PACRB_SP3)
1858 /*! @brief Set the SP3 field to a new value. */
1859 #define BW_AIPS_PACRB_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP3) = (v))
1863 * @name Register AIPS_PACRB, field TP2[20] (RW)
1865 * Determines whether the peripheral allows accesses from an untrusted master.
1866 * When this field is set and an access is attempted by an untrusted master, the
1867 * access terminates with an error response and no peripheral access initiates.
1870 * - 0 - Accesses from an untrusted master are allowed.
1871 * - 1 - Accesses from an untrusted master are not allowed.
1874 #define BP_AIPS_PACRB_TP2 (20U) /*!< Bit position for AIPS_PACRB_TP2. */
1875 #define BM_AIPS_PACRB_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRB_TP2. */
1876 #define BS_AIPS_PACRB_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRB_TP2. */
1878 /*! @brief Read current value of the AIPS_PACRB_TP2 field. */
1879 #define BR_AIPS_PACRB_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP2))
1881 /*! @brief Format value for bitfield AIPS_PACRB_TP2. */
1882 #define BF_AIPS_PACRB_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_TP2) & BM_AIPS_PACRB_TP2)
1884 /*! @brief Set the TP2 field to a new value. */
1885 #define BW_AIPS_PACRB_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP2) = (v))
1889 * @name Register AIPS_PACRB, field WP2[21] (RW)
1891 * Determines whether the peripheral allows write accesss. When this bit is set
1892 * and a write access is attempted, access terminates with an error response and
1893 * no peripheral access initiates.
1896 * - 0 - This peripheral allows write accesses.
1897 * - 1 - This peripheral is write protected.
1900 #define BP_AIPS_PACRB_WP2 (21U) /*!< Bit position for AIPS_PACRB_WP2. */
1901 #define BM_AIPS_PACRB_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRB_WP2. */
1902 #define BS_AIPS_PACRB_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRB_WP2. */
1904 /*! @brief Read current value of the AIPS_PACRB_WP2 field. */
1905 #define BR_AIPS_PACRB_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP2))
1907 /*! @brief Format value for bitfield AIPS_PACRB_WP2. */
1908 #define BF_AIPS_PACRB_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_WP2) & BM_AIPS_PACRB_WP2)
1910 /*! @brief Set the WP2 field to a new value. */
1911 #define BW_AIPS_PACRB_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP2) = (v))
1915 * @name Register AIPS_PACRB, field SP2[22] (RW)
1917 * Determines whether the peripheral requires supervisor privilege level for
1918 * accesses. When this field is set, the master privilege level must indicate the
1919 * supervisor access attribute, and the MPRx[MPLn] control field for the master
1920 * must be set. If not, access terminates with an error response and no peripheral
1924 * - 0 - This peripheral does not require supervisor privilege level for
1926 * - 1 - This peripheral requires supervisor privilege level for accesses.
1929 #define BP_AIPS_PACRB_SP2 (22U) /*!< Bit position for AIPS_PACRB_SP2. */
1930 #define BM_AIPS_PACRB_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRB_SP2. */
1931 #define BS_AIPS_PACRB_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRB_SP2. */
1933 /*! @brief Read current value of the AIPS_PACRB_SP2 field. */
1934 #define BR_AIPS_PACRB_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP2))
1936 /*! @brief Format value for bitfield AIPS_PACRB_SP2. */
1937 #define BF_AIPS_PACRB_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_SP2) & BM_AIPS_PACRB_SP2)
1939 /*! @brief Set the SP2 field to a new value. */
1940 #define BW_AIPS_PACRB_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP2) = (v))
1944 * @name Register AIPS_PACRB, field TP1[24] (RW)
1946 * Determines whether the peripheral allows accesses from an untrusted master.
1947 * When this bit is set and an access is attempted by an untrusted master, the
1948 * access terminates with an error response and no peripheral access initiates.
1951 * - 0 - Accesses from an untrusted master are allowed.
1952 * - 1 - Accesses from an untrusted master are not allowed.
1955 #define BP_AIPS_PACRB_TP1 (24U) /*!< Bit position for AIPS_PACRB_TP1. */
1956 #define BM_AIPS_PACRB_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRB_TP1. */
1957 #define BS_AIPS_PACRB_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRB_TP1. */
1959 /*! @brief Read current value of the AIPS_PACRB_TP1 field. */
1960 #define BR_AIPS_PACRB_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP1))
1962 /*! @brief Format value for bitfield AIPS_PACRB_TP1. */
1963 #define BF_AIPS_PACRB_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_TP1) & BM_AIPS_PACRB_TP1)
1965 /*! @brief Set the TP1 field to a new value. */
1966 #define BW_AIPS_PACRB_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP1) = (v))
1970 * @name Register AIPS_PACRB, field WP1[25] (RW)
1972 * Determines whether the peripheral allows write accesses. When this field is
1973 * set and a write access is attempted, access terminates with an error response
1974 * and no peripheral access initiates.
1977 * - 0 - This peripheral allows write accesses.
1978 * - 1 - This peripheral is write protected.
1981 #define BP_AIPS_PACRB_WP1 (25U) /*!< Bit position for AIPS_PACRB_WP1. */
1982 #define BM_AIPS_PACRB_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRB_WP1. */
1983 #define BS_AIPS_PACRB_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRB_WP1. */
1985 /*! @brief Read current value of the AIPS_PACRB_WP1 field. */
1986 #define BR_AIPS_PACRB_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP1))
1988 /*! @brief Format value for bitfield AIPS_PACRB_WP1. */
1989 #define BF_AIPS_PACRB_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_WP1) & BM_AIPS_PACRB_WP1)
1991 /*! @brief Set the WP1 field to a new value. */
1992 #define BW_AIPS_PACRB_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP1) = (v))
1996 * @name Register AIPS_PACRB, field SP1[26] (RW)
1998 * Determines whether the peripheral requires supervisor privilege level for
1999 * accesses. When this field is set, the master privilege level must indicate the
2000 * supervisor access attribute, and the MPRx[MPLn] control field for the master
2001 * must be set. If not, access terminates with an error response and no peripheral
2005 * - 0 - This peripheral does not require supervisor privilege level for
2007 * - 1 - This peripheral requires supervisor privilege level for accesses.
2010 #define BP_AIPS_PACRB_SP1 (26U) /*!< Bit position for AIPS_PACRB_SP1. */
2011 #define BM_AIPS_PACRB_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRB_SP1. */
2012 #define BS_AIPS_PACRB_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRB_SP1. */
2014 /*! @brief Read current value of the AIPS_PACRB_SP1 field. */
2015 #define BR_AIPS_PACRB_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP1))
2017 /*! @brief Format value for bitfield AIPS_PACRB_SP1. */
2018 #define BF_AIPS_PACRB_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_SP1) & BM_AIPS_PACRB_SP1)
2020 /*! @brief Set the SP1 field to a new value. */
2021 #define BW_AIPS_PACRB_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP1) = (v))
2025 * @name Register AIPS_PACRB, field TP0[28] (RW)
2027 * Determines whether the peripheral allows accesses from an untrusted master.
2028 * When this field is set and an access is attempted by an untrusted master, the
2029 * access terminates with an error response and no peripheral access initiates.
2032 * - 0 - Accesses from an untrusted master are allowed.
2033 * - 1 - Accesses from an untrusted master are not allowed.
2036 #define BP_AIPS_PACRB_TP0 (28U) /*!< Bit position for AIPS_PACRB_TP0. */
2037 #define BM_AIPS_PACRB_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRB_TP0. */
2038 #define BS_AIPS_PACRB_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRB_TP0. */
2040 /*! @brief Read current value of the AIPS_PACRB_TP0 field. */
2041 #define BR_AIPS_PACRB_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP0))
2043 /*! @brief Format value for bitfield AIPS_PACRB_TP0. */
2044 #define BF_AIPS_PACRB_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_TP0) & BM_AIPS_PACRB_TP0)
2046 /*! @brief Set the TP0 field to a new value. */
2047 #define BW_AIPS_PACRB_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP0) = (v))
2051 * @name Register AIPS_PACRB, field WP0[29] (RW)
2053 * Determines whether the peripheral allows write accesss. When this bit is set
2054 * and a write access is attempted, access terminates with an error response and
2055 * no peripheral access initiates.
2058 * - 0 - This peripheral allows write accesses.
2059 * - 1 - This peripheral is write protected.
2062 #define BP_AIPS_PACRB_WP0 (29U) /*!< Bit position for AIPS_PACRB_WP0. */
2063 #define BM_AIPS_PACRB_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRB_WP0. */
2064 #define BS_AIPS_PACRB_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRB_WP0. */
2066 /*! @brief Read current value of the AIPS_PACRB_WP0 field. */
2067 #define BR_AIPS_PACRB_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP0))
2069 /*! @brief Format value for bitfield AIPS_PACRB_WP0. */
2070 #define BF_AIPS_PACRB_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_WP0) & BM_AIPS_PACRB_WP0)
2072 /*! @brief Set the WP0 field to a new value. */
2073 #define BW_AIPS_PACRB_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP0) = (v))
2077 * @name Register AIPS_PACRB, field SP0[30] (RW)
2079 * Determines whether the peripheral requires supervisor privilege level for
2080 * accesses. When this field is set, the master privilege level must indicate the
2081 * supervisor access attribute, and the MPRx[MPLn] control field for the master
2082 * must be set. If not, access terminates with an error response and no peripheral
2086 * - 0 - This peripheral does not require supervisor privilege level for
2088 * - 1 - This peripheral requires supervisor privilege level for accesses.
2091 #define BP_AIPS_PACRB_SP0 (30U) /*!< Bit position for AIPS_PACRB_SP0. */
2092 #define BM_AIPS_PACRB_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRB_SP0. */
2093 #define BS_AIPS_PACRB_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRB_SP0. */
2095 /*! @brief Read current value of the AIPS_PACRB_SP0 field. */
2096 #define BR_AIPS_PACRB_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP0))
2098 /*! @brief Format value for bitfield AIPS_PACRB_SP0. */
2099 #define BF_AIPS_PACRB_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_SP0) & BM_AIPS_PACRB_SP0)
2101 /*! @brief Set the SP0 field to a new value. */
2102 #define BW_AIPS_PACRB_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP0) = (v))
2105 /*******************************************************************************
2106 * HW_AIPS_PACRC - Peripheral Access Control Register
2107 ******************************************************************************/
2110 * @brief HW_AIPS_PACRC - Peripheral Access Control Register (RW)
2112 * Reset value: 0x00000000U
2114 * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
2115 * defines the access levels for a particular peripheral. The mapping between a
2116 * peripheral and its PACR field is shown in the table below. The peripheral assignment
2117 * to each PACR is defined by the memory map slot that the peripheral is
2118 * assigned to. See this chip's memory map for the assignment of a particular
2119 * peripheral. The following table shows the location of each peripheral slot's PACR field
2120 * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
2121 * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
2122 * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
2123 * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
2124 * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
2125 * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
2126 * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
2127 * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
2128 * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
2129 * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
2130 * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
2131 * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
2132 * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
2133 * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
2134 * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
2135 * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
2136 * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
2137 * A-D, which control peripheral slots 0-31, are shown below. The following
2138 * section, PACRPeripheral Access Control Register , shows the register field
2139 * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
2140 * sections because they occupy two non-contiguous address spaces.
2142 typedef union _hw_aips_pacrc
2145 struct _hw_aips_pacrc_bitfields
2147 uint32_t TP7
: 1; /*!< [0] Trusted Protect */
2148 uint32_t WP7
: 1; /*!< [1] Write Protect */
2149 uint32_t SP7
: 1; /*!< [2] Supervisor Protect */
2150 uint32_t RESERVED0
: 1; /*!< [3] */
2151 uint32_t TP6
: 1; /*!< [4] Trusted Protect */
2152 uint32_t WP6
: 1; /*!< [5] Write Protect */
2153 uint32_t SP6
: 1; /*!< [6] Supervisor Protect */
2154 uint32_t RESERVED1
: 1; /*!< [7] */
2155 uint32_t TP5
: 1; /*!< [8] Trusted Protect */
2156 uint32_t WP5
: 1; /*!< [9] Write Protect */
2157 uint32_t SP5
: 1; /*!< [10] Supervisor Protect */
2158 uint32_t RESERVED2
: 1; /*!< [11] */
2159 uint32_t TP4
: 1; /*!< [12] Trusted Protect */
2160 uint32_t WP4
: 1; /*!< [13] Write Protect */
2161 uint32_t SP4
: 1; /*!< [14] Supervisor Protect */
2162 uint32_t RESERVED3
: 1; /*!< [15] */
2163 uint32_t TP3
: 1; /*!< [16] Trusted Protect */
2164 uint32_t WP3
: 1; /*!< [17] Write Protect */
2165 uint32_t SP3
: 1; /*!< [18] Supervisor Protect */
2166 uint32_t RESERVED4
: 1; /*!< [19] */
2167 uint32_t TP2
: 1; /*!< [20] Trusted Protect */
2168 uint32_t WP2
: 1; /*!< [21] Write Protect */
2169 uint32_t SP2
: 1; /*!< [22] Supervisor Protect */
2170 uint32_t RESERVED5
: 1; /*!< [23] */
2171 uint32_t TP1
: 1; /*!< [24] Trusted Protect */
2172 uint32_t WP1
: 1; /*!< [25] Write Protect */
2173 uint32_t SP1
: 1; /*!< [26] Supervisor Protect */
2174 uint32_t RESERVED6
: 1; /*!< [27] */
2175 uint32_t TP0
: 1; /*!< [28] Trusted Protect */
2176 uint32_t WP0
: 1; /*!< [29] Write Protect */
2177 uint32_t SP0
: 1; /*!< [30] Supervisor Protect */
2178 uint32_t RESERVED7
: 1; /*!< [31] */
2183 * @name Constants and macros for entire AIPS_PACRC register
2186 #define HW_AIPS_PACRC_ADDR(x) ((x) + 0x28U)
2188 #define HW_AIPS_PACRC(x) (*(__IO hw_aips_pacrc_t *) HW_AIPS_PACRC_ADDR(x))
2189 #define HW_AIPS_PACRC_RD(x) (HW_AIPS_PACRC(x).U)
2190 #define HW_AIPS_PACRC_WR(x, v) (HW_AIPS_PACRC(x).U = (v))
2191 #define HW_AIPS_PACRC_SET(x, v) (HW_AIPS_PACRC_WR(x, HW_AIPS_PACRC_RD(x) | (v)))
2192 #define HW_AIPS_PACRC_CLR(x, v) (HW_AIPS_PACRC_WR(x, HW_AIPS_PACRC_RD(x) & ~(v)))
2193 #define HW_AIPS_PACRC_TOG(x, v) (HW_AIPS_PACRC_WR(x, HW_AIPS_PACRC_RD(x) ^ (v)))
2197 * Constants & macros for individual AIPS_PACRC bitfields
2201 * @name Register AIPS_PACRC, field TP7[0] (RW)
2203 * Determines whether the peripheral allows accesses from an untrusted master.
2204 * When this field is set and an access is attempted by an untrusted master, the
2205 * access terminates with an error response and no peripheral access initiates.
2208 * - 0 - Accesses from an untrusted master are allowed.
2209 * - 1 - Accesses from an untrusted master are not allowed.
2212 #define BP_AIPS_PACRC_TP7 (0U) /*!< Bit position for AIPS_PACRC_TP7. */
2213 #define BM_AIPS_PACRC_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRC_TP7. */
2214 #define BS_AIPS_PACRC_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRC_TP7. */
2216 /*! @brief Read current value of the AIPS_PACRC_TP7 field. */
2217 #define BR_AIPS_PACRC_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP7))
2219 /*! @brief Format value for bitfield AIPS_PACRC_TP7. */
2220 #define BF_AIPS_PACRC_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_TP7) & BM_AIPS_PACRC_TP7)
2222 /*! @brief Set the TP7 field to a new value. */
2223 #define BW_AIPS_PACRC_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP7) = (v))
2227 * @name Register AIPS_PACRC, field WP7[1] (RW)
2229 * Determines whether the peripheral allows write accesses. When this field is
2230 * set and a write access is attempted, access terminates with an error response
2231 * and no peripheral access initiates.
2234 * - 0 - This peripheral allows write accesses.
2235 * - 1 - This peripheral is write protected.
2238 #define BP_AIPS_PACRC_WP7 (1U) /*!< Bit position for AIPS_PACRC_WP7. */
2239 #define BM_AIPS_PACRC_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRC_WP7. */
2240 #define BS_AIPS_PACRC_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRC_WP7. */
2242 /*! @brief Read current value of the AIPS_PACRC_WP7 field. */
2243 #define BR_AIPS_PACRC_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP7))
2245 /*! @brief Format value for bitfield AIPS_PACRC_WP7. */
2246 #define BF_AIPS_PACRC_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_WP7) & BM_AIPS_PACRC_WP7)
2248 /*! @brief Set the WP7 field to a new value. */
2249 #define BW_AIPS_PACRC_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP7) = (v))
2253 * @name Register AIPS_PACRC, field SP7[2] (RW)
2255 * Determines whether the peripheral requires supervisor privilege level for
2256 * accesses. When this field is set, the master privilege level must indicate the
2257 * supervisor access attribute, and the MPRx[MPLn] control field for the master
2258 * must be set. If not, access terminates with an error response and no peripheral
2262 * - 0 - This peripheral does not require supervisor privilege level for
2264 * - 1 - This peripheral requires supervisor privilege level for accesses.
2267 #define BP_AIPS_PACRC_SP7 (2U) /*!< Bit position for AIPS_PACRC_SP7. */
2268 #define BM_AIPS_PACRC_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRC_SP7. */
2269 #define BS_AIPS_PACRC_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRC_SP7. */
2271 /*! @brief Read current value of the AIPS_PACRC_SP7 field. */
2272 #define BR_AIPS_PACRC_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP7))
2274 /*! @brief Format value for bitfield AIPS_PACRC_SP7. */
2275 #define BF_AIPS_PACRC_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_SP7) & BM_AIPS_PACRC_SP7)
2277 /*! @brief Set the SP7 field to a new value. */
2278 #define BW_AIPS_PACRC_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP7) = (v))
2282 * @name Register AIPS_PACRC, field TP6[4] (RW)
2284 * Determines whether the peripheral allows accesses from an untrusted master.
2285 * When this field is set and an access is attempted by an untrusted master, the
2286 * access terminates with an error response and no peripheral access initiates.
2289 * - 0 - Accesses from an untrusted master are allowed.
2290 * - 1 - Accesses from an untrusted master are not allowed.
2293 #define BP_AIPS_PACRC_TP6 (4U) /*!< Bit position for AIPS_PACRC_TP6. */
2294 #define BM_AIPS_PACRC_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRC_TP6. */
2295 #define BS_AIPS_PACRC_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRC_TP6. */
2297 /*! @brief Read current value of the AIPS_PACRC_TP6 field. */
2298 #define BR_AIPS_PACRC_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP6))
2300 /*! @brief Format value for bitfield AIPS_PACRC_TP6. */
2301 #define BF_AIPS_PACRC_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_TP6) & BM_AIPS_PACRC_TP6)
2303 /*! @brief Set the TP6 field to a new value. */
2304 #define BW_AIPS_PACRC_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP6) = (v))
2308 * @name Register AIPS_PACRC, field WP6[5] (RW)
2310 * Determines whether the peripheral allows write accesses. When this field is
2311 * set and a write access is attempted, access terminates with an error response
2312 * and no peripheral access initiates.
2315 * - 0 - This peripheral allows write accesses.
2316 * - 1 - This peripheral is write protected.
2319 #define BP_AIPS_PACRC_WP6 (5U) /*!< Bit position for AIPS_PACRC_WP6. */
2320 #define BM_AIPS_PACRC_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRC_WP6. */
2321 #define BS_AIPS_PACRC_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRC_WP6. */
2323 /*! @brief Read current value of the AIPS_PACRC_WP6 field. */
2324 #define BR_AIPS_PACRC_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP6))
2326 /*! @brief Format value for bitfield AIPS_PACRC_WP6. */
2327 #define BF_AIPS_PACRC_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_WP6) & BM_AIPS_PACRC_WP6)
2329 /*! @brief Set the WP6 field to a new value. */
2330 #define BW_AIPS_PACRC_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP6) = (v))
2334 * @name Register AIPS_PACRC, field SP6[6] (RW)
2336 * Determines whether the peripheral requires supervisor privilege level for
2337 * accesses. When this field is set, the master privilege level must indicate the
2338 * supervisor access attribute, and the MPRx[MPLn] control field for the master
2339 * must be set. If not, access terminates with an error response and no peripheral
2343 * - 0 - This peripheral does not require supervisor privilege level for
2345 * - 1 - This peripheral requires supervisor privilege level for accesses.
2348 #define BP_AIPS_PACRC_SP6 (6U) /*!< Bit position for AIPS_PACRC_SP6. */
2349 #define BM_AIPS_PACRC_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRC_SP6. */
2350 #define BS_AIPS_PACRC_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRC_SP6. */
2352 /*! @brief Read current value of the AIPS_PACRC_SP6 field. */
2353 #define BR_AIPS_PACRC_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP6))
2355 /*! @brief Format value for bitfield AIPS_PACRC_SP6. */
2356 #define BF_AIPS_PACRC_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_SP6) & BM_AIPS_PACRC_SP6)
2358 /*! @brief Set the SP6 field to a new value. */
2359 #define BW_AIPS_PACRC_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP6) = (v))
2363 * @name Register AIPS_PACRC, field TP5[8] (RW)
2365 * Determines whether the peripheral allows accesses from an untrusted master.
2366 * When this field is set and an access is attempted by an untrusted master, the
2367 * access terminates with an error response and no peripheral access initiates.
2370 * - 0 - Accesses from an untrusted master are allowed.
2371 * - 1 - Accesses from an untrusted master are not allowed.
2374 #define BP_AIPS_PACRC_TP5 (8U) /*!< Bit position for AIPS_PACRC_TP5. */
2375 #define BM_AIPS_PACRC_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRC_TP5. */
2376 #define BS_AIPS_PACRC_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRC_TP5. */
2378 /*! @brief Read current value of the AIPS_PACRC_TP5 field. */
2379 #define BR_AIPS_PACRC_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP5))
2381 /*! @brief Format value for bitfield AIPS_PACRC_TP5. */
2382 #define BF_AIPS_PACRC_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_TP5) & BM_AIPS_PACRC_TP5)
2384 /*! @brief Set the TP5 field to a new value. */
2385 #define BW_AIPS_PACRC_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP5) = (v))
2389 * @name Register AIPS_PACRC, field WP5[9] (RW)
2391 * Determines whether the peripheral allows write accesses. When this field is
2392 * set and a write access is attempted, access terminates with an error response
2393 * and no peripheral access initiates.
2396 * - 0 - This peripheral allows write accesses.
2397 * - 1 - This peripheral is write protected.
2400 #define BP_AIPS_PACRC_WP5 (9U) /*!< Bit position for AIPS_PACRC_WP5. */
2401 #define BM_AIPS_PACRC_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRC_WP5. */
2402 #define BS_AIPS_PACRC_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRC_WP5. */
2404 /*! @brief Read current value of the AIPS_PACRC_WP5 field. */
2405 #define BR_AIPS_PACRC_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP5))
2407 /*! @brief Format value for bitfield AIPS_PACRC_WP5. */
2408 #define BF_AIPS_PACRC_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_WP5) & BM_AIPS_PACRC_WP5)
2410 /*! @brief Set the WP5 field to a new value. */
2411 #define BW_AIPS_PACRC_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP5) = (v))
2415 * @name Register AIPS_PACRC, field SP5[10] (RW)
2417 * Determines whether the peripheral requires supervisor privilege level for
2418 * accesses. When this field is set, the master privilege level must indicate the
2419 * supervisor access attribute, and the MPRx[MPLn] control field for the master
2420 * must be set. If not, access terminates with an error response and no peripheral
2424 * - 0 - This peripheral does not require supervisor privilege level for
2426 * - 1 - This peripheral requires supervisor privilege level for accesses.
2429 #define BP_AIPS_PACRC_SP5 (10U) /*!< Bit position for AIPS_PACRC_SP5. */
2430 #define BM_AIPS_PACRC_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRC_SP5. */
2431 #define BS_AIPS_PACRC_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRC_SP5. */
2433 /*! @brief Read current value of the AIPS_PACRC_SP5 field. */
2434 #define BR_AIPS_PACRC_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP5))
2436 /*! @brief Format value for bitfield AIPS_PACRC_SP5. */
2437 #define BF_AIPS_PACRC_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_SP5) & BM_AIPS_PACRC_SP5)
2439 /*! @brief Set the SP5 field to a new value. */
2440 #define BW_AIPS_PACRC_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP5) = (v))
2444 * @name Register AIPS_PACRC, field TP4[12] (RW)
2446 * Determines whether the peripheral allows accesses from an untrusted master.
2447 * When this field is set and an access is attempted by an untrusted master, the
2448 * access terminates with an error response and no peripheral access initiates.
2451 * - 0 - Accesses from an untrusted master are allowed.
2452 * - 1 - Accesses from an untrusted master are not allowed.
2455 #define BP_AIPS_PACRC_TP4 (12U) /*!< Bit position for AIPS_PACRC_TP4. */
2456 #define BM_AIPS_PACRC_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRC_TP4. */
2457 #define BS_AIPS_PACRC_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRC_TP4. */
2459 /*! @brief Read current value of the AIPS_PACRC_TP4 field. */
2460 #define BR_AIPS_PACRC_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP4))
2462 /*! @brief Format value for bitfield AIPS_PACRC_TP4. */
2463 #define BF_AIPS_PACRC_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_TP4) & BM_AIPS_PACRC_TP4)
2465 /*! @brief Set the TP4 field to a new value. */
2466 #define BW_AIPS_PACRC_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP4) = (v))
2470 * @name Register AIPS_PACRC, field WP4[13] (RW)
2472 * Determines whether the peripheral allows write accesss. When this bit is set
2473 * and a write access is attempted, access terminates with an error response and
2474 * no peripheral access initiates.
2477 * - 0 - This peripheral allows write accesses.
2478 * - 1 - This peripheral is write protected.
2481 #define BP_AIPS_PACRC_WP4 (13U) /*!< Bit position for AIPS_PACRC_WP4. */
2482 #define BM_AIPS_PACRC_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRC_WP4. */
2483 #define BS_AIPS_PACRC_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRC_WP4. */
2485 /*! @brief Read current value of the AIPS_PACRC_WP4 field. */
2486 #define BR_AIPS_PACRC_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP4))
2488 /*! @brief Format value for bitfield AIPS_PACRC_WP4. */
2489 #define BF_AIPS_PACRC_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_WP4) & BM_AIPS_PACRC_WP4)
2491 /*! @brief Set the WP4 field to a new value. */
2492 #define BW_AIPS_PACRC_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP4) = (v))
2496 * @name Register AIPS_PACRC, field SP4[14] (RW)
2498 * Determines whether the peripheral requires supervisor privilege level for
2499 * accesses. When this field is set, the master privilege level must indicate the
2500 * supervisor access attribute, and the MPRx[MPLn] control field for the master
2501 * must be set. If not, access terminates with an error response and no peripheral
2505 * - 0 - This peripheral does not require supervisor privilege level for
2507 * - 1 - This peripheral requires supervisor privilege level for accesses.
2510 #define BP_AIPS_PACRC_SP4 (14U) /*!< Bit position for AIPS_PACRC_SP4. */
2511 #define BM_AIPS_PACRC_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRC_SP4. */
2512 #define BS_AIPS_PACRC_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRC_SP4. */
2514 /*! @brief Read current value of the AIPS_PACRC_SP4 field. */
2515 #define BR_AIPS_PACRC_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP4))
2517 /*! @brief Format value for bitfield AIPS_PACRC_SP4. */
2518 #define BF_AIPS_PACRC_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_SP4) & BM_AIPS_PACRC_SP4)
2520 /*! @brief Set the SP4 field to a new value. */
2521 #define BW_AIPS_PACRC_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP4) = (v))
2525 * @name Register AIPS_PACRC, field TP3[16] (RW)
2527 * Determines whether the peripheral allows accesses from an untrusted master.
2528 * When this bit is set and an access is attempted by an untrusted master, the
2529 * access terminates with an error response and no peripheral access initiates.
2532 * - 0 - Accesses from an untrusted master are allowed.
2533 * - 1 - Accesses from an untrusted master are not allowed.
2536 #define BP_AIPS_PACRC_TP3 (16U) /*!< Bit position for AIPS_PACRC_TP3. */
2537 #define BM_AIPS_PACRC_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRC_TP3. */
2538 #define BS_AIPS_PACRC_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRC_TP3. */
2540 /*! @brief Read current value of the AIPS_PACRC_TP3 field. */
2541 #define BR_AIPS_PACRC_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP3))
2543 /*! @brief Format value for bitfield AIPS_PACRC_TP3. */
2544 #define BF_AIPS_PACRC_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_TP3) & BM_AIPS_PACRC_TP3)
2546 /*! @brief Set the TP3 field to a new value. */
2547 #define BW_AIPS_PACRC_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP3) = (v))
2551 * @name Register AIPS_PACRC, field WP3[17] (RW)
2553 * Determines whether the peripheral allows write accesses. When this field is
2554 * set and a write access is attempted, access terminates with an error response
2555 * and no peripheral access initiates.
2558 * - 0 - This peripheral allows write accesses.
2559 * - 1 - This peripheral is write protected.
2562 #define BP_AIPS_PACRC_WP3 (17U) /*!< Bit position for AIPS_PACRC_WP3. */
2563 #define BM_AIPS_PACRC_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRC_WP3. */
2564 #define BS_AIPS_PACRC_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRC_WP3. */
2566 /*! @brief Read current value of the AIPS_PACRC_WP3 field. */
2567 #define BR_AIPS_PACRC_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP3))
2569 /*! @brief Format value for bitfield AIPS_PACRC_WP3. */
2570 #define BF_AIPS_PACRC_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_WP3) & BM_AIPS_PACRC_WP3)
2572 /*! @brief Set the WP3 field to a new value. */
2573 #define BW_AIPS_PACRC_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP3) = (v))
2577 * @name Register AIPS_PACRC, field SP3[18] (RW)
2579 * Determines whether the peripheral requires supervisor privilege level for
2580 * access. When this bit is set, the master privilege level must indicate the
2581 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
2582 * set. If not, access terminates with an error response and no peripheral access
2586 * - 0 - This peripheral does not require supervisor privilege level for
2588 * - 1 - This peripheral requires supervisor privilege level for accesses.
2591 #define BP_AIPS_PACRC_SP3 (18U) /*!< Bit position for AIPS_PACRC_SP3. */
2592 #define BM_AIPS_PACRC_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRC_SP3. */
2593 #define BS_AIPS_PACRC_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRC_SP3. */
2595 /*! @brief Read current value of the AIPS_PACRC_SP3 field. */
2596 #define BR_AIPS_PACRC_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP3))
2598 /*! @brief Format value for bitfield AIPS_PACRC_SP3. */
2599 #define BF_AIPS_PACRC_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_SP3) & BM_AIPS_PACRC_SP3)
2601 /*! @brief Set the SP3 field to a new value. */
2602 #define BW_AIPS_PACRC_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP3) = (v))
2606 * @name Register AIPS_PACRC, field TP2[20] (RW)
2608 * Determines whether the peripheral allows accesses from an untrusted master.
2609 * When this field is set and an access is attempted by an untrusted master, the
2610 * access terminates with an error response and no peripheral access initiates.
2613 * - 0 - Accesses from an untrusted master are allowed.
2614 * - 1 - Accesses from an untrusted master are not allowed.
2617 #define BP_AIPS_PACRC_TP2 (20U) /*!< Bit position for AIPS_PACRC_TP2. */
2618 #define BM_AIPS_PACRC_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRC_TP2. */
2619 #define BS_AIPS_PACRC_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRC_TP2. */
2621 /*! @brief Read current value of the AIPS_PACRC_TP2 field. */
2622 #define BR_AIPS_PACRC_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP2))
2624 /*! @brief Format value for bitfield AIPS_PACRC_TP2. */
2625 #define BF_AIPS_PACRC_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_TP2) & BM_AIPS_PACRC_TP2)
2627 /*! @brief Set the TP2 field to a new value. */
2628 #define BW_AIPS_PACRC_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP2) = (v))
2632 * @name Register AIPS_PACRC, field WP2[21] (RW)
2634 * Determines whether the peripheral allows write accesss. When this bit is set
2635 * and a write access is attempted, access terminates with an error response and
2636 * no peripheral access initiates.
2639 * - 0 - This peripheral allows write accesses.
2640 * - 1 - This peripheral is write protected.
2643 #define BP_AIPS_PACRC_WP2 (21U) /*!< Bit position for AIPS_PACRC_WP2. */
2644 #define BM_AIPS_PACRC_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRC_WP2. */
2645 #define BS_AIPS_PACRC_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRC_WP2. */
2647 /*! @brief Read current value of the AIPS_PACRC_WP2 field. */
2648 #define BR_AIPS_PACRC_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP2))
2650 /*! @brief Format value for bitfield AIPS_PACRC_WP2. */
2651 #define BF_AIPS_PACRC_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_WP2) & BM_AIPS_PACRC_WP2)
2653 /*! @brief Set the WP2 field to a new value. */
2654 #define BW_AIPS_PACRC_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP2) = (v))
2658 * @name Register AIPS_PACRC, field SP2[22] (RW)
2660 * Determines whether the peripheral requires supervisor privilege level for
2661 * accesses. When this field is set, the master privilege level must indicate the
2662 * supervisor access attribute, and the MPRx[MPLn] control field for the master
2663 * must be set. If not, access terminates with an error response and no peripheral
2667 * - 0 - This peripheral does not require supervisor privilege level for
2669 * - 1 - This peripheral requires supervisor privilege level for accesses.
2672 #define BP_AIPS_PACRC_SP2 (22U) /*!< Bit position for AIPS_PACRC_SP2. */
2673 #define BM_AIPS_PACRC_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRC_SP2. */
2674 #define BS_AIPS_PACRC_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRC_SP2. */
2676 /*! @brief Read current value of the AIPS_PACRC_SP2 field. */
2677 #define BR_AIPS_PACRC_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP2))
2679 /*! @brief Format value for bitfield AIPS_PACRC_SP2. */
2680 #define BF_AIPS_PACRC_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_SP2) & BM_AIPS_PACRC_SP2)
2682 /*! @brief Set the SP2 field to a new value. */
2683 #define BW_AIPS_PACRC_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP2) = (v))
2687 * @name Register AIPS_PACRC, field TP1[24] (RW)
2689 * Determines whether the peripheral allows accesses from an untrusted master.
2690 * When this bit is set and an access is attempted by an untrusted master, the
2691 * access terminates with an error response and no peripheral access initiates.
2694 * - 0 - Accesses from an untrusted master are allowed.
2695 * - 1 - Accesses from an untrusted master are not allowed.
2698 #define BP_AIPS_PACRC_TP1 (24U) /*!< Bit position for AIPS_PACRC_TP1. */
2699 #define BM_AIPS_PACRC_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRC_TP1. */
2700 #define BS_AIPS_PACRC_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRC_TP1. */
2702 /*! @brief Read current value of the AIPS_PACRC_TP1 field. */
2703 #define BR_AIPS_PACRC_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP1))
2705 /*! @brief Format value for bitfield AIPS_PACRC_TP1. */
2706 #define BF_AIPS_PACRC_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_TP1) & BM_AIPS_PACRC_TP1)
2708 /*! @brief Set the TP1 field to a new value. */
2709 #define BW_AIPS_PACRC_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP1) = (v))
2713 * @name Register AIPS_PACRC, field WP1[25] (RW)
2715 * Determines whether the peripheral allows write accesses. When this field is
2716 * set and a write access is attempted, access terminates with an error response
2717 * and no peripheral access initiates.
2720 * - 0 - This peripheral allows write accesses.
2721 * - 1 - This peripheral is write protected.
2724 #define BP_AIPS_PACRC_WP1 (25U) /*!< Bit position for AIPS_PACRC_WP1. */
2725 #define BM_AIPS_PACRC_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRC_WP1. */
2726 #define BS_AIPS_PACRC_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRC_WP1. */
2728 /*! @brief Read current value of the AIPS_PACRC_WP1 field. */
2729 #define BR_AIPS_PACRC_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP1))
2731 /*! @brief Format value for bitfield AIPS_PACRC_WP1. */
2732 #define BF_AIPS_PACRC_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_WP1) & BM_AIPS_PACRC_WP1)
2734 /*! @brief Set the WP1 field to a new value. */
2735 #define BW_AIPS_PACRC_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP1) = (v))
2739 * @name Register AIPS_PACRC, field SP1[26] (RW)
2741 * Determines whether the peripheral requires supervisor privilege level for
2742 * accesses. When this field is set, the master privilege level must indicate the
2743 * supervisor access attribute, and the MPRx[MPLn] control field for the master
2744 * must be set. If not, access terminates with an error response and no peripheral
2748 * - 0 - This peripheral does not require supervisor privilege level for
2750 * - 1 - This peripheral requires supervisor privilege level for accesses.
2753 #define BP_AIPS_PACRC_SP1 (26U) /*!< Bit position for AIPS_PACRC_SP1. */
2754 #define BM_AIPS_PACRC_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRC_SP1. */
2755 #define BS_AIPS_PACRC_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRC_SP1. */
2757 /*! @brief Read current value of the AIPS_PACRC_SP1 field. */
2758 #define BR_AIPS_PACRC_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP1))
2760 /*! @brief Format value for bitfield AIPS_PACRC_SP1. */
2761 #define BF_AIPS_PACRC_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_SP1) & BM_AIPS_PACRC_SP1)
2763 /*! @brief Set the SP1 field to a new value. */
2764 #define BW_AIPS_PACRC_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP1) = (v))
2768 * @name Register AIPS_PACRC, field TP0[28] (RW)
2770 * Determines whether the peripheral allows accesses from an untrusted master.
2771 * When this field is set and an access is attempted by an untrusted master, the
2772 * access terminates with an error response and no peripheral access initiates.
2775 * - 0 - Accesses from an untrusted master are allowed.
2776 * - 1 - Accesses from an untrusted master are not allowed.
2779 #define BP_AIPS_PACRC_TP0 (28U) /*!< Bit position for AIPS_PACRC_TP0. */
2780 #define BM_AIPS_PACRC_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRC_TP0. */
2781 #define BS_AIPS_PACRC_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRC_TP0. */
2783 /*! @brief Read current value of the AIPS_PACRC_TP0 field. */
2784 #define BR_AIPS_PACRC_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP0))
2786 /*! @brief Format value for bitfield AIPS_PACRC_TP0. */
2787 #define BF_AIPS_PACRC_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_TP0) & BM_AIPS_PACRC_TP0)
2789 /*! @brief Set the TP0 field to a new value. */
2790 #define BW_AIPS_PACRC_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP0) = (v))
2794 * @name Register AIPS_PACRC, field WP0[29] (RW)
2796 * Determines whether the peripheral allows write accesss. When this bit is set
2797 * and a write access is attempted, access terminates with an error response and
2798 * no peripheral access initiates.
2801 * - 0 - This peripheral allows write accesses.
2802 * - 1 - This peripheral is write protected.
2805 #define BP_AIPS_PACRC_WP0 (29U) /*!< Bit position for AIPS_PACRC_WP0. */
2806 #define BM_AIPS_PACRC_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRC_WP0. */
2807 #define BS_AIPS_PACRC_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRC_WP0. */
2809 /*! @brief Read current value of the AIPS_PACRC_WP0 field. */
2810 #define BR_AIPS_PACRC_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP0))
2812 /*! @brief Format value for bitfield AIPS_PACRC_WP0. */
2813 #define BF_AIPS_PACRC_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_WP0) & BM_AIPS_PACRC_WP0)
2815 /*! @brief Set the WP0 field to a new value. */
2816 #define BW_AIPS_PACRC_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP0) = (v))
2820 * @name Register AIPS_PACRC, field SP0[30] (RW)
2822 * Determines whether the peripheral requires supervisor privilege level for
2823 * accesses. When this field is set, the master privilege level must indicate the
2824 * supervisor access attribute, and the MPRx[MPLn] control field for the master
2825 * must be set. If not, access terminates with an error response and no peripheral
2829 * - 0 - This peripheral does not require supervisor privilege level for
2831 * - 1 - This peripheral requires supervisor privilege level for accesses.
2834 #define BP_AIPS_PACRC_SP0 (30U) /*!< Bit position for AIPS_PACRC_SP0. */
2835 #define BM_AIPS_PACRC_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRC_SP0. */
2836 #define BS_AIPS_PACRC_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRC_SP0. */
2838 /*! @brief Read current value of the AIPS_PACRC_SP0 field. */
2839 #define BR_AIPS_PACRC_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP0))
2841 /*! @brief Format value for bitfield AIPS_PACRC_SP0. */
2842 #define BF_AIPS_PACRC_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_SP0) & BM_AIPS_PACRC_SP0)
2844 /*! @brief Set the SP0 field to a new value. */
2845 #define BW_AIPS_PACRC_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP0) = (v))
2848 /*******************************************************************************
2849 * HW_AIPS_PACRD - Peripheral Access Control Register
2850 ******************************************************************************/
2853 * @brief HW_AIPS_PACRD - Peripheral Access Control Register (RW)
2855 * Reset value: 0x00000004U
2857 * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
2858 * defines the access levels for a particular peripheral. The mapping between a
2859 * peripheral and its PACR field is shown in the table below. The peripheral assignment
2860 * to each PACR is defined by the memory map slot that the peripheral is
2861 * assigned to. See this chip's memory map for the assignment of a particular
2862 * peripheral. The following table shows the location of each peripheral slot's PACR field
2863 * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
2864 * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
2865 * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
2866 * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
2867 * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
2868 * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
2869 * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
2870 * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
2871 * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
2872 * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
2873 * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
2874 * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
2875 * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
2876 * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
2877 * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
2878 * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
2879 * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
2880 * A-D, which control peripheral slots 0-31, are shown below. The following
2881 * section, PACRPeripheral Access Control Register , shows the register field
2882 * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
2883 * sections because they occupy two non-contiguous address spaces.
2885 typedef union _hw_aips_pacrd
2888 struct _hw_aips_pacrd_bitfields
2890 uint32_t TP7
: 1; /*!< [0] Trusted Protect */
2891 uint32_t WP7
: 1; /*!< [1] Write Protect */
2892 uint32_t SP7
: 1; /*!< [2] Supervisor Protect */
2893 uint32_t RESERVED0
: 1; /*!< [3] */
2894 uint32_t TP6
: 1; /*!< [4] Trusted Protect */
2895 uint32_t WP6
: 1; /*!< [5] Write Protect */
2896 uint32_t SP6
: 1; /*!< [6] Supervisor Protect */
2897 uint32_t RESERVED1
: 1; /*!< [7] */
2898 uint32_t TP5
: 1; /*!< [8] Trusted Protect */
2899 uint32_t WP5
: 1; /*!< [9] Write Protect */
2900 uint32_t SP5
: 1; /*!< [10] Supervisor Protect */
2901 uint32_t RESERVED2
: 1; /*!< [11] */
2902 uint32_t TP4
: 1; /*!< [12] Trusted Protect */
2903 uint32_t WP4
: 1; /*!< [13] Write Protect */
2904 uint32_t SP4
: 1; /*!< [14] Supervisor Protect */
2905 uint32_t RESERVED3
: 1; /*!< [15] */
2906 uint32_t TP3
: 1; /*!< [16] Trusted Protect */
2907 uint32_t WP3
: 1; /*!< [17] Write Protect */
2908 uint32_t SP3
: 1; /*!< [18] Supervisor Protect */
2909 uint32_t RESERVED4
: 1; /*!< [19] */
2910 uint32_t TP2
: 1; /*!< [20] Trusted Protect */
2911 uint32_t WP2
: 1; /*!< [21] Write Protect */
2912 uint32_t SP2
: 1; /*!< [22] Supervisor Protect */
2913 uint32_t RESERVED5
: 1; /*!< [23] */
2914 uint32_t TP1
: 1; /*!< [24] Trusted Protect */
2915 uint32_t WP1
: 1; /*!< [25] Write Protect */
2916 uint32_t SP1
: 1; /*!< [26] Supervisor Protect */
2917 uint32_t RESERVED6
: 1; /*!< [27] */
2918 uint32_t TP0
: 1; /*!< [28] Trusted Protect */
2919 uint32_t WP0
: 1; /*!< [29] Write Protect */
2920 uint32_t SP0
: 1; /*!< [30] Supervisor Protect */
2921 uint32_t RESERVED7
: 1; /*!< [31] */
2926 * @name Constants and macros for entire AIPS_PACRD register
2929 #define HW_AIPS_PACRD_ADDR(x) ((x) + 0x2CU)
2931 #define HW_AIPS_PACRD(x) (*(__IO hw_aips_pacrd_t *) HW_AIPS_PACRD_ADDR(x))
2932 #define HW_AIPS_PACRD_RD(x) (HW_AIPS_PACRD(x).U)
2933 #define HW_AIPS_PACRD_WR(x, v) (HW_AIPS_PACRD(x).U = (v))
2934 #define HW_AIPS_PACRD_SET(x, v) (HW_AIPS_PACRD_WR(x, HW_AIPS_PACRD_RD(x) | (v)))
2935 #define HW_AIPS_PACRD_CLR(x, v) (HW_AIPS_PACRD_WR(x, HW_AIPS_PACRD_RD(x) & ~(v)))
2936 #define HW_AIPS_PACRD_TOG(x, v) (HW_AIPS_PACRD_WR(x, HW_AIPS_PACRD_RD(x) ^ (v)))
2940 * Constants & macros for individual AIPS_PACRD bitfields
2944 * @name Register AIPS_PACRD, field TP7[0] (RW)
2946 * Determines whether the peripheral allows accesses from an untrusted master.
2947 * When this field is set and an access is attempted by an untrusted master, the
2948 * access terminates with an error response and no peripheral access initiates.
2951 * - 0 - Accesses from an untrusted master are allowed.
2952 * - 1 - Accesses from an untrusted master are not allowed.
2955 #define BP_AIPS_PACRD_TP7 (0U) /*!< Bit position for AIPS_PACRD_TP7. */
2956 #define BM_AIPS_PACRD_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRD_TP7. */
2957 #define BS_AIPS_PACRD_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRD_TP7. */
2959 /*! @brief Read current value of the AIPS_PACRD_TP7 field. */
2960 #define BR_AIPS_PACRD_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP7))
2962 /*! @brief Format value for bitfield AIPS_PACRD_TP7. */
2963 #define BF_AIPS_PACRD_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_TP7) & BM_AIPS_PACRD_TP7)
2965 /*! @brief Set the TP7 field to a new value. */
2966 #define BW_AIPS_PACRD_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP7) = (v))
2970 * @name Register AIPS_PACRD, field WP7[1] (RW)
2972 * Determines whether the peripheral allows write accesses. When this field is
2973 * set and a write access is attempted, access terminates with an error response
2974 * and no peripheral access initiates.
2977 * - 0 - This peripheral allows write accesses.
2978 * - 1 - This peripheral is write protected.
2981 #define BP_AIPS_PACRD_WP7 (1U) /*!< Bit position for AIPS_PACRD_WP7. */
2982 #define BM_AIPS_PACRD_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRD_WP7. */
2983 #define BS_AIPS_PACRD_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRD_WP7. */
2985 /*! @brief Read current value of the AIPS_PACRD_WP7 field. */
2986 #define BR_AIPS_PACRD_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP7))
2988 /*! @brief Format value for bitfield AIPS_PACRD_WP7. */
2989 #define BF_AIPS_PACRD_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_WP7) & BM_AIPS_PACRD_WP7)
2991 /*! @brief Set the WP7 field to a new value. */
2992 #define BW_AIPS_PACRD_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP7) = (v))
2996 * @name Register AIPS_PACRD, field SP7[2] (RW)
2998 * Determines whether the peripheral requires supervisor privilege level for
2999 * accesses. When this field is set, the master privilege level must indicate the
3000 * supervisor access attribute, and the MPRx[MPLn] control field for the master
3001 * must be set. If not, access terminates with an error response and no peripheral
3005 * - 0 - This peripheral does not require supervisor privilege level for
3007 * - 1 - This peripheral requires supervisor privilege level for accesses.
3010 #define BP_AIPS_PACRD_SP7 (2U) /*!< Bit position for AIPS_PACRD_SP7. */
3011 #define BM_AIPS_PACRD_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRD_SP7. */
3012 #define BS_AIPS_PACRD_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRD_SP7. */
3014 /*! @brief Read current value of the AIPS_PACRD_SP7 field. */
3015 #define BR_AIPS_PACRD_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP7))
3017 /*! @brief Format value for bitfield AIPS_PACRD_SP7. */
3018 #define BF_AIPS_PACRD_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_SP7) & BM_AIPS_PACRD_SP7)
3020 /*! @brief Set the SP7 field to a new value. */
3021 #define BW_AIPS_PACRD_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP7) = (v))
3025 * @name Register AIPS_PACRD, field TP6[4] (RW)
3027 * Determines whether the peripheral allows accesses from an untrusted master.
3028 * When this field is set and an access is attempted by an untrusted master, the
3029 * access terminates with an error response and no peripheral access initiates.
3032 * - 0 - Accesses from an untrusted master are allowed.
3033 * - 1 - Accesses from an untrusted master are not allowed.
3036 #define BP_AIPS_PACRD_TP6 (4U) /*!< Bit position for AIPS_PACRD_TP6. */
3037 #define BM_AIPS_PACRD_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRD_TP6. */
3038 #define BS_AIPS_PACRD_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRD_TP6. */
3040 /*! @brief Read current value of the AIPS_PACRD_TP6 field. */
3041 #define BR_AIPS_PACRD_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP6))
3043 /*! @brief Format value for bitfield AIPS_PACRD_TP6. */
3044 #define BF_AIPS_PACRD_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_TP6) & BM_AIPS_PACRD_TP6)
3046 /*! @brief Set the TP6 field to a new value. */
3047 #define BW_AIPS_PACRD_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP6) = (v))
3051 * @name Register AIPS_PACRD, field WP6[5] (RW)
3053 * Determines whether the peripheral allows write accesses. When this field is
3054 * set and a write access is attempted, access terminates with an error response
3055 * and no peripheral access initiates.
3058 * - 0 - This peripheral allows write accesses.
3059 * - 1 - This peripheral is write protected.
3062 #define BP_AIPS_PACRD_WP6 (5U) /*!< Bit position for AIPS_PACRD_WP6. */
3063 #define BM_AIPS_PACRD_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRD_WP6. */
3064 #define BS_AIPS_PACRD_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRD_WP6. */
3066 /*! @brief Read current value of the AIPS_PACRD_WP6 field. */
3067 #define BR_AIPS_PACRD_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP6))
3069 /*! @brief Format value for bitfield AIPS_PACRD_WP6. */
3070 #define BF_AIPS_PACRD_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_WP6) & BM_AIPS_PACRD_WP6)
3072 /*! @brief Set the WP6 field to a new value. */
3073 #define BW_AIPS_PACRD_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP6) = (v))
3077 * @name Register AIPS_PACRD, field SP6[6] (RW)
3079 * Determines whether the peripheral requires supervisor privilege level for
3080 * accesses. When this field is set, the master privilege level must indicate the
3081 * supervisor access attribute, and the MPRx[MPLn] control field for the master
3082 * must be set. If not, access terminates with an error response and no peripheral
3086 * - 0 - This peripheral does not require supervisor privilege level for
3088 * - 1 - This peripheral requires supervisor privilege level for accesses.
3091 #define BP_AIPS_PACRD_SP6 (6U) /*!< Bit position for AIPS_PACRD_SP6. */
3092 #define BM_AIPS_PACRD_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRD_SP6. */
3093 #define BS_AIPS_PACRD_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRD_SP6. */
3095 /*! @brief Read current value of the AIPS_PACRD_SP6 field. */
3096 #define BR_AIPS_PACRD_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP6))
3098 /*! @brief Format value for bitfield AIPS_PACRD_SP6. */
3099 #define BF_AIPS_PACRD_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_SP6) & BM_AIPS_PACRD_SP6)
3101 /*! @brief Set the SP6 field to a new value. */
3102 #define BW_AIPS_PACRD_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP6) = (v))
3106 * @name Register AIPS_PACRD, field TP5[8] (RW)
3108 * Determines whether the peripheral allows accesses from an untrusted master.
3109 * When this field is set and an access is attempted by an untrusted master, the
3110 * access terminates with an error response and no peripheral access initiates.
3113 * - 0 - Accesses from an untrusted master are allowed.
3114 * - 1 - Accesses from an untrusted master are not allowed.
3117 #define BP_AIPS_PACRD_TP5 (8U) /*!< Bit position for AIPS_PACRD_TP5. */
3118 #define BM_AIPS_PACRD_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRD_TP5. */
3119 #define BS_AIPS_PACRD_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRD_TP5. */
3121 /*! @brief Read current value of the AIPS_PACRD_TP5 field. */
3122 #define BR_AIPS_PACRD_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP5))
3124 /*! @brief Format value for bitfield AIPS_PACRD_TP5. */
3125 #define BF_AIPS_PACRD_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_TP5) & BM_AIPS_PACRD_TP5)
3127 /*! @brief Set the TP5 field to a new value. */
3128 #define BW_AIPS_PACRD_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP5) = (v))
3132 * @name Register AIPS_PACRD, field WP5[9] (RW)
3134 * Determines whether the peripheral allows write accesses. When this field is
3135 * set and a write access is attempted, access terminates with an error response
3136 * and no peripheral access initiates.
3139 * - 0 - This peripheral allows write accesses.
3140 * - 1 - This peripheral is write protected.
3143 #define BP_AIPS_PACRD_WP5 (9U) /*!< Bit position for AIPS_PACRD_WP5. */
3144 #define BM_AIPS_PACRD_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRD_WP5. */
3145 #define BS_AIPS_PACRD_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRD_WP5. */
3147 /*! @brief Read current value of the AIPS_PACRD_WP5 field. */
3148 #define BR_AIPS_PACRD_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP5))
3150 /*! @brief Format value for bitfield AIPS_PACRD_WP5. */
3151 #define BF_AIPS_PACRD_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_WP5) & BM_AIPS_PACRD_WP5)
3153 /*! @brief Set the WP5 field to a new value. */
3154 #define BW_AIPS_PACRD_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP5) = (v))
3158 * @name Register AIPS_PACRD, field SP5[10] (RW)
3160 * Determines whether the peripheral requires supervisor privilege level for
3161 * accesses. When this field is set, the master privilege level must indicate the
3162 * supervisor access attribute, and the MPRx[MPLn] control field for the master
3163 * must be set. If not, access terminates with an error response and no peripheral
3167 * - 0 - This peripheral does not require supervisor privilege level for
3169 * - 1 - This peripheral requires supervisor privilege level for accesses.
3172 #define BP_AIPS_PACRD_SP5 (10U) /*!< Bit position for AIPS_PACRD_SP5. */
3173 #define BM_AIPS_PACRD_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRD_SP5. */
3174 #define BS_AIPS_PACRD_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRD_SP5. */
3176 /*! @brief Read current value of the AIPS_PACRD_SP5 field. */
3177 #define BR_AIPS_PACRD_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP5))
3179 /*! @brief Format value for bitfield AIPS_PACRD_SP5. */
3180 #define BF_AIPS_PACRD_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_SP5) & BM_AIPS_PACRD_SP5)
3182 /*! @brief Set the SP5 field to a new value. */
3183 #define BW_AIPS_PACRD_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP5) = (v))
3187 * @name Register AIPS_PACRD, field TP4[12] (RW)
3189 * Determines whether the peripheral allows accesses from an untrusted master.
3190 * When this field is set and an access is attempted by an untrusted master, the
3191 * access terminates with an error response and no peripheral access initiates.
3194 * - 0 - Accesses from an untrusted master are allowed.
3195 * - 1 - Accesses from an untrusted master are not allowed.
3198 #define BP_AIPS_PACRD_TP4 (12U) /*!< Bit position for AIPS_PACRD_TP4. */
3199 #define BM_AIPS_PACRD_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRD_TP4. */
3200 #define BS_AIPS_PACRD_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRD_TP4. */
3202 /*! @brief Read current value of the AIPS_PACRD_TP4 field. */
3203 #define BR_AIPS_PACRD_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP4))
3205 /*! @brief Format value for bitfield AIPS_PACRD_TP4. */
3206 #define BF_AIPS_PACRD_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_TP4) & BM_AIPS_PACRD_TP4)
3208 /*! @brief Set the TP4 field to a new value. */
3209 #define BW_AIPS_PACRD_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP4) = (v))
3213 * @name Register AIPS_PACRD, field WP4[13] (RW)
3215 * Determines whether the peripheral allows write accesss. When this bit is set
3216 * and a write access is attempted, access terminates with an error response and
3217 * no peripheral access initiates.
3220 * - 0 - This peripheral allows write accesses.
3221 * - 1 - This peripheral is write protected.
3224 #define BP_AIPS_PACRD_WP4 (13U) /*!< Bit position for AIPS_PACRD_WP4. */
3225 #define BM_AIPS_PACRD_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRD_WP4. */
3226 #define BS_AIPS_PACRD_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRD_WP4. */
3228 /*! @brief Read current value of the AIPS_PACRD_WP4 field. */
3229 #define BR_AIPS_PACRD_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP4))
3231 /*! @brief Format value for bitfield AIPS_PACRD_WP4. */
3232 #define BF_AIPS_PACRD_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_WP4) & BM_AIPS_PACRD_WP4)
3234 /*! @brief Set the WP4 field to a new value. */
3235 #define BW_AIPS_PACRD_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP4) = (v))
3239 * @name Register AIPS_PACRD, field SP4[14] (RW)
3241 * Determines whether the peripheral requires supervisor privilege level for
3242 * accesses. When this field is set, the master privilege level must indicate the
3243 * supervisor access attribute, and the MPRx[MPLn] control field for the master
3244 * must be set. If not, access terminates with an error response and no peripheral
3248 * - 0 - This peripheral does not require supervisor privilege level for
3250 * - 1 - This peripheral requires supervisor privilege level for accesses.
3253 #define BP_AIPS_PACRD_SP4 (14U) /*!< Bit position for AIPS_PACRD_SP4. */
3254 #define BM_AIPS_PACRD_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRD_SP4. */
3255 #define BS_AIPS_PACRD_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRD_SP4. */
3257 /*! @brief Read current value of the AIPS_PACRD_SP4 field. */
3258 #define BR_AIPS_PACRD_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP4))
3260 /*! @brief Format value for bitfield AIPS_PACRD_SP4. */
3261 #define BF_AIPS_PACRD_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_SP4) & BM_AIPS_PACRD_SP4)
3263 /*! @brief Set the SP4 field to a new value. */
3264 #define BW_AIPS_PACRD_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP4) = (v))
3268 * @name Register AIPS_PACRD, field TP3[16] (RW)
3270 * Determines whether the peripheral allows accesses from an untrusted master.
3271 * When this bit is set and an access is attempted by an untrusted master, the
3272 * access terminates with an error response and no peripheral access initiates.
3275 * - 0 - Accesses from an untrusted master are allowed.
3276 * - 1 - Accesses from an untrusted master are not allowed.
3279 #define BP_AIPS_PACRD_TP3 (16U) /*!< Bit position for AIPS_PACRD_TP3. */
3280 #define BM_AIPS_PACRD_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRD_TP3. */
3281 #define BS_AIPS_PACRD_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRD_TP3. */
3283 /*! @brief Read current value of the AIPS_PACRD_TP3 field. */
3284 #define BR_AIPS_PACRD_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP3))
3286 /*! @brief Format value for bitfield AIPS_PACRD_TP3. */
3287 #define BF_AIPS_PACRD_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_TP3) & BM_AIPS_PACRD_TP3)
3289 /*! @brief Set the TP3 field to a new value. */
3290 #define BW_AIPS_PACRD_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP3) = (v))
3294 * @name Register AIPS_PACRD, field WP3[17] (RW)
3296 * Determines whether the peripheral allows write accesses. When this field is
3297 * set and a write access is attempted, access terminates with an error response
3298 * and no peripheral access initiates.
3301 * - 0 - This peripheral allows write accesses.
3302 * - 1 - This peripheral is write protected.
3305 #define BP_AIPS_PACRD_WP3 (17U) /*!< Bit position for AIPS_PACRD_WP3. */
3306 #define BM_AIPS_PACRD_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRD_WP3. */
3307 #define BS_AIPS_PACRD_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRD_WP3. */
3309 /*! @brief Read current value of the AIPS_PACRD_WP3 field. */
3310 #define BR_AIPS_PACRD_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP3))
3312 /*! @brief Format value for bitfield AIPS_PACRD_WP3. */
3313 #define BF_AIPS_PACRD_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_WP3) & BM_AIPS_PACRD_WP3)
3315 /*! @brief Set the WP3 field to a new value. */
3316 #define BW_AIPS_PACRD_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP3) = (v))
3320 * @name Register AIPS_PACRD, field SP3[18] (RW)
3322 * Determines whether the peripheral requires supervisor privilege level for
3323 * access. When this bit is set, the master privilege level must indicate the
3324 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
3325 * set. If not, access terminates with an error response and no peripheral access
3329 * - 0 - This peripheral does not require supervisor privilege level for
3331 * - 1 - This peripheral requires supervisor privilege level for accesses.
3334 #define BP_AIPS_PACRD_SP3 (18U) /*!< Bit position for AIPS_PACRD_SP3. */
3335 #define BM_AIPS_PACRD_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRD_SP3. */
3336 #define BS_AIPS_PACRD_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRD_SP3. */
3338 /*! @brief Read current value of the AIPS_PACRD_SP3 field. */
3339 #define BR_AIPS_PACRD_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP3))
3341 /*! @brief Format value for bitfield AIPS_PACRD_SP3. */
3342 #define BF_AIPS_PACRD_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_SP3) & BM_AIPS_PACRD_SP3)
3344 /*! @brief Set the SP3 field to a new value. */
3345 #define BW_AIPS_PACRD_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP3) = (v))
3349 * @name Register AIPS_PACRD, field TP2[20] (RW)
3351 * Determines whether the peripheral allows accesses from an untrusted master.
3352 * When this field is set and an access is attempted by an untrusted master, the
3353 * access terminates with an error response and no peripheral access initiates.
3356 * - 0 - Accesses from an untrusted master are allowed.
3357 * - 1 - Accesses from an untrusted master are not allowed.
3360 #define BP_AIPS_PACRD_TP2 (20U) /*!< Bit position for AIPS_PACRD_TP2. */
3361 #define BM_AIPS_PACRD_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRD_TP2. */
3362 #define BS_AIPS_PACRD_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRD_TP2. */
3364 /*! @brief Read current value of the AIPS_PACRD_TP2 field. */
3365 #define BR_AIPS_PACRD_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP2))
3367 /*! @brief Format value for bitfield AIPS_PACRD_TP2. */
3368 #define BF_AIPS_PACRD_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_TP2) & BM_AIPS_PACRD_TP2)
3370 /*! @brief Set the TP2 field to a new value. */
3371 #define BW_AIPS_PACRD_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP2) = (v))
3375 * @name Register AIPS_PACRD, field WP2[21] (RW)
3377 * Determines whether the peripheral allows write accesss. When this bit is set
3378 * and a write access is attempted, access terminates with an error response and
3379 * no peripheral access initiates.
3382 * - 0 - This peripheral allows write accesses.
3383 * - 1 - This peripheral is write protected.
3386 #define BP_AIPS_PACRD_WP2 (21U) /*!< Bit position for AIPS_PACRD_WP2. */
3387 #define BM_AIPS_PACRD_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRD_WP2. */
3388 #define BS_AIPS_PACRD_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRD_WP2. */
3390 /*! @brief Read current value of the AIPS_PACRD_WP2 field. */
3391 #define BR_AIPS_PACRD_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP2))
3393 /*! @brief Format value for bitfield AIPS_PACRD_WP2. */
3394 #define BF_AIPS_PACRD_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_WP2) & BM_AIPS_PACRD_WP2)
3396 /*! @brief Set the WP2 field to a new value. */
3397 #define BW_AIPS_PACRD_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP2) = (v))
3401 * @name Register AIPS_PACRD, field SP2[22] (RW)
3403 * Determines whether the peripheral requires supervisor privilege level for
3404 * accesses. When this field is set, the master privilege level must indicate the
3405 * supervisor access attribute, and the MPRx[MPLn] control field for the master
3406 * must be set. If not, access terminates with an error response and no peripheral
3410 * - 0 - This peripheral does not require supervisor privilege level for
3412 * - 1 - This peripheral requires supervisor privilege level for accesses.
3415 #define BP_AIPS_PACRD_SP2 (22U) /*!< Bit position for AIPS_PACRD_SP2. */
3416 #define BM_AIPS_PACRD_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRD_SP2. */
3417 #define BS_AIPS_PACRD_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRD_SP2. */
3419 /*! @brief Read current value of the AIPS_PACRD_SP2 field. */
3420 #define BR_AIPS_PACRD_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP2))
3422 /*! @brief Format value for bitfield AIPS_PACRD_SP2. */
3423 #define BF_AIPS_PACRD_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_SP2) & BM_AIPS_PACRD_SP2)
3425 /*! @brief Set the SP2 field to a new value. */
3426 #define BW_AIPS_PACRD_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP2) = (v))
3430 * @name Register AIPS_PACRD, field TP1[24] (RW)
3432 * Determines whether the peripheral allows accesses from an untrusted master.
3433 * When this bit is set and an access is attempted by an untrusted master, the
3434 * access terminates with an error response and no peripheral access initiates.
3437 * - 0 - Accesses from an untrusted master are allowed.
3438 * - 1 - Accesses from an untrusted master are not allowed.
3441 #define BP_AIPS_PACRD_TP1 (24U) /*!< Bit position for AIPS_PACRD_TP1. */
3442 #define BM_AIPS_PACRD_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRD_TP1. */
3443 #define BS_AIPS_PACRD_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRD_TP1. */
3445 /*! @brief Read current value of the AIPS_PACRD_TP1 field. */
3446 #define BR_AIPS_PACRD_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP1))
3448 /*! @brief Format value for bitfield AIPS_PACRD_TP1. */
3449 #define BF_AIPS_PACRD_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_TP1) & BM_AIPS_PACRD_TP1)
3451 /*! @brief Set the TP1 field to a new value. */
3452 #define BW_AIPS_PACRD_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP1) = (v))
3456 * @name Register AIPS_PACRD, field WP1[25] (RW)
3458 * Determines whether the peripheral allows write accesses. When this field is
3459 * set and a write access is attempted, access terminates with an error response
3460 * and no peripheral access initiates.
3463 * - 0 - This peripheral allows write accesses.
3464 * - 1 - This peripheral is write protected.
3467 #define BP_AIPS_PACRD_WP1 (25U) /*!< Bit position for AIPS_PACRD_WP1. */
3468 #define BM_AIPS_PACRD_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRD_WP1. */
3469 #define BS_AIPS_PACRD_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRD_WP1. */
3471 /*! @brief Read current value of the AIPS_PACRD_WP1 field. */
3472 #define BR_AIPS_PACRD_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP1))
3474 /*! @brief Format value for bitfield AIPS_PACRD_WP1. */
3475 #define BF_AIPS_PACRD_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_WP1) & BM_AIPS_PACRD_WP1)
3477 /*! @brief Set the WP1 field to a new value. */
3478 #define BW_AIPS_PACRD_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP1) = (v))
3482 * @name Register AIPS_PACRD, field SP1[26] (RW)
3484 * Determines whether the peripheral requires supervisor privilege level for
3485 * accesses. When this field is set, the master privilege level must indicate the
3486 * supervisor access attribute, and the MPRx[MPLn] control field for the master
3487 * must be set. If not, access terminates with an error response and no peripheral
3491 * - 0 - This peripheral does not require supervisor privilege level for
3493 * - 1 - This peripheral requires supervisor privilege level for accesses.
3496 #define BP_AIPS_PACRD_SP1 (26U) /*!< Bit position for AIPS_PACRD_SP1. */
3497 #define BM_AIPS_PACRD_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRD_SP1. */
3498 #define BS_AIPS_PACRD_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRD_SP1. */
3500 /*! @brief Read current value of the AIPS_PACRD_SP1 field. */
3501 #define BR_AIPS_PACRD_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP1))
3503 /*! @brief Format value for bitfield AIPS_PACRD_SP1. */
3504 #define BF_AIPS_PACRD_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_SP1) & BM_AIPS_PACRD_SP1)
3506 /*! @brief Set the SP1 field to a new value. */
3507 #define BW_AIPS_PACRD_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP1) = (v))
3511 * @name Register AIPS_PACRD, field TP0[28] (RW)
3513 * Determines whether the peripheral allows accesses from an untrusted master.
3514 * When this field is set and an access is attempted by an untrusted master, the
3515 * access terminates with an error response and no peripheral access initiates.
3518 * - 0 - Accesses from an untrusted master are allowed.
3519 * - 1 - Accesses from an untrusted master are not allowed.
3522 #define BP_AIPS_PACRD_TP0 (28U) /*!< Bit position for AIPS_PACRD_TP0. */
3523 #define BM_AIPS_PACRD_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRD_TP0. */
3524 #define BS_AIPS_PACRD_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRD_TP0. */
3526 /*! @brief Read current value of the AIPS_PACRD_TP0 field. */
3527 #define BR_AIPS_PACRD_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP0))
3529 /*! @brief Format value for bitfield AIPS_PACRD_TP0. */
3530 #define BF_AIPS_PACRD_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_TP0) & BM_AIPS_PACRD_TP0)
3532 /*! @brief Set the TP0 field to a new value. */
3533 #define BW_AIPS_PACRD_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP0) = (v))
3537 * @name Register AIPS_PACRD, field WP0[29] (RW)
3539 * Determines whether the peripheral allows write accesss. When this bit is set
3540 * and a write access is attempted, access terminates with an error response and
3541 * no peripheral access initiates.
3544 * - 0 - This peripheral allows write accesses.
3545 * - 1 - This peripheral is write protected.
3548 #define BP_AIPS_PACRD_WP0 (29U) /*!< Bit position for AIPS_PACRD_WP0. */
3549 #define BM_AIPS_PACRD_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRD_WP0. */
3550 #define BS_AIPS_PACRD_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRD_WP0. */
3552 /*! @brief Read current value of the AIPS_PACRD_WP0 field. */
3553 #define BR_AIPS_PACRD_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP0))
3555 /*! @brief Format value for bitfield AIPS_PACRD_WP0. */
3556 #define BF_AIPS_PACRD_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_WP0) & BM_AIPS_PACRD_WP0)
3558 /*! @brief Set the WP0 field to a new value. */
3559 #define BW_AIPS_PACRD_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP0) = (v))
3563 * @name Register AIPS_PACRD, field SP0[30] (RW)
3565 * Determines whether the peripheral requires supervisor privilege level for
3566 * accesses. When this field is set, the master privilege level must indicate the
3567 * supervisor access attribute, and the MPRx[MPLn] control field for the master
3568 * must be set. If not, access terminates with an error response and no peripheral
3572 * - 0 - This peripheral does not require supervisor privilege level for
3574 * - 1 - This peripheral requires supervisor privilege level for accesses.
3577 #define BP_AIPS_PACRD_SP0 (30U) /*!< Bit position for AIPS_PACRD_SP0. */
3578 #define BM_AIPS_PACRD_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRD_SP0. */
3579 #define BS_AIPS_PACRD_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRD_SP0. */
3581 /*! @brief Read current value of the AIPS_PACRD_SP0 field. */
3582 #define BR_AIPS_PACRD_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP0))
3584 /*! @brief Format value for bitfield AIPS_PACRD_SP0. */
3585 #define BF_AIPS_PACRD_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_SP0) & BM_AIPS_PACRD_SP0)
3587 /*! @brief Set the SP0 field to a new value. */
3588 #define BW_AIPS_PACRD_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP0) = (v))
3591 /*******************************************************************************
3592 * HW_AIPS_PACRE - Peripheral Access Control Register
3593 ******************************************************************************/
3596 * @brief HW_AIPS_PACRE - Peripheral Access Control Register (RW)
3598 * Reset value: 0x44444444U
3600 * This section describes PACR registers E-P, which control peripheral slots
3601 * 32-127. See PACRPeripheral Access Control Register for the description of these
3604 typedef union _hw_aips_pacre
3607 struct _hw_aips_pacre_bitfields
3609 uint32_t TP7
: 1; /*!< [0] Trusted Protect */
3610 uint32_t WP7
: 1; /*!< [1] Write Protect */
3611 uint32_t SP7
: 1; /*!< [2] Supervisor Protect */
3612 uint32_t RESERVED0
: 1; /*!< [3] */
3613 uint32_t TP6
: 1; /*!< [4] Trusted Protect */
3614 uint32_t WP6
: 1; /*!< [5] Write Protect */
3615 uint32_t SP6
: 1; /*!< [6] Supervisor Protect */
3616 uint32_t RESERVED1
: 1; /*!< [7] */
3617 uint32_t TP5
: 1; /*!< [8] Trusted Protect */
3618 uint32_t WP5
: 1; /*!< [9] Write Protect */
3619 uint32_t SP5
: 1; /*!< [10] Supervisor Protect */
3620 uint32_t RESERVED2
: 1; /*!< [11] */
3621 uint32_t TP4
: 1; /*!< [12] Trusted Protect */
3622 uint32_t WP4
: 1; /*!< [13] Write Protect */
3623 uint32_t SP4
: 1; /*!< [14] Supervisor Protect */
3624 uint32_t RESERVED3
: 1; /*!< [15] */
3625 uint32_t TP3
: 1; /*!< [16] Trusted Protect */
3626 uint32_t WP3
: 1; /*!< [17] Write Protect */
3627 uint32_t SP3
: 1; /*!< [18] Supervisor Protect */
3628 uint32_t RESERVED4
: 1; /*!< [19] */
3629 uint32_t TP2
: 1; /*!< [20] Trusted Protect */
3630 uint32_t WP2
: 1; /*!< [21] Write Protect */
3631 uint32_t SP2
: 1; /*!< [22] Supervisor Protect */
3632 uint32_t RESERVED5
: 1; /*!< [23] */
3633 uint32_t TP1
: 1; /*!< [24] Trusted Protect */
3634 uint32_t WP1
: 1; /*!< [25] Write Protect */
3635 uint32_t SP1
: 1; /*!< [26] Supervisor Protect */
3636 uint32_t RESERVED6
: 1; /*!< [27] */
3637 uint32_t TP0
: 1; /*!< [28] Trusted Protect */
3638 uint32_t WP0
: 1; /*!< [29] Write Protect */
3639 uint32_t SP0
: 1; /*!< [30] Supervisor Protect */
3640 uint32_t RESERVED7
: 1; /*!< [31] */
3645 * @name Constants and macros for entire AIPS_PACRE register
3648 #define HW_AIPS_PACRE_ADDR(x) ((x) + 0x40U)
3650 #define HW_AIPS_PACRE(x) (*(__IO hw_aips_pacre_t *) HW_AIPS_PACRE_ADDR(x))
3651 #define HW_AIPS_PACRE_RD(x) (HW_AIPS_PACRE(x).U)
3652 #define HW_AIPS_PACRE_WR(x, v) (HW_AIPS_PACRE(x).U = (v))
3653 #define HW_AIPS_PACRE_SET(x, v) (HW_AIPS_PACRE_WR(x, HW_AIPS_PACRE_RD(x) | (v)))
3654 #define HW_AIPS_PACRE_CLR(x, v) (HW_AIPS_PACRE_WR(x, HW_AIPS_PACRE_RD(x) & ~(v)))
3655 #define HW_AIPS_PACRE_TOG(x, v) (HW_AIPS_PACRE_WR(x, HW_AIPS_PACRE_RD(x) ^ (v)))
3659 * Constants & macros for individual AIPS_PACRE bitfields
3663 * @name Register AIPS_PACRE, field TP7[0] (RW)
3665 * Determines whether the peripheral allows accesses from an untrusted master.
3666 * When this field is set and an access is attempted by an untrusted master, the
3667 * access terminates with an error response and no peripheral access initiates.
3670 * - 0 - Accesses from an untrusted master are allowed.
3671 * - 1 - Accesses from an untrusted master are not allowed.
3674 #define BP_AIPS_PACRE_TP7 (0U) /*!< Bit position for AIPS_PACRE_TP7. */
3675 #define BM_AIPS_PACRE_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRE_TP7. */
3676 #define BS_AIPS_PACRE_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRE_TP7. */
3678 /*! @brief Read current value of the AIPS_PACRE_TP7 field. */
3679 #define BR_AIPS_PACRE_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP7))
3681 /*! @brief Format value for bitfield AIPS_PACRE_TP7. */
3682 #define BF_AIPS_PACRE_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_TP7) & BM_AIPS_PACRE_TP7)
3684 /*! @brief Set the TP7 field to a new value. */
3685 #define BW_AIPS_PACRE_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP7) = (v))
3689 * @name Register AIPS_PACRE, field WP7[1] (RW)
3691 * Determines whether the peripheral allows write accesses. When this field is
3692 * set and a write access is attempted, access terminates with an error response
3693 * and no peripheral access initiates.
3696 * - 0 - This peripheral allows write accesses.
3697 * - 1 - This peripheral is write protected.
3700 #define BP_AIPS_PACRE_WP7 (1U) /*!< Bit position for AIPS_PACRE_WP7. */
3701 #define BM_AIPS_PACRE_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRE_WP7. */
3702 #define BS_AIPS_PACRE_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRE_WP7. */
3704 /*! @brief Read current value of the AIPS_PACRE_WP7 field. */
3705 #define BR_AIPS_PACRE_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP7))
3707 /*! @brief Format value for bitfield AIPS_PACRE_WP7. */
3708 #define BF_AIPS_PACRE_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_WP7) & BM_AIPS_PACRE_WP7)
3710 /*! @brief Set the WP7 field to a new value. */
3711 #define BW_AIPS_PACRE_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP7) = (v))
3715 * @name Register AIPS_PACRE, field SP7[2] (RW)
3717 * Determines whether the peripheral requires supervisor privilege level for
3718 * accesses. When this field is set, the master privilege level must indicate the
3719 * supervisor access attribute, and the MPRx[MPLn] control field for the master
3720 * must be set. If not, access terminates with an error response and no peripheral
3724 * - 0 - This peripheral does not require supervisor privilege level for
3726 * - 1 - This peripheral requires supervisor privilege level for accesses.
3729 #define BP_AIPS_PACRE_SP7 (2U) /*!< Bit position for AIPS_PACRE_SP7. */
3730 #define BM_AIPS_PACRE_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRE_SP7. */
3731 #define BS_AIPS_PACRE_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRE_SP7. */
3733 /*! @brief Read current value of the AIPS_PACRE_SP7 field. */
3734 #define BR_AIPS_PACRE_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP7))
3736 /*! @brief Format value for bitfield AIPS_PACRE_SP7. */
3737 #define BF_AIPS_PACRE_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_SP7) & BM_AIPS_PACRE_SP7)
3739 /*! @brief Set the SP7 field to a new value. */
3740 #define BW_AIPS_PACRE_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP7) = (v))
3744 * @name Register AIPS_PACRE, field TP6[4] (RW)
3746 * Determines whether the peripheral allows accesses from an untrusted master.
3747 * When this field is set and an access is attempted by an untrusted master, the
3748 * access terminates with an error response and no peripheral access initiates.
3751 * - 0 - Accesses from an untrusted master are allowed.
3752 * - 1 - Accesses from an untrusted master are not allowed.
3755 #define BP_AIPS_PACRE_TP6 (4U) /*!< Bit position for AIPS_PACRE_TP6. */
3756 #define BM_AIPS_PACRE_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRE_TP6. */
3757 #define BS_AIPS_PACRE_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRE_TP6. */
3759 /*! @brief Read current value of the AIPS_PACRE_TP6 field. */
3760 #define BR_AIPS_PACRE_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP6))
3762 /*! @brief Format value for bitfield AIPS_PACRE_TP6. */
3763 #define BF_AIPS_PACRE_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_TP6) & BM_AIPS_PACRE_TP6)
3765 /*! @brief Set the TP6 field to a new value. */
3766 #define BW_AIPS_PACRE_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP6) = (v))
3770 * @name Register AIPS_PACRE, field WP6[5] (RW)
3772 * Determines whether the peripheral allows write accesses. When this field is
3773 * set and a write access is attempted, access terminates with an error response
3774 * and no peripheral access initiates.
3777 * - 0 - This peripheral allows write accesses.
3778 * - 1 - This peripheral is write protected.
3781 #define BP_AIPS_PACRE_WP6 (5U) /*!< Bit position for AIPS_PACRE_WP6. */
3782 #define BM_AIPS_PACRE_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRE_WP6. */
3783 #define BS_AIPS_PACRE_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRE_WP6. */
3785 /*! @brief Read current value of the AIPS_PACRE_WP6 field. */
3786 #define BR_AIPS_PACRE_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP6))
3788 /*! @brief Format value for bitfield AIPS_PACRE_WP6. */
3789 #define BF_AIPS_PACRE_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_WP6) & BM_AIPS_PACRE_WP6)
3791 /*! @brief Set the WP6 field to a new value. */
3792 #define BW_AIPS_PACRE_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP6) = (v))
3796 * @name Register AIPS_PACRE, field SP6[6] (RW)
3798 * Determines whether the peripheral requires supervisor privilege level for
3799 * accesses. When this field is set, the master privilege level must indicate the
3800 * supervisor access attribute, and the MPRx[MPLn] control field for the master
3801 * must be set. If not, access terminates with an error response and no peripheral
3805 * - 0 - This peripheral does not require supervisor privilege level for
3807 * - 1 - This peripheral requires supervisor privilege level for accesses.
3810 #define BP_AIPS_PACRE_SP6 (6U) /*!< Bit position for AIPS_PACRE_SP6. */
3811 #define BM_AIPS_PACRE_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRE_SP6. */
3812 #define BS_AIPS_PACRE_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRE_SP6. */
3814 /*! @brief Read current value of the AIPS_PACRE_SP6 field. */
3815 #define BR_AIPS_PACRE_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP6))
3817 /*! @brief Format value for bitfield AIPS_PACRE_SP6. */
3818 #define BF_AIPS_PACRE_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_SP6) & BM_AIPS_PACRE_SP6)
3820 /*! @brief Set the SP6 field to a new value. */
3821 #define BW_AIPS_PACRE_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP6) = (v))
3825 * @name Register AIPS_PACRE, field TP5[8] (RW)
3827 * Determines whether the peripheral allows accesses from an untrusted master.
3828 * When this field is set and an access is attempted by an untrusted master, the
3829 * access terminates with an error response and no peripheral access initiates.
3832 * - 0 - Accesses from an untrusted master are allowed.
3833 * - 1 - Accesses from an untrusted master are not allowed.
3836 #define BP_AIPS_PACRE_TP5 (8U) /*!< Bit position for AIPS_PACRE_TP5. */
3837 #define BM_AIPS_PACRE_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRE_TP5. */
3838 #define BS_AIPS_PACRE_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRE_TP5. */
3840 /*! @brief Read current value of the AIPS_PACRE_TP5 field. */
3841 #define BR_AIPS_PACRE_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP5))
3843 /*! @brief Format value for bitfield AIPS_PACRE_TP5. */
3844 #define BF_AIPS_PACRE_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_TP5) & BM_AIPS_PACRE_TP5)
3846 /*! @brief Set the TP5 field to a new value. */
3847 #define BW_AIPS_PACRE_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP5) = (v))
3851 * @name Register AIPS_PACRE, field WP5[9] (RW)
3853 * Determines whether the peripheral allows write accesses. When this field is
3854 * set and a write access is attempted, access terminates with an error response
3855 * and no peripheral access initiates.
3858 * - 0 - This peripheral allows write accesses.
3859 * - 1 - This peripheral is write protected.
3862 #define BP_AIPS_PACRE_WP5 (9U) /*!< Bit position for AIPS_PACRE_WP5. */
3863 #define BM_AIPS_PACRE_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRE_WP5. */
3864 #define BS_AIPS_PACRE_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRE_WP5. */
3866 /*! @brief Read current value of the AIPS_PACRE_WP5 field. */
3867 #define BR_AIPS_PACRE_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP5))
3869 /*! @brief Format value for bitfield AIPS_PACRE_WP5. */
3870 #define BF_AIPS_PACRE_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_WP5) & BM_AIPS_PACRE_WP5)
3872 /*! @brief Set the WP5 field to a new value. */
3873 #define BW_AIPS_PACRE_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP5) = (v))
3877 * @name Register AIPS_PACRE, field SP5[10] (RW)
3879 * Determines whether the peripheral requires supervisor privilege level for
3880 * accesses. When this field is set, the master privilege level must indicate the
3881 * supervisor access attribute, and the MPRx[MPLn] control field for the master
3882 * must be set. If not, access terminates with an error response and no peripheral
3886 * - 0 - This peripheral does not require supervisor privilege level for
3888 * - 1 - This peripheral requires supervisor privilege level for accesses.
3891 #define BP_AIPS_PACRE_SP5 (10U) /*!< Bit position for AIPS_PACRE_SP5. */
3892 #define BM_AIPS_PACRE_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRE_SP5. */
3893 #define BS_AIPS_PACRE_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRE_SP5. */
3895 /*! @brief Read current value of the AIPS_PACRE_SP5 field. */
3896 #define BR_AIPS_PACRE_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP5))
3898 /*! @brief Format value for bitfield AIPS_PACRE_SP5. */
3899 #define BF_AIPS_PACRE_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_SP5) & BM_AIPS_PACRE_SP5)
3901 /*! @brief Set the SP5 field to a new value. */
3902 #define BW_AIPS_PACRE_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP5) = (v))
3906 * @name Register AIPS_PACRE, field TP4[12] (RW)
3908 * Determines whether the peripheral allows accesses from an untrusted master.
3909 * When this bit is set and an access is attempted by an untrusted master, the
3910 * access terminates with an error response and no peripheral access initiates.
3913 * - 0 - Accesses from an untrusted master are allowed.
3914 * - 1 - Accesses from an untrusted master are not allowed.
3917 #define BP_AIPS_PACRE_TP4 (12U) /*!< Bit position for AIPS_PACRE_TP4. */
3918 #define BM_AIPS_PACRE_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRE_TP4. */
3919 #define BS_AIPS_PACRE_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRE_TP4. */
3921 /*! @brief Read current value of the AIPS_PACRE_TP4 field. */
3922 #define BR_AIPS_PACRE_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP4))
3924 /*! @brief Format value for bitfield AIPS_PACRE_TP4. */
3925 #define BF_AIPS_PACRE_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_TP4) & BM_AIPS_PACRE_TP4)
3927 /*! @brief Set the TP4 field to a new value. */
3928 #define BW_AIPS_PACRE_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP4) = (v))
3932 * @name Register AIPS_PACRE, field WP4[13] (RW)
3934 * Determines whether the peripheral allows write accesses. When this field is
3935 * set and a write access is attempted, access terminates with an error response
3936 * and no peripheral access initiates.
3939 * - 0 - This peripheral allows write accesses.
3940 * - 1 - This peripheral is write protected.
3943 #define BP_AIPS_PACRE_WP4 (13U) /*!< Bit position for AIPS_PACRE_WP4. */
3944 #define BM_AIPS_PACRE_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRE_WP4. */
3945 #define BS_AIPS_PACRE_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRE_WP4. */
3947 /*! @brief Read current value of the AIPS_PACRE_WP4 field. */
3948 #define BR_AIPS_PACRE_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP4))
3950 /*! @brief Format value for bitfield AIPS_PACRE_WP4. */
3951 #define BF_AIPS_PACRE_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_WP4) & BM_AIPS_PACRE_WP4)
3953 /*! @brief Set the WP4 field to a new value. */
3954 #define BW_AIPS_PACRE_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP4) = (v))
3958 * @name Register AIPS_PACRE, field SP4[14] (RW)
3960 * Determines whether the peripheral requires supervisor privilege level for
3961 * access. When this bit is set, the master privilege level must indicate the
3962 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
3963 * set. If not, access terminates with an error response and no peripheral access
3967 * - 0 - This peripheral does not require supervisor privilege level for
3969 * - 1 - This peripheral requires supervisor privilege level for accesses.
3972 #define BP_AIPS_PACRE_SP4 (14U) /*!< Bit position for AIPS_PACRE_SP4. */
3973 #define BM_AIPS_PACRE_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRE_SP4. */
3974 #define BS_AIPS_PACRE_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRE_SP4. */
3976 /*! @brief Read current value of the AIPS_PACRE_SP4 field. */
3977 #define BR_AIPS_PACRE_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP4))
3979 /*! @brief Format value for bitfield AIPS_PACRE_SP4. */
3980 #define BF_AIPS_PACRE_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_SP4) & BM_AIPS_PACRE_SP4)
3982 /*! @brief Set the SP4 field to a new value. */
3983 #define BW_AIPS_PACRE_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP4) = (v))
3987 * @name Register AIPS_PACRE, field TP3[16] (RW)
3989 * Determines whether the peripheral allows accesses from an untrusted master.
3990 * When this field is set and an access is attempted by an untrusted master, the
3991 * access terminates with an error response and no peripheral access initiates.
3994 * - 0 - Accesses from an untrusted master are allowed.
3995 * - 1 - Accesses from an untrusted master are not allowed.
3998 #define BP_AIPS_PACRE_TP3 (16U) /*!< Bit position for AIPS_PACRE_TP3. */
3999 #define BM_AIPS_PACRE_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRE_TP3. */
4000 #define BS_AIPS_PACRE_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRE_TP3. */
4002 /*! @brief Read current value of the AIPS_PACRE_TP3 field. */
4003 #define BR_AIPS_PACRE_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP3))
4005 /*! @brief Format value for bitfield AIPS_PACRE_TP3. */
4006 #define BF_AIPS_PACRE_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_TP3) & BM_AIPS_PACRE_TP3)
4008 /*! @brief Set the TP3 field to a new value. */
4009 #define BW_AIPS_PACRE_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP3) = (v))
4013 * @name Register AIPS_PACRE, field WP3[17] (RW)
4015 * Determines whether the peripheral allows write accesss. When this bit is set
4016 * and a write access is attempted, access terminates with an error response and
4017 * no peripheral access initiates.
4020 * - 0 - This peripheral allows write accesses.
4021 * - 1 - This peripheral is write protected.
4024 #define BP_AIPS_PACRE_WP3 (17U) /*!< Bit position for AIPS_PACRE_WP3. */
4025 #define BM_AIPS_PACRE_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRE_WP3. */
4026 #define BS_AIPS_PACRE_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRE_WP3. */
4028 /*! @brief Read current value of the AIPS_PACRE_WP3 field. */
4029 #define BR_AIPS_PACRE_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP3))
4031 /*! @brief Format value for bitfield AIPS_PACRE_WP3. */
4032 #define BF_AIPS_PACRE_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_WP3) & BM_AIPS_PACRE_WP3)
4034 /*! @brief Set the WP3 field to a new value. */
4035 #define BW_AIPS_PACRE_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP3) = (v))
4039 * @name Register AIPS_PACRE, field SP3[18] (RW)
4041 * Determines whether the peripheral requires supervisor privilege level for
4042 * accesses. When this field is set, the master privilege level must indicate the
4043 * supervisor access attribute, and the MPRx[MPLn] control field for the master
4044 * must be set. If not, access terminates with an error response and no peripheral
4048 * - 0 - This peripheral does not require supervisor privilege level for
4050 * - 1 - This peripheral requires supervisor privilege level for accesses.
4053 #define BP_AIPS_PACRE_SP3 (18U) /*!< Bit position for AIPS_PACRE_SP3. */
4054 #define BM_AIPS_PACRE_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRE_SP3. */
4055 #define BS_AIPS_PACRE_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRE_SP3. */
4057 /*! @brief Read current value of the AIPS_PACRE_SP3 field. */
4058 #define BR_AIPS_PACRE_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP3))
4060 /*! @brief Format value for bitfield AIPS_PACRE_SP3. */
4061 #define BF_AIPS_PACRE_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_SP3) & BM_AIPS_PACRE_SP3)
4063 /*! @brief Set the SP3 field to a new value. */
4064 #define BW_AIPS_PACRE_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP3) = (v))
4068 * @name Register AIPS_PACRE, field TP2[20] (RW)
4070 * Determines whether the peripheral allows accesses from an untrusted master.
4071 * When this bit is set and an access is attempted by an untrusted master, the
4072 * access terminates with an error response and no peripheral access initiates.
4075 * - 0 - Accesses from an untrusted master are allowed.
4076 * - 1 - Accesses from an untrusted master are not allowed.
4079 #define BP_AIPS_PACRE_TP2 (20U) /*!< Bit position for AIPS_PACRE_TP2. */
4080 #define BM_AIPS_PACRE_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRE_TP2. */
4081 #define BS_AIPS_PACRE_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRE_TP2. */
4083 /*! @brief Read current value of the AIPS_PACRE_TP2 field. */
4084 #define BR_AIPS_PACRE_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP2))
4086 /*! @brief Format value for bitfield AIPS_PACRE_TP2. */
4087 #define BF_AIPS_PACRE_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_TP2) & BM_AIPS_PACRE_TP2)
4089 /*! @brief Set the TP2 field to a new value. */
4090 #define BW_AIPS_PACRE_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP2) = (v))
4094 * @name Register AIPS_PACRE, field WP2[21] (RW)
4096 * Determines whether the peripheral allows write accesses. When this field is
4097 * set and a write access is attempted, access terminates with an error response
4098 * and no peripheral access initiates.
4101 * - 0 - This peripheral allows write accesses.
4102 * - 1 - This peripheral is write protected.
4105 #define BP_AIPS_PACRE_WP2 (21U) /*!< Bit position for AIPS_PACRE_WP2. */
4106 #define BM_AIPS_PACRE_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRE_WP2. */
4107 #define BS_AIPS_PACRE_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRE_WP2. */
4109 /*! @brief Read current value of the AIPS_PACRE_WP2 field. */
4110 #define BR_AIPS_PACRE_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP2))
4112 /*! @brief Format value for bitfield AIPS_PACRE_WP2. */
4113 #define BF_AIPS_PACRE_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_WP2) & BM_AIPS_PACRE_WP2)
4115 /*! @brief Set the WP2 field to a new value. */
4116 #define BW_AIPS_PACRE_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP2) = (v))
4120 * @name Register AIPS_PACRE, field SP2[22] (RW)
4122 * Determines whether the peripheral requires supervisor privilege level for
4123 * access. When this bit is set, the master privilege level must indicate the
4124 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
4125 * set. If not, access terminates with an error response and no peripheral access
4129 * - 0 - This peripheral does not require supervisor privilege level for
4131 * - 1 - This peripheral requires supervisor privilege level for accesses.
4134 #define BP_AIPS_PACRE_SP2 (22U) /*!< Bit position for AIPS_PACRE_SP2. */
4135 #define BM_AIPS_PACRE_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRE_SP2. */
4136 #define BS_AIPS_PACRE_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRE_SP2. */
4138 /*! @brief Read current value of the AIPS_PACRE_SP2 field. */
4139 #define BR_AIPS_PACRE_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP2))
4141 /*! @brief Format value for bitfield AIPS_PACRE_SP2. */
4142 #define BF_AIPS_PACRE_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_SP2) & BM_AIPS_PACRE_SP2)
4144 /*! @brief Set the SP2 field to a new value. */
4145 #define BW_AIPS_PACRE_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP2) = (v))
4149 * @name Register AIPS_PACRE, field TP1[24] (RW)
4151 * Determines whether the peripheral allows accesses from an untrusted master.
4152 * When this field is set and an access is attempted by an untrusted master, the
4153 * access terminates with an error response and no peripheral access initiates.
4156 * - 0 - Accesses from an untrusted master are allowed.
4157 * - 1 - Accesses from an untrusted master are not allowed.
4160 #define BP_AIPS_PACRE_TP1 (24U) /*!< Bit position for AIPS_PACRE_TP1. */
4161 #define BM_AIPS_PACRE_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRE_TP1. */
4162 #define BS_AIPS_PACRE_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRE_TP1. */
4164 /*! @brief Read current value of the AIPS_PACRE_TP1 field. */
4165 #define BR_AIPS_PACRE_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP1))
4167 /*! @brief Format value for bitfield AIPS_PACRE_TP1. */
4168 #define BF_AIPS_PACRE_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_TP1) & BM_AIPS_PACRE_TP1)
4170 /*! @brief Set the TP1 field to a new value. */
4171 #define BW_AIPS_PACRE_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP1) = (v))
4175 * @name Register AIPS_PACRE, field WP1[25] (RW)
4177 * Determines whether the peripheral allows write accesses. When this field is
4178 * set and a write access is attempted, access terminates with an error response
4179 * and no peripheral access initiates.
4182 * - 0 - This peripheral allows write accesses.
4183 * - 1 - This peripheral is write protected.
4186 #define BP_AIPS_PACRE_WP1 (25U) /*!< Bit position for AIPS_PACRE_WP1. */
4187 #define BM_AIPS_PACRE_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRE_WP1. */
4188 #define BS_AIPS_PACRE_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRE_WP1. */
4190 /*! @brief Read current value of the AIPS_PACRE_WP1 field. */
4191 #define BR_AIPS_PACRE_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP1))
4193 /*! @brief Format value for bitfield AIPS_PACRE_WP1. */
4194 #define BF_AIPS_PACRE_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_WP1) & BM_AIPS_PACRE_WP1)
4196 /*! @brief Set the WP1 field to a new value. */
4197 #define BW_AIPS_PACRE_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP1) = (v))
4201 * @name Register AIPS_PACRE, field SP1[26] (RW)
4203 * Determines whether the peripheral requires supervisor privilege level for
4204 * access. When this field is set, the master privilege level must indicate the
4205 * supervisor access attribute, and the MPRx[MPLn] control field for the master must
4206 * be set. If not, access terminates with an error response and no peripheral
4210 * - 0 - This peripheral does not require supervisor privilege level for
4212 * - 1 - This peripheral requires supervisor privilege level for accesses.
4215 #define BP_AIPS_PACRE_SP1 (26U) /*!< Bit position for AIPS_PACRE_SP1. */
4216 #define BM_AIPS_PACRE_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRE_SP1. */
4217 #define BS_AIPS_PACRE_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRE_SP1. */
4219 /*! @brief Read current value of the AIPS_PACRE_SP1 field. */
4220 #define BR_AIPS_PACRE_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP1))
4222 /*! @brief Format value for bitfield AIPS_PACRE_SP1. */
4223 #define BF_AIPS_PACRE_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_SP1) & BM_AIPS_PACRE_SP1)
4225 /*! @brief Set the SP1 field to a new value. */
4226 #define BW_AIPS_PACRE_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP1) = (v))
4230 * @name Register AIPS_PACRE, field TP0[28] (RW)
4232 * Determines whether the peripheral allows accesses from an untrusted master.
4233 * When this bit is set and an access is attempted by an untrusted master, the
4234 * access terminates with an error response and no peripheral access initiates.
4237 * - 0 - Accesses from an untrusted master are allowed.
4238 * - 1 - Accesses from an untrusted master are not allowed.
4241 #define BP_AIPS_PACRE_TP0 (28U) /*!< Bit position for AIPS_PACRE_TP0. */
4242 #define BM_AIPS_PACRE_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRE_TP0. */
4243 #define BS_AIPS_PACRE_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRE_TP0. */
4245 /*! @brief Read current value of the AIPS_PACRE_TP0 field. */
4246 #define BR_AIPS_PACRE_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP0))
4248 /*! @brief Format value for bitfield AIPS_PACRE_TP0. */
4249 #define BF_AIPS_PACRE_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_TP0) & BM_AIPS_PACRE_TP0)
4251 /*! @brief Set the TP0 field to a new value. */
4252 #define BW_AIPS_PACRE_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP0) = (v))
4256 * @name Register AIPS_PACRE, field WP0[29] (RW)
4258 * Determines whether the peripheral allows write accesses. When this field is
4259 * set and a write access is attempted, access terminates with an error response
4260 * and no peripheral access initiates.
4263 * - 0 - This peripheral allows write accesses.
4264 * - 1 - This peripheral is write protected.
4267 #define BP_AIPS_PACRE_WP0 (29U) /*!< Bit position for AIPS_PACRE_WP0. */
4268 #define BM_AIPS_PACRE_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRE_WP0. */
4269 #define BS_AIPS_PACRE_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRE_WP0. */
4271 /*! @brief Read current value of the AIPS_PACRE_WP0 field. */
4272 #define BR_AIPS_PACRE_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP0))
4274 /*! @brief Format value for bitfield AIPS_PACRE_WP0. */
4275 #define BF_AIPS_PACRE_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_WP0) & BM_AIPS_PACRE_WP0)
4277 /*! @brief Set the WP0 field to a new value. */
4278 #define BW_AIPS_PACRE_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP0) = (v))
4282 * @name Register AIPS_PACRE, field SP0[30] (RW)
4284 * Determines whether the peripheral requires supervisor privilege level for
4285 * accesses. When this field is set, the master privilege level must indicate the
4286 * supervisor access attribute, and the MPRx[MPLn] control field for the master
4287 * must be set. If not, access terminates with an error response and no peripheral
4291 * - 0 - This peripheral does not require supervisor privilege level for
4293 * - 1 - This peripheral requires supervisor privilege level for accesses.
4296 #define BP_AIPS_PACRE_SP0 (30U) /*!< Bit position for AIPS_PACRE_SP0. */
4297 #define BM_AIPS_PACRE_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRE_SP0. */
4298 #define BS_AIPS_PACRE_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRE_SP0. */
4300 /*! @brief Read current value of the AIPS_PACRE_SP0 field. */
4301 #define BR_AIPS_PACRE_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP0))
4303 /*! @brief Format value for bitfield AIPS_PACRE_SP0. */
4304 #define BF_AIPS_PACRE_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_SP0) & BM_AIPS_PACRE_SP0)
4306 /*! @brief Set the SP0 field to a new value. */
4307 #define BW_AIPS_PACRE_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP0) = (v))
4310 /*******************************************************************************
4311 * HW_AIPS_PACRF - Peripheral Access Control Register
4312 ******************************************************************************/
4315 * @brief HW_AIPS_PACRF - Peripheral Access Control Register (RW)
4317 * Reset value: 0x44444444U
4319 * This section describes PACR registers E-P, which control peripheral slots
4320 * 32-127. See PACRPeripheral Access Control Register for the description of these
4323 typedef union _hw_aips_pacrf
4326 struct _hw_aips_pacrf_bitfields
4328 uint32_t TP7
: 1; /*!< [0] Trusted Protect */
4329 uint32_t WP7
: 1; /*!< [1] Write Protect */
4330 uint32_t SP7
: 1; /*!< [2] Supervisor Protect */
4331 uint32_t RESERVED0
: 1; /*!< [3] */
4332 uint32_t TP6
: 1; /*!< [4] Trusted Protect */
4333 uint32_t WP6
: 1; /*!< [5] Write Protect */
4334 uint32_t SP6
: 1; /*!< [6] Supervisor Protect */
4335 uint32_t RESERVED1
: 1; /*!< [7] */
4336 uint32_t TP5
: 1; /*!< [8] Trusted Protect */
4337 uint32_t WP5
: 1; /*!< [9] Write Protect */
4338 uint32_t SP5
: 1; /*!< [10] Supervisor Protect */
4339 uint32_t RESERVED2
: 1; /*!< [11] */
4340 uint32_t TP4
: 1; /*!< [12] Trusted Protect */
4341 uint32_t WP4
: 1; /*!< [13] Write Protect */
4342 uint32_t SP4
: 1; /*!< [14] Supervisor Protect */
4343 uint32_t RESERVED3
: 1; /*!< [15] */
4344 uint32_t TP3
: 1; /*!< [16] Trusted Protect */
4345 uint32_t WP3
: 1; /*!< [17] Write Protect */
4346 uint32_t SP3
: 1; /*!< [18] Supervisor Protect */
4347 uint32_t RESERVED4
: 1; /*!< [19] */
4348 uint32_t TP2
: 1; /*!< [20] Trusted Protect */
4349 uint32_t WP2
: 1; /*!< [21] Write Protect */
4350 uint32_t SP2
: 1; /*!< [22] Supervisor Protect */
4351 uint32_t RESERVED5
: 1; /*!< [23] */
4352 uint32_t TP1
: 1; /*!< [24] Trusted Protect */
4353 uint32_t WP1
: 1; /*!< [25] Write Protect */
4354 uint32_t SP1
: 1; /*!< [26] Supervisor Protect */
4355 uint32_t RESERVED6
: 1; /*!< [27] */
4356 uint32_t TP0
: 1; /*!< [28] Trusted Protect */
4357 uint32_t WP0
: 1; /*!< [29] Write Protect */
4358 uint32_t SP0
: 1; /*!< [30] Supervisor Protect */
4359 uint32_t RESERVED7
: 1; /*!< [31] */
4364 * @name Constants and macros for entire AIPS_PACRF register
4367 #define HW_AIPS_PACRF_ADDR(x) ((x) + 0x44U)
4369 #define HW_AIPS_PACRF(x) (*(__IO hw_aips_pacrf_t *) HW_AIPS_PACRF_ADDR(x))
4370 #define HW_AIPS_PACRF_RD(x) (HW_AIPS_PACRF(x).U)
4371 #define HW_AIPS_PACRF_WR(x, v) (HW_AIPS_PACRF(x).U = (v))
4372 #define HW_AIPS_PACRF_SET(x, v) (HW_AIPS_PACRF_WR(x, HW_AIPS_PACRF_RD(x) | (v)))
4373 #define HW_AIPS_PACRF_CLR(x, v) (HW_AIPS_PACRF_WR(x, HW_AIPS_PACRF_RD(x) & ~(v)))
4374 #define HW_AIPS_PACRF_TOG(x, v) (HW_AIPS_PACRF_WR(x, HW_AIPS_PACRF_RD(x) ^ (v)))
4378 * Constants & macros for individual AIPS_PACRF bitfields
4382 * @name Register AIPS_PACRF, field TP7[0] (RW)
4384 * Determines whether the peripheral allows accesses from an untrusted master.
4385 * When this field is set and an access is attempted by an untrusted master, the
4386 * access terminates with an error response and no peripheral access initiates.
4389 * - 0 - Accesses from an untrusted master are allowed.
4390 * - 1 - Accesses from an untrusted master are not allowed.
4393 #define BP_AIPS_PACRF_TP7 (0U) /*!< Bit position for AIPS_PACRF_TP7. */
4394 #define BM_AIPS_PACRF_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRF_TP7. */
4395 #define BS_AIPS_PACRF_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRF_TP7. */
4397 /*! @brief Read current value of the AIPS_PACRF_TP7 field. */
4398 #define BR_AIPS_PACRF_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP7))
4400 /*! @brief Format value for bitfield AIPS_PACRF_TP7. */
4401 #define BF_AIPS_PACRF_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_TP7) & BM_AIPS_PACRF_TP7)
4403 /*! @brief Set the TP7 field to a new value. */
4404 #define BW_AIPS_PACRF_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP7) = (v))
4408 * @name Register AIPS_PACRF, field WP7[1] (RW)
4410 * Determines whether the peripheral allows write accesses. When this field is
4411 * set and a write access is attempted, access terminates with an error response
4412 * and no peripheral access initiates.
4415 * - 0 - This peripheral allows write accesses.
4416 * - 1 - This peripheral is write protected.
4419 #define BP_AIPS_PACRF_WP7 (1U) /*!< Bit position for AIPS_PACRF_WP7. */
4420 #define BM_AIPS_PACRF_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRF_WP7. */
4421 #define BS_AIPS_PACRF_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRF_WP7. */
4423 /*! @brief Read current value of the AIPS_PACRF_WP7 field. */
4424 #define BR_AIPS_PACRF_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP7))
4426 /*! @brief Format value for bitfield AIPS_PACRF_WP7. */
4427 #define BF_AIPS_PACRF_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_WP7) & BM_AIPS_PACRF_WP7)
4429 /*! @brief Set the WP7 field to a new value. */
4430 #define BW_AIPS_PACRF_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP7) = (v))
4434 * @name Register AIPS_PACRF, field SP7[2] (RW)
4436 * Determines whether the peripheral requires supervisor privilege level for
4437 * accesses. When this field is set, the master privilege level must indicate the
4438 * supervisor access attribute, and the MPRx[MPLn] control field for the master
4439 * must be set. If not, access terminates with an error response and no peripheral
4443 * - 0 - This peripheral does not require supervisor privilege level for
4445 * - 1 - This peripheral requires supervisor privilege level for accesses.
4448 #define BP_AIPS_PACRF_SP7 (2U) /*!< Bit position for AIPS_PACRF_SP7. */
4449 #define BM_AIPS_PACRF_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRF_SP7. */
4450 #define BS_AIPS_PACRF_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRF_SP7. */
4452 /*! @brief Read current value of the AIPS_PACRF_SP7 field. */
4453 #define BR_AIPS_PACRF_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP7))
4455 /*! @brief Format value for bitfield AIPS_PACRF_SP7. */
4456 #define BF_AIPS_PACRF_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_SP7) & BM_AIPS_PACRF_SP7)
4458 /*! @brief Set the SP7 field to a new value. */
4459 #define BW_AIPS_PACRF_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP7) = (v))
4463 * @name Register AIPS_PACRF, field TP6[4] (RW)
4465 * Determines whether the peripheral allows accesses from an untrusted master.
4466 * When this field is set and an access is attempted by an untrusted master, the
4467 * access terminates with an error response and no peripheral access initiates.
4470 * - 0 - Accesses from an untrusted master are allowed.
4471 * - 1 - Accesses from an untrusted master are not allowed.
4474 #define BP_AIPS_PACRF_TP6 (4U) /*!< Bit position for AIPS_PACRF_TP6. */
4475 #define BM_AIPS_PACRF_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRF_TP6. */
4476 #define BS_AIPS_PACRF_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRF_TP6. */
4478 /*! @brief Read current value of the AIPS_PACRF_TP6 field. */
4479 #define BR_AIPS_PACRF_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP6))
4481 /*! @brief Format value for bitfield AIPS_PACRF_TP6. */
4482 #define BF_AIPS_PACRF_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_TP6) & BM_AIPS_PACRF_TP6)
4484 /*! @brief Set the TP6 field to a new value. */
4485 #define BW_AIPS_PACRF_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP6) = (v))
4489 * @name Register AIPS_PACRF, field WP6[5] (RW)
4491 * Determines whether the peripheral allows write accesses. When this field is
4492 * set and a write access is attempted, access terminates with an error response
4493 * and no peripheral access initiates.
4496 * - 0 - This peripheral allows write accesses.
4497 * - 1 - This peripheral is write protected.
4500 #define BP_AIPS_PACRF_WP6 (5U) /*!< Bit position for AIPS_PACRF_WP6. */
4501 #define BM_AIPS_PACRF_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRF_WP6. */
4502 #define BS_AIPS_PACRF_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRF_WP6. */
4504 /*! @brief Read current value of the AIPS_PACRF_WP6 field. */
4505 #define BR_AIPS_PACRF_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP6))
4507 /*! @brief Format value for bitfield AIPS_PACRF_WP6. */
4508 #define BF_AIPS_PACRF_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_WP6) & BM_AIPS_PACRF_WP6)
4510 /*! @brief Set the WP6 field to a new value. */
4511 #define BW_AIPS_PACRF_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP6) = (v))
4515 * @name Register AIPS_PACRF, field SP6[6] (RW)
4517 * Determines whether the peripheral requires supervisor privilege level for
4518 * accesses. When this field is set, the master privilege level must indicate the
4519 * supervisor access attribute, and the MPRx[MPLn] control field for the master
4520 * must be set. If not, access terminates with an error response and no peripheral
4524 * - 0 - This peripheral does not require supervisor privilege level for
4526 * - 1 - This peripheral requires supervisor privilege level for accesses.
4529 #define BP_AIPS_PACRF_SP6 (6U) /*!< Bit position for AIPS_PACRF_SP6. */
4530 #define BM_AIPS_PACRF_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRF_SP6. */
4531 #define BS_AIPS_PACRF_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRF_SP6. */
4533 /*! @brief Read current value of the AIPS_PACRF_SP6 field. */
4534 #define BR_AIPS_PACRF_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP6))
4536 /*! @brief Format value for bitfield AIPS_PACRF_SP6. */
4537 #define BF_AIPS_PACRF_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_SP6) & BM_AIPS_PACRF_SP6)
4539 /*! @brief Set the SP6 field to a new value. */
4540 #define BW_AIPS_PACRF_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP6) = (v))
4544 * @name Register AIPS_PACRF, field TP5[8] (RW)
4546 * Determines whether the peripheral allows accesses from an untrusted master.
4547 * When this field is set and an access is attempted by an untrusted master, the
4548 * access terminates with an error response and no peripheral access initiates.
4551 * - 0 - Accesses from an untrusted master are allowed.
4552 * - 1 - Accesses from an untrusted master are not allowed.
4555 #define BP_AIPS_PACRF_TP5 (8U) /*!< Bit position for AIPS_PACRF_TP5. */
4556 #define BM_AIPS_PACRF_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRF_TP5. */
4557 #define BS_AIPS_PACRF_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRF_TP5. */
4559 /*! @brief Read current value of the AIPS_PACRF_TP5 field. */
4560 #define BR_AIPS_PACRF_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP5))
4562 /*! @brief Format value for bitfield AIPS_PACRF_TP5. */
4563 #define BF_AIPS_PACRF_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_TP5) & BM_AIPS_PACRF_TP5)
4565 /*! @brief Set the TP5 field to a new value. */
4566 #define BW_AIPS_PACRF_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP5) = (v))
4570 * @name Register AIPS_PACRF, field WP5[9] (RW)
4572 * Determines whether the peripheral allows write accesses. When this field is
4573 * set and a write access is attempted, access terminates with an error response
4574 * and no peripheral access initiates.
4577 * - 0 - This peripheral allows write accesses.
4578 * - 1 - This peripheral is write protected.
4581 #define BP_AIPS_PACRF_WP5 (9U) /*!< Bit position for AIPS_PACRF_WP5. */
4582 #define BM_AIPS_PACRF_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRF_WP5. */
4583 #define BS_AIPS_PACRF_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRF_WP5. */
4585 /*! @brief Read current value of the AIPS_PACRF_WP5 field. */
4586 #define BR_AIPS_PACRF_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP5))
4588 /*! @brief Format value for bitfield AIPS_PACRF_WP5. */
4589 #define BF_AIPS_PACRF_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_WP5) & BM_AIPS_PACRF_WP5)
4591 /*! @brief Set the WP5 field to a new value. */
4592 #define BW_AIPS_PACRF_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP5) = (v))
4596 * @name Register AIPS_PACRF, field SP5[10] (RW)
4598 * Determines whether the peripheral requires supervisor privilege level for
4599 * accesses. When this field is set, the master privilege level must indicate the
4600 * supervisor access attribute, and the MPRx[MPLn] control field for the master
4601 * must be set. If not, access terminates with an error response and no peripheral
4605 * - 0 - This peripheral does not require supervisor privilege level for
4607 * - 1 - This peripheral requires supervisor privilege level for accesses.
4610 #define BP_AIPS_PACRF_SP5 (10U) /*!< Bit position for AIPS_PACRF_SP5. */
4611 #define BM_AIPS_PACRF_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRF_SP5. */
4612 #define BS_AIPS_PACRF_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRF_SP5. */
4614 /*! @brief Read current value of the AIPS_PACRF_SP5 field. */
4615 #define BR_AIPS_PACRF_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP5))
4617 /*! @brief Format value for bitfield AIPS_PACRF_SP5. */
4618 #define BF_AIPS_PACRF_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_SP5) & BM_AIPS_PACRF_SP5)
4620 /*! @brief Set the SP5 field to a new value. */
4621 #define BW_AIPS_PACRF_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP5) = (v))
4625 * @name Register AIPS_PACRF, field TP4[12] (RW)
4627 * Determines whether the peripheral allows accesses from an untrusted master.
4628 * When this bit is set and an access is attempted by an untrusted master, the
4629 * access terminates with an error response and no peripheral access initiates.
4632 * - 0 - Accesses from an untrusted master are allowed.
4633 * - 1 - Accesses from an untrusted master are not allowed.
4636 #define BP_AIPS_PACRF_TP4 (12U) /*!< Bit position for AIPS_PACRF_TP4. */
4637 #define BM_AIPS_PACRF_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRF_TP4. */
4638 #define BS_AIPS_PACRF_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRF_TP4. */
4640 /*! @brief Read current value of the AIPS_PACRF_TP4 field. */
4641 #define BR_AIPS_PACRF_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP4))
4643 /*! @brief Format value for bitfield AIPS_PACRF_TP4. */
4644 #define BF_AIPS_PACRF_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_TP4) & BM_AIPS_PACRF_TP4)
4646 /*! @brief Set the TP4 field to a new value. */
4647 #define BW_AIPS_PACRF_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP4) = (v))
4651 * @name Register AIPS_PACRF, field WP4[13] (RW)
4653 * Determines whether the peripheral allows write accesses. When this field is
4654 * set and a write access is attempted, access terminates with an error response
4655 * and no peripheral access initiates.
4658 * - 0 - This peripheral allows write accesses.
4659 * - 1 - This peripheral is write protected.
4662 #define BP_AIPS_PACRF_WP4 (13U) /*!< Bit position for AIPS_PACRF_WP4. */
4663 #define BM_AIPS_PACRF_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRF_WP4. */
4664 #define BS_AIPS_PACRF_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRF_WP4. */
4666 /*! @brief Read current value of the AIPS_PACRF_WP4 field. */
4667 #define BR_AIPS_PACRF_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP4))
4669 /*! @brief Format value for bitfield AIPS_PACRF_WP4. */
4670 #define BF_AIPS_PACRF_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_WP4) & BM_AIPS_PACRF_WP4)
4672 /*! @brief Set the WP4 field to a new value. */
4673 #define BW_AIPS_PACRF_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP4) = (v))
4677 * @name Register AIPS_PACRF, field SP4[14] (RW)
4679 * Determines whether the peripheral requires supervisor privilege level for
4680 * access. When this bit is set, the master privilege level must indicate the
4681 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
4682 * set. If not, access terminates with an error response and no peripheral access
4686 * - 0 - This peripheral does not require supervisor privilege level for
4688 * - 1 - This peripheral requires supervisor privilege level for accesses.
4691 #define BP_AIPS_PACRF_SP4 (14U) /*!< Bit position for AIPS_PACRF_SP4. */
4692 #define BM_AIPS_PACRF_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRF_SP4. */
4693 #define BS_AIPS_PACRF_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRF_SP4. */
4695 /*! @brief Read current value of the AIPS_PACRF_SP4 field. */
4696 #define BR_AIPS_PACRF_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP4))
4698 /*! @brief Format value for bitfield AIPS_PACRF_SP4. */
4699 #define BF_AIPS_PACRF_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_SP4) & BM_AIPS_PACRF_SP4)
4701 /*! @brief Set the SP4 field to a new value. */
4702 #define BW_AIPS_PACRF_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP4) = (v))
4706 * @name Register AIPS_PACRF, field TP3[16] (RW)
4708 * Determines whether the peripheral allows accesses from an untrusted master.
4709 * When this field is set and an access is attempted by an untrusted master, the
4710 * access terminates with an error response and no peripheral access initiates.
4713 * - 0 - Accesses from an untrusted master are allowed.
4714 * - 1 - Accesses from an untrusted master are not allowed.
4717 #define BP_AIPS_PACRF_TP3 (16U) /*!< Bit position for AIPS_PACRF_TP3. */
4718 #define BM_AIPS_PACRF_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRF_TP3. */
4719 #define BS_AIPS_PACRF_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRF_TP3. */
4721 /*! @brief Read current value of the AIPS_PACRF_TP3 field. */
4722 #define BR_AIPS_PACRF_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP3))
4724 /*! @brief Format value for bitfield AIPS_PACRF_TP3. */
4725 #define BF_AIPS_PACRF_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_TP3) & BM_AIPS_PACRF_TP3)
4727 /*! @brief Set the TP3 field to a new value. */
4728 #define BW_AIPS_PACRF_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP3) = (v))
4732 * @name Register AIPS_PACRF, field WP3[17] (RW)
4734 * Determines whether the peripheral allows write accesss. When this bit is set
4735 * and a write access is attempted, access terminates with an error response and
4736 * no peripheral access initiates.
4739 * - 0 - This peripheral allows write accesses.
4740 * - 1 - This peripheral is write protected.
4743 #define BP_AIPS_PACRF_WP3 (17U) /*!< Bit position for AIPS_PACRF_WP3. */
4744 #define BM_AIPS_PACRF_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRF_WP3. */
4745 #define BS_AIPS_PACRF_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRF_WP3. */
4747 /*! @brief Read current value of the AIPS_PACRF_WP3 field. */
4748 #define BR_AIPS_PACRF_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP3))
4750 /*! @brief Format value for bitfield AIPS_PACRF_WP3. */
4751 #define BF_AIPS_PACRF_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_WP3) & BM_AIPS_PACRF_WP3)
4753 /*! @brief Set the WP3 field to a new value. */
4754 #define BW_AIPS_PACRF_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP3) = (v))
4758 * @name Register AIPS_PACRF, field SP3[18] (RW)
4760 * Determines whether the peripheral requires supervisor privilege level for
4761 * accesses. When this field is set, the master privilege level must indicate the
4762 * supervisor access attribute, and the MPRx[MPLn] control field for the master
4763 * must be set. If not, access terminates with an error response and no peripheral
4767 * - 0 - This peripheral does not require supervisor privilege level for
4769 * - 1 - This peripheral requires supervisor privilege level for accesses.
4772 #define BP_AIPS_PACRF_SP3 (18U) /*!< Bit position for AIPS_PACRF_SP3. */
4773 #define BM_AIPS_PACRF_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRF_SP3. */
4774 #define BS_AIPS_PACRF_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRF_SP3. */
4776 /*! @brief Read current value of the AIPS_PACRF_SP3 field. */
4777 #define BR_AIPS_PACRF_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP3))
4779 /*! @brief Format value for bitfield AIPS_PACRF_SP3. */
4780 #define BF_AIPS_PACRF_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_SP3) & BM_AIPS_PACRF_SP3)
4782 /*! @brief Set the SP3 field to a new value. */
4783 #define BW_AIPS_PACRF_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP3) = (v))
4787 * @name Register AIPS_PACRF, field TP2[20] (RW)
4789 * Determines whether the peripheral allows accesses from an untrusted master.
4790 * When this bit is set and an access is attempted by an untrusted master, the
4791 * access terminates with an error response and no peripheral access initiates.
4794 * - 0 - Accesses from an untrusted master are allowed.
4795 * - 1 - Accesses from an untrusted master are not allowed.
4798 #define BP_AIPS_PACRF_TP2 (20U) /*!< Bit position for AIPS_PACRF_TP2. */
4799 #define BM_AIPS_PACRF_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRF_TP2. */
4800 #define BS_AIPS_PACRF_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRF_TP2. */
4802 /*! @brief Read current value of the AIPS_PACRF_TP2 field. */
4803 #define BR_AIPS_PACRF_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP2))
4805 /*! @brief Format value for bitfield AIPS_PACRF_TP2. */
4806 #define BF_AIPS_PACRF_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_TP2) & BM_AIPS_PACRF_TP2)
4808 /*! @brief Set the TP2 field to a new value. */
4809 #define BW_AIPS_PACRF_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP2) = (v))
4813 * @name Register AIPS_PACRF, field WP2[21] (RW)
4815 * Determines whether the peripheral allows write accesses. When this field is
4816 * set and a write access is attempted, access terminates with an error response
4817 * and no peripheral access initiates.
4820 * - 0 - This peripheral allows write accesses.
4821 * - 1 - This peripheral is write protected.
4824 #define BP_AIPS_PACRF_WP2 (21U) /*!< Bit position for AIPS_PACRF_WP2. */
4825 #define BM_AIPS_PACRF_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRF_WP2. */
4826 #define BS_AIPS_PACRF_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRF_WP2. */
4828 /*! @brief Read current value of the AIPS_PACRF_WP2 field. */
4829 #define BR_AIPS_PACRF_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP2))
4831 /*! @brief Format value for bitfield AIPS_PACRF_WP2. */
4832 #define BF_AIPS_PACRF_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_WP2) & BM_AIPS_PACRF_WP2)
4834 /*! @brief Set the WP2 field to a new value. */
4835 #define BW_AIPS_PACRF_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP2) = (v))
4839 * @name Register AIPS_PACRF, field SP2[22] (RW)
4841 * Determines whether the peripheral requires supervisor privilege level for
4842 * access. When this bit is set, the master privilege level must indicate the
4843 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
4844 * set. If not, access terminates with an error response and no peripheral access
4848 * - 0 - This peripheral does not require supervisor privilege level for
4850 * - 1 - This peripheral requires supervisor privilege level for accesses.
4853 #define BP_AIPS_PACRF_SP2 (22U) /*!< Bit position for AIPS_PACRF_SP2. */
4854 #define BM_AIPS_PACRF_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRF_SP2. */
4855 #define BS_AIPS_PACRF_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRF_SP2. */
4857 /*! @brief Read current value of the AIPS_PACRF_SP2 field. */
4858 #define BR_AIPS_PACRF_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP2))
4860 /*! @brief Format value for bitfield AIPS_PACRF_SP2. */
4861 #define BF_AIPS_PACRF_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_SP2) & BM_AIPS_PACRF_SP2)
4863 /*! @brief Set the SP2 field to a new value. */
4864 #define BW_AIPS_PACRF_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP2) = (v))
4868 * @name Register AIPS_PACRF, field TP1[24] (RW)
4870 * Determines whether the peripheral allows accesses from an untrusted master.
4871 * When this field is set and an access is attempted by an untrusted master, the
4872 * access terminates with an error response and no peripheral access initiates.
4875 * - 0 - Accesses from an untrusted master are allowed.
4876 * - 1 - Accesses from an untrusted master are not allowed.
4879 #define BP_AIPS_PACRF_TP1 (24U) /*!< Bit position for AIPS_PACRF_TP1. */
4880 #define BM_AIPS_PACRF_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRF_TP1. */
4881 #define BS_AIPS_PACRF_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRF_TP1. */
4883 /*! @brief Read current value of the AIPS_PACRF_TP1 field. */
4884 #define BR_AIPS_PACRF_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP1))
4886 /*! @brief Format value for bitfield AIPS_PACRF_TP1. */
4887 #define BF_AIPS_PACRF_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_TP1) & BM_AIPS_PACRF_TP1)
4889 /*! @brief Set the TP1 field to a new value. */
4890 #define BW_AIPS_PACRF_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP1) = (v))
4894 * @name Register AIPS_PACRF, field WP1[25] (RW)
4896 * Determines whether the peripheral allows write accesses. When this field is
4897 * set and a write access is attempted, access terminates with an error response
4898 * and no peripheral access initiates.
4901 * - 0 - This peripheral allows write accesses.
4902 * - 1 - This peripheral is write protected.
4905 #define BP_AIPS_PACRF_WP1 (25U) /*!< Bit position for AIPS_PACRF_WP1. */
4906 #define BM_AIPS_PACRF_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRF_WP1. */
4907 #define BS_AIPS_PACRF_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRF_WP1. */
4909 /*! @brief Read current value of the AIPS_PACRF_WP1 field. */
4910 #define BR_AIPS_PACRF_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP1))
4912 /*! @brief Format value for bitfield AIPS_PACRF_WP1. */
4913 #define BF_AIPS_PACRF_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_WP1) & BM_AIPS_PACRF_WP1)
4915 /*! @brief Set the WP1 field to a new value. */
4916 #define BW_AIPS_PACRF_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP1) = (v))
4920 * @name Register AIPS_PACRF, field SP1[26] (RW)
4922 * Determines whether the peripheral requires supervisor privilege level for
4923 * access. When this field is set, the master privilege level must indicate the
4924 * supervisor access attribute, and the MPRx[MPLn] control field for the master must
4925 * be set. If not, access terminates with an error response and no peripheral
4929 * - 0 - This peripheral does not require supervisor privilege level for
4931 * - 1 - This peripheral requires supervisor privilege level for accesses.
4934 #define BP_AIPS_PACRF_SP1 (26U) /*!< Bit position for AIPS_PACRF_SP1. */
4935 #define BM_AIPS_PACRF_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRF_SP1. */
4936 #define BS_AIPS_PACRF_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRF_SP1. */
4938 /*! @brief Read current value of the AIPS_PACRF_SP1 field. */
4939 #define BR_AIPS_PACRF_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP1))
4941 /*! @brief Format value for bitfield AIPS_PACRF_SP1. */
4942 #define BF_AIPS_PACRF_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_SP1) & BM_AIPS_PACRF_SP1)
4944 /*! @brief Set the SP1 field to a new value. */
4945 #define BW_AIPS_PACRF_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP1) = (v))
4949 * @name Register AIPS_PACRF, field TP0[28] (RW)
4951 * Determines whether the peripheral allows accesses from an untrusted master.
4952 * When this bit is set and an access is attempted by an untrusted master, the
4953 * access terminates with an error response and no peripheral access initiates.
4956 * - 0 - Accesses from an untrusted master are allowed.
4957 * - 1 - Accesses from an untrusted master are not allowed.
4960 #define BP_AIPS_PACRF_TP0 (28U) /*!< Bit position for AIPS_PACRF_TP0. */
4961 #define BM_AIPS_PACRF_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRF_TP0. */
4962 #define BS_AIPS_PACRF_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRF_TP0. */
4964 /*! @brief Read current value of the AIPS_PACRF_TP0 field. */
4965 #define BR_AIPS_PACRF_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP0))
4967 /*! @brief Format value for bitfield AIPS_PACRF_TP0. */
4968 #define BF_AIPS_PACRF_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_TP0) & BM_AIPS_PACRF_TP0)
4970 /*! @brief Set the TP0 field to a new value. */
4971 #define BW_AIPS_PACRF_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP0) = (v))
4975 * @name Register AIPS_PACRF, field WP0[29] (RW)
4977 * Determines whether the peripheral allows write accesses. When this field is
4978 * set and a write access is attempted, access terminates with an error response
4979 * and no peripheral access initiates.
4982 * - 0 - This peripheral allows write accesses.
4983 * - 1 - This peripheral is write protected.
4986 #define BP_AIPS_PACRF_WP0 (29U) /*!< Bit position for AIPS_PACRF_WP0. */
4987 #define BM_AIPS_PACRF_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRF_WP0. */
4988 #define BS_AIPS_PACRF_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRF_WP0. */
4990 /*! @brief Read current value of the AIPS_PACRF_WP0 field. */
4991 #define BR_AIPS_PACRF_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP0))
4993 /*! @brief Format value for bitfield AIPS_PACRF_WP0. */
4994 #define BF_AIPS_PACRF_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_WP0) & BM_AIPS_PACRF_WP0)
4996 /*! @brief Set the WP0 field to a new value. */
4997 #define BW_AIPS_PACRF_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP0) = (v))
5001 * @name Register AIPS_PACRF, field SP0[30] (RW)
5003 * Determines whether the peripheral requires supervisor privilege level for
5004 * accesses. When this field is set, the master privilege level must indicate the
5005 * supervisor access attribute, and the MPRx[MPLn] control field for the master
5006 * must be set. If not, access terminates with an error response and no peripheral
5010 * - 0 - This peripheral does not require supervisor privilege level for
5012 * - 1 - This peripheral requires supervisor privilege level for accesses.
5015 #define BP_AIPS_PACRF_SP0 (30U) /*!< Bit position for AIPS_PACRF_SP0. */
5016 #define BM_AIPS_PACRF_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRF_SP0. */
5017 #define BS_AIPS_PACRF_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRF_SP0. */
5019 /*! @brief Read current value of the AIPS_PACRF_SP0 field. */
5020 #define BR_AIPS_PACRF_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP0))
5022 /*! @brief Format value for bitfield AIPS_PACRF_SP0. */
5023 #define BF_AIPS_PACRF_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_SP0) & BM_AIPS_PACRF_SP0)
5025 /*! @brief Set the SP0 field to a new value. */
5026 #define BW_AIPS_PACRF_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP0) = (v))
5029 /*******************************************************************************
5030 * HW_AIPS_PACRG - Peripheral Access Control Register
5031 ******************************************************************************/
5034 * @brief HW_AIPS_PACRG - Peripheral Access Control Register (RW)
5036 * Reset value: 0x44444444U
5038 * This section describes PACR registers E-P, which control peripheral slots
5039 * 32-127. See PACRPeripheral Access Control Register for the description of these
5042 typedef union _hw_aips_pacrg
5045 struct _hw_aips_pacrg_bitfields
5047 uint32_t TP7
: 1; /*!< [0] Trusted Protect */
5048 uint32_t WP7
: 1; /*!< [1] Write Protect */
5049 uint32_t SP7
: 1; /*!< [2] Supervisor Protect */
5050 uint32_t RESERVED0
: 1; /*!< [3] */
5051 uint32_t TP6
: 1; /*!< [4] Trusted Protect */
5052 uint32_t WP6
: 1; /*!< [5] Write Protect */
5053 uint32_t SP6
: 1; /*!< [6] Supervisor Protect */
5054 uint32_t RESERVED1
: 1; /*!< [7] */
5055 uint32_t TP5
: 1; /*!< [8] Trusted Protect */
5056 uint32_t WP5
: 1; /*!< [9] Write Protect */
5057 uint32_t SP5
: 1; /*!< [10] Supervisor Protect */
5058 uint32_t RESERVED2
: 1; /*!< [11] */
5059 uint32_t TP4
: 1; /*!< [12] Trusted Protect */
5060 uint32_t WP4
: 1; /*!< [13] Write Protect */
5061 uint32_t SP4
: 1; /*!< [14] Supervisor Protect */
5062 uint32_t RESERVED3
: 1; /*!< [15] */
5063 uint32_t TP3
: 1; /*!< [16] Trusted Protect */
5064 uint32_t WP3
: 1; /*!< [17] Write Protect */
5065 uint32_t SP3
: 1; /*!< [18] Supervisor Protect */
5066 uint32_t RESERVED4
: 1; /*!< [19] */
5067 uint32_t TP2
: 1; /*!< [20] Trusted Protect */
5068 uint32_t WP2
: 1; /*!< [21] Write Protect */
5069 uint32_t SP2
: 1; /*!< [22] Supervisor Protect */
5070 uint32_t RESERVED5
: 1; /*!< [23] */
5071 uint32_t TP1
: 1; /*!< [24] Trusted Protect */
5072 uint32_t WP1
: 1; /*!< [25] Write Protect */
5073 uint32_t SP1
: 1; /*!< [26] Supervisor Protect */
5074 uint32_t RESERVED6
: 1; /*!< [27] */
5075 uint32_t TP0
: 1; /*!< [28] Trusted Protect */
5076 uint32_t WP0
: 1; /*!< [29] Write Protect */
5077 uint32_t SP0
: 1; /*!< [30] Supervisor Protect */
5078 uint32_t RESERVED7
: 1; /*!< [31] */
5083 * @name Constants and macros for entire AIPS_PACRG register
5086 #define HW_AIPS_PACRG_ADDR(x) ((x) + 0x48U)
5088 #define HW_AIPS_PACRG(x) (*(__IO hw_aips_pacrg_t *) HW_AIPS_PACRG_ADDR(x))
5089 #define HW_AIPS_PACRG_RD(x) (HW_AIPS_PACRG(x).U)
5090 #define HW_AIPS_PACRG_WR(x, v) (HW_AIPS_PACRG(x).U = (v))
5091 #define HW_AIPS_PACRG_SET(x, v) (HW_AIPS_PACRG_WR(x, HW_AIPS_PACRG_RD(x) | (v)))
5092 #define HW_AIPS_PACRG_CLR(x, v) (HW_AIPS_PACRG_WR(x, HW_AIPS_PACRG_RD(x) & ~(v)))
5093 #define HW_AIPS_PACRG_TOG(x, v) (HW_AIPS_PACRG_WR(x, HW_AIPS_PACRG_RD(x) ^ (v)))
5097 * Constants & macros for individual AIPS_PACRG bitfields
5101 * @name Register AIPS_PACRG, field TP7[0] (RW)
5103 * Determines whether the peripheral allows accesses from an untrusted master.
5104 * When this field is set and an access is attempted by an untrusted master, the
5105 * access terminates with an error response and no peripheral access initiates.
5108 * - 0 - Accesses from an untrusted master are allowed.
5109 * - 1 - Accesses from an untrusted master are not allowed.
5112 #define BP_AIPS_PACRG_TP7 (0U) /*!< Bit position for AIPS_PACRG_TP7. */
5113 #define BM_AIPS_PACRG_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRG_TP7. */
5114 #define BS_AIPS_PACRG_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRG_TP7. */
5116 /*! @brief Read current value of the AIPS_PACRG_TP7 field. */
5117 #define BR_AIPS_PACRG_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP7))
5119 /*! @brief Format value for bitfield AIPS_PACRG_TP7. */
5120 #define BF_AIPS_PACRG_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_TP7) & BM_AIPS_PACRG_TP7)
5122 /*! @brief Set the TP7 field to a new value. */
5123 #define BW_AIPS_PACRG_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP7) = (v))
5127 * @name Register AIPS_PACRG, field WP7[1] (RW)
5129 * Determines whether the peripheral allows write accesses. When this field is
5130 * set and a write access is attempted, access terminates with an error response
5131 * and no peripheral access initiates.
5134 * - 0 - This peripheral allows write accesses.
5135 * - 1 - This peripheral is write protected.
5138 #define BP_AIPS_PACRG_WP7 (1U) /*!< Bit position for AIPS_PACRG_WP7. */
5139 #define BM_AIPS_PACRG_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRG_WP7. */
5140 #define BS_AIPS_PACRG_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRG_WP7. */
5142 /*! @brief Read current value of the AIPS_PACRG_WP7 field. */
5143 #define BR_AIPS_PACRG_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP7))
5145 /*! @brief Format value for bitfield AIPS_PACRG_WP7. */
5146 #define BF_AIPS_PACRG_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_WP7) & BM_AIPS_PACRG_WP7)
5148 /*! @brief Set the WP7 field to a new value. */
5149 #define BW_AIPS_PACRG_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP7) = (v))
5153 * @name Register AIPS_PACRG, field SP7[2] (RW)
5155 * Determines whether the peripheral requires supervisor privilege level for
5156 * accesses. When this field is set, the master privilege level must indicate the
5157 * supervisor access attribute, and the MPRx[MPLn] control field for the master
5158 * must be set. If not, access terminates with an error response and no peripheral
5162 * - 0 - This peripheral does not require supervisor privilege level for
5164 * - 1 - This peripheral requires supervisor privilege level for accesses.
5167 #define BP_AIPS_PACRG_SP7 (2U) /*!< Bit position for AIPS_PACRG_SP7. */
5168 #define BM_AIPS_PACRG_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRG_SP7. */
5169 #define BS_AIPS_PACRG_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRG_SP7. */
5171 /*! @brief Read current value of the AIPS_PACRG_SP7 field. */
5172 #define BR_AIPS_PACRG_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP7))
5174 /*! @brief Format value for bitfield AIPS_PACRG_SP7. */
5175 #define BF_AIPS_PACRG_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_SP7) & BM_AIPS_PACRG_SP7)
5177 /*! @brief Set the SP7 field to a new value. */
5178 #define BW_AIPS_PACRG_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP7) = (v))
5182 * @name Register AIPS_PACRG, field TP6[4] (RW)
5184 * Determines whether the peripheral allows accesses from an untrusted master.
5185 * When this field is set and an access is attempted by an untrusted master, the
5186 * access terminates with an error response and no peripheral access initiates.
5189 * - 0 - Accesses from an untrusted master are allowed.
5190 * - 1 - Accesses from an untrusted master are not allowed.
5193 #define BP_AIPS_PACRG_TP6 (4U) /*!< Bit position for AIPS_PACRG_TP6. */
5194 #define BM_AIPS_PACRG_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRG_TP6. */
5195 #define BS_AIPS_PACRG_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRG_TP6. */
5197 /*! @brief Read current value of the AIPS_PACRG_TP6 field. */
5198 #define BR_AIPS_PACRG_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP6))
5200 /*! @brief Format value for bitfield AIPS_PACRG_TP6. */
5201 #define BF_AIPS_PACRG_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_TP6) & BM_AIPS_PACRG_TP6)
5203 /*! @brief Set the TP6 field to a new value. */
5204 #define BW_AIPS_PACRG_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP6) = (v))
5208 * @name Register AIPS_PACRG, field WP6[5] (RW)
5210 * Determines whether the peripheral allows write accesses. When this field is
5211 * set and a write access is attempted, access terminates with an error response
5212 * and no peripheral access initiates.
5215 * - 0 - This peripheral allows write accesses.
5216 * - 1 - This peripheral is write protected.
5219 #define BP_AIPS_PACRG_WP6 (5U) /*!< Bit position for AIPS_PACRG_WP6. */
5220 #define BM_AIPS_PACRG_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRG_WP6. */
5221 #define BS_AIPS_PACRG_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRG_WP6. */
5223 /*! @brief Read current value of the AIPS_PACRG_WP6 field. */
5224 #define BR_AIPS_PACRG_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP6))
5226 /*! @brief Format value for bitfield AIPS_PACRG_WP6. */
5227 #define BF_AIPS_PACRG_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_WP6) & BM_AIPS_PACRG_WP6)
5229 /*! @brief Set the WP6 field to a new value. */
5230 #define BW_AIPS_PACRG_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP6) = (v))
5234 * @name Register AIPS_PACRG, field SP6[6] (RW)
5236 * Determines whether the peripheral requires supervisor privilege level for
5237 * accesses. When this field is set, the master privilege level must indicate the
5238 * supervisor access attribute, and the MPRx[MPLn] control field for the master
5239 * must be set. If not, access terminates with an error response and no peripheral
5243 * - 0 - This peripheral does not require supervisor privilege level for
5245 * - 1 - This peripheral requires supervisor privilege level for accesses.
5248 #define BP_AIPS_PACRG_SP6 (6U) /*!< Bit position for AIPS_PACRG_SP6. */
5249 #define BM_AIPS_PACRG_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRG_SP6. */
5250 #define BS_AIPS_PACRG_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRG_SP6. */
5252 /*! @brief Read current value of the AIPS_PACRG_SP6 field. */
5253 #define BR_AIPS_PACRG_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP6))
5255 /*! @brief Format value for bitfield AIPS_PACRG_SP6. */
5256 #define BF_AIPS_PACRG_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_SP6) & BM_AIPS_PACRG_SP6)
5258 /*! @brief Set the SP6 field to a new value. */
5259 #define BW_AIPS_PACRG_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP6) = (v))
5263 * @name Register AIPS_PACRG, field TP5[8] (RW)
5265 * Determines whether the peripheral allows accesses from an untrusted master.
5266 * When this field is set and an access is attempted by an untrusted master, the
5267 * access terminates with an error response and no peripheral access initiates.
5270 * - 0 - Accesses from an untrusted master are allowed.
5271 * - 1 - Accesses from an untrusted master are not allowed.
5274 #define BP_AIPS_PACRG_TP5 (8U) /*!< Bit position for AIPS_PACRG_TP5. */
5275 #define BM_AIPS_PACRG_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRG_TP5. */
5276 #define BS_AIPS_PACRG_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRG_TP5. */
5278 /*! @brief Read current value of the AIPS_PACRG_TP5 field. */
5279 #define BR_AIPS_PACRG_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP5))
5281 /*! @brief Format value for bitfield AIPS_PACRG_TP5. */
5282 #define BF_AIPS_PACRG_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_TP5) & BM_AIPS_PACRG_TP5)
5284 /*! @brief Set the TP5 field to a new value. */
5285 #define BW_AIPS_PACRG_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP5) = (v))
5289 * @name Register AIPS_PACRG, field WP5[9] (RW)
5291 * Determines whether the peripheral allows write accesses. When this field is
5292 * set and a write access is attempted, access terminates with an error response
5293 * and no peripheral access initiates.
5296 * - 0 - This peripheral allows write accesses.
5297 * - 1 - This peripheral is write protected.
5300 #define BP_AIPS_PACRG_WP5 (9U) /*!< Bit position for AIPS_PACRG_WP5. */
5301 #define BM_AIPS_PACRG_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRG_WP5. */
5302 #define BS_AIPS_PACRG_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRG_WP5. */
5304 /*! @brief Read current value of the AIPS_PACRG_WP5 field. */
5305 #define BR_AIPS_PACRG_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP5))
5307 /*! @brief Format value for bitfield AIPS_PACRG_WP5. */
5308 #define BF_AIPS_PACRG_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_WP5) & BM_AIPS_PACRG_WP5)
5310 /*! @brief Set the WP5 field to a new value. */
5311 #define BW_AIPS_PACRG_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP5) = (v))
5315 * @name Register AIPS_PACRG, field SP5[10] (RW)
5317 * Determines whether the peripheral requires supervisor privilege level for
5318 * accesses. When this field is set, the master privilege level must indicate the
5319 * supervisor access attribute, and the MPRx[MPLn] control field for the master
5320 * must be set. If not, access terminates with an error response and no peripheral
5324 * - 0 - This peripheral does not require supervisor privilege level for
5326 * - 1 - This peripheral requires supervisor privilege level for accesses.
5329 #define BP_AIPS_PACRG_SP5 (10U) /*!< Bit position for AIPS_PACRG_SP5. */
5330 #define BM_AIPS_PACRG_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRG_SP5. */
5331 #define BS_AIPS_PACRG_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRG_SP5. */
5333 /*! @brief Read current value of the AIPS_PACRG_SP5 field. */
5334 #define BR_AIPS_PACRG_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP5))
5336 /*! @brief Format value for bitfield AIPS_PACRG_SP5. */
5337 #define BF_AIPS_PACRG_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_SP5) & BM_AIPS_PACRG_SP5)
5339 /*! @brief Set the SP5 field to a new value. */
5340 #define BW_AIPS_PACRG_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP5) = (v))
5344 * @name Register AIPS_PACRG, field TP4[12] (RW)
5346 * Determines whether the peripheral allows accesses from an untrusted master.
5347 * When this bit is set and an access is attempted by an untrusted master, the
5348 * access terminates with an error response and no peripheral access initiates.
5351 * - 0 - Accesses from an untrusted master are allowed.
5352 * - 1 - Accesses from an untrusted master are not allowed.
5355 #define BP_AIPS_PACRG_TP4 (12U) /*!< Bit position for AIPS_PACRG_TP4. */
5356 #define BM_AIPS_PACRG_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRG_TP4. */
5357 #define BS_AIPS_PACRG_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRG_TP4. */
5359 /*! @brief Read current value of the AIPS_PACRG_TP4 field. */
5360 #define BR_AIPS_PACRG_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP4))
5362 /*! @brief Format value for bitfield AIPS_PACRG_TP4. */
5363 #define BF_AIPS_PACRG_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_TP4) & BM_AIPS_PACRG_TP4)
5365 /*! @brief Set the TP4 field to a new value. */
5366 #define BW_AIPS_PACRG_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP4) = (v))
5370 * @name Register AIPS_PACRG, field WP4[13] (RW)
5372 * Determines whether the peripheral allows write accesses. When this field is
5373 * set and a write access is attempted, access terminates with an error response
5374 * and no peripheral access initiates.
5377 * - 0 - This peripheral allows write accesses.
5378 * - 1 - This peripheral is write protected.
5381 #define BP_AIPS_PACRG_WP4 (13U) /*!< Bit position for AIPS_PACRG_WP4. */
5382 #define BM_AIPS_PACRG_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRG_WP4. */
5383 #define BS_AIPS_PACRG_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRG_WP4. */
5385 /*! @brief Read current value of the AIPS_PACRG_WP4 field. */
5386 #define BR_AIPS_PACRG_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP4))
5388 /*! @brief Format value for bitfield AIPS_PACRG_WP4. */
5389 #define BF_AIPS_PACRG_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_WP4) & BM_AIPS_PACRG_WP4)
5391 /*! @brief Set the WP4 field to a new value. */
5392 #define BW_AIPS_PACRG_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP4) = (v))
5396 * @name Register AIPS_PACRG, field SP4[14] (RW)
5398 * Determines whether the peripheral requires supervisor privilege level for
5399 * access. When this bit is set, the master privilege level must indicate the
5400 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
5401 * set. If not, access terminates with an error response and no peripheral access
5405 * - 0 - This peripheral does not require supervisor privilege level for
5407 * - 1 - This peripheral requires supervisor privilege level for accesses.
5410 #define BP_AIPS_PACRG_SP4 (14U) /*!< Bit position for AIPS_PACRG_SP4. */
5411 #define BM_AIPS_PACRG_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRG_SP4. */
5412 #define BS_AIPS_PACRG_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRG_SP4. */
5414 /*! @brief Read current value of the AIPS_PACRG_SP4 field. */
5415 #define BR_AIPS_PACRG_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP4))
5417 /*! @brief Format value for bitfield AIPS_PACRG_SP4. */
5418 #define BF_AIPS_PACRG_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_SP4) & BM_AIPS_PACRG_SP4)
5420 /*! @brief Set the SP4 field to a new value. */
5421 #define BW_AIPS_PACRG_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP4) = (v))
5425 * @name Register AIPS_PACRG, field TP3[16] (RW)
5427 * Determines whether the peripheral allows accesses from an untrusted master.
5428 * When this field is set and an access is attempted by an untrusted master, the
5429 * access terminates with an error response and no peripheral access initiates.
5432 * - 0 - Accesses from an untrusted master are allowed.
5433 * - 1 - Accesses from an untrusted master are not allowed.
5436 #define BP_AIPS_PACRG_TP3 (16U) /*!< Bit position for AIPS_PACRG_TP3. */
5437 #define BM_AIPS_PACRG_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRG_TP3. */
5438 #define BS_AIPS_PACRG_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRG_TP3. */
5440 /*! @brief Read current value of the AIPS_PACRG_TP3 field. */
5441 #define BR_AIPS_PACRG_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP3))
5443 /*! @brief Format value for bitfield AIPS_PACRG_TP3. */
5444 #define BF_AIPS_PACRG_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_TP3) & BM_AIPS_PACRG_TP3)
5446 /*! @brief Set the TP3 field to a new value. */
5447 #define BW_AIPS_PACRG_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP3) = (v))
5451 * @name Register AIPS_PACRG, field WP3[17] (RW)
5453 * Determines whether the peripheral allows write accesss. When this bit is set
5454 * and a write access is attempted, access terminates with an error response and
5455 * no peripheral access initiates.
5458 * - 0 - This peripheral allows write accesses.
5459 * - 1 - This peripheral is write protected.
5462 #define BP_AIPS_PACRG_WP3 (17U) /*!< Bit position for AIPS_PACRG_WP3. */
5463 #define BM_AIPS_PACRG_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRG_WP3. */
5464 #define BS_AIPS_PACRG_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRG_WP3. */
5466 /*! @brief Read current value of the AIPS_PACRG_WP3 field. */
5467 #define BR_AIPS_PACRG_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP3))
5469 /*! @brief Format value for bitfield AIPS_PACRG_WP3. */
5470 #define BF_AIPS_PACRG_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_WP3) & BM_AIPS_PACRG_WP3)
5472 /*! @brief Set the WP3 field to a new value. */
5473 #define BW_AIPS_PACRG_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP3) = (v))
5477 * @name Register AIPS_PACRG, field SP3[18] (RW)
5479 * Determines whether the peripheral requires supervisor privilege level for
5480 * accesses. When this field is set, the master privilege level must indicate the
5481 * supervisor access attribute, and the MPRx[MPLn] control field for the master
5482 * must be set. If not, access terminates with an error response and no peripheral
5486 * - 0 - This peripheral does not require supervisor privilege level for
5488 * - 1 - This peripheral requires supervisor privilege level for accesses.
5491 #define BP_AIPS_PACRG_SP3 (18U) /*!< Bit position for AIPS_PACRG_SP3. */
5492 #define BM_AIPS_PACRG_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRG_SP3. */
5493 #define BS_AIPS_PACRG_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRG_SP3. */
5495 /*! @brief Read current value of the AIPS_PACRG_SP3 field. */
5496 #define BR_AIPS_PACRG_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP3))
5498 /*! @brief Format value for bitfield AIPS_PACRG_SP3. */
5499 #define BF_AIPS_PACRG_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_SP3) & BM_AIPS_PACRG_SP3)
5501 /*! @brief Set the SP3 field to a new value. */
5502 #define BW_AIPS_PACRG_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP3) = (v))
5506 * @name Register AIPS_PACRG, field TP2[20] (RW)
5508 * Determines whether the peripheral allows accesses from an untrusted master.
5509 * When this bit is set and an access is attempted by an untrusted master, the
5510 * access terminates with an error response and no peripheral access initiates.
5513 * - 0 - Accesses from an untrusted master are allowed.
5514 * - 1 - Accesses from an untrusted master are not allowed.
5517 #define BP_AIPS_PACRG_TP2 (20U) /*!< Bit position for AIPS_PACRG_TP2. */
5518 #define BM_AIPS_PACRG_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRG_TP2. */
5519 #define BS_AIPS_PACRG_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRG_TP2. */
5521 /*! @brief Read current value of the AIPS_PACRG_TP2 field. */
5522 #define BR_AIPS_PACRG_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP2))
5524 /*! @brief Format value for bitfield AIPS_PACRG_TP2. */
5525 #define BF_AIPS_PACRG_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_TP2) & BM_AIPS_PACRG_TP2)
5527 /*! @brief Set the TP2 field to a new value. */
5528 #define BW_AIPS_PACRG_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP2) = (v))
5532 * @name Register AIPS_PACRG, field WP2[21] (RW)
5534 * Determines whether the peripheral allows write accesses. When this field is
5535 * set and a write access is attempted, access terminates with an error response
5536 * and no peripheral access initiates.
5539 * - 0 - This peripheral allows write accesses.
5540 * - 1 - This peripheral is write protected.
5543 #define BP_AIPS_PACRG_WP2 (21U) /*!< Bit position for AIPS_PACRG_WP2. */
5544 #define BM_AIPS_PACRG_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRG_WP2. */
5545 #define BS_AIPS_PACRG_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRG_WP2. */
5547 /*! @brief Read current value of the AIPS_PACRG_WP2 field. */
5548 #define BR_AIPS_PACRG_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP2))
5550 /*! @brief Format value for bitfield AIPS_PACRG_WP2. */
5551 #define BF_AIPS_PACRG_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_WP2) & BM_AIPS_PACRG_WP2)
5553 /*! @brief Set the WP2 field to a new value. */
5554 #define BW_AIPS_PACRG_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP2) = (v))
5558 * @name Register AIPS_PACRG, field SP2[22] (RW)
5560 * Determines whether the peripheral requires supervisor privilege level for
5561 * access. When this bit is set, the master privilege level must indicate the
5562 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
5563 * set. If not, access terminates with an error response and no peripheral access
5567 * - 0 - This peripheral does not require supervisor privilege level for
5569 * - 1 - This peripheral requires supervisor privilege level for accesses.
5572 #define BP_AIPS_PACRG_SP2 (22U) /*!< Bit position for AIPS_PACRG_SP2. */
5573 #define BM_AIPS_PACRG_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRG_SP2. */
5574 #define BS_AIPS_PACRG_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRG_SP2. */
5576 /*! @brief Read current value of the AIPS_PACRG_SP2 field. */
5577 #define BR_AIPS_PACRG_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP2))
5579 /*! @brief Format value for bitfield AIPS_PACRG_SP2. */
5580 #define BF_AIPS_PACRG_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_SP2) & BM_AIPS_PACRG_SP2)
5582 /*! @brief Set the SP2 field to a new value. */
5583 #define BW_AIPS_PACRG_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP2) = (v))
5587 * @name Register AIPS_PACRG, field TP1[24] (RW)
5589 * Determines whether the peripheral allows accesses from an untrusted master.
5590 * When this field is set and an access is attempted by an untrusted master, the
5591 * access terminates with an error response and no peripheral access initiates.
5594 * - 0 - Accesses from an untrusted master are allowed.
5595 * - 1 - Accesses from an untrusted master are not allowed.
5598 #define BP_AIPS_PACRG_TP1 (24U) /*!< Bit position for AIPS_PACRG_TP1. */
5599 #define BM_AIPS_PACRG_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRG_TP1. */
5600 #define BS_AIPS_PACRG_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRG_TP1. */
5602 /*! @brief Read current value of the AIPS_PACRG_TP1 field. */
5603 #define BR_AIPS_PACRG_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP1))
5605 /*! @brief Format value for bitfield AIPS_PACRG_TP1. */
5606 #define BF_AIPS_PACRG_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_TP1) & BM_AIPS_PACRG_TP1)
5608 /*! @brief Set the TP1 field to a new value. */
5609 #define BW_AIPS_PACRG_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP1) = (v))
5613 * @name Register AIPS_PACRG, field WP1[25] (RW)
5615 * Determines whether the peripheral allows write accesses. When this field is
5616 * set and a write access is attempted, access terminates with an error response
5617 * and no peripheral access initiates.
5620 * - 0 - This peripheral allows write accesses.
5621 * - 1 - This peripheral is write protected.
5624 #define BP_AIPS_PACRG_WP1 (25U) /*!< Bit position for AIPS_PACRG_WP1. */
5625 #define BM_AIPS_PACRG_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRG_WP1. */
5626 #define BS_AIPS_PACRG_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRG_WP1. */
5628 /*! @brief Read current value of the AIPS_PACRG_WP1 field. */
5629 #define BR_AIPS_PACRG_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP1))
5631 /*! @brief Format value for bitfield AIPS_PACRG_WP1. */
5632 #define BF_AIPS_PACRG_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_WP1) & BM_AIPS_PACRG_WP1)
5634 /*! @brief Set the WP1 field to a new value. */
5635 #define BW_AIPS_PACRG_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP1) = (v))
5639 * @name Register AIPS_PACRG, field SP1[26] (RW)
5641 * Determines whether the peripheral requires supervisor privilege level for
5642 * access. When this field is set, the master privilege level must indicate the
5643 * supervisor access attribute, and the MPRx[MPLn] control field for the master must
5644 * be set. If not, access terminates with an error response and no peripheral
5648 * - 0 - This peripheral does not require supervisor privilege level for
5650 * - 1 - This peripheral requires supervisor privilege level for accesses.
5653 #define BP_AIPS_PACRG_SP1 (26U) /*!< Bit position for AIPS_PACRG_SP1. */
5654 #define BM_AIPS_PACRG_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRG_SP1. */
5655 #define BS_AIPS_PACRG_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRG_SP1. */
5657 /*! @brief Read current value of the AIPS_PACRG_SP1 field. */
5658 #define BR_AIPS_PACRG_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP1))
5660 /*! @brief Format value for bitfield AIPS_PACRG_SP1. */
5661 #define BF_AIPS_PACRG_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_SP1) & BM_AIPS_PACRG_SP1)
5663 /*! @brief Set the SP1 field to a new value. */
5664 #define BW_AIPS_PACRG_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP1) = (v))
5668 * @name Register AIPS_PACRG, field TP0[28] (RW)
5670 * Determines whether the peripheral allows accesses from an untrusted master.
5671 * When this bit is set and an access is attempted by an untrusted master, the
5672 * access terminates with an error response and no peripheral access initiates.
5675 * - 0 - Accesses from an untrusted master are allowed.
5676 * - 1 - Accesses from an untrusted master are not allowed.
5679 #define BP_AIPS_PACRG_TP0 (28U) /*!< Bit position for AIPS_PACRG_TP0. */
5680 #define BM_AIPS_PACRG_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRG_TP0. */
5681 #define BS_AIPS_PACRG_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRG_TP0. */
5683 /*! @brief Read current value of the AIPS_PACRG_TP0 field. */
5684 #define BR_AIPS_PACRG_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP0))
5686 /*! @brief Format value for bitfield AIPS_PACRG_TP0. */
5687 #define BF_AIPS_PACRG_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_TP0) & BM_AIPS_PACRG_TP0)
5689 /*! @brief Set the TP0 field to a new value. */
5690 #define BW_AIPS_PACRG_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP0) = (v))
5694 * @name Register AIPS_PACRG, field WP0[29] (RW)
5696 * Determines whether the peripheral allows write accesses. When this field is
5697 * set and a write access is attempted, access terminates with an error response
5698 * and no peripheral access initiates.
5701 * - 0 - This peripheral allows write accesses.
5702 * - 1 - This peripheral is write protected.
5705 #define BP_AIPS_PACRG_WP0 (29U) /*!< Bit position for AIPS_PACRG_WP0. */
5706 #define BM_AIPS_PACRG_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRG_WP0. */
5707 #define BS_AIPS_PACRG_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRG_WP0. */
5709 /*! @brief Read current value of the AIPS_PACRG_WP0 field. */
5710 #define BR_AIPS_PACRG_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP0))
5712 /*! @brief Format value for bitfield AIPS_PACRG_WP0. */
5713 #define BF_AIPS_PACRG_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_WP0) & BM_AIPS_PACRG_WP0)
5715 /*! @brief Set the WP0 field to a new value. */
5716 #define BW_AIPS_PACRG_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP0) = (v))
5720 * @name Register AIPS_PACRG, field SP0[30] (RW)
5722 * Determines whether the peripheral requires supervisor privilege level for
5723 * accesses. When this field is set, the master privilege level must indicate the
5724 * supervisor access attribute, and the MPRx[MPLn] control field for the master
5725 * must be set. If not, access terminates with an error response and no peripheral
5729 * - 0 - This peripheral does not require supervisor privilege level for
5731 * - 1 - This peripheral requires supervisor privilege level for accesses.
5734 #define BP_AIPS_PACRG_SP0 (30U) /*!< Bit position for AIPS_PACRG_SP0. */
5735 #define BM_AIPS_PACRG_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRG_SP0. */
5736 #define BS_AIPS_PACRG_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRG_SP0. */
5738 /*! @brief Read current value of the AIPS_PACRG_SP0 field. */
5739 #define BR_AIPS_PACRG_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP0))
5741 /*! @brief Format value for bitfield AIPS_PACRG_SP0. */
5742 #define BF_AIPS_PACRG_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_SP0) & BM_AIPS_PACRG_SP0)
5744 /*! @brief Set the SP0 field to a new value. */
5745 #define BW_AIPS_PACRG_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP0) = (v))
5748 /*******************************************************************************
5749 * HW_AIPS_PACRH - Peripheral Access Control Register
5750 ******************************************************************************/
5753 * @brief HW_AIPS_PACRH - Peripheral Access Control Register (RW)
5755 * Reset value: 0x44444444U
5757 * This section describes PACR registers E-P, which control peripheral slots
5758 * 32-127. See PACRPeripheral Access Control Register for the description of these
5761 typedef union _hw_aips_pacrh
5764 struct _hw_aips_pacrh_bitfields
5766 uint32_t TP7
: 1; /*!< [0] Trusted Protect */
5767 uint32_t WP7
: 1; /*!< [1] Write Protect */
5768 uint32_t SP7
: 1; /*!< [2] Supervisor Protect */
5769 uint32_t RESERVED0
: 1; /*!< [3] */
5770 uint32_t TP6
: 1; /*!< [4] Trusted Protect */
5771 uint32_t WP6
: 1; /*!< [5] Write Protect */
5772 uint32_t SP6
: 1; /*!< [6] Supervisor Protect */
5773 uint32_t RESERVED1
: 1; /*!< [7] */
5774 uint32_t TP5
: 1; /*!< [8] Trusted Protect */
5775 uint32_t WP5
: 1; /*!< [9] Write Protect */
5776 uint32_t SP5
: 1; /*!< [10] Supervisor Protect */
5777 uint32_t RESERVED2
: 1; /*!< [11] */
5778 uint32_t TP4
: 1; /*!< [12] Trusted Protect */
5779 uint32_t WP4
: 1; /*!< [13] Write Protect */
5780 uint32_t SP4
: 1; /*!< [14] Supervisor Protect */
5781 uint32_t RESERVED3
: 1; /*!< [15] */
5782 uint32_t TP3
: 1; /*!< [16] Trusted Protect */
5783 uint32_t WP3
: 1; /*!< [17] Write Protect */
5784 uint32_t SP3
: 1; /*!< [18] Supervisor Protect */
5785 uint32_t RESERVED4
: 1; /*!< [19] */
5786 uint32_t TP2
: 1; /*!< [20] Trusted Protect */
5787 uint32_t WP2
: 1; /*!< [21] Write Protect */
5788 uint32_t SP2
: 1; /*!< [22] Supervisor Protect */
5789 uint32_t RESERVED5
: 1; /*!< [23] */
5790 uint32_t TP1
: 1; /*!< [24] Trusted Protect */
5791 uint32_t WP1
: 1; /*!< [25] Write Protect */
5792 uint32_t SP1
: 1; /*!< [26] Supervisor Protect */
5793 uint32_t RESERVED6
: 1; /*!< [27] */
5794 uint32_t TP0
: 1; /*!< [28] Trusted Protect */
5795 uint32_t WP0
: 1; /*!< [29] Write Protect */
5796 uint32_t SP0
: 1; /*!< [30] Supervisor Protect */
5797 uint32_t RESERVED7
: 1; /*!< [31] */
5802 * @name Constants and macros for entire AIPS_PACRH register
5805 #define HW_AIPS_PACRH_ADDR(x) ((x) + 0x4CU)
5807 #define HW_AIPS_PACRH(x) (*(__IO hw_aips_pacrh_t *) HW_AIPS_PACRH_ADDR(x))
5808 #define HW_AIPS_PACRH_RD(x) (HW_AIPS_PACRH(x).U)
5809 #define HW_AIPS_PACRH_WR(x, v) (HW_AIPS_PACRH(x).U = (v))
5810 #define HW_AIPS_PACRH_SET(x, v) (HW_AIPS_PACRH_WR(x, HW_AIPS_PACRH_RD(x) | (v)))
5811 #define HW_AIPS_PACRH_CLR(x, v) (HW_AIPS_PACRH_WR(x, HW_AIPS_PACRH_RD(x) & ~(v)))
5812 #define HW_AIPS_PACRH_TOG(x, v) (HW_AIPS_PACRH_WR(x, HW_AIPS_PACRH_RD(x) ^ (v)))
5816 * Constants & macros for individual AIPS_PACRH bitfields
5820 * @name Register AIPS_PACRH, field TP7[0] (RW)
5822 * Determines whether the peripheral allows accesses from an untrusted master.
5823 * When this field is set and an access is attempted by an untrusted master, the
5824 * access terminates with an error response and no peripheral access initiates.
5827 * - 0 - Accesses from an untrusted master are allowed.
5828 * - 1 - Accesses from an untrusted master are not allowed.
5831 #define BP_AIPS_PACRH_TP7 (0U) /*!< Bit position for AIPS_PACRH_TP7. */
5832 #define BM_AIPS_PACRH_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRH_TP7. */
5833 #define BS_AIPS_PACRH_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRH_TP7. */
5835 /*! @brief Read current value of the AIPS_PACRH_TP7 field. */
5836 #define BR_AIPS_PACRH_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP7))
5838 /*! @brief Format value for bitfield AIPS_PACRH_TP7. */
5839 #define BF_AIPS_PACRH_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_TP7) & BM_AIPS_PACRH_TP7)
5841 /*! @brief Set the TP7 field to a new value. */
5842 #define BW_AIPS_PACRH_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP7) = (v))
5846 * @name Register AIPS_PACRH, field WP7[1] (RW)
5848 * Determines whether the peripheral allows write accesses. When this field is
5849 * set and a write access is attempted, access terminates with an error response
5850 * and no peripheral access initiates.
5853 * - 0 - This peripheral allows write accesses.
5854 * - 1 - This peripheral is write protected.
5857 #define BP_AIPS_PACRH_WP7 (1U) /*!< Bit position for AIPS_PACRH_WP7. */
5858 #define BM_AIPS_PACRH_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRH_WP7. */
5859 #define BS_AIPS_PACRH_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRH_WP7. */
5861 /*! @brief Read current value of the AIPS_PACRH_WP7 field. */
5862 #define BR_AIPS_PACRH_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP7))
5864 /*! @brief Format value for bitfield AIPS_PACRH_WP7. */
5865 #define BF_AIPS_PACRH_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_WP7) & BM_AIPS_PACRH_WP7)
5867 /*! @brief Set the WP7 field to a new value. */
5868 #define BW_AIPS_PACRH_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP7) = (v))
5872 * @name Register AIPS_PACRH, field SP7[2] (RW)
5874 * Determines whether the peripheral requires supervisor privilege level for
5875 * accesses. When this field is set, the master privilege level must indicate the
5876 * supervisor access attribute, and the MPRx[MPLn] control field for the master
5877 * must be set. If not, access terminates with an error response and no peripheral
5881 * - 0 - This peripheral does not require supervisor privilege level for
5883 * - 1 - This peripheral requires supervisor privilege level for accesses.
5886 #define BP_AIPS_PACRH_SP7 (2U) /*!< Bit position for AIPS_PACRH_SP7. */
5887 #define BM_AIPS_PACRH_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRH_SP7. */
5888 #define BS_AIPS_PACRH_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRH_SP7. */
5890 /*! @brief Read current value of the AIPS_PACRH_SP7 field. */
5891 #define BR_AIPS_PACRH_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP7))
5893 /*! @brief Format value for bitfield AIPS_PACRH_SP7. */
5894 #define BF_AIPS_PACRH_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_SP7) & BM_AIPS_PACRH_SP7)
5896 /*! @brief Set the SP7 field to a new value. */
5897 #define BW_AIPS_PACRH_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP7) = (v))
5901 * @name Register AIPS_PACRH, field TP6[4] (RW)
5903 * Determines whether the peripheral allows accesses from an untrusted master.
5904 * When this field is set and an access is attempted by an untrusted master, the
5905 * access terminates with an error response and no peripheral access initiates.
5908 * - 0 - Accesses from an untrusted master are allowed.
5909 * - 1 - Accesses from an untrusted master are not allowed.
5912 #define BP_AIPS_PACRH_TP6 (4U) /*!< Bit position for AIPS_PACRH_TP6. */
5913 #define BM_AIPS_PACRH_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRH_TP6. */
5914 #define BS_AIPS_PACRH_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRH_TP6. */
5916 /*! @brief Read current value of the AIPS_PACRH_TP6 field. */
5917 #define BR_AIPS_PACRH_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP6))
5919 /*! @brief Format value for bitfield AIPS_PACRH_TP6. */
5920 #define BF_AIPS_PACRH_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_TP6) & BM_AIPS_PACRH_TP6)
5922 /*! @brief Set the TP6 field to a new value. */
5923 #define BW_AIPS_PACRH_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP6) = (v))
5927 * @name Register AIPS_PACRH, field WP6[5] (RW)
5929 * Determines whether the peripheral allows write accesses. When this field is
5930 * set and a write access is attempted, access terminates with an error response
5931 * and no peripheral access initiates.
5934 * - 0 - This peripheral allows write accesses.
5935 * - 1 - This peripheral is write protected.
5938 #define BP_AIPS_PACRH_WP6 (5U) /*!< Bit position for AIPS_PACRH_WP6. */
5939 #define BM_AIPS_PACRH_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRH_WP6. */
5940 #define BS_AIPS_PACRH_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRH_WP6. */
5942 /*! @brief Read current value of the AIPS_PACRH_WP6 field. */
5943 #define BR_AIPS_PACRH_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP6))
5945 /*! @brief Format value for bitfield AIPS_PACRH_WP6. */
5946 #define BF_AIPS_PACRH_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_WP6) & BM_AIPS_PACRH_WP6)
5948 /*! @brief Set the WP6 field to a new value. */
5949 #define BW_AIPS_PACRH_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP6) = (v))
5953 * @name Register AIPS_PACRH, field SP6[6] (RW)
5955 * Determines whether the peripheral requires supervisor privilege level for
5956 * accesses. When this field is set, the master privilege level must indicate the
5957 * supervisor access attribute, and the MPRx[MPLn] control field for the master
5958 * must be set. If not, access terminates with an error response and no peripheral
5962 * - 0 - This peripheral does not require supervisor privilege level for
5964 * - 1 - This peripheral requires supervisor privilege level for accesses.
5967 #define BP_AIPS_PACRH_SP6 (6U) /*!< Bit position for AIPS_PACRH_SP6. */
5968 #define BM_AIPS_PACRH_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRH_SP6. */
5969 #define BS_AIPS_PACRH_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRH_SP6. */
5971 /*! @brief Read current value of the AIPS_PACRH_SP6 field. */
5972 #define BR_AIPS_PACRH_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP6))
5974 /*! @brief Format value for bitfield AIPS_PACRH_SP6. */
5975 #define BF_AIPS_PACRH_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_SP6) & BM_AIPS_PACRH_SP6)
5977 /*! @brief Set the SP6 field to a new value. */
5978 #define BW_AIPS_PACRH_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP6) = (v))
5982 * @name Register AIPS_PACRH, field TP5[8] (RW)
5984 * Determines whether the peripheral allows accesses from an untrusted master.
5985 * When this field is set and an access is attempted by an untrusted master, the
5986 * access terminates with an error response and no peripheral access initiates.
5989 * - 0 - Accesses from an untrusted master are allowed.
5990 * - 1 - Accesses from an untrusted master are not allowed.
5993 #define BP_AIPS_PACRH_TP5 (8U) /*!< Bit position for AIPS_PACRH_TP5. */
5994 #define BM_AIPS_PACRH_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRH_TP5. */
5995 #define BS_AIPS_PACRH_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRH_TP5. */
5997 /*! @brief Read current value of the AIPS_PACRH_TP5 field. */
5998 #define BR_AIPS_PACRH_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP5))
6000 /*! @brief Format value for bitfield AIPS_PACRH_TP5. */
6001 #define BF_AIPS_PACRH_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_TP5) & BM_AIPS_PACRH_TP5)
6003 /*! @brief Set the TP5 field to a new value. */
6004 #define BW_AIPS_PACRH_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP5) = (v))
6008 * @name Register AIPS_PACRH, field WP5[9] (RW)
6010 * Determines whether the peripheral allows write accesses. When this field is
6011 * set and a write access is attempted, access terminates with an error response
6012 * and no peripheral access initiates.
6015 * - 0 - This peripheral allows write accesses.
6016 * - 1 - This peripheral is write protected.
6019 #define BP_AIPS_PACRH_WP5 (9U) /*!< Bit position for AIPS_PACRH_WP5. */
6020 #define BM_AIPS_PACRH_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRH_WP5. */
6021 #define BS_AIPS_PACRH_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRH_WP5. */
6023 /*! @brief Read current value of the AIPS_PACRH_WP5 field. */
6024 #define BR_AIPS_PACRH_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP5))
6026 /*! @brief Format value for bitfield AIPS_PACRH_WP5. */
6027 #define BF_AIPS_PACRH_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_WP5) & BM_AIPS_PACRH_WP5)
6029 /*! @brief Set the WP5 field to a new value. */
6030 #define BW_AIPS_PACRH_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP5) = (v))
6034 * @name Register AIPS_PACRH, field SP5[10] (RW)
6036 * Determines whether the peripheral requires supervisor privilege level for
6037 * accesses. When this field is set, the master privilege level must indicate the
6038 * supervisor access attribute, and the MPRx[MPLn] control field for the master
6039 * must be set. If not, access terminates with an error response and no peripheral
6043 * - 0 - This peripheral does not require supervisor privilege level for
6045 * - 1 - This peripheral requires supervisor privilege level for accesses.
6048 #define BP_AIPS_PACRH_SP5 (10U) /*!< Bit position for AIPS_PACRH_SP5. */
6049 #define BM_AIPS_PACRH_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRH_SP5. */
6050 #define BS_AIPS_PACRH_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRH_SP5. */
6052 /*! @brief Read current value of the AIPS_PACRH_SP5 field. */
6053 #define BR_AIPS_PACRH_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP5))
6055 /*! @brief Format value for bitfield AIPS_PACRH_SP5. */
6056 #define BF_AIPS_PACRH_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_SP5) & BM_AIPS_PACRH_SP5)
6058 /*! @brief Set the SP5 field to a new value. */
6059 #define BW_AIPS_PACRH_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP5) = (v))
6063 * @name Register AIPS_PACRH, field TP4[12] (RW)
6065 * Determines whether the peripheral allows accesses from an untrusted master.
6066 * When this bit is set and an access is attempted by an untrusted master, the
6067 * access terminates with an error response and no peripheral access initiates.
6070 * - 0 - Accesses from an untrusted master are allowed.
6071 * - 1 - Accesses from an untrusted master are not allowed.
6074 #define BP_AIPS_PACRH_TP4 (12U) /*!< Bit position for AIPS_PACRH_TP4. */
6075 #define BM_AIPS_PACRH_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRH_TP4. */
6076 #define BS_AIPS_PACRH_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRH_TP4. */
6078 /*! @brief Read current value of the AIPS_PACRH_TP4 field. */
6079 #define BR_AIPS_PACRH_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP4))
6081 /*! @brief Format value for bitfield AIPS_PACRH_TP4. */
6082 #define BF_AIPS_PACRH_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_TP4) & BM_AIPS_PACRH_TP4)
6084 /*! @brief Set the TP4 field to a new value. */
6085 #define BW_AIPS_PACRH_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP4) = (v))
6089 * @name Register AIPS_PACRH, field WP4[13] (RW)
6091 * Determines whether the peripheral allows write accesses. When this field is
6092 * set and a write access is attempted, access terminates with an error response
6093 * and no peripheral access initiates.
6096 * - 0 - This peripheral allows write accesses.
6097 * - 1 - This peripheral is write protected.
6100 #define BP_AIPS_PACRH_WP4 (13U) /*!< Bit position for AIPS_PACRH_WP4. */
6101 #define BM_AIPS_PACRH_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRH_WP4. */
6102 #define BS_AIPS_PACRH_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRH_WP4. */
6104 /*! @brief Read current value of the AIPS_PACRH_WP4 field. */
6105 #define BR_AIPS_PACRH_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP4))
6107 /*! @brief Format value for bitfield AIPS_PACRH_WP4. */
6108 #define BF_AIPS_PACRH_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_WP4) & BM_AIPS_PACRH_WP4)
6110 /*! @brief Set the WP4 field to a new value. */
6111 #define BW_AIPS_PACRH_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP4) = (v))
6115 * @name Register AIPS_PACRH, field SP4[14] (RW)
6117 * Determines whether the peripheral requires supervisor privilege level for
6118 * access. When this bit is set, the master privilege level must indicate the
6119 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
6120 * set. If not, access terminates with an error response and no peripheral access
6124 * - 0 - This peripheral does not require supervisor privilege level for
6126 * - 1 - This peripheral requires supervisor privilege level for accesses.
6129 #define BP_AIPS_PACRH_SP4 (14U) /*!< Bit position for AIPS_PACRH_SP4. */
6130 #define BM_AIPS_PACRH_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRH_SP4. */
6131 #define BS_AIPS_PACRH_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRH_SP4. */
6133 /*! @brief Read current value of the AIPS_PACRH_SP4 field. */
6134 #define BR_AIPS_PACRH_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP4))
6136 /*! @brief Format value for bitfield AIPS_PACRH_SP4. */
6137 #define BF_AIPS_PACRH_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_SP4) & BM_AIPS_PACRH_SP4)
6139 /*! @brief Set the SP4 field to a new value. */
6140 #define BW_AIPS_PACRH_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP4) = (v))
6144 * @name Register AIPS_PACRH, field TP3[16] (RW)
6146 * Determines whether the peripheral allows accesses from an untrusted master.
6147 * When this field is set and an access is attempted by an untrusted master, the
6148 * access terminates with an error response and no peripheral access initiates.
6151 * - 0 - Accesses from an untrusted master are allowed.
6152 * - 1 - Accesses from an untrusted master are not allowed.
6155 #define BP_AIPS_PACRH_TP3 (16U) /*!< Bit position for AIPS_PACRH_TP3. */
6156 #define BM_AIPS_PACRH_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRH_TP3. */
6157 #define BS_AIPS_PACRH_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRH_TP3. */
6159 /*! @brief Read current value of the AIPS_PACRH_TP3 field. */
6160 #define BR_AIPS_PACRH_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP3))
6162 /*! @brief Format value for bitfield AIPS_PACRH_TP3. */
6163 #define BF_AIPS_PACRH_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_TP3) & BM_AIPS_PACRH_TP3)
6165 /*! @brief Set the TP3 field to a new value. */
6166 #define BW_AIPS_PACRH_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP3) = (v))
6170 * @name Register AIPS_PACRH, field WP3[17] (RW)
6172 * Determines whether the peripheral allows write accesss. When this bit is set
6173 * and a write access is attempted, access terminates with an error response and
6174 * no peripheral access initiates.
6177 * - 0 - This peripheral allows write accesses.
6178 * - 1 - This peripheral is write protected.
6181 #define BP_AIPS_PACRH_WP3 (17U) /*!< Bit position for AIPS_PACRH_WP3. */
6182 #define BM_AIPS_PACRH_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRH_WP3. */
6183 #define BS_AIPS_PACRH_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRH_WP3. */
6185 /*! @brief Read current value of the AIPS_PACRH_WP3 field. */
6186 #define BR_AIPS_PACRH_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP3))
6188 /*! @brief Format value for bitfield AIPS_PACRH_WP3. */
6189 #define BF_AIPS_PACRH_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_WP3) & BM_AIPS_PACRH_WP3)
6191 /*! @brief Set the WP3 field to a new value. */
6192 #define BW_AIPS_PACRH_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP3) = (v))
6196 * @name Register AIPS_PACRH, field SP3[18] (RW)
6198 * Determines whether the peripheral requires supervisor privilege level for
6199 * accesses. When this field is set, the master privilege level must indicate the
6200 * supervisor access attribute, and the MPRx[MPLn] control field for the master
6201 * must be set. If not, access terminates with an error response and no peripheral
6205 * - 0 - This peripheral does not require supervisor privilege level for
6207 * - 1 - This peripheral requires supervisor privilege level for accesses.
6210 #define BP_AIPS_PACRH_SP3 (18U) /*!< Bit position for AIPS_PACRH_SP3. */
6211 #define BM_AIPS_PACRH_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRH_SP3. */
6212 #define BS_AIPS_PACRH_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRH_SP3. */
6214 /*! @brief Read current value of the AIPS_PACRH_SP3 field. */
6215 #define BR_AIPS_PACRH_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP3))
6217 /*! @brief Format value for bitfield AIPS_PACRH_SP3. */
6218 #define BF_AIPS_PACRH_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_SP3) & BM_AIPS_PACRH_SP3)
6220 /*! @brief Set the SP3 field to a new value. */
6221 #define BW_AIPS_PACRH_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP3) = (v))
6225 * @name Register AIPS_PACRH, field TP2[20] (RW)
6227 * Determines whether the peripheral allows accesses from an untrusted master.
6228 * When this bit is set and an access is attempted by an untrusted master, the
6229 * access terminates with an error response and no peripheral access initiates.
6232 * - 0 - Accesses from an untrusted master are allowed.
6233 * - 1 - Accesses from an untrusted master are not allowed.
6236 #define BP_AIPS_PACRH_TP2 (20U) /*!< Bit position for AIPS_PACRH_TP2. */
6237 #define BM_AIPS_PACRH_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRH_TP2. */
6238 #define BS_AIPS_PACRH_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRH_TP2. */
6240 /*! @brief Read current value of the AIPS_PACRH_TP2 field. */
6241 #define BR_AIPS_PACRH_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP2))
6243 /*! @brief Format value for bitfield AIPS_PACRH_TP2. */
6244 #define BF_AIPS_PACRH_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_TP2) & BM_AIPS_PACRH_TP2)
6246 /*! @brief Set the TP2 field to a new value. */
6247 #define BW_AIPS_PACRH_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP2) = (v))
6251 * @name Register AIPS_PACRH, field WP2[21] (RW)
6253 * Determines whether the peripheral allows write accesses. When this field is
6254 * set and a write access is attempted, access terminates with an error response
6255 * and no peripheral access initiates.
6258 * - 0 - This peripheral allows write accesses.
6259 * - 1 - This peripheral is write protected.
6262 #define BP_AIPS_PACRH_WP2 (21U) /*!< Bit position for AIPS_PACRH_WP2. */
6263 #define BM_AIPS_PACRH_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRH_WP2. */
6264 #define BS_AIPS_PACRH_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRH_WP2. */
6266 /*! @brief Read current value of the AIPS_PACRH_WP2 field. */
6267 #define BR_AIPS_PACRH_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP2))
6269 /*! @brief Format value for bitfield AIPS_PACRH_WP2. */
6270 #define BF_AIPS_PACRH_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_WP2) & BM_AIPS_PACRH_WP2)
6272 /*! @brief Set the WP2 field to a new value. */
6273 #define BW_AIPS_PACRH_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP2) = (v))
6277 * @name Register AIPS_PACRH, field SP2[22] (RW)
6279 * Determines whether the peripheral requires supervisor privilege level for
6280 * access. When this bit is set, the master privilege level must indicate the
6281 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
6282 * set. If not, access terminates with an error response and no peripheral access
6286 * - 0 - This peripheral does not require supervisor privilege level for
6288 * - 1 - This peripheral requires supervisor privilege level for accesses.
6291 #define BP_AIPS_PACRH_SP2 (22U) /*!< Bit position for AIPS_PACRH_SP2. */
6292 #define BM_AIPS_PACRH_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRH_SP2. */
6293 #define BS_AIPS_PACRH_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRH_SP2. */
6295 /*! @brief Read current value of the AIPS_PACRH_SP2 field. */
6296 #define BR_AIPS_PACRH_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP2))
6298 /*! @brief Format value for bitfield AIPS_PACRH_SP2. */
6299 #define BF_AIPS_PACRH_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_SP2) & BM_AIPS_PACRH_SP2)
6301 /*! @brief Set the SP2 field to a new value. */
6302 #define BW_AIPS_PACRH_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP2) = (v))
6306 * @name Register AIPS_PACRH, field TP1[24] (RW)
6308 * Determines whether the peripheral allows accesses from an untrusted master.
6309 * When this field is set and an access is attempted by an untrusted master, the
6310 * access terminates with an error response and no peripheral access initiates.
6313 * - 0 - Accesses from an untrusted master are allowed.
6314 * - 1 - Accesses from an untrusted master are not allowed.
6317 #define BP_AIPS_PACRH_TP1 (24U) /*!< Bit position for AIPS_PACRH_TP1. */
6318 #define BM_AIPS_PACRH_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRH_TP1. */
6319 #define BS_AIPS_PACRH_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRH_TP1. */
6321 /*! @brief Read current value of the AIPS_PACRH_TP1 field. */
6322 #define BR_AIPS_PACRH_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP1))
6324 /*! @brief Format value for bitfield AIPS_PACRH_TP1. */
6325 #define BF_AIPS_PACRH_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_TP1) & BM_AIPS_PACRH_TP1)
6327 /*! @brief Set the TP1 field to a new value. */
6328 #define BW_AIPS_PACRH_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP1) = (v))
6332 * @name Register AIPS_PACRH, field WP1[25] (RW)
6334 * Determines whether the peripheral allows write accesses. When this field is
6335 * set and a write access is attempted, access terminates with an error response
6336 * and no peripheral access initiates.
6339 * - 0 - This peripheral allows write accesses.
6340 * - 1 - This peripheral is write protected.
6343 #define BP_AIPS_PACRH_WP1 (25U) /*!< Bit position for AIPS_PACRH_WP1. */
6344 #define BM_AIPS_PACRH_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRH_WP1. */
6345 #define BS_AIPS_PACRH_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRH_WP1. */
6347 /*! @brief Read current value of the AIPS_PACRH_WP1 field. */
6348 #define BR_AIPS_PACRH_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP1))
6350 /*! @brief Format value for bitfield AIPS_PACRH_WP1. */
6351 #define BF_AIPS_PACRH_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_WP1) & BM_AIPS_PACRH_WP1)
6353 /*! @brief Set the WP1 field to a new value. */
6354 #define BW_AIPS_PACRH_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP1) = (v))
6358 * @name Register AIPS_PACRH, field SP1[26] (RW)
6360 * Determines whether the peripheral requires supervisor privilege level for
6361 * access. When this field is set, the master privilege level must indicate the
6362 * supervisor access attribute, and the MPRx[MPLn] control field for the master must
6363 * be set. If not, access terminates with an error response and no peripheral
6367 * - 0 - This peripheral does not require supervisor privilege level for
6369 * - 1 - This peripheral requires supervisor privilege level for accesses.
6372 #define BP_AIPS_PACRH_SP1 (26U) /*!< Bit position for AIPS_PACRH_SP1. */
6373 #define BM_AIPS_PACRH_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRH_SP1. */
6374 #define BS_AIPS_PACRH_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRH_SP1. */
6376 /*! @brief Read current value of the AIPS_PACRH_SP1 field. */
6377 #define BR_AIPS_PACRH_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP1))
6379 /*! @brief Format value for bitfield AIPS_PACRH_SP1. */
6380 #define BF_AIPS_PACRH_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_SP1) & BM_AIPS_PACRH_SP1)
6382 /*! @brief Set the SP1 field to a new value. */
6383 #define BW_AIPS_PACRH_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP1) = (v))
6387 * @name Register AIPS_PACRH, field TP0[28] (RW)
6389 * Determines whether the peripheral allows accesses from an untrusted master.
6390 * When this bit is set and an access is attempted by an untrusted master, the
6391 * access terminates with an error response and no peripheral access initiates.
6394 * - 0 - Accesses from an untrusted master are allowed.
6395 * - 1 - Accesses from an untrusted master are not allowed.
6398 #define BP_AIPS_PACRH_TP0 (28U) /*!< Bit position for AIPS_PACRH_TP0. */
6399 #define BM_AIPS_PACRH_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRH_TP0. */
6400 #define BS_AIPS_PACRH_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRH_TP0. */
6402 /*! @brief Read current value of the AIPS_PACRH_TP0 field. */
6403 #define BR_AIPS_PACRH_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP0))
6405 /*! @brief Format value for bitfield AIPS_PACRH_TP0. */
6406 #define BF_AIPS_PACRH_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_TP0) & BM_AIPS_PACRH_TP0)
6408 /*! @brief Set the TP0 field to a new value. */
6409 #define BW_AIPS_PACRH_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP0) = (v))
6413 * @name Register AIPS_PACRH, field WP0[29] (RW)
6415 * Determines whether the peripheral allows write accesses. When this field is
6416 * set and a write access is attempted, access terminates with an error response
6417 * and no peripheral access initiates.
6420 * - 0 - This peripheral allows write accesses.
6421 * - 1 - This peripheral is write protected.
6424 #define BP_AIPS_PACRH_WP0 (29U) /*!< Bit position for AIPS_PACRH_WP0. */
6425 #define BM_AIPS_PACRH_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRH_WP0. */
6426 #define BS_AIPS_PACRH_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRH_WP0. */
6428 /*! @brief Read current value of the AIPS_PACRH_WP0 field. */
6429 #define BR_AIPS_PACRH_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP0))
6431 /*! @brief Format value for bitfield AIPS_PACRH_WP0. */
6432 #define BF_AIPS_PACRH_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_WP0) & BM_AIPS_PACRH_WP0)
6434 /*! @brief Set the WP0 field to a new value. */
6435 #define BW_AIPS_PACRH_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP0) = (v))
6439 * @name Register AIPS_PACRH, field SP0[30] (RW)
6441 * Determines whether the peripheral requires supervisor privilege level for
6442 * accesses. When this field is set, the master privilege level must indicate the
6443 * supervisor access attribute, and the MPRx[MPLn] control field for the master
6444 * must be set. If not, access terminates with an error response and no peripheral
6448 * - 0 - This peripheral does not require supervisor privilege level for
6450 * - 1 - This peripheral requires supervisor privilege level for accesses.
6453 #define BP_AIPS_PACRH_SP0 (30U) /*!< Bit position for AIPS_PACRH_SP0. */
6454 #define BM_AIPS_PACRH_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRH_SP0. */
6455 #define BS_AIPS_PACRH_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRH_SP0. */
6457 /*! @brief Read current value of the AIPS_PACRH_SP0 field. */
6458 #define BR_AIPS_PACRH_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP0))
6460 /*! @brief Format value for bitfield AIPS_PACRH_SP0. */
6461 #define BF_AIPS_PACRH_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_SP0) & BM_AIPS_PACRH_SP0)
6463 /*! @brief Set the SP0 field to a new value. */
6464 #define BW_AIPS_PACRH_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP0) = (v))
6467 /*******************************************************************************
6468 * HW_AIPS_PACRI - Peripheral Access Control Register
6469 ******************************************************************************/
6472 * @brief HW_AIPS_PACRI - Peripheral Access Control Register (RW)
6474 * Reset value: 0x44444444U
6476 * This section describes PACR registers E-P, which control peripheral slots
6477 * 32-127. See PACRPeripheral Access Control Register for the description of these
6480 typedef union _hw_aips_pacri
6483 struct _hw_aips_pacri_bitfields
6485 uint32_t TP7
: 1; /*!< [0] Trusted Protect */
6486 uint32_t WP7
: 1; /*!< [1] Write Protect */
6487 uint32_t SP7
: 1; /*!< [2] Supervisor Protect */
6488 uint32_t RESERVED0
: 1; /*!< [3] */
6489 uint32_t TP6
: 1; /*!< [4] Trusted Protect */
6490 uint32_t WP6
: 1; /*!< [5] Write Protect */
6491 uint32_t SP6
: 1; /*!< [6] Supervisor Protect */
6492 uint32_t RESERVED1
: 1; /*!< [7] */
6493 uint32_t TP5
: 1; /*!< [8] Trusted Protect */
6494 uint32_t WP5
: 1; /*!< [9] Write Protect */
6495 uint32_t SP5
: 1; /*!< [10] Supervisor Protect */
6496 uint32_t RESERVED2
: 1; /*!< [11] */
6497 uint32_t TP4
: 1; /*!< [12] Trusted Protect */
6498 uint32_t WP4
: 1; /*!< [13] Write Protect */
6499 uint32_t SP4
: 1; /*!< [14] Supervisor Protect */
6500 uint32_t RESERVED3
: 1; /*!< [15] */
6501 uint32_t TP3
: 1; /*!< [16] Trusted Protect */
6502 uint32_t WP3
: 1; /*!< [17] Write Protect */
6503 uint32_t SP3
: 1; /*!< [18] Supervisor Protect */
6504 uint32_t RESERVED4
: 1; /*!< [19] */
6505 uint32_t TP2
: 1; /*!< [20] Trusted Protect */
6506 uint32_t WP2
: 1; /*!< [21] Write Protect */
6507 uint32_t SP2
: 1; /*!< [22] Supervisor Protect */
6508 uint32_t RESERVED5
: 1; /*!< [23] */
6509 uint32_t TP1
: 1; /*!< [24] Trusted Protect */
6510 uint32_t WP1
: 1; /*!< [25] Write Protect */
6511 uint32_t SP1
: 1; /*!< [26] Supervisor Protect */
6512 uint32_t RESERVED6
: 1; /*!< [27] */
6513 uint32_t TP0
: 1; /*!< [28] Trusted Protect */
6514 uint32_t WP0
: 1; /*!< [29] Write Protect */
6515 uint32_t SP0
: 1; /*!< [30] Supervisor Protect */
6516 uint32_t RESERVED7
: 1; /*!< [31] */
6521 * @name Constants and macros for entire AIPS_PACRI register
6524 #define HW_AIPS_PACRI_ADDR(x) ((x) + 0x50U)
6526 #define HW_AIPS_PACRI(x) (*(__IO hw_aips_pacri_t *) HW_AIPS_PACRI_ADDR(x))
6527 #define HW_AIPS_PACRI_RD(x) (HW_AIPS_PACRI(x).U)
6528 #define HW_AIPS_PACRI_WR(x, v) (HW_AIPS_PACRI(x).U = (v))
6529 #define HW_AIPS_PACRI_SET(x, v) (HW_AIPS_PACRI_WR(x, HW_AIPS_PACRI_RD(x) | (v)))
6530 #define HW_AIPS_PACRI_CLR(x, v) (HW_AIPS_PACRI_WR(x, HW_AIPS_PACRI_RD(x) & ~(v)))
6531 #define HW_AIPS_PACRI_TOG(x, v) (HW_AIPS_PACRI_WR(x, HW_AIPS_PACRI_RD(x) ^ (v)))
6535 * Constants & macros for individual AIPS_PACRI bitfields
6539 * @name Register AIPS_PACRI, field TP7[0] (RW)
6541 * Determines whether the peripheral allows accesses from an untrusted master.
6542 * When this field is set and an access is attempted by an untrusted master, the
6543 * access terminates with an error response and no peripheral access initiates.
6546 * - 0 - Accesses from an untrusted master are allowed.
6547 * - 1 - Accesses from an untrusted master are not allowed.
6550 #define BP_AIPS_PACRI_TP7 (0U) /*!< Bit position for AIPS_PACRI_TP7. */
6551 #define BM_AIPS_PACRI_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRI_TP7. */
6552 #define BS_AIPS_PACRI_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRI_TP7. */
6554 /*! @brief Read current value of the AIPS_PACRI_TP7 field. */
6555 #define BR_AIPS_PACRI_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP7))
6557 /*! @brief Format value for bitfield AIPS_PACRI_TP7. */
6558 #define BF_AIPS_PACRI_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_TP7) & BM_AIPS_PACRI_TP7)
6560 /*! @brief Set the TP7 field to a new value. */
6561 #define BW_AIPS_PACRI_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP7) = (v))
6565 * @name Register AIPS_PACRI, field WP7[1] (RW)
6567 * Determines whether the peripheral allows write accesses. When this field is
6568 * set and a write access is attempted, access terminates with an error response
6569 * and no peripheral access initiates.
6572 * - 0 - This peripheral allows write accesses.
6573 * - 1 - This peripheral is write protected.
6576 #define BP_AIPS_PACRI_WP7 (1U) /*!< Bit position for AIPS_PACRI_WP7. */
6577 #define BM_AIPS_PACRI_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRI_WP7. */
6578 #define BS_AIPS_PACRI_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRI_WP7. */
6580 /*! @brief Read current value of the AIPS_PACRI_WP7 field. */
6581 #define BR_AIPS_PACRI_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP7))
6583 /*! @brief Format value for bitfield AIPS_PACRI_WP7. */
6584 #define BF_AIPS_PACRI_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_WP7) & BM_AIPS_PACRI_WP7)
6586 /*! @brief Set the WP7 field to a new value. */
6587 #define BW_AIPS_PACRI_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP7) = (v))
6591 * @name Register AIPS_PACRI, field SP7[2] (RW)
6593 * Determines whether the peripheral requires supervisor privilege level for
6594 * accesses. When this field is set, the master privilege level must indicate the
6595 * supervisor access attribute, and the MPRx[MPLn] control field for the master
6596 * must be set. If not, access terminates with an error response and no peripheral
6600 * - 0 - This peripheral does not require supervisor privilege level for
6602 * - 1 - This peripheral requires supervisor privilege level for accesses.
6605 #define BP_AIPS_PACRI_SP7 (2U) /*!< Bit position for AIPS_PACRI_SP7. */
6606 #define BM_AIPS_PACRI_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRI_SP7. */
6607 #define BS_AIPS_PACRI_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRI_SP7. */
6609 /*! @brief Read current value of the AIPS_PACRI_SP7 field. */
6610 #define BR_AIPS_PACRI_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP7))
6612 /*! @brief Format value for bitfield AIPS_PACRI_SP7. */
6613 #define BF_AIPS_PACRI_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_SP7) & BM_AIPS_PACRI_SP7)
6615 /*! @brief Set the SP7 field to a new value. */
6616 #define BW_AIPS_PACRI_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP7) = (v))
6620 * @name Register AIPS_PACRI, field TP6[4] (RW)
6622 * Determines whether the peripheral allows accesses from an untrusted master.
6623 * When this field is set and an access is attempted by an untrusted master, the
6624 * access terminates with an error response and no peripheral access initiates.
6627 * - 0 - Accesses from an untrusted master are allowed.
6628 * - 1 - Accesses from an untrusted master are not allowed.
6631 #define BP_AIPS_PACRI_TP6 (4U) /*!< Bit position for AIPS_PACRI_TP6. */
6632 #define BM_AIPS_PACRI_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRI_TP6. */
6633 #define BS_AIPS_PACRI_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRI_TP6. */
6635 /*! @brief Read current value of the AIPS_PACRI_TP6 field. */
6636 #define BR_AIPS_PACRI_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP6))
6638 /*! @brief Format value for bitfield AIPS_PACRI_TP6. */
6639 #define BF_AIPS_PACRI_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_TP6) & BM_AIPS_PACRI_TP6)
6641 /*! @brief Set the TP6 field to a new value. */
6642 #define BW_AIPS_PACRI_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP6) = (v))
6646 * @name Register AIPS_PACRI, field WP6[5] (RW)
6648 * Determines whether the peripheral allows write accesses. When this field is
6649 * set and a write access is attempted, access terminates with an error response
6650 * and no peripheral access initiates.
6653 * - 0 - This peripheral allows write accesses.
6654 * - 1 - This peripheral is write protected.
6657 #define BP_AIPS_PACRI_WP6 (5U) /*!< Bit position for AIPS_PACRI_WP6. */
6658 #define BM_AIPS_PACRI_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRI_WP6. */
6659 #define BS_AIPS_PACRI_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRI_WP6. */
6661 /*! @brief Read current value of the AIPS_PACRI_WP6 field. */
6662 #define BR_AIPS_PACRI_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP6))
6664 /*! @brief Format value for bitfield AIPS_PACRI_WP6. */
6665 #define BF_AIPS_PACRI_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_WP6) & BM_AIPS_PACRI_WP6)
6667 /*! @brief Set the WP6 field to a new value. */
6668 #define BW_AIPS_PACRI_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP6) = (v))
6672 * @name Register AIPS_PACRI, field SP6[6] (RW)
6674 * Determines whether the peripheral requires supervisor privilege level for
6675 * accesses. When this field is set, the master privilege level must indicate the
6676 * supervisor access attribute, and the MPRx[MPLn] control field for the master
6677 * must be set. If not, access terminates with an error response and no peripheral
6681 * - 0 - This peripheral does not require supervisor privilege level for
6683 * - 1 - This peripheral requires supervisor privilege level for accesses.
6686 #define BP_AIPS_PACRI_SP6 (6U) /*!< Bit position for AIPS_PACRI_SP6. */
6687 #define BM_AIPS_PACRI_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRI_SP6. */
6688 #define BS_AIPS_PACRI_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRI_SP6. */
6690 /*! @brief Read current value of the AIPS_PACRI_SP6 field. */
6691 #define BR_AIPS_PACRI_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP6))
6693 /*! @brief Format value for bitfield AIPS_PACRI_SP6. */
6694 #define BF_AIPS_PACRI_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_SP6) & BM_AIPS_PACRI_SP6)
6696 /*! @brief Set the SP6 field to a new value. */
6697 #define BW_AIPS_PACRI_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP6) = (v))
6701 * @name Register AIPS_PACRI, field TP5[8] (RW)
6703 * Determines whether the peripheral allows accesses from an untrusted master.
6704 * When this field is set and an access is attempted by an untrusted master, the
6705 * access terminates with an error response and no peripheral access initiates.
6708 * - 0 - Accesses from an untrusted master are allowed.
6709 * - 1 - Accesses from an untrusted master are not allowed.
6712 #define BP_AIPS_PACRI_TP5 (8U) /*!< Bit position for AIPS_PACRI_TP5. */
6713 #define BM_AIPS_PACRI_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRI_TP5. */
6714 #define BS_AIPS_PACRI_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRI_TP5. */
6716 /*! @brief Read current value of the AIPS_PACRI_TP5 field. */
6717 #define BR_AIPS_PACRI_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP5))
6719 /*! @brief Format value for bitfield AIPS_PACRI_TP5. */
6720 #define BF_AIPS_PACRI_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_TP5) & BM_AIPS_PACRI_TP5)
6722 /*! @brief Set the TP5 field to a new value. */
6723 #define BW_AIPS_PACRI_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP5) = (v))
6727 * @name Register AIPS_PACRI, field WP5[9] (RW)
6729 * Determines whether the peripheral allows write accesses. When this field is
6730 * set and a write access is attempted, access terminates with an error response
6731 * and no peripheral access initiates.
6734 * - 0 - This peripheral allows write accesses.
6735 * - 1 - This peripheral is write protected.
6738 #define BP_AIPS_PACRI_WP5 (9U) /*!< Bit position for AIPS_PACRI_WP5. */
6739 #define BM_AIPS_PACRI_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRI_WP5. */
6740 #define BS_AIPS_PACRI_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRI_WP5. */
6742 /*! @brief Read current value of the AIPS_PACRI_WP5 field. */
6743 #define BR_AIPS_PACRI_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP5))
6745 /*! @brief Format value for bitfield AIPS_PACRI_WP5. */
6746 #define BF_AIPS_PACRI_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_WP5) & BM_AIPS_PACRI_WP5)
6748 /*! @brief Set the WP5 field to a new value. */
6749 #define BW_AIPS_PACRI_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP5) = (v))
6753 * @name Register AIPS_PACRI, field SP5[10] (RW)
6755 * Determines whether the peripheral requires supervisor privilege level for
6756 * accesses. When this field is set, the master privilege level must indicate the
6757 * supervisor access attribute, and the MPRx[MPLn] control field for the master
6758 * must be set. If not, access terminates with an error response and no peripheral
6762 * - 0 - This peripheral does not require supervisor privilege level for
6764 * - 1 - This peripheral requires supervisor privilege level for accesses.
6767 #define BP_AIPS_PACRI_SP5 (10U) /*!< Bit position for AIPS_PACRI_SP5. */
6768 #define BM_AIPS_PACRI_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRI_SP5. */
6769 #define BS_AIPS_PACRI_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRI_SP5. */
6771 /*! @brief Read current value of the AIPS_PACRI_SP5 field. */
6772 #define BR_AIPS_PACRI_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP5))
6774 /*! @brief Format value for bitfield AIPS_PACRI_SP5. */
6775 #define BF_AIPS_PACRI_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_SP5) & BM_AIPS_PACRI_SP5)
6777 /*! @brief Set the SP5 field to a new value. */
6778 #define BW_AIPS_PACRI_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP5) = (v))
6782 * @name Register AIPS_PACRI, field TP4[12] (RW)
6784 * Determines whether the peripheral allows accesses from an untrusted master.
6785 * When this bit is set and an access is attempted by an untrusted master, the
6786 * access terminates with an error response and no peripheral access initiates.
6789 * - 0 - Accesses from an untrusted master are allowed.
6790 * - 1 - Accesses from an untrusted master are not allowed.
6793 #define BP_AIPS_PACRI_TP4 (12U) /*!< Bit position for AIPS_PACRI_TP4. */
6794 #define BM_AIPS_PACRI_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRI_TP4. */
6795 #define BS_AIPS_PACRI_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRI_TP4. */
6797 /*! @brief Read current value of the AIPS_PACRI_TP4 field. */
6798 #define BR_AIPS_PACRI_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP4))
6800 /*! @brief Format value for bitfield AIPS_PACRI_TP4. */
6801 #define BF_AIPS_PACRI_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_TP4) & BM_AIPS_PACRI_TP4)
6803 /*! @brief Set the TP4 field to a new value. */
6804 #define BW_AIPS_PACRI_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP4) = (v))
6808 * @name Register AIPS_PACRI, field WP4[13] (RW)
6810 * Determines whether the peripheral allows write accesses. When this field is
6811 * set and a write access is attempted, access terminates with an error response
6812 * and no peripheral access initiates.
6815 * - 0 - This peripheral allows write accesses.
6816 * - 1 - This peripheral is write protected.
6819 #define BP_AIPS_PACRI_WP4 (13U) /*!< Bit position for AIPS_PACRI_WP4. */
6820 #define BM_AIPS_PACRI_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRI_WP4. */
6821 #define BS_AIPS_PACRI_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRI_WP4. */
6823 /*! @brief Read current value of the AIPS_PACRI_WP4 field. */
6824 #define BR_AIPS_PACRI_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP4))
6826 /*! @brief Format value for bitfield AIPS_PACRI_WP4. */
6827 #define BF_AIPS_PACRI_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_WP4) & BM_AIPS_PACRI_WP4)
6829 /*! @brief Set the WP4 field to a new value. */
6830 #define BW_AIPS_PACRI_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP4) = (v))
6834 * @name Register AIPS_PACRI, field SP4[14] (RW)
6836 * Determines whether the peripheral requires supervisor privilege level for
6837 * access. When this bit is set, the master privilege level must indicate the
6838 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
6839 * set. If not, access terminates with an error response and no peripheral access
6843 * - 0 - This peripheral does not require supervisor privilege level for
6845 * - 1 - This peripheral requires supervisor privilege level for accesses.
6848 #define BP_AIPS_PACRI_SP4 (14U) /*!< Bit position for AIPS_PACRI_SP4. */
6849 #define BM_AIPS_PACRI_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRI_SP4. */
6850 #define BS_AIPS_PACRI_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRI_SP4. */
6852 /*! @brief Read current value of the AIPS_PACRI_SP4 field. */
6853 #define BR_AIPS_PACRI_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP4))
6855 /*! @brief Format value for bitfield AIPS_PACRI_SP4. */
6856 #define BF_AIPS_PACRI_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_SP4) & BM_AIPS_PACRI_SP4)
6858 /*! @brief Set the SP4 field to a new value. */
6859 #define BW_AIPS_PACRI_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP4) = (v))
6863 * @name Register AIPS_PACRI, field TP3[16] (RW)
6865 * Determines whether the peripheral allows accesses from an untrusted master.
6866 * When this field is set and an access is attempted by an untrusted master, the
6867 * access terminates with an error response and no peripheral access initiates.
6870 * - 0 - Accesses from an untrusted master are allowed.
6871 * - 1 - Accesses from an untrusted master are not allowed.
6874 #define BP_AIPS_PACRI_TP3 (16U) /*!< Bit position for AIPS_PACRI_TP3. */
6875 #define BM_AIPS_PACRI_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRI_TP3. */
6876 #define BS_AIPS_PACRI_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRI_TP3. */
6878 /*! @brief Read current value of the AIPS_PACRI_TP3 field. */
6879 #define BR_AIPS_PACRI_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP3))
6881 /*! @brief Format value for bitfield AIPS_PACRI_TP3. */
6882 #define BF_AIPS_PACRI_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_TP3) & BM_AIPS_PACRI_TP3)
6884 /*! @brief Set the TP3 field to a new value. */
6885 #define BW_AIPS_PACRI_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP3) = (v))
6889 * @name Register AIPS_PACRI, field WP3[17] (RW)
6891 * Determines whether the peripheral allows write accesss. When this bit is set
6892 * and a write access is attempted, access terminates with an error response and
6893 * no peripheral access initiates.
6896 * - 0 - This peripheral allows write accesses.
6897 * - 1 - This peripheral is write protected.
6900 #define BP_AIPS_PACRI_WP3 (17U) /*!< Bit position for AIPS_PACRI_WP3. */
6901 #define BM_AIPS_PACRI_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRI_WP3. */
6902 #define BS_AIPS_PACRI_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRI_WP3. */
6904 /*! @brief Read current value of the AIPS_PACRI_WP3 field. */
6905 #define BR_AIPS_PACRI_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP3))
6907 /*! @brief Format value for bitfield AIPS_PACRI_WP3. */
6908 #define BF_AIPS_PACRI_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_WP3) & BM_AIPS_PACRI_WP3)
6910 /*! @brief Set the WP3 field to a new value. */
6911 #define BW_AIPS_PACRI_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP3) = (v))
6915 * @name Register AIPS_PACRI, field SP3[18] (RW)
6917 * Determines whether the peripheral requires supervisor privilege level for
6918 * accesses. When this field is set, the master privilege level must indicate the
6919 * supervisor access attribute, and the MPRx[MPLn] control field for the master
6920 * must be set. If not, access terminates with an error response and no peripheral
6924 * - 0 - This peripheral does not require supervisor privilege level for
6926 * - 1 - This peripheral requires supervisor privilege level for accesses.
6929 #define BP_AIPS_PACRI_SP3 (18U) /*!< Bit position for AIPS_PACRI_SP3. */
6930 #define BM_AIPS_PACRI_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRI_SP3. */
6931 #define BS_AIPS_PACRI_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRI_SP3. */
6933 /*! @brief Read current value of the AIPS_PACRI_SP3 field. */
6934 #define BR_AIPS_PACRI_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP3))
6936 /*! @brief Format value for bitfield AIPS_PACRI_SP3. */
6937 #define BF_AIPS_PACRI_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_SP3) & BM_AIPS_PACRI_SP3)
6939 /*! @brief Set the SP3 field to a new value. */
6940 #define BW_AIPS_PACRI_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP3) = (v))
6944 * @name Register AIPS_PACRI, field TP2[20] (RW)
6946 * Determines whether the peripheral allows accesses from an untrusted master.
6947 * When this bit is set and an access is attempted by an untrusted master, the
6948 * access terminates with an error response and no peripheral access initiates.
6951 * - 0 - Accesses from an untrusted master are allowed.
6952 * - 1 - Accesses from an untrusted master are not allowed.
6955 #define BP_AIPS_PACRI_TP2 (20U) /*!< Bit position for AIPS_PACRI_TP2. */
6956 #define BM_AIPS_PACRI_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRI_TP2. */
6957 #define BS_AIPS_PACRI_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRI_TP2. */
6959 /*! @brief Read current value of the AIPS_PACRI_TP2 field. */
6960 #define BR_AIPS_PACRI_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP2))
6962 /*! @brief Format value for bitfield AIPS_PACRI_TP2. */
6963 #define BF_AIPS_PACRI_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_TP2) & BM_AIPS_PACRI_TP2)
6965 /*! @brief Set the TP2 field to a new value. */
6966 #define BW_AIPS_PACRI_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP2) = (v))
6970 * @name Register AIPS_PACRI, field WP2[21] (RW)
6972 * Determines whether the peripheral allows write accesses. When this field is
6973 * set and a write access is attempted, access terminates with an error response
6974 * and no peripheral access initiates.
6977 * - 0 - This peripheral allows write accesses.
6978 * - 1 - This peripheral is write protected.
6981 #define BP_AIPS_PACRI_WP2 (21U) /*!< Bit position for AIPS_PACRI_WP2. */
6982 #define BM_AIPS_PACRI_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRI_WP2. */
6983 #define BS_AIPS_PACRI_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRI_WP2. */
6985 /*! @brief Read current value of the AIPS_PACRI_WP2 field. */
6986 #define BR_AIPS_PACRI_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP2))
6988 /*! @brief Format value for bitfield AIPS_PACRI_WP2. */
6989 #define BF_AIPS_PACRI_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_WP2) & BM_AIPS_PACRI_WP2)
6991 /*! @brief Set the WP2 field to a new value. */
6992 #define BW_AIPS_PACRI_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP2) = (v))
6996 * @name Register AIPS_PACRI, field SP2[22] (RW)
6998 * Determines whether the peripheral requires supervisor privilege level for
6999 * access. When this bit is set, the master privilege level must indicate the
7000 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
7001 * set. If not, access terminates with an error response and no peripheral access
7005 * - 0 - This peripheral does not require supervisor privilege level for
7007 * - 1 - This peripheral requires supervisor privilege level for accesses.
7010 #define BP_AIPS_PACRI_SP2 (22U) /*!< Bit position for AIPS_PACRI_SP2. */
7011 #define BM_AIPS_PACRI_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRI_SP2. */
7012 #define BS_AIPS_PACRI_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRI_SP2. */
7014 /*! @brief Read current value of the AIPS_PACRI_SP2 field. */
7015 #define BR_AIPS_PACRI_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP2))
7017 /*! @brief Format value for bitfield AIPS_PACRI_SP2. */
7018 #define BF_AIPS_PACRI_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_SP2) & BM_AIPS_PACRI_SP2)
7020 /*! @brief Set the SP2 field to a new value. */
7021 #define BW_AIPS_PACRI_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP2) = (v))
7025 * @name Register AIPS_PACRI, field TP1[24] (RW)
7027 * Determines whether the peripheral allows accesses from an untrusted master.
7028 * When this field is set and an access is attempted by an untrusted master, the
7029 * access terminates with an error response and no peripheral access initiates.
7032 * - 0 - Accesses from an untrusted master are allowed.
7033 * - 1 - Accesses from an untrusted master are not allowed.
7036 #define BP_AIPS_PACRI_TP1 (24U) /*!< Bit position for AIPS_PACRI_TP1. */
7037 #define BM_AIPS_PACRI_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRI_TP1. */
7038 #define BS_AIPS_PACRI_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRI_TP1. */
7040 /*! @brief Read current value of the AIPS_PACRI_TP1 field. */
7041 #define BR_AIPS_PACRI_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP1))
7043 /*! @brief Format value for bitfield AIPS_PACRI_TP1. */
7044 #define BF_AIPS_PACRI_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_TP1) & BM_AIPS_PACRI_TP1)
7046 /*! @brief Set the TP1 field to a new value. */
7047 #define BW_AIPS_PACRI_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP1) = (v))
7051 * @name Register AIPS_PACRI, field WP1[25] (RW)
7053 * Determines whether the peripheral allows write accesses. When this field is
7054 * set and a write access is attempted, access terminates with an error response
7055 * and no peripheral access initiates.
7058 * - 0 - This peripheral allows write accesses.
7059 * - 1 - This peripheral is write protected.
7062 #define BP_AIPS_PACRI_WP1 (25U) /*!< Bit position for AIPS_PACRI_WP1. */
7063 #define BM_AIPS_PACRI_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRI_WP1. */
7064 #define BS_AIPS_PACRI_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRI_WP1. */
7066 /*! @brief Read current value of the AIPS_PACRI_WP1 field. */
7067 #define BR_AIPS_PACRI_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP1))
7069 /*! @brief Format value for bitfield AIPS_PACRI_WP1. */
7070 #define BF_AIPS_PACRI_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_WP1) & BM_AIPS_PACRI_WP1)
7072 /*! @brief Set the WP1 field to a new value. */
7073 #define BW_AIPS_PACRI_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP1) = (v))
7077 * @name Register AIPS_PACRI, field SP1[26] (RW)
7079 * Determines whether the peripheral requires supervisor privilege level for
7080 * access. When this field is set, the master privilege level must indicate the
7081 * supervisor access attribute, and the MPRx[MPLn] control field for the master must
7082 * be set. If not, access terminates with an error response and no peripheral
7086 * - 0 - This peripheral does not require supervisor privilege level for
7088 * - 1 - This peripheral requires supervisor privilege level for accesses.
7091 #define BP_AIPS_PACRI_SP1 (26U) /*!< Bit position for AIPS_PACRI_SP1. */
7092 #define BM_AIPS_PACRI_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRI_SP1. */
7093 #define BS_AIPS_PACRI_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRI_SP1. */
7095 /*! @brief Read current value of the AIPS_PACRI_SP1 field. */
7096 #define BR_AIPS_PACRI_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP1))
7098 /*! @brief Format value for bitfield AIPS_PACRI_SP1. */
7099 #define BF_AIPS_PACRI_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_SP1) & BM_AIPS_PACRI_SP1)
7101 /*! @brief Set the SP1 field to a new value. */
7102 #define BW_AIPS_PACRI_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP1) = (v))
7106 * @name Register AIPS_PACRI, field TP0[28] (RW)
7108 * Determines whether the peripheral allows accesses from an untrusted master.
7109 * When this bit is set and an access is attempted by an untrusted master, the
7110 * access terminates with an error response and no peripheral access initiates.
7113 * - 0 - Accesses from an untrusted master are allowed.
7114 * - 1 - Accesses from an untrusted master are not allowed.
7117 #define BP_AIPS_PACRI_TP0 (28U) /*!< Bit position for AIPS_PACRI_TP0. */
7118 #define BM_AIPS_PACRI_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRI_TP0. */
7119 #define BS_AIPS_PACRI_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRI_TP0. */
7121 /*! @brief Read current value of the AIPS_PACRI_TP0 field. */
7122 #define BR_AIPS_PACRI_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP0))
7124 /*! @brief Format value for bitfield AIPS_PACRI_TP0. */
7125 #define BF_AIPS_PACRI_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_TP0) & BM_AIPS_PACRI_TP0)
7127 /*! @brief Set the TP0 field to a new value. */
7128 #define BW_AIPS_PACRI_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP0) = (v))
7132 * @name Register AIPS_PACRI, field WP0[29] (RW)
7134 * Determines whether the peripheral allows write accesses. When this field is
7135 * set and a write access is attempted, access terminates with an error response
7136 * and no peripheral access initiates.
7139 * - 0 - This peripheral allows write accesses.
7140 * - 1 - This peripheral is write protected.
7143 #define BP_AIPS_PACRI_WP0 (29U) /*!< Bit position for AIPS_PACRI_WP0. */
7144 #define BM_AIPS_PACRI_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRI_WP0. */
7145 #define BS_AIPS_PACRI_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRI_WP0. */
7147 /*! @brief Read current value of the AIPS_PACRI_WP0 field. */
7148 #define BR_AIPS_PACRI_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP0))
7150 /*! @brief Format value for bitfield AIPS_PACRI_WP0. */
7151 #define BF_AIPS_PACRI_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_WP0) & BM_AIPS_PACRI_WP0)
7153 /*! @brief Set the WP0 field to a new value. */
7154 #define BW_AIPS_PACRI_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP0) = (v))
7158 * @name Register AIPS_PACRI, field SP0[30] (RW)
7160 * Determines whether the peripheral requires supervisor privilege level for
7161 * accesses. When this field is set, the master privilege level must indicate the
7162 * supervisor access attribute, and the MPRx[MPLn] control field for the master
7163 * must be set. If not, access terminates with an error response and no peripheral
7167 * - 0 - This peripheral does not require supervisor privilege level for
7169 * - 1 - This peripheral requires supervisor privilege level for accesses.
7172 #define BP_AIPS_PACRI_SP0 (30U) /*!< Bit position for AIPS_PACRI_SP0. */
7173 #define BM_AIPS_PACRI_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRI_SP0. */
7174 #define BS_AIPS_PACRI_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRI_SP0. */
7176 /*! @brief Read current value of the AIPS_PACRI_SP0 field. */
7177 #define BR_AIPS_PACRI_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP0))
7179 /*! @brief Format value for bitfield AIPS_PACRI_SP0. */
7180 #define BF_AIPS_PACRI_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_SP0) & BM_AIPS_PACRI_SP0)
7182 /*! @brief Set the SP0 field to a new value. */
7183 #define BW_AIPS_PACRI_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP0) = (v))
7186 /*******************************************************************************
7187 * HW_AIPS_PACRJ - Peripheral Access Control Register
7188 ******************************************************************************/
7191 * @brief HW_AIPS_PACRJ - Peripheral Access Control Register (RW)
7193 * Reset value: 0x44444444U
7195 * This section describes PACR registers E-P, which control peripheral slots
7196 * 32-127. See PACRPeripheral Access Control Register for the description of these
7199 typedef union _hw_aips_pacrj
7202 struct _hw_aips_pacrj_bitfields
7204 uint32_t TP7
: 1; /*!< [0] Trusted Protect */
7205 uint32_t WP7
: 1; /*!< [1] Write Protect */
7206 uint32_t SP7
: 1; /*!< [2] Supervisor Protect */
7207 uint32_t RESERVED0
: 1; /*!< [3] */
7208 uint32_t TP6
: 1; /*!< [4] Trusted Protect */
7209 uint32_t WP6
: 1; /*!< [5] Write Protect */
7210 uint32_t SP6
: 1; /*!< [6] Supervisor Protect */
7211 uint32_t RESERVED1
: 1; /*!< [7] */
7212 uint32_t TP5
: 1; /*!< [8] Trusted Protect */
7213 uint32_t WP5
: 1; /*!< [9] Write Protect */
7214 uint32_t SP5
: 1; /*!< [10] Supervisor Protect */
7215 uint32_t RESERVED2
: 1; /*!< [11] */
7216 uint32_t TP4
: 1; /*!< [12] Trusted Protect */
7217 uint32_t WP4
: 1; /*!< [13] Write Protect */
7218 uint32_t SP4
: 1; /*!< [14] Supervisor Protect */
7219 uint32_t RESERVED3
: 1; /*!< [15] */
7220 uint32_t TP3
: 1; /*!< [16] Trusted Protect */
7221 uint32_t WP3
: 1; /*!< [17] Write Protect */
7222 uint32_t SP3
: 1; /*!< [18] Supervisor Protect */
7223 uint32_t RESERVED4
: 1; /*!< [19] */
7224 uint32_t TP2
: 1; /*!< [20] Trusted Protect */
7225 uint32_t WP2
: 1; /*!< [21] Write Protect */
7226 uint32_t SP2
: 1; /*!< [22] Supervisor Protect */
7227 uint32_t RESERVED5
: 1; /*!< [23] */
7228 uint32_t TP1
: 1; /*!< [24] Trusted Protect */
7229 uint32_t WP1
: 1; /*!< [25] Write Protect */
7230 uint32_t SP1
: 1; /*!< [26] Supervisor Protect */
7231 uint32_t RESERVED6
: 1; /*!< [27] */
7232 uint32_t TP0
: 1; /*!< [28] Trusted Protect */
7233 uint32_t WP0
: 1; /*!< [29] Write Protect */
7234 uint32_t SP0
: 1; /*!< [30] Supervisor Protect */
7235 uint32_t RESERVED7
: 1; /*!< [31] */
7240 * @name Constants and macros for entire AIPS_PACRJ register
7243 #define HW_AIPS_PACRJ_ADDR(x) ((x) + 0x54U)
7245 #define HW_AIPS_PACRJ(x) (*(__IO hw_aips_pacrj_t *) HW_AIPS_PACRJ_ADDR(x))
7246 #define HW_AIPS_PACRJ_RD(x) (HW_AIPS_PACRJ(x).U)
7247 #define HW_AIPS_PACRJ_WR(x, v) (HW_AIPS_PACRJ(x).U = (v))
7248 #define HW_AIPS_PACRJ_SET(x, v) (HW_AIPS_PACRJ_WR(x, HW_AIPS_PACRJ_RD(x) | (v)))
7249 #define HW_AIPS_PACRJ_CLR(x, v) (HW_AIPS_PACRJ_WR(x, HW_AIPS_PACRJ_RD(x) & ~(v)))
7250 #define HW_AIPS_PACRJ_TOG(x, v) (HW_AIPS_PACRJ_WR(x, HW_AIPS_PACRJ_RD(x) ^ (v)))
7254 * Constants & macros for individual AIPS_PACRJ bitfields
7258 * @name Register AIPS_PACRJ, field TP7[0] (RW)
7260 * Determines whether the peripheral allows accesses from an untrusted master.
7261 * When this field is set and an access is attempted by an untrusted master, the
7262 * access terminates with an error response and no peripheral access initiates.
7265 * - 0 - Accesses from an untrusted master are allowed.
7266 * - 1 - Accesses from an untrusted master are not allowed.
7269 #define BP_AIPS_PACRJ_TP7 (0U) /*!< Bit position for AIPS_PACRJ_TP7. */
7270 #define BM_AIPS_PACRJ_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRJ_TP7. */
7271 #define BS_AIPS_PACRJ_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRJ_TP7. */
7273 /*! @brief Read current value of the AIPS_PACRJ_TP7 field. */
7274 #define BR_AIPS_PACRJ_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP7))
7276 /*! @brief Format value for bitfield AIPS_PACRJ_TP7. */
7277 #define BF_AIPS_PACRJ_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_TP7) & BM_AIPS_PACRJ_TP7)
7279 /*! @brief Set the TP7 field to a new value. */
7280 #define BW_AIPS_PACRJ_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP7) = (v))
7284 * @name Register AIPS_PACRJ, field WP7[1] (RW)
7286 * Determines whether the peripheral allows write accesses. When this field is
7287 * set and a write access is attempted, access terminates with an error response
7288 * and no peripheral access initiates.
7291 * - 0 - This peripheral allows write accesses.
7292 * - 1 - This peripheral is write protected.
7295 #define BP_AIPS_PACRJ_WP7 (1U) /*!< Bit position for AIPS_PACRJ_WP7. */
7296 #define BM_AIPS_PACRJ_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRJ_WP7. */
7297 #define BS_AIPS_PACRJ_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRJ_WP7. */
7299 /*! @brief Read current value of the AIPS_PACRJ_WP7 field. */
7300 #define BR_AIPS_PACRJ_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP7))
7302 /*! @brief Format value for bitfield AIPS_PACRJ_WP7. */
7303 #define BF_AIPS_PACRJ_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_WP7) & BM_AIPS_PACRJ_WP7)
7305 /*! @brief Set the WP7 field to a new value. */
7306 #define BW_AIPS_PACRJ_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP7) = (v))
7310 * @name Register AIPS_PACRJ, field SP7[2] (RW)
7312 * Determines whether the peripheral requires supervisor privilege level for
7313 * accesses. When this field is set, the master privilege level must indicate the
7314 * supervisor access attribute, and the MPRx[MPLn] control field for the master
7315 * must be set. If not, access terminates with an error response and no peripheral
7319 * - 0 - This peripheral does not require supervisor privilege level for
7321 * - 1 - This peripheral requires supervisor privilege level for accesses.
7324 #define BP_AIPS_PACRJ_SP7 (2U) /*!< Bit position for AIPS_PACRJ_SP7. */
7325 #define BM_AIPS_PACRJ_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRJ_SP7. */
7326 #define BS_AIPS_PACRJ_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRJ_SP7. */
7328 /*! @brief Read current value of the AIPS_PACRJ_SP7 field. */
7329 #define BR_AIPS_PACRJ_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP7))
7331 /*! @brief Format value for bitfield AIPS_PACRJ_SP7. */
7332 #define BF_AIPS_PACRJ_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_SP7) & BM_AIPS_PACRJ_SP7)
7334 /*! @brief Set the SP7 field to a new value. */
7335 #define BW_AIPS_PACRJ_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP7) = (v))
7339 * @name Register AIPS_PACRJ, field TP6[4] (RW)
7341 * Determines whether the peripheral allows accesses from an untrusted master.
7342 * When this field is set and an access is attempted by an untrusted master, the
7343 * access terminates with an error response and no peripheral access initiates.
7346 * - 0 - Accesses from an untrusted master are allowed.
7347 * - 1 - Accesses from an untrusted master are not allowed.
7350 #define BP_AIPS_PACRJ_TP6 (4U) /*!< Bit position for AIPS_PACRJ_TP6. */
7351 #define BM_AIPS_PACRJ_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRJ_TP6. */
7352 #define BS_AIPS_PACRJ_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRJ_TP6. */
7354 /*! @brief Read current value of the AIPS_PACRJ_TP6 field. */
7355 #define BR_AIPS_PACRJ_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP6))
7357 /*! @brief Format value for bitfield AIPS_PACRJ_TP6. */
7358 #define BF_AIPS_PACRJ_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_TP6) & BM_AIPS_PACRJ_TP6)
7360 /*! @brief Set the TP6 field to a new value. */
7361 #define BW_AIPS_PACRJ_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP6) = (v))
7365 * @name Register AIPS_PACRJ, field WP6[5] (RW)
7367 * Determines whether the peripheral allows write accesses. When this field is
7368 * set and a write access is attempted, access terminates with an error response
7369 * and no peripheral access initiates.
7372 * - 0 - This peripheral allows write accesses.
7373 * - 1 - This peripheral is write protected.
7376 #define BP_AIPS_PACRJ_WP6 (5U) /*!< Bit position for AIPS_PACRJ_WP6. */
7377 #define BM_AIPS_PACRJ_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRJ_WP6. */
7378 #define BS_AIPS_PACRJ_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRJ_WP6. */
7380 /*! @brief Read current value of the AIPS_PACRJ_WP6 field. */
7381 #define BR_AIPS_PACRJ_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP6))
7383 /*! @brief Format value for bitfield AIPS_PACRJ_WP6. */
7384 #define BF_AIPS_PACRJ_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_WP6) & BM_AIPS_PACRJ_WP6)
7386 /*! @brief Set the WP6 field to a new value. */
7387 #define BW_AIPS_PACRJ_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP6) = (v))
7391 * @name Register AIPS_PACRJ, field SP6[6] (RW)
7393 * Determines whether the peripheral requires supervisor privilege level for
7394 * accesses. When this field is set, the master privilege level must indicate the
7395 * supervisor access attribute, and the MPRx[MPLn] control field for the master
7396 * must be set. If not, access terminates with an error response and no peripheral
7400 * - 0 - This peripheral does not require supervisor privilege level for
7402 * - 1 - This peripheral requires supervisor privilege level for accesses.
7405 #define BP_AIPS_PACRJ_SP6 (6U) /*!< Bit position for AIPS_PACRJ_SP6. */
7406 #define BM_AIPS_PACRJ_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRJ_SP6. */
7407 #define BS_AIPS_PACRJ_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRJ_SP6. */
7409 /*! @brief Read current value of the AIPS_PACRJ_SP6 field. */
7410 #define BR_AIPS_PACRJ_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP6))
7412 /*! @brief Format value for bitfield AIPS_PACRJ_SP6. */
7413 #define BF_AIPS_PACRJ_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_SP6) & BM_AIPS_PACRJ_SP6)
7415 /*! @brief Set the SP6 field to a new value. */
7416 #define BW_AIPS_PACRJ_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP6) = (v))
7420 * @name Register AIPS_PACRJ, field TP5[8] (RW)
7422 * Determines whether the peripheral allows accesses from an untrusted master.
7423 * When this field is set and an access is attempted by an untrusted master, the
7424 * access terminates with an error response and no peripheral access initiates.
7427 * - 0 - Accesses from an untrusted master are allowed.
7428 * - 1 - Accesses from an untrusted master are not allowed.
7431 #define BP_AIPS_PACRJ_TP5 (8U) /*!< Bit position for AIPS_PACRJ_TP5. */
7432 #define BM_AIPS_PACRJ_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRJ_TP5. */
7433 #define BS_AIPS_PACRJ_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRJ_TP5. */
7435 /*! @brief Read current value of the AIPS_PACRJ_TP5 field. */
7436 #define BR_AIPS_PACRJ_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP5))
7438 /*! @brief Format value for bitfield AIPS_PACRJ_TP5. */
7439 #define BF_AIPS_PACRJ_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_TP5) & BM_AIPS_PACRJ_TP5)
7441 /*! @brief Set the TP5 field to a new value. */
7442 #define BW_AIPS_PACRJ_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP5) = (v))
7446 * @name Register AIPS_PACRJ, field WP5[9] (RW)
7448 * Determines whether the peripheral allows write accesses. When this field is
7449 * set and a write access is attempted, access terminates with an error response
7450 * and no peripheral access initiates.
7453 * - 0 - This peripheral allows write accesses.
7454 * - 1 - This peripheral is write protected.
7457 #define BP_AIPS_PACRJ_WP5 (9U) /*!< Bit position for AIPS_PACRJ_WP5. */
7458 #define BM_AIPS_PACRJ_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRJ_WP5. */
7459 #define BS_AIPS_PACRJ_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRJ_WP5. */
7461 /*! @brief Read current value of the AIPS_PACRJ_WP5 field. */
7462 #define BR_AIPS_PACRJ_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP5))
7464 /*! @brief Format value for bitfield AIPS_PACRJ_WP5. */
7465 #define BF_AIPS_PACRJ_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_WP5) & BM_AIPS_PACRJ_WP5)
7467 /*! @brief Set the WP5 field to a new value. */
7468 #define BW_AIPS_PACRJ_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP5) = (v))
7472 * @name Register AIPS_PACRJ, field SP5[10] (RW)
7474 * Determines whether the peripheral requires supervisor privilege level for
7475 * accesses. When this field is set, the master privilege level must indicate the
7476 * supervisor access attribute, and the MPRx[MPLn] control field for the master
7477 * must be set. If not, access terminates with an error response and no peripheral
7481 * - 0 - This peripheral does not require supervisor privilege level for
7483 * - 1 - This peripheral requires supervisor privilege level for accesses.
7486 #define BP_AIPS_PACRJ_SP5 (10U) /*!< Bit position for AIPS_PACRJ_SP5. */
7487 #define BM_AIPS_PACRJ_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRJ_SP5. */
7488 #define BS_AIPS_PACRJ_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRJ_SP5. */
7490 /*! @brief Read current value of the AIPS_PACRJ_SP5 field. */
7491 #define BR_AIPS_PACRJ_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP5))
7493 /*! @brief Format value for bitfield AIPS_PACRJ_SP5. */
7494 #define BF_AIPS_PACRJ_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_SP5) & BM_AIPS_PACRJ_SP5)
7496 /*! @brief Set the SP5 field to a new value. */
7497 #define BW_AIPS_PACRJ_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP5) = (v))
7501 * @name Register AIPS_PACRJ, field TP4[12] (RW)
7503 * Determines whether the peripheral allows accesses from an untrusted master.
7504 * When this bit is set and an access is attempted by an untrusted master, the
7505 * access terminates with an error response and no peripheral access initiates.
7508 * - 0 - Accesses from an untrusted master are allowed.
7509 * - 1 - Accesses from an untrusted master are not allowed.
7512 #define BP_AIPS_PACRJ_TP4 (12U) /*!< Bit position for AIPS_PACRJ_TP4. */
7513 #define BM_AIPS_PACRJ_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRJ_TP4. */
7514 #define BS_AIPS_PACRJ_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRJ_TP4. */
7516 /*! @brief Read current value of the AIPS_PACRJ_TP4 field. */
7517 #define BR_AIPS_PACRJ_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP4))
7519 /*! @brief Format value for bitfield AIPS_PACRJ_TP4. */
7520 #define BF_AIPS_PACRJ_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_TP4) & BM_AIPS_PACRJ_TP4)
7522 /*! @brief Set the TP4 field to a new value. */
7523 #define BW_AIPS_PACRJ_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP4) = (v))
7527 * @name Register AIPS_PACRJ, field WP4[13] (RW)
7529 * Determines whether the peripheral allows write accesses. When this field is
7530 * set and a write access is attempted, access terminates with an error response
7531 * and no peripheral access initiates.
7534 * - 0 - This peripheral allows write accesses.
7535 * - 1 - This peripheral is write protected.
7538 #define BP_AIPS_PACRJ_WP4 (13U) /*!< Bit position for AIPS_PACRJ_WP4. */
7539 #define BM_AIPS_PACRJ_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRJ_WP4. */
7540 #define BS_AIPS_PACRJ_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRJ_WP4. */
7542 /*! @brief Read current value of the AIPS_PACRJ_WP4 field. */
7543 #define BR_AIPS_PACRJ_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP4))
7545 /*! @brief Format value for bitfield AIPS_PACRJ_WP4. */
7546 #define BF_AIPS_PACRJ_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_WP4) & BM_AIPS_PACRJ_WP4)
7548 /*! @brief Set the WP4 field to a new value. */
7549 #define BW_AIPS_PACRJ_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP4) = (v))
7553 * @name Register AIPS_PACRJ, field SP4[14] (RW)
7555 * Determines whether the peripheral requires supervisor privilege level for
7556 * access. When this bit is set, the master privilege level must indicate the
7557 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
7558 * set. If not, access terminates with an error response and no peripheral access
7562 * - 0 - This peripheral does not require supervisor privilege level for
7564 * - 1 - This peripheral requires supervisor privilege level for accesses.
7567 #define BP_AIPS_PACRJ_SP4 (14U) /*!< Bit position for AIPS_PACRJ_SP4. */
7568 #define BM_AIPS_PACRJ_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRJ_SP4. */
7569 #define BS_AIPS_PACRJ_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRJ_SP4. */
7571 /*! @brief Read current value of the AIPS_PACRJ_SP4 field. */
7572 #define BR_AIPS_PACRJ_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP4))
7574 /*! @brief Format value for bitfield AIPS_PACRJ_SP4. */
7575 #define BF_AIPS_PACRJ_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_SP4) & BM_AIPS_PACRJ_SP4)
7577 /*! @brief Set the SP4 field to a new value. */
7578 #define BW_AIPS_PACRJ_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP4) = (v))
7582 * @name Register AIPS_PACRJ, field TP3[16] (RW)
7584 * Determines whether the peripheral allows accesses from an untrusted master.
7585 * When this field is set and an access is attempted by an untrusted master, the
7586 * access terminates with an error response and no peripheral access initiates.
7589 * - 0 - Accesses from an untrusted master are allowed.
7590 * - 1 - Accesses from an untrusted master are not allowed.
7593 #define BP_AIPS_PACRJ_TP3 (16U) /*!< Bit position for AIPS_PACRJ_TP3. */
7594 #define BM_AIPS_PACRJ_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRJ_TP3. */
7595 #define BS_AIPS_PACRJ_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRJ_TP3. */
7597 /*! @brief Read current value of the AIPS_PACRJ_TP3 field. */
7598 #define BR_AIPS_PACRJ_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP3))
7600 /*! @brief Format value for bitfield AIPS_PACRJ_TP3. */
7601 #define BF_AIPS_PACRJ_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_TP3) & BM_AIPS_PACRJ_TP3)
7603 /*! @brief Set the TP3 field to a new value. */
7604 #define BW_AIPS_PACRJ_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP3) = (v))
7608 * @name Register AIPS_PACRJ, field WP3[17] (RW)
7610 * Determines whether the peripheral allows write accesss. When this bit is set
7611 * and a write access is attempted, access terminates with an error response and
7612 * no peripheral access initiates.
7615 * - 0 - This peripheral allows write accesses.
7616 * - 1 - This peripheral is write protected.
7619 #define BP_AIPS_PACRJ_WP3 (17U) /*!< Bit position for AIPS_PACRJ_WP3. */
7620 #define BM_AIPS_PACRJ_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRJ_WP3. */
7621 #define BS_AIPS_PACRJ_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRJ_WP3. */
7623 /*! @brief Read current value of the AIPS_PACRJ_WP3 field. */
7624 #define BR_AIPS_PACRJ_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP3))
7626 /*! @brief Format value for bitfield AIPS_PACRJ_WP3. */
7627 #define BF_AIPS_PACRJ_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_WP3) & BM_AIPS_PACRJ_WP3)
7629 /*! @brief Set the WP3 field to a new value. */
7630 #define BW_AIPS_PACRJ_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP3) = (v))
7634 * @name Register AIPS_PACRJ, field SP3[18] (RW)
7636 * Determines whether the peripheral requires supervisor privilege level for
7637 * accesses. When this field is set, the master privilege level must indicate the
7638 * supervisor access attribute, and the MPRx[MPLn] control field for the master
7639 * must be set. If not, access terminates with an error response and no peripheral
7643 * - 0 - This peripheral does not require supervisor privilege level for
7645 * - 1 - This peripheral requires supervisor privilege level for accesses.
7648 #define BP_AIPS_PACRJ_SP3 (18U) /*!< Bit position for AIPS_PACRJ_SP3. */
7649 #define BM_AIPS_PACRJ_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRJ_SP3. */
7650 #define BS_AIPS_PACRJ_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRJ_SP3. */
7652 /*! @brief Read current value of the AIPS_PACRJ_SP3 field. */
7653 #define BR_AIPS_PACRJ_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP3))
7655 /*! @brief Format value for bitfield AIPS_PACRJ_SP3. */
7656 #define BF_AIPS_PACRJ_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_SP3) & BM_AIPS_PACRJ_SP3)
7658 /*! @brief Set the SP3 field to a new value. */
7659 #define BW_AIPS_PACRJ_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP3) = (v))
7663 * @name Register AIPS_PACRJ, field TP2[20] (RW)
7665 * Determines whether the peripheral allows accesses from an untrusted master.
7666 * When this bit is set and an access is attempted by an untrusted master, the
7667 * access terminates with an error response and no peripheral access initiates.
7670 * - 0 - Accesses from an untrusted master are allowed.
7671 * - 1 - Accesses from an untrusted master are not allowed.
7674 #define BP_AIPS_PACRJ_TP2 (20U) /*!< Bit position for AIPS_PACRJ_TP2. */
7675 #define BM_AIPS_PACRJ_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRJ_TP2. */
7676 #define BS_AIPS_PACRJ_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRJ_TP2. */
7678 /*! @brief Read current value of the AIPS_PACRJ_TP2 field. */
7679 #define BR_AIPS_PACRJ_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP2))
7681 /*! @brief Format value for bitfield AIPS_PACRJ_TP2. */
7682 #define BF_AIPS_PACRJ_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_TP2) & BM_AIPS_PACRJ_TP2)
7684 /*! @brief Set the TP2 field to a new value. */
7685 #define BW_AIPS_PACRJ_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP2) = (v))
7689 * @name Register AIPS_PACRJ, field WP2[21] (RW)
7691 * Determines whether the peripheral allows write accesses. When this field is
7692 * set and a write access is attempted, access terminates with an error response
7693 * and no peripheral access initiates.
7696 * - 0 - This peripheral allows write accesses.
7697 * - 1 - This peripheral is write protected.
7700 #define BP_AIPS_PACRJ_WP2 (21U) /*!< Bit position for AIPS_PACRJ_WP2. */
7701 #define BM_AIPS_PACRJ_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRJ_WP2. */
7702 #define BS_AIPS_PACRJ_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRJ_WP2. */
7704 /*! @brief Read current value of the AIPS_PACRJ_WP2 field. */
7705 #define BR_AIPS_PACRJ_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP2))
7707 /*! @brief Format value for bitfield AIPS_PACRJ_WP2. */
7708 #define BF_AIPS_PACRJ_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_WP2) & BM_AIPS_PACRJ_WP2)
7710 /*! @brief Set the WP2 field to a new value. */
7711 #define BW_AIPS_PACRJ_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP2) = (v))
7715 * @name Register AIPS_PACRJ, field SP2[22] (RW)
7717 * Determines whether the peripheral requires supervisor privilege level for
7718 * access. When this bit is set, the master privilege level must indicate the
7719 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
7720 * set. If not, access terminates with an error response and no peripheral access
7724 * - 0 - This peripheral does not require supervisor privilege level for
7726 * - 1 - This peripheral requires supervisor privilege level for accesses.
7729 #define BP_AIPS_PACRJ_SP2 (22U) /*!< Bit position for AIPS_PACRJ_SP2. */
7730 #define BM_AIPS_PACRJ_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRJ_SP2. */
7731 #define BS_AIPS_PACRJ_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRJ_SP2. */
7733 /*! @brief Read current value of the AIPS_PACRJ_SP2 field. */
7734 #define BR_AIPS_PACRJ_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP2))
7736 /*! @brief Format value for bitfield AIPS_PACRJ_SP2. */
7737 #define BF_AIPS_PACRJ_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_SP2) & BM_AIPS_PACRJ_SP2)
7739 /*! @brief Set the SP2 field to a new value. */
7740 #define BW_AIPS_PACRJ_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP2) = (v))
7744 * @name Register AIPS_PACRJ, field TP1[24] (RW)
7746 * Determines whether the peripheral allows accesses from an untrusted master.
7747 * When this field is set and an access is attempted by an untrusted master, the
7748 * access terminates with an error response and no peripheral access initiates.
7751 * - 0 - Accesses from an untrusted master are allowed.
7752 * - 1 - Accesses from an untrusted master are not allowed.
7755 #define BP_AIPS_PACRJ_TP1 (24U) /*!< Bit position for AIPS_PACRJ_TP1. */
7756 #define BM_AIPS_PACRJ_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRJ_TP1. */
7757 #define BS_AIPS_PACRJ_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRJ_TP1. */
7759 /*! @brief Read current value of the AIPS_PACRJ_TP1 field. */
7760 #define BR_AIPS_PACRJ_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP1))
7762 /*! @brief Format value for bitfield AIPS_PACRJ_TP1. */
7763 #define BF_AIPS_PACRJ_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_TP1) & BM_AIPS_PACRJ_TP1)
7765 /*! @brief Set the TP1 field to a new value. */
7766 #define BW_AIPS_PACRJ_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP1) = (v))
7770 * @name Register AIPS_PACRJ, field WP1[25] (RW)
7772 * Determines whether the peripheral allows write accesses. When this field is
7773 * set and a write access is attempted, access terminates with an error response
7774 * and no peripheral access initiates.
7777 * - 0 - This peripheral allows write accesses.
7778 * - 1 - This peripheral is write protected.
7781 #define BP_AIPS_PACRJ_WP1 (25U) /*!< Bit position for AIPS_PACRJ_WP1. */
7782 #define BM_AIPS_PACRJ_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRJ_WP1. */
7783 #define BS_AIPS_PACRJ_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRJ_WP1. */
7785 /*! @brief Read current value of the AIPS_PACRJ_WP1 field. */
7786 #define BR_AIPS_PACRJ_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP1))
7788 /*! @brief Format value for bitfield AIPS_PACRJ_WP1. */
7789 #define BF_AIPS_PACRJ_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_WP1) & BM_AIPS_PACRJ_WP1)
7791 /*! @brief Set the WP1 field to a new value. */
7792 #define BW_AIPS_PACRJ_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP1) = (v))
7796 * @name Register AIPS_PACRJ, field SP1[26] (RW)
7798 * Determines whether the peripheral requires supervisor privilege level for
7799 * access. When this field is set, the master privilege level must indicate the
7800 * supervisor access attribute, and the MPRx[MPLn] control field for the master must
7801 * be set. If not, access terminates with an error response and no peripheral
7805 * - 0 - This peripheral does not require supervisor privilege level for
7807 * - 1 - This peripheral requires supervisor privilege level for accesses.
7810 #define BP_AIPS_PACRJ_SP1 (26U) /*!< Bit position for AIPS_PACRJ_SP1. */
7811 #define BM_AIPS_PACRJ_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRJ_SP1. */
7812 #define BS_AIPS_PACRJ_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRJ_SP1. */
7814 /*! @brief Read current value of the AIPS_PACRJ_SP1 field. */
7815 #define BR_AIPS_PACRJ_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP1))
7817 /*! @brief Format value for bitfield AIPS_PACRJ_SP1. */
7818 #define BF_AIPS_PACRJ_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_SP1) & BM_AIPS_PACRJ_SP1)
7820 /*! @brief Set the SP1 field to a new value. */
7821 #define BW_AIPS_PACRJ_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP1) = (v))
7825 * @name Register AIPS_PACRJ, field TP0[28] (RW)
7827 * Determines whether the peripheral allows accesses from an untrusted master.
7828 * When this bit is set and an access is attempted by an untrusted master, the
7829 * access terminates with an error response and no peripheral access initiates.
7832 * - 0 - Accesses from an untrusted master are allowed.
7833 * - 1 - Accesses from an untrusted master are not allowed.
7836 #define BP_AIPS_PACRJ_TP0 (28U) /*!< Bit position for AIPS_PACRJ_TP0. */
7837 #define BM_AIPS_PACRJ_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRJ_TP0. */
7838 #define BS_AIPS_PACRJ_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRJ_TP0. */
7840 /*! @brief Read current value of the AIPS_PACRJ_TP0 field. */
7841 #define BR_AIPS_PACRJ_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP0))
7843 /*! @brief Format value for bitfield AIPS_PACRJ_TP0. */
7844 #define BF_AIPS_PACRJ_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_TP0) & BM_AIPS_PACRJ_TP0)
7846 /*! @brief Set the TP0 field to a new value. */
7847 #define BW_AIPS_PACRJ_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP0) = (v))
7851 * @name Register AIPS_PACRJ, field WP0[29] (RW)
7853 * Determines whether the peripheral allows write accesses. When this field is
7854 * set and a write access is attempted, access terminates with an error response
7855 * and no peripheral access initiates.
7858 * - 0 - This peripheral allows write accesses.
7859 * - 1 - This peripheral is write protected.
7862 #define BP_AIPS_PACRJ_WP0 (29U) /*!< Bit position for AIPS_PACRJ_WP0. */
7863 #define BM_AIPS_PACRJ_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRJ_WP0. */
7864 #define BS_AIPS_PACRJ_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRJ_WP0. */
7866 /*! @brief Read current value of the AIPS_PACRJ_WP0 field. */
7867 #define BR_AIPS_PACRJ_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP0))
7869 /*! @brief Format value for bitfield AIPS_PACRJ_WP0. */
7870 #define BF_AIPS_PACRJ_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_WP0) & BM_AIPS_PACRJ_WP0)
7872 /*! @brief Set the WP0 field to a new value. */
7873 #define BW_AIPS_PACRJ_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP0) = (v))
7877 * @name Register AIPS_PACRJ, field SP0[30] (RW)
7879 * Determines whether the peripheral requires supervisor privilege level for
7880 * accesses. When this field is set, the master privilege level must indicate the
7881 * supervisor access attribute, and the MPRx[MPLn] control field for the master
7882 * must be set. If not, access terminates with an error response and no peripheral
7886 * - 0 - This peripheral does not require supervisor privilege level for
7888 * - 1 - This peripheral requires supervisor privilege level for accesses.
7891 #define BP_AIPS_PACRJ_SP0 (30U) /*!< Bit position for AIPS_PACRJ_SP0. */
7892 #define BM_AIPS_PACRJ_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRJ_SP0. */
7893 #define BS_AIPS_PACRJ_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRJ_SP0. */
7895 /*! @brief Read current value of the AIPS_PACRJ_SP0 field. */
7896 #define BR_AIPS_PACRJ_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP0))
7898 /*! @brief Format value for bitfield AIPS_PACRJ_SP0. */
7899 #define BF_AIPS_PACRJ_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_SP0) & BM_AIPS_PACRJ_SP0)
7901 /*! @brief Set the SP0 field to a new value. */
7902 #define BW_AIPS_PACRJ_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP0) = (v))
7905 /*******************************************************************************
7906 * HW_AIPS_PACRK - Peripheral Access Control Register
7907 ******************************************************************************/
7910 * @brief HW_AIPS_PACRK - Peripheral Access Control Register (RW)
7912 * Reset value: 0x44444444U
7914 * This section describes PACR registers E-P, which control peripheral slots
7915 * 32-127. See PACRPeripheral Access Control Register for the description of these
7918 typedef union _hw_aips_pacrk
7921 struct _hw_aips_pacrk_bitfields
7923 uint32_t TP7
: 1; /*!< [0] Trusted Protect */
7924 uint32_t WP7
: 1; /*!< [1] Write Protect */
7925 uint32_t SP7
: 1; /*!< [2] Supervisor Protect */
7926 uint32_t RESERVED0
: 1; /*!< [3] */
7927 uint32_t TP6
: 1; /*!< [4] Trusted Protect */
7928 uint32_t WP6
: 1; /*!< [5] Write Protect */
7929 uint32_t SP6
: 1; /*!< [6] Supervisor Protect */
7930 uint32_t RESERVED1
: 1; /*!< [7] */
7931 uint32_t TP5
: 1; /*!< [8] Trusted Protect */
7932 uint32_t WP5
: 1; /*!< [9] Write Protect */
7933 uint32_t SP5
: 1; /*!< [10] Supervisor Protect */
7934 uint32_t RESERVED2
: 1; /*!< [11] */
7935 uint32_t TP4
: 1; /*!< [12] Trusted Protect */
7936 uint32_t WP4
: 1; /*!< [13] Write Protect */
7937 uint32_t SP4
: 1; /*!< [14] Supervisor Protect */
7938 uint32_t RESERVED3
: 1; /*!< [15] */
7939 uint32_t TP3
: 1; /*!< [16] Trusted Protect */
7940 uint32_t WP3
: 1; /*!< [17] Write Protect */
7941 uint32_t SP3
: 1; /*!< [18] Supervisor Protect */
7942 uint32_t RESERVED4
: 1; /*!< [19] */
7943 uint32_t TP2
: 1; /*!< [20] Trusted Protect */
7944 uint32_t WP2
: 1; /*!< [21] Write Protect */
7945 uint32_t SP2
: 1; /*!< [22] Supervisor Protect */
7946 uint32_t RESERVED5
: 1; /*!< [23] */
7947 uint32_t TP1
: 1; /*!< [24] Trusted Protect */
7948 uint32_t WP1
: 1; /*!< [25] Write Protect */
7949 uint32_t SP1
: 1; /*!< [26] Supervisor Protect */
7950 uint32_t RESERVED6
: 1; /*!< [27] */
7951 uint32_t TP0
: 1; /*!< [28] Trusted Protect */
7952 uint32_t WP0
: 1; /*!< [29] Write Protect */
7953 uint32_t SP0
: 1; /*!< [30] Supervisor Protect */
7954 uint32_t RESERVED7
: 1; /*!< [31] */
7959 * @name Constants and macros for entire AIPS_PACRK register
7962 #define HW_AIPS_PACRK_ADDR(x) ((x) + 0x58U)
7964 #define HW_AIPS_PACRK(x) (*(__IO hw_aips_pacrk_t *) HW_AIPS_PACRK_ADDR(x))
7965 #define HW_AIPS_PACRK_RD(x) (HW_AIPS_PACRK(x).U)
7966 #define HW_AIPS_PACRK_WR(x, v) (HW_AIPS_PACRK(x).U = (v))
7967 #define HW_AIPS_PACRK_SET(x, v) (HW_AIPS_PACRK_WR(x, HW_AIPS_PACRK_RD(x) | (v)))
7968 #define HW_AIPS_PACRK_CLR(x, v) (HW_AIPS_PACRK_WR(x, HW_AIPS_PACRK_RD(x) & ~(v)))
7969 #define HW_AIPS_PACRK_TOG(x, v) (HW_AIPS_PACRK_WR(x, HW_AIPS_PACRK_RD(x) ^ (v)))
7973 * Constants & macros for individual AIPS_PACRK bitfields
7977 * @name Register AIPS_PACRK, field TP7[0] (RW)
7979 * Determines whether the peripheral allows accesses from an untrusted master.
7980 * When this field is set and an access is attempted by an untrusted master, the
7981 * access terminates with an error response and no peripheral access initiates.
7984 * - 0 - Accesses from an untrusted master are allowed.
7985 * - 1 - Accesses from an untrusted master are not allowed.
7988 #define BP_AIPS_PACRK_TP7 (0U) /*!< Bit position for AIPS_PACRK_TP7. */
7989 #define BM_AIPS_PACRK_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRK_TP7. */
7990 #define BS_AIPS_PACRK_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRK_TP7. */
7992 /*! @brief Read current value of the AIPS_PACRK_TP7 field. */
7993 #define BR_AIPS_PACRK_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP7))
7995 /*! @brief Format value for bitfield AIPS_PACRK_TP7. */
7996 #define BF_AIPS_PACRK_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_TP7) & BM_AIPS_PACRK_TP7)
7998 /*! @brief Set the TP7 field to a new value. */
7999 #define BW_AIPS_PACRK_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP7) = (v))
8003 * @name Register AIPS_PACRK, field WP7[1] (RW)
8005 * Determines whether the peripheral allows write accesses. When this field is
8006 * set and a write access is attempted, access terminates with an error response
8007 * and no peripheral access initiates.
8010 * - 0 - This peripheral allows write accesses.
8011 * - 1 - This peripheral is write protected.
8014 #define BP_AIPS_PACRK_WP7 (1U) /*!< Bit position for AIPS_PACRK_WP7. */
8015 #define BM_AIPS_PACRK_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRK_WP7. */
8016 #define BS_AIPS_PACRK_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRK_WP7. */
8018 /*! @brief Read current value of the AIPS_PACRK_WP7 field. */
8019 #define BR_AIPS_PACRK_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP7))
8021 /*! @brief Format value for bitfield AIPS_PACRK_WP7. */
8022 #define BF_AIPS_PACRK_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_WP7) & BM_AIPS_PACRK_WP7)
8024 /*! @brief Set the WP7 field to a new value. */
8025 #define BW_AIPS_PACRK_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP7) = (v))
8029 * @name Register AIPS_PACRK, field SP7[2] (RW)
8031 * Determines whether the peripheral requires supervisor privilege level for
8032 * accesses. When this field is set, the master privilege level must indicate the
8033 * supervisor access attribute, and the MPRx[MPLn] control field for the master
8034 * must be set. If not, access terminates with an error response and no peripheral
8038 * - 0 - This peripheral does not require supervisor privilege level for
8040 * - 1 - This peripheral requires supervisor privilege level for accesses.
8043 #define BP_AIPS_PACRK_SP7 (2U) /*!< Bit position for AIPS_PACRK_SP7. */
8044 #define BM_AIPS_PACRK_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRK_SP7. */
8045 #define BS_AIPS_PACRK_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRK_SP7. */
8047 /*! @brief Read current value of the AIPS_PACRK_SP7 field. */
8048 #define BR_AIPS_PACRK_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP7))
8050 /*! @brief Format value for bitfield AIPS_PACRK_SP7. */
8051 #define BF_AIPS_PACRK_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_SP7) & BM_AIPS_PACRK_SP7)
8053 /*! @brief Set the SP7 field to a new value. */
8054 #define BW_AIPS_PACRK_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP7) = (v))
8058 * @name Register AIPS_PACRK, field TP6[4] (RW)
8060 * Determines whether the peripheral allows accesses from an untrusted master.
8061 * When this field is set and an access is attempted by an untrusted master, the
8062 * access terminates with an error response and no peripheral access initiates.
8065 * - 0 - Accesses from an untrusted master are allowed.
8066 * - 1 - Accesses from an untrusted master are not allowed.
8069 #define BP_AIPS_PACRK_TP6 (4U) /*!< Bit position for AIPS_PACRK_TP6. */
8070 #define BM_AIPS_PACRK_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRK_TP6. */
8071 #define BS_AIPS_PACRK_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRK_TP6. */
8073 /*! @brief Read current value of the AIPS_PACRK_TP6 field. */
8074 #define BR_AIPS_PACRK_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP6))
8076 /*! @brief Format value for bitfield AIPS_PACRK_TP6. */
8077 #define BF_AIPS_PACRK_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_TP6) & BM_AIPS_PACRK_TP6)
8079 /*! @brief Set the TP6 field to a new value. */
8080 #define BW_AIPS_PACRK_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP6) = (v))
8084 * @name Register AIPS_PACRK, field WP6[5] (RW)
8086 * Determines whether the peripheral allows write accesses. When this field is
8087 * set and a write access is attempted, access terminates with an error response
8088 * and no peripheral access initiates.
8091 * - 0 - This peripheral allows write accesses.
8092 * - 1 - This peripheral is write protected.
8095 #define BP_AIPS_PACRK_WP6 (5U) /*!< Bit position for AIPS_PACRK_WP6. */
8096 #define BM_AIPS_PACRK_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRK_WP6. */
8097 #define BS_AIPS_PACRK_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRK_WP6. */
8099 /*! @brief Read current value of the AIPS_PACRK_WP6 field. */
8100 #define BR_AIPS_PACRK_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP6))
8102 /*! @brief Format value for bitfield AIPS_PACRK_WP6. */
8103 #define BF_AIPS_PACRK_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_WP6) & BM_AIPS_PACRK_WP6)
8105 /*! @brief Set the WP6 field to a new value. */
8106 #define BW_AIPS_PACRK_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP6) = (v))
8110 * @name Register AIPS_PACRK, field SP6[6] (RW)
8112 * Determines whether the peripheral requires supervisor privilege level for
8113 * accesses. When this field is set, the master privilege level must indicate the
8114 * supervisor access attribute, and the MPRx[MPLn] control field for the master
8115 * must be set. If not, access terminates with an error response and no peripheral
8119 * - 0 - This peripheral does not require supervisor privilege level for
8121 * - 1 - This peripheral requires supervisor privilege level for accesses.
8124 #define BP_AIPS_PACRK_SP6 (6U) /*!< Bit position for AIPS_PACRK_SP6. */
8125 #define BM_AIPS_PACRK_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRK_SP6. */
8126 #define BS_AIPS_PACRK_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRK_SP6. */
8128 /*! @brief Read current value of the AIPS_PACRK_SP6 field. */
8129 #define BR_AIPS_PACRK_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP6))
8131 /*! @brief Format value for bitfield AIPS_PACRK_SP6. */
8132 #define BF_AIPS_PACRK_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_SP6) & BM_AIPS_PACRK_SP6)
8134 /*! @brief Set the SP6 field to a new value. */
8135 #define BW_AIPS_PACRK_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP6) = (v))
8139 * @name Register AIPS_PACRK, field TP5[8] (RW)
8141 * Determines whether the peripheral allows accesses from an untrusted master.
8142 * When this field is set and an access is attempted by an untrusted master, the
8143 * access terminates with an error response and no peripheral access initiates.
8146 * - 0 - Accesses from an untrusted master are allowed.
8147 * - 1 - Accesses from an untrusted master are not allowed.
8150 #define BP_AIPS_PACRK_TP5 (8U) /*!< Bit position for AIPS_PACRK_TP5. */
8151 #define BM_AIPS_PACRK_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRK_TP5. */
8152 #define BS_AIPS_PACRK_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRK_TP5. */
8154 /*! @brief Read current value of the AIPS_PACRK_TP5 field. */
8155 #define BR_AIPS_PACRK_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP5))
8157 /*! @brief Format value for bitfield AIPS_PACRK_TP5. */
8158 #define BF_AIPS_PACRK_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_TP5) & BM_AIPS_PACRK_TP5)
8160 /*! @brief Set the TP5 field to a new value. */
8161 #define BW_AIPS_PACRK_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP5) = (v))
8165 * @name Register AIPS_PACRK, field WP5[9] (RW)
8167 * Determines whether the peripheral allows write accesses. When this field is
8168 * set and a write access is attempted, access terminates with an error response
8169 * and no peripheral access initiates.
8172 * - 0 - This peripheral allows write accesses.
8173 * - 1 - This peripheral is write protected.
8176 #define BP_AIPS_PACRK_WP5 (9U) /*!< Bit position for AIPS_PACRK_WP5. */
8177 #define BM_AIPS_PACRK_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRK_WP5. */
8178 #define BS_AIPS_PACRK_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRK_WP5. */
8180 /*! @brief Read current value of the AIPS_PACRK_WP5 field. */
8181 #define BR_AIPS_PACRK_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP5))
8183 /*! @brief Format value for bitfield AIPS_PACRK_WP5. */
8184 #define BF_AIPS_PACRK_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_WP5) & BM_AIPS_PACRK_WP5)
8186 /*! @brief Set the WP5 field to a new value. */
8187 #define BW_AIPS_PACRK_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP5) = (v))
8191 * @name Register AIPS_PACRK, field SP5[10] (RW)
8193 * Determines whether the peripheral requires supervisor privilege level for
8194 * accesses. When this field is set, the master privilege level must indicate the
8195 * supervisor access attribute, and the MPRx[MPLn] control field for the master
8196 * must be set. If not, access terminates with an error response and no peripheral
8200 * - 0 - This peripheral does not require supervisor privilege level for
8202 * - 1 - This peripheral requires supervisor privilege level for accesses.
8205 #define BP_AIPS_PACRK_SP5 (10U) /*!< Bit position for AIPS_PACRK_SP5. */
8206 #define BM_AIPS_PACRK_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRK_SP5. */
8207 #define BS_AIPS_PACRK_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRK_SP5. */
8209 /*! @brief Read current value of the AIPS_PACRK_SP5 field. */
8210 #define BR_AIPS_PACRK_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP5))
8212 /*! @brief Format value for bitfield AIPS_PACRK_SP5. */
8213 #define BF_AIPS_PACRK_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_SP5) & BM_AIPS_PACRK_SP5)
8215 /*! @brief Set the SP5 field to a new value. */
8216 #define BW_AIPS_PACRK_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP5) = (v))
8220 * @name Register AIPS_PACRK, field TP4[12] (RW)
8222 * Determines whether the peripheral allows accesses from an untrusted master.
8223 * When this bit is set and an access is attempted by an untrusted master, the
8224 * access terminates with an error response and no peripheral access initiates.
8227 * - 0 - Accesses from an untrusted master are allowed.
8228 * - 1 - Accesses from an untrusted master are not allowed.
8231 #define BP_AIPS_PACRK_TP4 (12U) /*!< Bit position for AIPS_PACRK_TP4. */
8232 #define BM_AIPS_PACRK_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRK_TP4. */
8233 #define BS_AIPS_PACRK_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRK_TP4. */
8235 /*! @brief Read current value of the AIPS_PACRK_TP4 field. */
8236 #define BR_AIPS_PACRK_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP4))
8238 /*! @brief Format value for bitfield AIPS_PACRK_TP4. */
8239 #define BF_AIPS_PACRK_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_TP4) & BM_AIPS_PACRK_TP4)
8241 /*! @brief Set the TP4 field to a new value. */
8242 #define BW_AIPS_PACRK_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP4) = (v))
8246 * @name Register AIPS_PACRK, field WP4[13] (RW)
8248 * Determines whether the peripheral allows write accesses. When this field is
8249 * set and a write access is attempted, access terminates with an error response
8250 * and no peripheral access initiates.
8253 * - 0 - This peripheral allows write accesses.
8254 * - 1 - This peripheral is write protected.
8257 #define BP_AIPS_PACRK_WP4 (13U) /*!< Bit position for AIPS_PACRK_WP4. */
8258 #define BM_AIPS_PACRK_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRK_WP4. */
8259 #define BS_AIPS_PACRK_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRK_WP4. */
8261 /*! @brief Read current value of the AIPS_PACRK_WP4 field. */
8262 #define BR_AIPS_PACRK_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP4))
8264 /*! @brief Format value for bitfield AIPS_PACRK_WP4. */
8265 #define BF_AIPS_PACRK_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_WP4) & BM_AIPS_PACRK_WP4)
8267 /*! @brief Set the WP4 field to a new value. */
8268 #define BW_AIPS_PACRK_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP4) = (v))
8272 * @name Register AIPS_PACRK, field SP4[14] (RW)
8274 * Determines whether the peripheral requires supervisor privilege level for
8275 * access. When this bit is set, the master privilege level must indicate the
8276 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
8277 * set. If not, access terminates with an error response and no peripheral access
8281 * - 0 - This peripheral does not require supervisor privilege level for
8283 * - 1 - This peripheral requires supervisor privilege level for accesses.
8286 #define BP_AIPS_PACRK_SP4 (14U) /*!< Bit position for AIPS_PACRK_SP4. */
8287 #define BM_AIPS_PACRK_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRK_SP4. */
8288 #define BS_AIPS_PACRK_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRK_SP4. */
8290 /*! @brief Read current value of the AIPS_PACRK_SP4 field. */
8291 #define BR_AIPS_PACRK_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP4))
8293 /*! @brief Format value for bitfield AIPS_PACRK_SP4. */
8294 #define BF_AIPS_PACRK_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_SP4) & BM_AIPS_PACRK_SP4)
8296 /*! @brief Set the SP4 field to a new value. */
8297 #define BW_AIPS_PACRK_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP4) = (v))
8301 * @name Register AIPS_PACRK, field TP3[16] (RW)
8303 * Determines whether the peripheral allows accesses from an untrusted master.
8304 * When this field is set and an access is attempted by an untrusted master, the
8305 * access terminates with an error response and no peripheral access initiates.
8308 * - 0 - Accesses from an untrusted master are allowed.
8309 * - 1 - Accesses from an untrusted master are not allowed.
8312 #define BP_AIPS_PACRK_TP3 (16U) /*!< Bit position for AIPS_PACRK_TP3. */
8313 #define BM_AIPS_PACRK_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRK_TP3. */
8314 #define BS_AIPS_PACRK_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRK_TP3. */
8316 /*! @brief Read current value of the AIPS_PACRK_TP3 field. */
8317 #define BR_AIPS_PACRK_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP3))
8319 /*! @brief Format value for bitfield AIPS_PACRK_TP3. */
8320 #define BF_AIPS_PACRK_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_TP3) & BM_AIPS_PACRK_TP3)
8322 /*! @brief Set the TP3 field to a new value. */
8323 #define BW_AIPS_PACRK_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP3) = (v))
8327 * @name Register AIPS_PACRK, field WP3[17] (RW)
8329 * Determines whether the peripheral allows write accesss. When this bit is set
8330 * and a write access is attempted, access terminates with an error response and
8331 * no peripheral access initiates.
8334 * - 0 - This peripheral allows write accesses.
8335 * - 1 - This peripheral is write protected.
8338 #define BP_AIPS_PACRK_WP3 (17U) /*!< Bit position for AIPS_PACRK_WP3. */
8339 #define BM_AIPS_PACRK_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRK_WP3. */
8340 #define BS_AIPS_PACRK_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRK_WP3. */
8342 /*! @brief Read current value of the AIPS_PACRK_WP3 field. */
8343 #define BR_AIPS_PACRK_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP3))
8345 /*! @brief Format value for bitfield AIPS_PACRK_WP3. */
8346 #define BF_AIPS_PACRK_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_WP3) & BM_AIPS_PACRK_WP3)
8348 /*! @brief Set the WP3 field to a new value. */
8349 #define BW_AIPS_PACRK_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP3) = (v))
8353 * @name Register AIPS_PACRK, field SP3[18] (RW)
8355 * Determines whether the peripheral requires supervisor privilege level for
8356 * accesses. When this field is set, the master privilege level must indicate the
8357 * supervisor access attribute, and the MPRx[MPLn] control field for the master
8358 * must be set. If not, access terminates with an error response and no peripheral
8362 * - 0 - This peripheral does not require supervisor privilege level for
8364 * - 1 - This peripheral requires supervisor privilege level for accesses.
8367 #define BP_AIPS_PACRK_SP3 (18U) /*!< Bit position for AIPS_PACRK_SP3. */
8368 #define BM_AIPS_PACRK_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRK_SP3. */
8369 #define BS_AIPS_PACRK_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRK_SP3. */
8371 /*! @brief Read current value of the AIPS_PACRK_SP3 field. */
8372 #define BR_AIPS_PACRK_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP3))
8374 /*! @brief Format value for bitfield AIPS_PACRK_SP3. */
8375 #define BF_AIPS_PACRK_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_SP3) & BM_AIPS_PACRK_SP3)
8377 /*! @brief Set the SP3 field to a new value. */
8378 #define BW_AIPS_PACRK_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP3) = (v))
8382 * @name Register AIPS_PACRK, field TP2[20] (RW)
8384 * Determines whether the peripheral allows accesses from an untrusted master.
8385 * When this bit is set and an access is attempted by an untrusted master, the
8386 * access terminates with an error response and no peripheral access initiates.
8389 * - 0 - Accesses from an untrusted master are allowed.
8390 * - 1 - Accesses from an untrusted master are not allowed.
8393 #define BP_AIPS_PACRK_TP2 (20U) /*!< Bit position for AIPS_PACRK_TP2. */
8394 #define BM_AIPS_PACRK_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRK_TP2. */
8395 #define BS_AIPS_PACRK_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRK_TP2. */
8397 /*! @brief Read current value of the AIPS_PACRK_TP2 field. */
8398 #define BR_AIPS_PACRK_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP2))
8400 /*! @brief Format value for bitfield AIPS_PACRK_TP2. */
8401 #define BF_AIPS_PACRK_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_TP2) & BM_AIPS_PACRK_TP2)
8403 /*! @brief Set the TP2 field to a new value. */
8404 #define BW_AIPS_PACRK_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP2) = (v))
8408 * @name Register AIPS_PACRK, field WP2[21] (RW)
8410 * Determines whether the peripheral allows write accesses. When this field is
8411 * set and a write access is attempted, access terminates with an error response
8412 * and no peripheral access initiates.
8415 * - 0 - This peripheral allows write accesses.
8416 * - 1 - This peripheral is write protected.
8419 #define BP_AIPS_PACRK_WP2 (21U) /*!< Bit position for AIPS_PACRK_WP2. */
8420 #define BM_AIPS_PACRK_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRK_WP2. */
8421 #define BS_AIPS_PACRK_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRK_WP2. */
8423 /*! @brief Read current value of the AIPS_PACRK_WP2 field. */
8424 #define BR_AIPS_PACRK_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP2))
8426 /*! @brief Format value for bitfield AIPS_PACRK_WP2. */
8427 #define BF_AIPS_PACRK_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_WP2) & BM_AIPS_PACRK_WP2)
8429 /*! @brief Set the WP2 field to a new value. */
8430 #define BW_AIPS_PACRK_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP2) = (v))
8434 * @name Register AIPS_PACRK, field SP2[22] (RW)
8436 * Determines whether the peripheral requires supervisor privilege level for
8437 * access. When this bit is set, the master privilege level must indicate the
8438 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
8439 * set. If not, access terminates with an error response and no peripheral access
8443 * - 0 - This peripheral does not require supervisor privilege level for
8445 * - 1 - This peripheral requires supervisor privilege level for accesses.
8448 #define BP_AIPS_PACRK_SP2 (22U) /*!< Bit position for AIPS_PACRK_SP2. */
8449 #define BM_AIPS_PACRK_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRK_SP2. */
8450 #define BS_AIPS_PACRK_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRK_SP2. */
8452 /*! @brief Read current value of the AIPS_PACRK_SP2 field. */
8453 #define BR_AIPS_PACRK_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP2))
8455 /*! @brief Format value for bitfield AIPS_PACRK_SP2. */
8456 #define BF_AIPS_PACRK_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_SP2) & BM_AIPS_PACRK_SP2)
8458 /*! @brief Set the SP2 field to a new value. */
8459 #define BW_AIPS_PACRK_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP2) = (v))
8463 * @name Register AIPS_PACRK, field TP1[24] (RW)
8465 * Determines whether the peripheral allows accesses from an untrusted master.
8466 * When this field is set and an access is attempted by an untrusted master, the
8467 * access terminates with an error response and no peripheral access initiates.
8470 * - 0 - Accesses from an untrusted master are allowed.
8471 * - 1 - Accesses from an untrusted master are not allowed.
8474 #define BP_AIPS_PACRK_TP1 (24U) /*!< Bit position for AIPS_PACRK_TP1. */
8475 #define BM_AIPS_PACRK_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRK_TP1. */
8476 #define BS_AIPS_PACRK_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRK_TP1. */
8478 /*! @brief Read current value of the AIPS_PACRK_TP1 field. */
8479 #define BR_AIPS_PACRK_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP1))
8481 /*! @brief Format value for bitfield AIPS_PACRK_TP1. */
8482 #define BF_AIPS_PACRK_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_TP1) & BM_AIPS_PACRK_TP1)
8484 /*! @brief Set the TP1 field to a new value. */
8485 #define BW_AIPS_PACRK_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP1) = (v))
8489 * @name Register AIPS_PACRK, field WP1[25] (RW)
8491 * Determines whether the peripheral allows write accesses. When this field is
8492 * set and a write access is attempted, access terminates with an error response
8493 * and no peripheral access initiates.
8496 * - 0 - This peripheral allows write accesses.
8497 * - 1 - This peripheral is write protected.
8500 #define BP_AIPS_PACRK_WP1 (25U) /*!< Bit position for AIPS_PACRK_WP1. */
8501 #define BM_AIPS_PACRK_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRK_WP1. */
8502 #define BS_AIPS_PACRK_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRK_WP1. */
8504 /*! @brief Read current value of the AIPS_PACRK_WP1 field. */
8505 #define BR_AIPS_PACRK_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP1))
8507 /*! @brief Format value for bitfield AIPS_PACRK_WP1. */
8508 #define BF_AIPS_PACRK_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_WP1) & BM_AIPS_PACRK_WP1)
8510 /*! @brief Set the WP1 field to a new value. */
8511 #define BW_AIPS_PACRK_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP1) = (v))
8515 * @name Register AIPS_PACRK, field SP1[26] (RW)
8517 * Determines whether the peripheral requires supervisor privilege level for
8518 * access. When this field is set, the master privilege level must indicate the
8519 * supervisor access attribute, and the MPRx[MPLn] control field for the master must
8520 * be set. If not, access terminates with an error response and no peripheral
8524 * - 0 - This peripheral does not require supervisor privilege level for
8526 * - 1 - This peripheral requires supervisor privilege level for accesses.
8529 #define BP_AIPS_PACRK_SP1 (26U) /*!< Bit position for AIPS_PACRK_SP1. */
8530 #define BM_AIPS_PACRK_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRK_SP1. */
8531 #define BS_AIPS_PACRK_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRK_SP1. */
8533 /*! @brief Read current value of the AIPS_PACRK_SP1 field. */
8534 #define BR_AIPS_PACRK_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP1))
8536 /*! @brief Format value for bitfield AIPS_PACRK_SP1. */
8537 #define BF_AIPS_PACRK_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_SP1) & BM_AIPS_PACRK_SP1)
8539 /*! @brief Set the SP1 field to a new value. */
8540 #define BW_AIPS_PACRK_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP1) = (v))
8544 * @name Register AIPS_PACRK, field TP0[28] (RW)
8546 * Determines whether the peripheral allows accesses from an untrusted master.
8547 * When this bit is set and an access is attempted by an untrusted master, the
8548 * access terminates with an error response and no peripheral access initiates.
8551 * - 0 - Accesses from an untrusted master are allowed.
8552 * - 1 - Accesses from an untrusted master are not allowed.
8555 #define BP_AIPS_PACRK_TP0 (28U) /*!< Bit position for AIPS_PACRK_TP0. */
8556 #define BM_AIPS_PACRK_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRK_TP0. */
8557 #define BS_AIPS_PACRK_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRK_TP0. */
8559 /*! @brief Read current value of the AIPS_PACRK_TP0 field. */
8560 #define BR_AIPS_PACRK_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP0))
8562 /*! @brief Format value for bitfield AIPS_PACRK_TP0. */
8563 #define BF_AIPS_PACRK_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_TP0) & BM_AIPS_PACRK_TP0)
8565 /*! @brief Set the TP0 field to a new value. */
8566 #define BW_AIPS_PACRK_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP0) = (v))
8570 * @name Register AIPS_PACRK, field WP0[29] (RW)
8572 * Determines whether the peripheral allows write accesses. When this field is
8573 * set and a write access is attempted, access terminates with an error response
8574 * and no peripheral access initiates.
8577 * - 0 - This peripheral allows write accesses.
8578 * - 1 - This peripheral is write protected.
8581 #define BP_AIPS_PACRK_WP0 (29U) /*!< Bit position for AIPS_PACRK_WP0. */
8582 #define BM_AIPS_PACRK_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRK_WP0. */
8583 #define BS_AIPS_PACRK_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRK_WP0. */
8585 /*! @brief Read current value of the AIPS_PACRK_WP0 field. */
8586 #define BR_AIPS_PACRK_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP0))
8588 /*! @brief Format value for bitfield AIPS_PACRK_WP0. */
8589 #define BF_AIPS_PACRK_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_WP0) & BM_AIPS_PACRK_WP0)
8591 /*! @brief Set the WP0 field to a new value. */
8592 #define BW_AIPS_PACRK_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP0) = (v))
8596 * @name Register AIPS_PACRK, field SP0[30] (RW)
8598 * Determines whether the peripheral requires supervisor privilege level for
8599 * accesses. When this field is set, the master privilege level must indicate the
8600 * supervisor access attribute, and the MPRx[MPLn] control field for the master
8601 * must be set. If not, access terminates with an error response and no peripheral
8605 * - 0 - This peripheral does not require supervisor privilege level for
8607 * - 1 - This peripheral requires supervisor privilege level for accesses.
8610 #define BP_AIPS_PACRK_SP0 (30U) /*!< Bit position for AIPS_PACRK_SP0. */
8611 #define BM_AIPS_PACRK_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRK_SP0. */
8612 #define BS_AIPS_PACRK_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRK_SP0. */
8614 /*! @brief Read current value of the AIPS_PACRK_SP0 field. */
8615 #define BR_AIPS_PACRK_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP0))
8617 /*! @brief Format value for bitfield AIPS_PACRK_SP0. */
8618 #define BF_AIPS_PACRK_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_SP0) & BM_AIPS_PACRK_SP0)
8620 /*! @brief Set the SP0 field to a new value. */
8621 #define BW_AIPS_PACRK_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP0) = (v))
8624 /*******************************************************************************
8625 * HW_AIPS_PACRL - Peripheral Access Control Register
8626 ******************************************************************************/
8629 * @brief HW_AIPS_PACRL - Peripheral Access Control Register (RW)
8631 * Reset value: 0x44444444U
8633 * This section describes PACR registers E-P, which control peripheral slots
8634 * 32-127. See PACRPeripheral Access Control Register for the description of these
8637 typedef union _hw_aips_pacrl
8640 struct _hw_aips_pacrl_bitfields
8642 uint32_t TP7
: 1; /*!< [0] Trusted Protect */
8643 uint32_t WP7
: 1; /*!< [1] Write Protect */
8644 uint32_t SP7
: 1; /*!< [2] Supervisor Protect */
8645 uint32_t RESERVED0
: 1; /*!< [3] */
8646 uint32_t TP6
: 1; /*!< [4] Trusted Protect */
8647 uint32_t WP6
: 1; /*!< [5] Write Protect */
8648 uint32_t SP6
: 1; /*!< [6] Supervisor Protect */
8649 uint32_t RESERVED1
: 1; /*!< [7] */
8650 uint32_t TP5
: 1; /*!< [8] Trusted Protect */
8651 uint32_t WP5
: 1; /*!< [9] Write Protect */
8652 uint32_t SP5
: 1; /*!< [10] Supervisor Protect */
8653 uint32_t RESERVED2
: 1; /*!< [11] */
8654 uint32_t TP4
: 1; /*!< [12] Trusted Protect */
8655 uint32_t WP4
: 1; /*!< [13] Write Protect */
8656 uint32_t SP4
: 1; /*!< [14] Supervisor Protect */
8657 uint32_t RESERVED3
: 1; /*!< [15] */
8658 uint32_t TP3
: 1; /*!< [16] Trusted Protect */
8659 uint32_t WP3
: 1; /*!< [17] Write Protect */
8660 uint32_t SP3
: 1; /*!< [18] Supervisor Protect */
8661 uint32_t RESERVED4
: 1; /*!< [19] */
8662 uint32_t TP2
: 1; /*!< [20] Trusted Protect */
8663 uint32_t WP2
: 1; /*!< [21] Write Protect */
8664 uint32_t SP2
: 1; /*!< [22] Supervisor Protect */
8665 uint32_t RESERVED5
: 1; /*!< [23] */
8666 uint32_t TP1
: 1; /*!< [24] Trusted Protect */
8667 uint32_t WP1
: 1; /*!< [25] Write Protect */
8668 uint32_t SP1
: 1; /*!< [26] Supervisor Protect */
8669 uint32_t RESERVED6
: 1; /*!< [27] */
8670 uint32_t TP0
: 1; /*!< [28] Trusted Protect */
8671 uint32_t WP0
: 1; /*!< [29] Write Protect */
8672 uint32_t SP0
: 1; /*!< [30] Supervisor Protect */
8673 uint32_t RESERVED7
: 1; /*!< [31] */
8678 * @name Constants and macros for entire AIPS_PACRL register
8681 #define HW_AIPS_PACRL_ADDR(x) ((x) + 0x5CU)
8683 #define HW_AIPS_PACRL(x) (*(__IO hw_aips_pacrl_t *) HW_AIPS_PACRL_ADDR(x))
8684 #define HW_AIPS_PACRL_RD(x) (HW_AIPS_PACRL(x).U)
8685 #define HW_AIPS_PACRL_WR(x, v) (HW_AIPS_PACRL(x).U = (v))
8686 #define HW_AIPS_PACRL_SET(x, v) (HW_AIPS_PACRL_WR(x, HW_AIPS_PACRL_RD(x) | (v)))
8687 #define HW_AIPS_PACRL_CLR(x, v) (HW_AIPS_PACRL_WR(x, HW_AIPS_PACRL_RD(x) & ~(v)))
8688 #define HW_AIPS_PACRL_TOG(x, v) (HW_AIPS_PACRL_WR(x, HW_AIPS_PACRL_RD(x) ^ (v)))
8692 * Constants & macros for individual AIPS_PACRL bitfields
8696 * @name Register AIPS_PACRL, field TP7[0] (RW)
8698 * Determines whether the peripheral allows accesses from an untrusted master.
8699 * When this field is set and an access is attempted by an untrusted master, the
8700 * access terminates with an error response and no peripheral access initiates.
8703 * - 0 - Accesses from an untrusted master are allowed.
8704 * - 1 - Accesses from an untrusted master are not allowed.
8707 #define BP_AIPS_PACRL_TP7 (0U) /*!< Bit position for AIPS_PACRL_TP7. */
8708 #define BM_AIPS_PACRL_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRL_TP7. */
8709 #define BS_AIPS_PACRL_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRL_TP7. */
8711 /*! @brief Read current value of the AIPS_PACRL_TP7 field. */
8712 #define BR_AIPS_PACRL_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP7))
8714 /*! @brief Format value for bitfield AIPS_PACRL_TP7. */
8715 #define BF_AIPS_PACRL_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_TP7) & BM_AIPS_PACRL_TP7)
8717 /*! @brief Set the TP7 field to a new value. */
8718 #define BW_AIPS_PACRL_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP7) = (v))
8722 * @name Register AIPS_PACRL, field WP7[1] (RW)
8724 * Determines whether the peripheral allows write accesses. When this field is
8725 * set and a write access is attempted, access terminates with an error response
8726 * and no peripheral access initiates.
8729 * - 0 - This peripheral allows write accesses.
8730 * - 1 - This peripheral is write protected.
8733 #define BP_AIPS_PACRL_WP7 (1U) /*!< Bit position for AIPS_PACRL_WP7. */
8734 #define BM_AIPS_PACRL_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRL_WP7. */
8735 #define BS_AIPS_PACRL_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRL_WP7. */
8737 /*! @brief Read current value of the AIPS_PACRL_WP7 field. */
8738 #define BR_AIPS_PACRL_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP7))
8740 /*! @brief Format value for bitfield AIPS_PACRL_WP7. */
8741 #define BF_AIPS_PACRL_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_WP7) & BM_AIPS_PACRL_WP7)
8743 /*! @brief Set the WP7 field to a new value. */
8744 #define BW_AIPS_PACRL_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP7) = (v))
8748 * @name Register AIPS_PACRL, field SP7[2] (RW)
8750 * Determines whether the peripheral requires supervisor privilege level for
8751 * accesses. When this field is set, the master privilege level must indicate the
8752 * supervisor access attribute, and the MPRx[MPLn] control field for the master
8753 * must be set. If not, access terminates with an error response and no peripheral
8757 * - 0 - This peripheral does not require supervisor privilege level for
8759 * - 1 - This peripheral requires supervisor privilege level for accesses.
8762 #define BP_AIPS_PACRL_SP7 (2U) /*!< Bit position for AIPS_PACRL_SP7. */
8763 #define BM_AIPS_PACRL_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRL_SP7. */
8764 #define BS_AIPS_PACRL_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRL_SP7. */
8766 /*! @brief Read current value of the AIPS_PACRL_SP7 field. */
8767 #define BR_AIPS_PACRL_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP7))
8769 /*! @brief Format value for bitfield AIPS_PACRL_SP7. */
8770 #define BF_AIPS_PACRL_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_SP7) & BM_AIPS_PACRL_SP7)
8772 /*! @brief Set the SP7 field to a new value. */
8773 #define BW_AIPS_PACRL_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP7) = (v))
8777 * @name Register AIPS_PACRL, field TP6[4] (RW)
8779 * Determines whether the peripheral allows accesses from an untrusted master.
8780 * When this field is set and an access is attempted by an untrusted master, the
8781 * access terminates with an error response and no peripheral access initiates.
8784 * - 0 - Accesses from an untrusted master are allowed.
8785 * - 1 - Accesses from an untrusted master are not allowed.
8788 #define BP_AIPS_PACRL_TP6 (4U) /*!< Bit position for AIPS_PACRL_TP6. */
8789 #define BM_AIPS_PACRL_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRL_TP6. */
8790 #define BS_AIPS_PACRL_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRL_TP6. */
8792 /*! @brief Read current value of the AIPS_PACRL_TP6 field. */
8793 #define BR_AIPS_PACRL_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP6))
8795 /*! @brief Format value for bitfield AIPS_PACRL_TP6. */
8796 #define BF_AIPS_PACRL_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_TP6) & BM_AIPS_PACRL_TP6)
8798 /*! @brief Set the TP6 field to a new value. */
8799 #define BW_AIPS_PACRL_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP6) = (v))
8803 * @name Register AIPS_PACRL, field WP6[5] (RW)
8805 * Determines whether the peripheral allows write accesses. When this field is
8806 * set and a write access is attempted, access terminates with an error response
8807 * and no peripheral access initiates.
8810 * - 0 - This peripheral allows write accesses.
8811 * - 1 - This peripheral is write protected.
8814 #define BP_AIPS_PACRL_WP6 (5U) /*!< Bit position for AIPS_PACRL_WP6. */
8815 #define BM_AIPS_PACRL_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRL_WP6. */
8816 #define BS_AIPS_PACRL_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRL_WP6. */
8818 /*! @brief Read current value of the AIPS_PACRL_WP6 field. */
8819 #define BR_AIPS_PACRL_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP6))
8821 /*! @brief Format value for bitfield AIPS_PACRL_WP6. */
8822 #define BF_AIPS_PACRL_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_WP6) & BM_AIPS_PACRL_WP6)
8824 /*! @brief Set the WP6 field to a new value. */
8825 #define BW_AIPS_PACRL_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP6) = (v))
8829 * @name Register AIPS_PACRL, field SP6[6] (RW)
8831 * Determines whether the peripheral requires supervisor privilege level for
8832 * accesses. When this field is set, the master privilege level must indicate the
8833 * supervisor access attribute, and the MPRx[MPLn] control field for the master
8834 * must be set. If not, access terminates with an error response and no peripheral
8838 * - 0 - This peripheral does not require supervisor privilege level for
8840 * - 1 - This peripheral requires supervisor privilege level for accesses.
8843 #define BP_AIPS_PACRL_SP6 (6U) /*!< Bit position for AIPS_PACRL_SP6. */
8844 #define BM_AIPS_PACRL_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRL_SP6. */
8845 #define BS_AIPS_PACRL_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRL_SP6. */
8847 /*! @brief Read current value of the AIPS_PACRL_SP6 field. */
8848 #define BR_AIPS_PACRL_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP6))
8850 /*! @brief Format value for bitfield AIPS_PACRL_SP6. */
8851 #define BF_AIPS_PACRL_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_SP6) & BM_AIPS_PACRL_SP6)
8853 /*! @brief Set the SP6 field to a new value. */
8854 #define BW_AIPS_PACRL_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP6) = (v))
8858 * @name Register AIPS_PACRL, field TP5[8] (RW)
8860 * Determines whether the peripheral allows accesses from an untrusted master.
8861 * When this field is set and an access is attempted by an untrusted master, the
8862 * access terminates with an error response and no peripheral access initiates.
8865 * - 0 - Accesses from an untrusted master are allowed.
8866 * - 1 - Accesses from an untrusted master are not allowed.
8869 #define BP_AIPS_PACRL_TP5 (8U) /*!< Bit position for AIPS_PACRL_TP5. */
8870 #define BM_AIPS_PACRL_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRL_TP5. */
8871 #define BS_AIPS_PACRL_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRL_TP5. */
8873 /*! @brief Read current value of the AIPS_PACRL_TP5 field. */
8874 #define BR_AIPS_PACRL_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP5))
8876 /*! @brief Format value for bitfield AIPS_PACRL_TP5. */
8877 #define BF_AIPS_PACRL_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_TP5) & BM_AIPS_PACRL_TP5)
8879 /*! @brief Set the TP5 field to a new value. */
8880 #define BW_AIPS_PACRL_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP5) = (v))
8884 * @name Register AIPS_PACRL, field WP5[9] (RW)
8886 * Determines whether the peripheral allows write accesses. When this field is
8887 * set and a write access is attempted, access terminates with an error response
8888 * and no peripheral access initiates.
8891 * - 0 - This peripheral allows write accesses.
8892 * - 1 - This peripheral is write protected.
8895 #define BP_AIPS_PACRL_WP5 (9U) /*!< Bit position for AIPS_PACRL_WP5. */
8896 #define BM_AIPS_PACRL_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRL_WP5. */
8897 #define BS_AIPS_PACRL_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRL_WP5. */
8899 /*! @brief Read current value of the AIPS_PACRL_WP5 field. */
8900 #define BR_AIPS_PACRL_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP5))
8902 /*! @brief Format value for bitfield AIPS_PACRL_WP5. */
8903 #define BF_AIPS_PACRL_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_WP5) & BM_AIPS_PACRL_WP5)
8905 /*! @brief Set the WP5 field to a new value. */
8906 #define BW_AIPS_PACRL_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP5) = (v))
8910 * @name Register AIPS_PACRL, field SP5[10] (RW)
8912 * Determines whether the peripheral requires supervisor privilege level for
8913 * accesses. When this field is set, the master privilege level must indicate the
8914 * supervisor access attribute, and the MPRx[MPLn] control field for the master
8915 * must be set. If not, access terminates with an error response and no peripheral
8919 * - 0 - This peripheral does not require supervisor privilege level for
8921 * - 1 - This peripheral requires supervisor privilege level for accesses.
8924 #define BP_AIPS_PACRL_SP5 (10U) /*!< Bit position for AIPS_PACRL_SP5. */
8925 #define BM_AIPS_PACRL_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRL_SP5. */
8926 #define BS_AIPS_PACRL_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRL_SP5. */
8928 /*! @brief Read current value of the AIPS_PACRL_SP5 field. */
8929 #define BR_AIPS_PACRL_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP5))
8931 /*! @brief Format value for bitfield AIPS_PACRL_SP5. */
8932 #define BF_AIPS_PACRL_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_SP5) & BM_AIPS_PACRL_SP5)
8934 /*! @brief Set the SP5 field to a new value. */
8935 #define BW_AIPS_PACRL_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP5) = (v))
8939 * @name Register AIPS_PACRL, field TP4[12] (RW)
8941 * Determines whether the peripheral allows accesses from an untrusted master.
8942 * When this bit is set and an access is attempted by an untrusted master, the
8943 * access terminates with an error response and no peripheral access initiates.
8946 * - 0 - Accesses from an untrusted master are allowed.
8947 * - 1 - Accesses from an untrusted master are not allowed.
8950 #define BP_AIPS_PACRL_TP4 (12U) /*!< Bit position for AIPS_PACRL_TP4. */
8951 #define BM_AIPS_PACRL_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRL_TP4. */
8952 #define BS_AIPS_PACRL_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRL_TP4. */
8954 /*! @brief Read current value of the AIPS_PACRL_TP4 field. */
8955 #define BR_AIPS_PACRL_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP4))
8957 /*! @brief Format value for bitfield AIPS_PACRL_TP4. */
8958 #define BF_AIPS_PACRL_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_TP4) & BM_AIPS_PACRL_TP4)
8960 /*! @brief Set the TP4 field to a new value. */
8961 #define BW_AIPS_PACRL_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP4) = (v))
8965 * @name Register AIPS_PACRL, field WP4[13] (RW)
8967 * Determines whether the peripheral allows write accesses. When this field is
8968 * set and a write access is attempted, access terminates with an error response
8969 * and no peripheral access initiates.
8972 * - 0 - This peripheral allows write accesses.
8973 * - 1 - This peripheral is write protected.
8976 #define BP_AIPS_PACRL_WP4 (13U) /*!< Bit position for AIPS_PACRL_WP4. */
8977 #define BM_AIPS_PACRL_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRL_WP4. */
8978 #define BS_AIPS_PACRL_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRL_WP4. */
8980 /*! @brief Read current value of the AIPS_PACRL_WP4 field. */
8981 #define BR_AIPS_PACRL_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP4))
8983 /*! @brief Format value for bitfield AIPS_PACRL_WP4. */
8984 #define BF_AIPS_PACRL_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_WP4) & BM_AIPS_PACRL_WP4)
8986 /*! @brief Set the WP4 field to a new value. */
8987 #define BW_AIPS_PACRL_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP4) = (v))
8991 * @name Register AIPS_PACRL, field SP4[14] (RW)
8993 * Determines whether the peripheral requires supervisor privilege level for
8994 * access. When this bit is set, the master privilege level must indicate the
8995 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
8996 * set. If not, access terminates with an error response and no peripheral access
9000 * - 0 - This peripheral does not require supervisor privilege level for
9002 * - 1 - This peripheral requires supervisor privilege level for accesses.
9005 #define BP_AIPS_PACRL_SP4 (14U) /*!< Bit position for AIPS_PACRL_SP4. */
9006 #define BM_AIPS_PACRL_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRL_SP4. */
9007 #define BS_AIPS_PACRL_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRL_SP4. */
9009 /*! @brief Read current value of the AIPS_PACRL_SP4 field. */
9010 #define BR_AIPS_PACRL_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP4))
9012 /*! @brief Format value for bitfield AIPS_PACRL_SP4. */
9013 #define BF_AIPS_PACRL_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_SP4) & BM_AIPS_PACRL_SP4)
9015 /*! @brief Set the SP4 field to a new value. */
9016 #define BW_AIPS_PACRL_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP4) = (v))
9020 * @name Register AIPS_PACRL, field TP3[16] (RW)
9022 * Determines whether the peripheral allows accesses from an untrusted master.
9023 * When this field is set and an access is attempted by an untrusted master, the
9024 * access terminates with an error response and no peripheral access initiates.
9027 * - 0 - Accesses from an untrusted master are allowed.
9028 * - 1 - Accesses from an untrusted master are not allowed.
9031 #define BP_AIPS_PACRL_TP3 (16U) /*!< Bit position for AIPS_PACRL_TP3. */
9032 #define BM_AIPS_PACRL_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRL_TP3. */
9033 #define BS_AIPS_PACRL_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRL_TP3. */
9035 /*! @brief Read current value of the AIPS_PACRL_TP3 field. */
9036 #define BR_AIPS_PACRL_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP3))
9038 /*! @brief Format value for bitfield AIPS_PACRL_TP3. */
9039 #define BF_AIPS_PACRL_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_TP3) & BM_AIPS_PACRL_TP3)
9041 /*! @brief Set the TP3 field to a new value. */
9042 #define BW_AIPS_PACRL_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP3) = (v))
9046 * @name Register AIPS_PACRL, field WP3[17] (RW)
9048 * Determines whether the peripheral allows write accesss. When this bit is set
9049 * and a write access is attempted, access terminates with an error response and
9050 * no peripheral access initiates.
9053 * - 0 - This peripheral allows write accesses.
9054 * - 1 - This peripheral is write protected.
9057 #define BP_AIPS_PACRL_WP3 (17U) /*!< Bit position for AIPS_PACRL_WP3. */
9058 #define BM_AIPS_PACRL_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRL_WP3. */
9059 #define BS_AIPS_PACRL_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRL_WP3. */
9061 /*! @brief Read current value of the AIPS_PACRL_WP3 field. */
9062 #define BR_AIPS_PACRL_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP3))
9064 /*! @brief Format value for bitfield AIPS_PACRL_WP3. */
9065 #define BF_AIPS_PACRL_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_WP3) & BM_AIPS_PACRL_WP3)
9067 /*! @brief Set the WP3 field to a new value. */
9068 #define BW_AIPS_PACRL_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP3) = (v))
9072 * @name Register AIPS_PACRL, field SP3[18] (RW)
9074 * Determines whether the peripheral requires supervisor privilege level for
9075 * accesses. When this field is set, the master privilege level must indicate the
9076 * supervisor access attribute, and the MPRx[MPLn] control field for the master
9077 * must be set. If not, access terminates with an error response and no peripheral
9081 * - 0 - This peripheral does not require supervisor privilege level for
9083 * - 1 - This peripheral requires supervisor privilege level for accesses.
9086 #define BP_AIPS_PACRL_SP3 (18U) /*!< Bit position for AIPS_PACRL_SP3. */
9087 #define BM_AIPS_PACRL_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRL_SP3. */
9088 #define BS_AIPS_PACRL_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRL_SP3. */
9090 /*! @brief Read current value of the AIPS_PACRL_SP3 field. */
9091 #define BR_AIPS_PACRL_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP3))
9093 /*! @brief Format value for bitfield AIPS_PACRL_SP3. */
9094 #define BF_AIPS_PACRL_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_SP3) & BM_AIPS_PACRL_SP3)
9096 /*! @brief Set the SP3 field to a new value. */
9097 #define BW_AIPS_PACRL_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP3) = (v))
9101 * @name Register AIPS_PACRL, field TP2[20] (RW)
9103 * Determines whether the peripheral allows accesses from an untrusted master.
9104 * When this bit is set and an access is attempted by an untrusted master, the
9105 * access terminates with an error response and no peripheral access initiates.
9108 * - 0 - Accesses from an untrusted master are allowed.
9109 * - 1 - Accesses from an untrusted master are not allowed.
9112 #define BP_AIPS_PACRL_TP2 (20U) /*!< Bit position for AIPS_PACRL_TP2. */
9113 #define BM_AIPS_PACRL_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRL_TP2. */
9114 #define BS_AIPS_PACRL_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRL_TP2. */
9116 /*! @brief Read current value of the AIPS_PACRL_TP2 field. */
9117 #define BR_AIPS_PACRL_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP2))
9119 /*! @brief Format value for bitfield AIPS_PACRL_TP2. */
9120 #define BF_AIPS_PACRL_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_TP2) & BM_AIPS_PACRL_TP2)
9122 /*! @brief Set the TP2 field to a new value. */
9123 #define BW_AIPS_PACRL_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP2) = (v))
9127 * @name Register AIPS_PACRL, field WP2[21] (RW)
9129 * Determines whether the peripheral allows write accesses. When this field is
9130 * set and a write access is attempted, access terminates with an error response
9131 * and no peripheral access initiates.
9134 * - 0 - This peripheral allows write accesses.
9135 * - 1 - This peripheral is write protected.
9138 #define BP_AIPS_PACRL_WP2 (21U) /*!< Bit position for AIPS_PACRL_WP2. */
9139 #define BM_AIPS_PACRL_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRL_WP2. */
9140 #define BS_AIPS_PACRL_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRL_WP2. */
9142 /*! @brief Read current value of the AIPS_PACRL_WP2 field. */
9143 #define BR_AIPS_PACRL_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP2))
9145 /*! @brief Format value for bitfield AIPS_PACRL_WP2. */
9146 #define BF_AIPS_PACRL_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_WP2) & BM_AIPS_PACRL_WP2)
9148 /*! @brief Set the WP2 field to a new value. */
9149 #define BW_AIPS_PACRL_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP2) = (v))
9153 * @name Register AIPS_PACRL, field SP2[22] (RW)
9155 * Determines whether the peripheral requires supervisor privilege level for
9156 * access. When this bit is set, the master privilege level must indicate the
9157 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
9158 * set. If not, access terminates with an error response and no peripheral access
9162 * - 0 - This peripheral does not require supervisor privilege level for
9164 * - 1 - This peripheral requires supervisor privilege level for accesses.
9167 #define BP_AIPS_PACRL_SP2 (22U) /*!< Bit position for AIPS_PACRL_SP2. */
9168 #define BM_AIPS_PACRL_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRL_SP2. */
9169 #define BS_AIPS_PACRL_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRL_SP2. */
9171 /*! @brief Read current value of the AIPS_PACRL_SP2 field. */
9172 #define BR_AIPS_PACRL_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP2))
9174 /*! @brief Format value for bitfield AIPS_PACRL_SP2. */
9175 #define BF_AIPS_PACRL_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_SP2) & BM_AIPS_PACRL_SP2)
9177 /*! @brief Set the SP2 field to a new value. */
9178 #define BW_AIPS_PACRL_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP2) = (v))
9182 * @name Register AIPS_PACRL, field TP1[24] (RW)
9184 * Determines whether the peripheral allows accesses from an untrusted master.
9185 * When this field is set and an access is attempted by an untrusted master, the
9186 * access terminates with an error response and no peripheral access initiates.
9189 * - 0 - Accesses from an untrusted master are allowed.
9190 * - 1 - Accesses from an untrusted master are not allowed.
9193 #define BP_AIPS_PACRL_TP1 (24U) /*!< Bit position for AIPS_PACRL_TP1. */
9194 #define BM_AIPS_PACRL_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRL_TP1. */
9195 #define BS_AIPS_PACRL_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRL_TP1. */
9197 /*! @brief Read current value of the AIPS_PACRL_TP1 field. */
9198 #define BR_AIPS_PACRL_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP1))
9200 /*! @brief Format value for bitfield AIPS_PACRL_TP1. */
9201 #define BF_AIPS_PACRL_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_TP1) & BM_AIPS_PACRL_TP1)
9203 /*! @brief Set the TP1 field to a new value. */
9204 #define BW_AIPS_PACRL_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP1) = (v))
9208 * @name Register AIPS_PACRL, field WP1[25] (RW)
9210 * Determines whether the peripheral allows write accesses. When this field is
9211 * set and a write access is attempted, access terminates with an error response
9212 * and no peripheral access initiates.
9215 * - 0 - This peripheral allows write accesses.
9216 * - 1 - This peripheral is write protected.
9219 #define BP_AIPS_PACRL_WP1 (25U) /*!< Bit position for AIPS_PACRL_WP1. */
9220 #define BM_AIPS_PACRL_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRL_WP1. */
9221 #define BS_AIPS_PACRL_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRL_WP1. */
9223 /*! @brief Read current value of the AIPS_PACRL_WP1 field. */
9224 #define BR_AIPS_PACRL_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP1))
9226 /*! @brief Format value for bitfield AIPS_PACRL_WP1. */
9227 #define BF_AIPS_PACRL_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_WP1) & BM_AIPS_PACRL_WP1)
9229 /*! @brief Set the WP1 field to a new value. */
9230 #define BW_AIPS_PACRL_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP1) = (v))
9234 * @name Register AIPS_PACRL, field SP1[26] (RW)
9236 * Determines whether the peripheral requires supervisor privilege level for
9237 * access. When this field is set, the master privilege level must indicate the
9238 * supervisor access attribute, and the MPRx[MPLn] control field for the master must
9239 * be set. If not, access terminates with an error response and no peripheral
9243 * - 0 - This peripheral does not require supervisor privilege level for
9245 * - 1 - This peripheral requires supervisor privilege level for accesses.
9248 #define BP_AIPS_PACRL_SP1 (26U) /*!< Bit position for AIPS_PACRL_SP1. */
9249 #define BM_AIPS_PACRL_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRL_SP1. */
9250 #define BS_AIPS_PACRL_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRL_SP1. */
9252 /*! @brief Read current value of the AIPS_PACRL_SP1 field. */
9253 #define BR_AIPS_PACRL_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP1))
9255 /*! @brief Format value for bitfield AIPS_PACRL_SP1. */
9256 #define BF_AIPS_PACRL_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_SP1) & BM_AIPS_PACRL_SP1)
9258 /*! @brief Set the SP1 field to a new value. */
9259 #define BW_AIPS_PACRL_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP1) = (v))
9263 * @name Register AIPS_PACRL, field TP0[28] (RW)
9265 * Determines whether the peripheral allows accesses from an untrusted master.
9266 * When this bit is set and an access is attempted by an untrusted master, the
9267 * access terminates with an error response and no peripheral access initiates.
9270 * - 0 - Accesses from an untrusted master are allowed.
9271 * - 1 - Accesses from an untrusted master are not allowed.
9274 #define BP_AIPS_PACRL_TP0 (28U) /*!< Bit position for AIPS_PACRL_TP0. */
9275 #define BM_AIPS_PACRL_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRL_TP0. */
9276 #define BS_AIPS_PACRL_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRL_TP0. */
9278 /*! @brief Read current value of the AIPS_PACRL_TP0 field. */
9279 #define BR_AIPS_PACRL_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP0))
9281 /*! @brief Format value for bitfield AIPS_PACRL_TP0. */
9282 #define BF_AIPS_PACRL_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_TP0) & BM_AIPS_PACRL_TP0)
9284 /*! @brief Set the TP0 field to a new value. */
9285 #define BW_AIPS_PACRL_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP0) = (v))
9289 * @name Register AIPS_PACRL, field WP0[29] (RW)
9291 * Determines whether the peripheral allows write accesses. When this field is
9292 * set and a write access is attempted, access terminates with an error response
9293 * and no peripheral access initiates.
9296 * - 0 - This peripheral allows write accesses.
9297 * - 1 - This peripheral is write protected.
9300 #define BP_AIPS_PACRL_WP0 (29U) /*!< Bit position for AIPS_PACRL_WP0. */
9301 #define BM_AIPS_PACRL_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRL_WP0. */
9302 #define BS_AIPS_PACRL_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRL_WP0. */
9304 /*! @brief Read current value of the AIPS_PACRL_WP0 field. */
9305 #define BR_AIPS_PACRL_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP0))
9307 /*! @brief Format value for bitfield AIPS_PACRL_WP0. */
9308 #define BF_AIPS_PACRL_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_WP0) & BM_AIPS_PACRL_WP0)
9310 /*! @brief Set the WP0 field to a new value. */
9311 #define BW_AIPS_PACRL_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP0) = (v))
9315 * @name Register AIPS_PACRL, field SP0[30] (RW)
9317 * Determines whether the peripheral requires supervisor privilege level for
9318 * accesses. When this field is set, the master privilege level must indicate the
9319 * supervisor access attribute, and the MPRx[MPLn] control field for the master
9320 * must be set. If not, access terminates with an error response and no peripheral
9324 * - 0 - This peripheral does not require supervisor privilege level for
9326 * - 1 - This peripheral requires supervisor privilege level for accesses.
9329 #define BP_AIPS_PACRL_SP0 (30U) /*!< Bit position for AIPS_PACRL_SP0. */
9330 #define BM_AIPS_PACRL_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRL_SP0. */
9331 #define BS_AIPS_PACRL_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRL_SP0. */
9333 /*! @brief Read current value of the AIPS_PACRL_SP0 field. */
9334 #define BR_AIPS_PACRL_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP0))
9336 /*! @brief Format value for bitfield AIPS_PACRL_SP0. */
9337 #define BF_AIPS_PACRL_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_SP0) & BM_AIPS_PACRL_SP0)
9339 /*! @brief Set the SP0 field to a new value. */
9340 #define BW_AIPS_PACRL_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP0) = (v))
9343 /*******************************************************************************
9344 * HW_AIPS_PACRM - Peripheral Access Control Register
9345 ******************************************************************************/
9348 * @brief HW_AIPS_PACRM - Peripheral Access Control Register (RW)
9350 * Reset value: 0x44444444U
9352 * This section describes PACR registers E-P, which control peripheral slots
9353 * 32-127. See PACRPeripheral Access Control Register for the description of these
9356 typedef union _hw_aips_pacrm
9359 struct _hw_aips_pacrm_bitfields
9361 uint32_t TP7
: 1; /*!< [0] Trusted Protect */
9362 uint32_t WP7
: 1; /*!< [1] Write Protect */
9363 uint32_t SP7
: 1; /*!< [2] Supervisor Protect */
9364 uint32_t RESERVED0
: 1; /*!< [3] */
9365 uint32_t TP6
: 1; /*!< [4] Trusted Protect */
9366 uint32_t WP6
: 1; /*!< [5] Write Protect */
9367 uint32_t SP6
: 1; /*!< [6] Supervisor Protect */
9368 uint32_t RESERVED1
: 1; /*!< [7] */
9369 uint32_t TP5
: 1; /*!< [8] Trusted Protect */
9370 uint32_t WP5
: 1; /*!< [9] Write Protect */
9371 uint32_t SP5
: 1; /*!< [10] Supervisor Protect */
9372 uint32_t RESERVED2
: 1; /*!< [11] */
9373 uint32_t TP4
: 1; /*!< [12] Trusted Protect */
9374 uint32_t WP4
: 1; /*!< [13] Write Protect */
9375 uint32_t SP4
: 1; /*!< [14] Supervisor Protect */
9376 uint32_t RESERVED3
: 1; /*!< [15] */
9377 uint32_t TP3
: 1; /*!< [16] Trusted Protect */
9378 uint32_t WP3
: 1; /*!< [17] Write Protect */
9379 uint32_t SP3
: 1; /*!< [18] Supervisor Protect */
9380 uint32_t RESERVED4
: 1; /*!< [19] */
9381 uint32_t TP2
: 1; /*!< [20] Trusted Protect */
9382 uint32_t WP2
: 1; /*!< [21] Write Protect */
9383 uint32_t SP2
: 1; /*!< [22] Supervisor Protect */
9384 uint32_t RESERVED5
: 1; /*!< [23] */
9385 uint32_t TP1
: 1; /*!< [24] Trusted Protect */
9386 uint32_t WP1
: 1; /*!< [25] Write Protect */
9387 uint32_t SP1
: 1; /*!< [26] Supervisor Protect */
9388 uint32_t RESERVED6
: 1; /*!< [27] */
9389 uint32_t TP0
: 1; /*!< [28] Trusted Protect */
9390 uint32_t WP0
: 1; /*!< [29] Write Protect */
9391 uint32_t SP0
: 1; /*!< [30] Supervisor Protect */
9392 uint32_t RESERVED7
: 1; /*!< [31] */
9397 * @name Constants and macros for entire AIPS_PACRM register
9400 #define HW_AIPS_PACRM_ADDR(x) ((x) + 0x60U)
9402 #define HW_AIPS_PACRM(x) (*(__IO hw_aips_pacrm_t *) HW_AIPS_PACRM_ADDR(x))
9403 #define HW_AIPS_PACRM_RD(x) (HW_AIPS_PACRM(x).U)
9404 #define HW_AIPS_PACRM_WR(x, v) (HW_AIPS_PACRM(x).U = (v))
9405 #define HW_AIPS_PACRM_SET(x, v) (HW_AIPS_PACRM_WR(x, HW_AIPS_PACRM_RD(x) | (v)))
9406 #define HW_AIPS_PACRM_CLR(x, v) (HW_AIPS_PACRM_WR(x, HW_AIPS_PACRM_RD(x) & ~(v)))
9407 #define HW_AIPS_PACRM_TOG(x, v) (HW_AIPS_PACRM_WR(x, HW_AIPS_PACRM_RD(x) ^ (v)))
9411 * Constants & macros for individual AIPS_PACRM bitfields
9415 * @name Register AIPS_PACRM, field TP7[0] (RW)
9417 * Determines whether the peripheral allows accesses from an untrusted master.
9418 * When this field is set and an access is attempted by an untrusted master, the
9419 * access terminates with an error response and no peripheral access initiates.
9422 * - 0 - Accesses from an untrusted master are allowed.
9423 * - 1 - Accesses from an untrusted master are not allowed.
9426 #define BP_AIPS_PACRM_TP7 (0U) /*!< Bit position for AIPS_PACRM_TP7. */
9427 #define BM_AIPS_PACRM_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRM_TP7. */
9428 #define BS_AIPS_PACRM_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRM_TP7. */
9430 /*! @brief Read current value of the AIPS_PACRM_TP7 field. */
9431 #define BR_AIPS_PACRM_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP7))
9433 /*! @brief Format value for bitfield AIPS_PACRM_TP7. */
9434 #define BF_AIPS_PACRM_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_TP7) & BM_AIPS_PACRM_TP7)
9436 /*! @brief Set the TP7 field to a new value. */
9437 #define BW_AIPS_PACRM_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP7) = (v))
9441 * @name Register AIPS_PACRM, field WP7[1] (RW)
9443 * Determines whether the peripheral allows write accesses. When this field is
9444 * set and a write access is attempted, access terminates with an error response
9445 * and no peripheral access initiates.
9448 * - 0 - This peripheral allows write accesses.
9449 * - 1 - This peripheral is write protected.
9452 #define BP_AIPS_PACRM_WP7 (1U) /*!< Bit position for AIPS_PACRM_WP7. */
9453 #define BM_AIPS_PACRM_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRM_WP7. */
9454 #define BS_AIPS_PACRM_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRM_WP7. */
9456 /*! @brief Read current value of the AIPS_PACRM_WP7 field. */
9457 #define BR_AIPS_PACRM_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP7))
9459 /*! @brief Format value for bitfield AIPS_PACRM_WP7. */
9460 #define BF_AIPS_PACRM_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_WP7) & BM_AIPS_PACRM_WP7)
9462 /*! @brief Set the WP7 field to a new value. */
9463 #define BW_AIPS_PACRM_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP7) = (v))
9467 * @name Register AIPS_PACRM, field SP7[2] (RW)
9469 * Determines whether the peripheral requires supervisor privilege level for
9470 * accesses. When this field is set, the master privilege level must indicate the
9471 * supervisor access attribute, and the MPRx[MPLn] control field for the master
9472 * must be set. If not, access terminates with an error response and no peripheral
9476 * - 0 - This peripheral does not require supervisor privilege level for
9478 * - 1 - This peripheral requires supervisor privilege level for accesses.
9481 #define BP_AIPS_PACRM_SP7 (2U) /*!< Bit position for AIPS_PACRM_SP7. */
9482 #define BM_AIPS_PACRM_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRM_SP7. */
9483 #define BS_AIPS_PACRM_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRM_SP7. */
9485 /*! @brief Read current value of the AIPS_PACRM_SP7 field. */
9486 #define BR_AIPS_PACRM_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP7))
9488 /*! @brief Format value for bitfield AIPS_PACRM_SP7. */
9489 #define BF_AIPS_PACRM_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_SP7) & BM_AIPS_PACRM_SP7)
9491 /*! @brief Set the SP7 field to a new value. */
9492 #define BW_AIPS_PACRM_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP7) = (v))
9496 * @name Register AIPS_PACRM, field TP6[4] (RW)
9498 * Determines whether the peripheral allows accesses from an untrusted master.
9499 * When this field is set and an access is attempted by an untrusted master, the
9500 * access terminates with an error response and no peripheral access initiates.
9503 * - 0 - Accesses from an untrusted master are allowed.
9504 * - 1 - Accesses from an untrusted master are not allowed.
9507 #define BP_AIPS_PACRM_TP6 (4U) /*!< Bit position for AIPS_PACRM_TP6. */
9508 #define BM_AIPS_PACRM_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRM_TP6. */
9509 #define BS_AIPS_PACRM_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRM_TP6. */
9511 /*! @brief Read current value of the AIPS_PACRM_TP6 field. */
9512 #define BR_AIPS_PACRM_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP6))
9514 /*! @brief Format value for bitfield AIPS_PACRM_TP6. */
9515 #define BF_AIPS_PACRM_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_TP6) & BM_AIPS_PACRM_TP6)
9517 /*! @brief Set the TP6 field to a new value. */
9518 #define BW_AIPS_PACRM_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP6) = (v))
9522 * @name Register AIPS_PACRM, field WP6[5] (RW)
9524 * Determines whether the peripheral allows write accesses. When this field is
9525 * set and a write access is attempted, access terminates with an error response
9526 * and no peripheral access initiates.
9529 * - 0 - This peripheral allows write accesses.
9530 * - 1 - This peripheral is write protected.
9533 #define BP_AIPS_PACRM_WP6 (5U) /*!< Bit position for AIPS_PACRM_WP6. */
9534 #define BM_AIPS_PACRM_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRM_WP6. */
9535 #define BS_AIPS_PACRM_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRM_WP6. */
9537 /*! @brief Read current value of the AIPS_PACRM_WP6 field. */
9538 #define BR_AIPS_PACRM_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP6))
9540 /*! @brief Format value for bitfield AIPS_PACRM_WP6. */
9541 #define BF_AIPS_PACRM_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_WP6) & BM_AIPS_PACRM_WP6)
9543 /*! @brief Set the WP6 field to a new value. */
9544 #define BW_AIPS_PACRM_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP6) = (v))
9548 * @name Register AIPS_PACRM, field SP6[6] (RW)
9550 * Determines whether the peripheral requires supervisor privilege level for
9551 * accesses. When this field is set, the master privilege level must indicate the
9552 * supervisor access attribute, and the MPRx[MPLn] control field for the master
9553 * must be set. If not, access terminates with an error response and no peripheral
9557 * - 0 - This peripheral does not require supervisor privilege level for
9559 * - 1 - This peripheral requires supervisor privilege level for accesses.
9562 #define BP_AIPS_PACRM_SP6 (6U) /*!< Bit position for AIPS_PACRM_SP6. */
9563 #define BM_AIPS_PACRM_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRM_SP6. */
9564 #define BS_AIPS_PACRM_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRM_SP6. */
9566 /*! @brief Read current value of the AIPS_PACRM_SP6 field. */
9567 #define BR_AIPS_PACRM_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP6))
9569 /*! @brief Format value for bitfield AIPS_PACRM_SP6. */
9570 #define BF_AIPS_PACRM_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_SP6) & BM_AIPS_PACRM_SP6)
9572 /*! @brief Set the SP6 field to a new value. */
9573 #define BW_AIPS_PACRM_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP6) = (v))
9577 * @name Register AIPS_PACRM, field TP5[8] (RW)
9579 * Determines whether the peripheral allows accesses from an untrusted master.
9580 * When this field is set and an access is attempted by an untrusted master, the
9581 * access terminates with an error response and no peripheral access initiates.
9584 * - 0 - Accesses from an untrusted master are allowed.
9585 * - 1 - Accesses from an untrusted master are not allowed.
9588 #define BP_AIPS_PACRM_TP5 (8U) /*!< Bit position for AIPS_PACRM_TP5. */
9589 #define BM_AIPS_PACRM_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRM_TP5. */
9590 #define BS_AIPS_PACRM_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRM_TP5. */
9592 /*! @brief Read current value of the AIPS_PACRM_TP5 field. */
9593 #define BR_AIPS_PACRM_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP5))
9595 /*! @brief Format value for bitfield AIPS_PACRM_TP5. */
9596 #define BF_AIPS_PACRM_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_TP5) & BM_AIPS_PACRM_TP5)
9598 /*! @brief Set the TP5 field to a new value. */
9599 #define BW_AIPS_PACRM_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP5) = (v))
9603 * @name Register AIPS_PACRM, field WP5[9] (RW)
9605 * Determines whether the peripheral allows write accesses. When this field is
9606 * set and a write access is attempted, access terminates with an error response
9607 * and no peripheral access initiates.
9610 * - 0 - This peripheral allows write accesses.
9611 * - 1 - This peripheral is write protected.
9614 #define BP_AIPS_PACRM_WP5 (9U) /*!< Bit position for AIPS_PACRM_WP5. */
9615 #define BM_AIPS_PACRM_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRM_WP5. */
9616 #define BS_AIPS_PACRM_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRM_WP5. */
9618 /*! @brief Read current value of the AIPS_PACRM_WP5 field. */
9619 #define BR_AIPS_PACRM_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP5))
9621 /*! @brief Format value for bitfield AIPS_PACRM_WP5. */
9622 #define BF_AIPS_PACRM_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_WP5) & BM_AIPS_PACRM_WP5)
9624 /*! @brief Set the WP5 field to a new value. */
9625 #define BW_AIPS_PACRM_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP5) = (v))
9629 * @name Register AIPS_PACRM, field SP5[10] (RW)
9631 * Determines whether the peripheral requires supervisor privilege level for
9632 * accesses. When this field is set, the master privilege level must indicate the
9633 * supervisor access attribute, and the MPRx[MPLn] control field for the master
9634 * must be set. If not, access terminates with an error response and no peripheral
9638 * - 0 - This peripheral does not require supervisor privilege level for
9640 * - 1 - This peripheral requires supervisor privilege level for accesses.
9643 #define BP_AIPS_PACRM_SP5 (10U) /*!< Bit position for AIPS_PACRM_SP5. */
9644 #define BM_AIPS_PACRM_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRM_SP5. */
9645 #define BS_AIPS_PACRM_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRM_SP5. */
9647 /*! @brief Read current value of the AIPS_PACRM_SP5 field. */
9648 #define BR_AIPS_PACRM_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP5))
9650 /*! @brief Format value for bitfield AIPS_PACRM_SP5. */
9651 #define BF_AIPS_PACRM_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_SP5) & BM_AIPS_PACRM_SP5)
9653 /*! @brief Set the SP5 field to a new value. */
9654 #define BW_AIPS_PACRM_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP5) = (v))
9658 * @name Register AIPS_PACRM, field TP4[12] (RW)
9660 * Determines whether the peripheral allows accesses from an untrusted master.
9661 * When this bit is set and an access is attempted by an untrusted master, the
9662 * access terminates with an error response and no peripheral access initiates.
9665 * - 0 - Accesses from an untrusted master are allowed.
9666 * - 1 - Accesses from an untrusted master are not allowed.
9669 #define BP_AIPS_PACRM_TP4 (12U) /*!< Bit position for AIPS_PACRM_TP4. */
9670 #define BM_AIPS_PACRM_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRM_TP4. */
9671 #define BS_AIPS_PACRM_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRM_TP4. */
9673 /*! @brief Read current value of the AIPS_PACRM_TP4 field. */
9674 #define BR_AIPS_PACRM_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP4))
9676 /*! @brief Format value for bitfield AIPS_PACRM_TP4. */
9677 #define BF_AIPS_PACRM_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_TP4) & BM_AIPS_PACRM_TP4)
9679 /*! @brief Set the TP4 field to a new value. */
9680 #define BW_AIPS_PACRM_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP4) = (v))
9684 * @name Register AIPS_PACRM, field WP4[13] (RW)
9686 * Determines whether the peripheral allows write accesses. When this field is
9687 * set and a write access is attempted, access terminates with an error response
9688 * and no peripheral access initiates.
9691 * - 0 - This peripheral allows write accesses.
9692 * - 1 - This peripheral is write protected.
9695 #define BP_AIPS_PACRM_WP4 (13U) /*!< Bit position for AIPS_PACRM_WP4. */
9696 #define BM_AIPS_PACRM_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRM_WP4. */
9697 #define BS_AIPS_PACRM_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRM_WP4. */
9699 /*! @brief Read current value of the AIPS_PACRM_WP4 field. */
9700 #define BR_AIPS_PACRM_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP4))
9702 /*! @brief Format value for bitfield AIPS_PACRM_WP4. */
9703 #define BF_AIPS_PACRM_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_WP4) & BM_AIPS_PACRM_WP4)
9705 /*! @brief Set the WP4 field to a new value. */
9706 #define BW_AIPS_PACRM_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP4) = (v))
9710 * @name Register AIPS_PACRM, field SP4[14] (RW)
9712 * Determines whether the peripheral requires supervisor privilege level for
9713 * access. When this bit is set, the master privilege level must indicate the
9714 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
9715 * set. If not, access terminates with an error response and no peripheral access
9719 * - 0 - This peripheral does not require supervisor privilege level for
9721 * - 1 - This peripheral requires supervisor privilege level for accesses.
9724 #define BP_AIPS_PACRM_SP4 (14U) /*!< Bit position for AIPS_PACRM_SP4. */
9725 #define BM_AIPS_PACRM_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRM_SP4. */
9726 #define BS_AIPS_PACRM_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRM_SP4. */
9728 /*! @brief Read current value of the AIPS_PACRM_SP4 field. */
9729 #define BR_AIPS_PACRM_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP4))
9731 /*! @brief Format value for bitfield AIPS_PACRM_SP4. */
9732 #define BF_AIPS_PACRM_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_SP4) & BM_AIPS_PACRM_SP4)
9734 /*! @brief Set the SP4 field to a new value. */
9735 #define BW_AIPS_PACRM_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP4) = (v))
9739 * @name Register AIPS_PACRM, field TP3[16] (RW)
9741 * Determines whether the peripheral allows accesses from an untrusted master.
9742 * When this field is set and an access is attempted by an untrusted master, the
9743 * access terminates with an error response and no peripheral access initiates.
9746 * - 0 - Accesses from an untrusted master are allowed.
9747 * - 1 - Accesses from an untrusted master are not allowed.
9750 #define BP_AIPS_PACRM_TP3 (16U) /*!< Bit position for AIPS_PACRM_TP3. */
9751 #define BM_AIPS_PACRM_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRM_TP3. */
9752 #define BS_AIPS_PACRM_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRM_TP3. */
9754 /*! @brief Read current value of the AIPS_PACRM_TP3 field. */
9755 #define BR_AIPS_PACRM_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP3))
9757 /*! @brief Format value for bitfield AIPS_PACRM_TP3. */
9758 #define BF_AIPS_PACRM_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_TP3) & BM_AIPS_PACRM_TP3)
9760 /*! @brief Set the TP3 field to a new value. */
9761 #define BW_AIPS_PACRM_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP3) = (v))
9765 * @name Register AIPS_PACRM, field WP3[17] (RW)
9767 * Determines whether the peripheral allows write accesss. When this bit is set
9768 * and a write access is attempted, access terminates with an error response and
9769 * no peripheral access initiates.
9772 * - 0 - This peripheral allows write accesses.
9773 * - 1 - This peripheral is write protected.
9776 #define BP_AIPS_PACRM_WP3 (17U) /*!< Bit position for AIPS_PACRM_WP3. */
9777 #define BM_AIPS_PACRM_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRM_WP3. */
9778 #define BS_AIPS_PACRM_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRM_WP3. */
9780 /*! @brief Read current value of the AIPS_PACRM_WP3 field. */
9781 #define BR_AIPS_PACRM_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP3))
9783 /*! @brief Format value for bitfield AIPS_PACRM_WP3. */
9784 #define BF_AIPS_PACRM_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_WP3) & BM_AIPS_PACRM_WP3)
9786 /*! @brief Set the WP3 field to a new value. */
9787 #define BW_AIPS_PACRM_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP3) = (v))
9791 * @name Register AIPS_PACRM, field SP3[18] (RW)
9793 * Determines whether the peripheral requires supervisor privilege level for
9794 * accesses. When this field is set, the master privilege level must indicate the
9795 * supervisor access attribute, and the MPRx[MPLn] control field for the master
9796 * must be set. If not, access terminates with an error response and no peripheral
9800 * - 0 - This peripheral does not require supervisor privilege level for
9802 * - 1 - This peripheral requires supervisor privilege level for accesses.
9805 #define BP_AIPS_PACRM_SP3 (18U) /*!< Bit position for AIPS_PACRM_SP3. */
9806 #define BM_AIPS_PACRM_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRM_SP3. */
9807 #define BS_AIPS_PACRM_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRM_SP3. */
9809 /*! @brief Read current value of the AIPS_PACRM_SP3 field. */
9810 #define BR_AIPS_PACRM_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP3))
9812 /*! @brief Format value for bitfield AIPS_PACRM_SP3. */
9813 #define BF_AIPS_PACRM_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_SP3) & BM_AIPS_PACRM_SP3)
9815 /*! @brief Set the SP3 field to a new value. */
9816 #define BW_AIPS_PACRM_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP3) = (v))
9820 * @name Register AIPS_PACRM, field TP2[20] (RW)
9822 * Determines whether the peripheral allows accesses from an untrusted master.
9823 * When this bit is set and an access is attempted by an untrusted master, the
9824 * access terminates with an error response and no peripheral access initiates.
9827 * - 0 - Accesses from an untrusted master are allowed.
9828 * - 1 - Accesses from an untrusted master are not allowed.
9831 #define BP_AIPS_PACRM_TP2 (20U) /*!< Bit position for AIPS_PACRM_TP2. */
9832 #define BM_AIPS_PACRM_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRM_TP2. */
9833 #define BS_AIPS_PACRM_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRM_TP2. */
9835 /*! @brief Read current value of the AIPS_PACRM_TP2 field. */
9836 #define BR_AIPS_PACRM_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP2))
9838 /*! @brief Format value for bitfield AIPS_PACRM_TP2. */
9839 #define BF_AIPS_PACRM_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_TP2) & BM_AIPS_PACRM_TP2)
9841 /*! @brief Set the TP2 field to a new value. */
9842 #define BW_AIPS_PACRM_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP2) = (v))
9846 * @name Register AIPS_PACRM, field WP2[21] (RW)
9848 * Determines whether the peripheral allows write accesses. When this field is
9849 * set and a write access is attempted, access terminates with an error response
9850 * and no peripheral access initiates.
9853 * - 0 - This peripheral allows write accesses.
9854 * - 1 - This peripheral is write protected.
9857 #define BP_AIPS_PACRM_WP2 (21U) /*!< Bit position for AIPS_PACRM_WP2. */
9858 #define BM_AIPS_PACRM_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRM_WP2. */
9859 #define BS_AIPS_PACRM_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRM_WP2. */
9861 /*! @brief Read current value of the AIPS_PACRM_WP2 field. */
9862 #define BR_AIPS_PACRM_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP2))
9864 /*! @brief Format value for bitfield AIPS_PACRM_WP2. */
9865 #define BF_AIPS_PACRM_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_WP2) & BM_AIPS_PACRM_WP2)
9867 /*! @brief Set the WP2 field to a new value. */
9868 #define BW_AIPS_PACRM_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP2) = (v))
9872 * @name Register AIPS_PACRM, field SP2[22] (RW)
9874 * Determines whether the peripheral requires supervisor privilege level for
9875 * access. When this bit is set, the master privilege level must indicate the
9876 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
9877 * set. If not, access terminates with an error response and no peripheral access
9881 * - 0 - This peripheral does not require supervisor privilege level for
9883 * - 1 - This peripheral requires supervisor privilege level for accesses.
9886 #define BP_AIPS_PACRM_SP2 (22U) /*!< Bit position for AIPS_PACRM_SP2. */
9887 #define BM_AIPS_PACRM_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRM_SP2. */
9888 #define BS_AIPS_PACRM_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRM_SP2. */
9890 /*! @brief Read current value of the AIPS_PACRM_SP2 field. */
9891 #define BR_AIPS_PACRM_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP2))
9893 /*! @brief Format value for bitfield AIPS_PACRM_SP2. */
9894 #define BF_AIPS_PACRM_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_SP2) & BM_AIPS_PACRM_SP2)
9896 /*! @brief Set the SP2 field to a new value. */
9897 #define BW_AIPS_PACRM_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP2) = (v))
9901 * @name Register AIPS_PACRM, field TP1[24] (RW)
9903 * Determines whether the peripheral allows accesses from an untrusted master.
9904 * When this field is set and an access is attempted by an untrusted master, the
9905 * access terminates with an error response and no peripheral access initiates.
9908 * - 0 - Accesses from an untrusted master are allowed.
9909 * - 1 - Accesses from an untrusted master are not allowed.
9912 #define BP_AIPS_PACRM_TP1 (24U) /*!< Bit position for AIPS_PACRM_TP1. */
9913 #define BM_AIPS_PACRM_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRM_TP1. */
9914 #define BS_AIPS_PACRM_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRM_TP1. */
9916 /*! @brief Read current value of the AIPS_PACRM_TP1 field. */
9917 #define BR_AIPS_PACRM_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP1))
9919 /*! @brief Format value for bitfield AIPS_PACRM_TP1. */
9920 #define BF_AIPS_PACRM_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_TP1) & BM_AIPS_PACRM_TP1)
9922 /*! @brief Set the TP1 field to a new value. */
9923 #define BW_AIPS_PACRM_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP1) = (v))
9927 * @name Register AIPS_PACRM, field WP1[25] (RW)
9929 * Determines whether the peripheral allows write accesses. When this field is
9930 * set and a write access is attempted, access terminates with an error response
9931 * and no peripheral access initiates.
9934 * - 0 - This peripheral allows write accesses.
9935 * - 1 - This peripheral is write protected.
9938 #define BP_AIPS_PACRM_WP1 (25U) /*!< Bit position for AIPS_PACRM_WP1. */
9939 #define BM_AIPS_PACRM_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRM_WP1. */
9940 #define BS_AIPS_PACRM_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRM_WP1. */
9942 /*! @brief Read current value of the AIPS_PACRM_WP1 field. */
9943 #define BR_AIPS_PACRM_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP1))
9945 /*! @brief Format value for bitfield AIPS_PACRM_WP1. */
9946 #define BF_AIPS_PACRM_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_WP1) & BM_AIPS_PACRM_WP1)
9948 /*! @brief Set the WP1 field to a new value. */
9949 #define BW_AIPS_PACRM_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP1) = (v))
9953 * @name Register AIPS_PACRM, field SP1[26] (RW)
9955 * Determines whether the peripheral requires supervisor privilege level for
9956 * access. When this field is set, the master privilege level must indicate the
9957 * supervisor access attribute, and the MPRx[MPLn] control field for the master must
9958 * be set. If not, access terminates with an error response and no peripheral
9962 * - 0 - This peripheral does not require supervisor privilege level for
9964 * - 1 - This peripheral requires supervisor privilege level for accesses.
9967 #define BP_AIPS_PACRM_SP1 (26U) /*!< Bit position for AIPS_PACRM_SP1. */
9968 #define BM_AIPS_PACRM_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRM_SP1. */
9969 #define BS_AIPS_PACRM_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRM_SP1. */
9971 /*! @brief Read current value of the AIPS_PACRM_SP1 field. */
9972 #define BR_AIPS_PACRM_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP1))
9974 /*! @brief Format value for bitfield AIPS_PACRM_SP1. */
9975 #define BF_AIPS_PACRM_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_SP1) & BM_AIPS_PACRM_SP1)
9977 /*! @brief Set the SP1 field to a new value. */
9978 #define BW_AIPS_PACRM_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP1) = (v))
9982 * @name Register AIPS_PACRM, field TP0[28] (RW)
9984 * Determines whether the peripheral allows accesses from an untrusted master.
9985 * When this bit is set and an access is attempted by an untrusted master, the
9986 * access terminates with an error response and no peripheral access initiates.
9989 * - 0 - Accesses from an untrusted master are allowed.
9990 * - 1 - Accesses from an untrusted master are not allowed.
9993 #define BP_AIPS_PACRM_TP0 (28U) /*!< Bit position for AIPS_PACRM_TP0. */
9994 #define BM_AIPS_PACRM_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRM_TP0. */
9995 #define BS_AIPS_PACRM_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRM_TP0. */
9997 /*! @brief Read current value of the AIPS_PACRM_TP0 field. */
9998 #define BR_AIPS_PACRM_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP0))
10000 /*! @brief Format value for bitfield AIPS_PACRM_TP0. */
10001 #define BF_AIPS_PACRM_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_TP0) & BM_AIPS_PACRM_TP0)
10003 /*! @brief Set the TP0 field to a new value. */
10004 #define BW_AIPS_PACRM_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP0) = (v))
10008 * @name Register AIPS_PACRM, field WP0[29] (RW)
10010 * Determines whether the peripheral allows write accesses. When this field is
10011 * set and a write access is attempted, access terminates with an error response
10012 * and no peripheral access initiates.
10015 * - 0 - This peripheral allows write accesses.
10016 * - 1 - This peripheral is write protected.
10019 #define BP_AIPS_PACRM_WP0 (29U) /*!< Bit position for AIPS_PACRM_WP0. */
10020 #define BM_AIPS_PACRM_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRM_WP0. */
10021 #define BS_AIPS_PACRM_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRM_WP0. */
10023 /*! @brief Read current value of the AIPS_PACRM_WP0 field. */
10024 #define BR_AIPS_PACRM_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP0))
10026 /*! @brief Format value for bitfield AIPS_PACRM_WP0. */
10027 #define BF_AIPS_PACRM_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_WP0) & BM_AIPS_PACRM_WP0)
10029 /*! @brief Set the WP0 field to a new value. */
10030 #define BW_AIPS_PACRM_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP0) = (v))
10034 * @name Register AIPS_PACRM, field SP0[30] (RW)
10036 * Determines whether the peripheral requires supervisor privilege level for
10037 * accesses. When this field is set, the master privilege level must indicate the
10038 * supervisor access attribute, and the MPRx[MPLn] control field for the master
10039 * must be set. If not, access terminates with an error response and no peripheral
10040 * access initiates.
10043 * - 0 - This peripheral does not require supervisor privilege level for
10045 * - 1 - This peripheral requires supervisor privilege level for accesses.
10048 #define BP_AIPS_PACRM_SP0 (30U) /*!< Bit position for AIPS_PACRM_SP0. */
10049 #define BM_AIPS_PACRM_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRM_SP0. */
10050 #define BS_AIPS_PACRM_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRM_SP0. */
10052 /*! @brief Read current value of the AIPS_PACRM_SP0 field. */
10053 #define BR_AIPS_PACRM_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP0))
10055 /*! @brief Format value for bitfield AIPS_PACRM_SP0. */
10056 #define BF_AIPS_PACRM_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_SP0) & BM_AIPS_PACRM_SP0)
10058 /*! @brief Set the SP0 field to a new value. */
10059 #define BW_AIPS_PACRM_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP0) = (v))
10062 /*******************************************************************************
10063 * HW_AIPS_PACRN - Peripheral Access Control Register
10064 ******************************************************************************/
10067 * @brief HW_AIPS_PACRN - Peripheral Access Control Register (RW)
10069 * Reset value: 0x44444444U
10071 * This section describes PACR registers E-P, which control peripheral slots
10072 * 32-127. See PACRPeripheral Access Control Register for the description of these
10075 typedef union _hw_aips_pacrn
10078 struct _hw_aips_pacrn_bitfields
10080 uint32_t TP7
: 1; /*!< [0] Trusted Protect */
10081 uint32_t WP7
: 1; /*!< [1] Write Protect */
10082 uint32_t SP7
: 1; /*!< [2] Supervisor Protect */
10083 uint32_t RESERVED0
: 1; /*!< [3] */
10084 uint32_t TP6
: 1; /*!< [4] Trusted Protect */
10085 uint32_t WP6
: 1; /*!< [5] Write Protect */
10086 uint32_t SP6
: 1; /*!< [6] Supervisor Protect */
10087 uint32_t RESERVED1
: 1; /*!< [7] */
10088 uint32_t TP5
: 1; /*!< [8] Trusted Protect */
10089 uint32_t WP5
: 1; /*!< [9] Write Protect */
10090 uint32_t SP5
: 1; /*!< [10] Supervisor Protect */
10091 uint32_t RESERVED2
: 1; /*!< [11] */
10092 uint32_t TP4
: 1; /*!< [12] Trusted Protect */
10093 uint32_t WP4
: 1; /*!< [13] Write Protect */
10094 uint32_t SP4
: 1; /*!< [14] Supervisor Protect */
10095 uint32_t RESERVED3
: 1; /*!< [15] */
10096 uint32_t TP3
: 1; /*!< [16] Trusted Protect */
10097 uint32_t WP3
: 1; /*!< [17] Write Protect */
10098 uint32_t SP3
: 1; /*!< [18] Supervisor Protect */
10099 uint32_t RESERVED4
: 1; /*!< [19] */
10100 uint32_t TP2
: 1; /*!< [20] Trusted Protect */
10101 uint32_t WP2
: 1; /*!< [21] Write Protect */
10102 uint32_t SP2
: 1; /*!< [22] Supervisor Protect */
10103 uint32_t RESERVED5
: 1; /*!< [23] */
10104 uint32_t TP1
: 1; /*!< [24] Trusted Protect */
10105 uint32_t WP1
: 1; /*!< [25] Write Protect */
10106 uint32_t SP1
: 1; /*!< [26] Supervisor Protect */
10107 uint32_t RESERVED6
: 1; /*!< [27] */
10108 uint32_t TP0
: 1; /*!< [28] Trusted Protect */
10109 uint32_t WP0
: 1; /*!< [29] Write Protect */
10110 uint32_t SP0
: 1; /*!< [30] Supervisor Protect */
10111 uint32_t RESERVED7
: 1; /*!< [31] */
10116 * @name Constants and macros for entire AIPS_PACRN register
10119 #define HW_AIPS_PACRN_ADDR(x) ((x) + 0x64U)
10121 #define HW_AIPS_PACRN(x) (*(__IO hw_aips_pacrn_t *) HW_AIPS_PACRN_ADDR(x))
10122 #define HW_AIPS_PACRN_RD(x) (HW_AIPS_PACRN(x).U)
10123 #define HW_AIPS_PACRN_WR(x, v) (HW_AIPS_PACRN(x).U = (v))
10124 #define HW_AIPS_PACRN_SET(x, v) (HW_AIPS_PACRN_WR(x, HW_AIPS_PACRN_RD(x) | (v)))
10125 #define HW_AIPS_PACRN_CLR(x, v) (HW_AIPS_PACRN_WR(x, HW_AIPS_PACRN_RD(x) & ~(v)))
10126 #define HW_AIPS_PACRN_TOG(x, v) (HW_AIPS_PACRN_WR(x, HW_AIPS_PACRN_RD(x) ^ (v)))
10130 * Constants & macros for individual AIPS_PACRN bitfields
10134 * @name Register AIPS_PACRN, field TP7[0] (RW)
10136 * Determines whether the peripheral allows accesses from an untrusted master.
10137 * When this field is set and an access is attempted by an untrusted master, the
10138 * access terminates with an error response and no peripheral access initiates.
10141 * - 0 - Accesses from an untrusted master are allowed.
10142 * - 1 - Accesses from an untrusted master are not allowed.
10145 #define BP_AIPS_PACRN_TP7 (0U) /*!< Bit position for AIPS_PACRN_TP7. */
10146 #define BM_AIPS_PACRN_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRN_TP7. */
10147 #define BS_AIPS_PACRN_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRN_TP7. */
10149 /*! @brief Read current value of the AIPS_PACRN_TP7 field. */
10150 #define BR_AIPS_PACRN_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP7))
10152 /*! @brief Format value for bitfield AIPS_PACRN_TP7. */
10153 #define BF_AIPS_PACRN_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_TP7) & BM_AIPS_PACRN_TP7)
10155 /*! @brief Set the TP7 field to a new value. */
10156 #define BW_AIPS_PACRN_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP7) = (v))
10160 * @name Register AIPS_PACRN, field WP7[1] (RW)
10162 * Determines whether the peripheral allows write accesses. When this field is
10163 * set and a write access is attempted, access terminates with an error response
10164 * and no peripheral access initiates.
10167 * - 0 - This peripheral allows write accesses.
10168 * - 1 - This peripheral is write protected.
10171 #define BP_AIPS_PACRN_WP7 (1U) /*!< Bit position for AIPS_PACRN_WP7. */
10172 #define BM_AIPS_PACRN_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRN_WP7. */
10173 #define BS_AIPS_PACRN_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRN_WP7. */
10175 /*! @brief Read current value of the AIPS_PACRN_WP7 field. */
10176 #define BR_AIPS_PACRN_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP7))
10178 /*! @brief Format value for bitfield AIPS_PACRN_WP7. */
10179 #define BF_AIPS_PACRN_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_WP7) & BM_AIPS_PACRN_WP7)
10181 /*! @brief Set the WP7 field to a new value. */
10182 #define BW_AIPS_PACRN_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP7) = (v))
10186 * @name Register AIPS_PACRN, field SP7[2] (RW)
10188 * Determines whether the peripheral requires supervisor privilege level for
10189 * accesses. When this field is set, the master privilege level must indicate the
10190 * supervisor access attribute, and the MPRx[MPLn] control field for the master
10191 * must be set. If not, access terminates with an error response and no peripheral
10192 * access initiates.
10195 * - 0 - This peripheral does not require supervisor privilege level for
10197 * - 1 - This peripheral requires supervisor privilege level for accesses.
10200 #define BP_AIPS_PACRN_SP7 (2U) /*!< Bit position for AIPS_PACRN_SP7. */
10201 #define BM_AIPS_PACRN_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRN_SP7. */
10202 #define BS_AIPS_PACRN_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRN_SP7. */
10204 /*! @brief Read current value of the AIPS_PACRN_SP7 field. */
10205 #define BR_AIPS_PACRN_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP7))
10207 /*! @brief Format value for bitfield AIPS_PACRN_SP7. */
10208 #define BF_AIPS_PACRN_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_SP7) & BM_AIPS_PACRN_SP7)
10210 /*! @brief Set the SP7 field to a new value. */
10211 #define BW_AIPS_PACRN_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP7) = (v))
10215 * @name Register AIPS_PACRN, field TP6[4] (RW)
10217 * Determines whether the peripheral allows accesses from an untrusted master.
10218 * When this field is set and an access is attempted by an untrusted master, the
10219 * access terminates with an error response and no peripheral access initiates.
10222 * - 0 - Accesses from an untrusted master are allowed.
10223 * - 1 - Accesses from an untrusted master are not allowed.
10226 #define BP_AIPS_PACRN_TP6 (4U) /*!< Bit position for AIPS_PACRN_TP6. */
10227 #define BM_AIPS_PACRN_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRN_TP6. */
10228 #define BS_AIPS_PACRN_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRN_TP6. */
10230 /*! @brief Read current value of the AIPS_PACRN_TP6 field. */
10231 #define BR_AIPS_PACRN_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP6))
10233 /*! @brief Format value for bitfield AIPS_PACRN_TP6. */
10234 #define BF_AIPS_PACRN_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_TP6) & BM_AIPS_PACRN_TP6)
10236 /*! @brief Set the TP6 field to a new value. */
10237 #define BW_AIPS_PACRN_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP6) = (v))
10241 * @name Register AIPS_PACRN, field WP6[5] (RW)
10243 * Determines whether the peripheral allows write accesses. When this field is
10244 * set and a write access is attempted, access terminates with an error response
10245 * and no peripheral access initiates.
10248 * - 0 - This peripheral allows write accesses.
10249 * - 1 - This peripheral is write protected.
10252 #define BP_AIPS_PACRN_WP6 (5U) /*!< Bit position for AIPS_PACRN_WP6. */
10253 #define BM_AIPS_PACRN_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRN_WP6. */
10254 #define BS_AIPS_PACRN_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRN_WP6. */
10256 /*! @brief Read current value of the AIPS_PACRN_WP6 field. */
10257 #define BR_AIPS_PACRN_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP6))
10259 /*! @brief Format value for bitfield AIPS_PACRN_WP6. */
10260 #define BF_AIPS_PACRN_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_WP6) & BM_AIPS_PACRN_WP6)
10262 /*! @brief Set the WP6 field to a new value. */
10263 #define BW_AIPS_PACRN_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP6) = (v))
10267 * @name Register AIPS_PACRN, field SP6[6] (RW)
10269 * Determines whether the peripheral requires supervisor privilege level for
10270 * accesses. When this field is set, the master privilege level must indicate the
10271 * supervisor access attribute, and the MPRx[MPLn] control field for the master
10272 * must be set. If not, access terminates with an error response and no peripheral
10273 * access initiates.
10276 * - 0 - This peripheral does not require supervisor privilege level for
10278 * - 1 - This peripheral requires supervisor privilege level for accesses.
10281 #define BP_AIPS_PACRN_SP6 (6U) /*!< Bit position for AIPS_PACRN_SP6. */
10282 #define BM_AIPS_PACRN_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRN_SP6. */
10283 #define BS_AIPS_PACRN_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRN_SP6. */
10285 /*! @brief Read current value of the AIPS_PACRN_SP6 field. */
10286 #define BR_AIPS_PACRN_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP6))
10288 /*! @brief Format value for bitfield AIPS_PACRN_SP6. */
10289 #define BF_AIPS_PACRN_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_SP6) & BM_AIPS_PACRN_SP6)
10291 /*! @brief Set the SP6 field to a new value. */
10292 #define BW_AIPS_PACRN_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP6) = (v))
10296 * @name Register AIPS_PACRN, field TP5[8] (RW)
10298 * Determines whether the peripheral allows accesses from an untrusted master.
10299 * When this field is set and an access is attempted by an untrusted master, the
10300 * access terminates with an error response and no peripheral access initiates.
10303 * - 0 - Accesses from an untrusted master are allowed.
10304 * - 1 - Accesses from an untrusted master are not allowed.
10307 #define BP_AIPS_PACRN_TP5 (8U) /*!< Bit position for AIPS_PACRN_TP5. */
10308 #define BM_AIPS_PACRN_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRN_TP5. */
10309 #define BS_AIPS_PACRN_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRN_TP5. */
10311 /*! @brief Read current value of the AIPS_PACRN_TP5 field. */
10312 #define BR_AIPS_PACRN_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP5))
10314 /*! @brief Format value for bitfield AIPS_PACRN_TP5. */
10315 #define BF_AIPS_PACRN_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_TP5) & BM_AIPS_PACRN_TP5)
10317 /*! @brief Set the TP5 field to a new value. */
10318 #define BW_AIPS_PACRN_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP5) = (v))
10322 * @name Register AIPS_PACRN, field WP5[9] (RW)
10324 * Determines whether the peripheral allows write accesses. When this field is
10325 * set and a write access is attempted, access terminates with an error response
10326 * and no peripheral access initiates.
10329 * - 0 - This peripheral allows write accesses.
10330 * - 1 - This peripheral is write protected.
10333 #define BP_AIPS_PACRN_WP5 (9U) /*!< Bit position for AIPS_PACRN_WP5. */
10334 #define BM_AIPS_PACRN_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRN_WP5. */
10335 #define BS_AIPS_PACRN_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRN_WP5. */
10337 /*! @brief Read current value of the AIPS_PACRN_WP5 field. */
10338 #define BR_AIPS_PACRN_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP5))
10340 /*! @brief Format value for bitfield AIPS_PACRN_WP5. */
10341 #define BF_AIPS_PACRN_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_WP5) & BM_AIPS_PACRN_WP5)
10343 /*! @brief Set the WP5 field to a new value. */
10344 #define BW_AIPS_PACRN_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP5) = (v))
10348 * @name Register AIPS_PACRN, field SP5[10] (RW)
10350 * Determines whether the peripheral requires supervisor privilege level for
10351 * accesses. When this field is set, the master privilege level must indicate the
10352 * supervisor access attribute, and the MPRx[MPLn] control field for the master
10353 * must be set. If not, access terminates with an error response and no peripheral
10354 * access initiates.
10357 * - 0 - This peripheral does not require supervisor privilege level for
10359 * - 1 - This peripheral requires supervisor privilege level for accesses.
10362 #define BP_AIPS_PACRN_SP5 (10U) /*!< Bit position for AIPS_PACRN_SP5. */
10363 #define BM_AIPS_PACRN_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRN_SP5. */
10364 #define BS_AIPS_PACRN_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRN_SP5. */
10366 /*! @brief Read current value of the AIPS_PACRN_SP5 field. */
10367 #define BR_AIPS_PACRN_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP5))
10369 /*! @brief Format value for bitfield AIPS_PACRN_SP5. */
10370 #define BF_AIPS_PACRN_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_SP5) & BM_AIPS_PACRN_SP5)
10372 /*! @brief Set the SP5 field to a new value. */
10373 #define BW_AIPS_PACRN_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP5) = (v))
10377 * @name Register AIPS_PACRN, field TP4[12] (RW)
10379 * Determines whether the peripheral allows accesses from an untrusted master.
10380 * When this bit is set and an access is attempted by an untrusted master, the
10381 * access terminates with an error response and no peripheral access initiates.
10384 * - 0 - Accesses from an untrusted master are allowed.
10385 * - 1 - Accesses from an untrusted master are not allowed.
10388 #define BP_AIPS_PACRN_TP4 (12U) /*!< Bit position for AIPS_PACRN_TP4. */
10389 #define BM_AIPS_PACRN_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRN_TP4. */
10390 #define BS_AIPS_PACRN_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRN_TP4. */
10392 /*! @brief Read current value of the AIPS_PACRN_TP4 field. */
10393 #define BR_AIPS_PACRN_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP4))
10395 /*! @brief Format value for bitfield AIPS_PACRN_TP4. */
10396 #define BF_AIPS_PACRN_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_TP4) & BM_AIPS_PACRN_TP4)
10398 /*! @brief Set the TP4 field to a new value. */
10399 #define BW_AIPS_PACRN_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP4) = (v))
10403 * @name Register AIPS_PACRN, field WP4[13] (RW)
10405 * Determines whether the peripheral allows write accesses. When this field is
10406 * set and a write access is attempted, access terminates with an error response
10407 * and no peripheral access initiates.
10410 * - 0 - This peripheral allows write accesses.
10411 * - 1 - This peripheral is write protected.
10414 #define BP_AIPS_PACRN_WP4 (13U) /*!< Bit position for AIPS_PACRN_WP4. */
10415 #define BM_AIPS_PACRN_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRN_WP4. */
10416 #define BS_AIPS_PACRN_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRN_WP4. */
10418 /*! @brief Read current value of the AIPS_PACRN_WP4 field. */
10419 #define BR_AIPS_PACRN_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP4))
10421 /*! @brief Format value for bitfield AIPS_PACRN_WP4. */
10422 #define BF_AIPS_PACRN_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_WP4) & BM_AIPS_PACRN_WP4)
10424 /*! @brief Set the WP4 field to a new value. */
10425 #define BW_AIPS_PACRN_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP4) = (v))
10429 * @name Register AIPS_PACRN, field SP4[14] (RW)
10431 * Determines whether the peripheral requires supervisor privilege level for
10432 * access. When this bit is set, the master privilege level must indicate the
10433 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
10434 * set. If not, access terminates with an error response and no peripheral access
10438 * - 0 - This peripheral does not require supervisor privilege level for
10440 * - 1 - This peripheral requires supervisor privilege level for accesses.
10443 #define BP_AIPS_PACRN_SP4 (14U) /*!< Bit position for AIPS_PACRN_SP4. */
10444 #define BM_AIPS_PACRN_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRN_SP4. */
10445 #define BS_AIPS_PACRN_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRN_SP4. */
10447 /*! @brief Read current value of the AIPS_PACRN_SP4 field. */
10448 #define BR_AIPS_PACRN_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP4))
10450 /*! @brief Format value for bitfield AIPS_PACRN_SP4. */
10451 #define BF_AIPS_PACRN_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_SP4) & BM_AIPS_PACRN_SP4)
10453 /*! @brief Set the SP4 field to a new value. */
10454 #define BW_AIPS_PACRN_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP4) = (v))
10458 * @name Register AIPS_PACRN, field TP3[16] (RW)
10460 * Determines whether the peripheral allows accesses from an untrusted master.
10461 * When this field is set and an access is attempted by an untrusted master, the
10462 * access terminates with an error response and no peripheral access initiates.
10465 * - 0 - Accesses from an untrusted master are allowed.
10466 * - 1 - Accesses from an untrusted master are not allowed.
10469 #define BP_AIPS_PACRN_TP3 (16U) /*!< Bit position for AIPS_PACRN_TP3. */
10470 #define BM_AIPS_PACRN_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRN_TP3. */
10471 #define BS_AIPS_PACRN_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRN_TP3. */
10473 /*! @brief Read current value of the AIPS_PACRN_TP3 field. */
10474 #define BR_AIPS_PACRN_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP3))
10476 /*! @brief Format value for bitfield AIPS_PACRN_TP3. */
10477 #define BF_AIPS_PACRN_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_TP3) & BM_AIPS_PACRN_TP3)
10479 /*! @brief Set the TP3 field to a new value. */
10480 #define BW_AIPS_PACRN_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP3) = (v))
10484 * @name Register AIPS_PACRN, field WP3[17] (RW)
10486 * Determines whether the peripheral allows write accesss. When this bit is set
10487 * and a write access is attempted, access terminates with an error response and
10488 * no peripheral access initiates.
10491 * - 0 - This peripheral allows write accesses.
10492 * - 1 - This peripheral is write protected.
10495 #define BP_AIPS_PACRN_WP3 (17U) /*!< Bit position for AIPS_PACRN_WP3. */
10496 #define BM_AIPS_PACRN_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRN_WP3. */
10497 #define BS_AIPS_PACRN_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRN_WP3. */
10499 /*! @brief Read current value of the AIPS_PACRN_WP3 field. */
10500 #define BR_AIPS_PACRN_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP3))
10502 /*! @brief Format value for bitfield AIPS_PACRN_WP3. */
10503 #define BF_AIPS_PACRN_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_WP3) & BM_AIPS_PACRN_WP3)
10505 /*! @brief Set the WP3 field to a new value. */
10506 #define BW_AIPS_PACRN_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP3) = (v))
10510 * @name Register AIPS_PACRN, field SP3[18] (RW)
10512 * Determines whether the peripheral requires supervisor privilege level for
10513 * accesses. When this field is set, the master privilege level must indicate the
10514 * supervisor access attribute, and the MPRx[MPLn] control field for the master
10515 * must be set. If not, access terminates with an error response and no peripheral
10516 * access initiates.
10519 * - 0 - This peripheral does not require supervisor privilege level for
10521 * - 1 - This peripheral requires supervisor privilege level for accesses.
10524 #define BP_AIPS_PACRN_SP3 (18U) /*!< Bit position for AIPS_PACRN_SP3. */
10525 #define BM_AIPS_PACRN_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRN_SP3. */
10526 #define BS_AIPS_PACRN_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRN_SP3. */
10528 /*! @brief Read current value of the AIPS_PACRN_SP3 field. */
10529 #define BR_AIPS_PACRN_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP3))
10531 /*! @brief Format value for bitfield AIPS_PACRN_SP3. */
10532 #define BF_AIPS_PACRN_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_SP3) & BM_AIPS_PACRN_SP3)
10534 /*! @brief Set the SP3 field to a new value. */
10535 #define BW_AIPS_PACRN_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP3) = (v))
10539 * @name Register AIPS_PACRN, field TP2[20] (RW)
10541 * Determines whether the peripheral allows accesses from an untrusted master.
10542 * When this bit is set and an access is attempted by an untrusted master, the
10543 * access terminates with an error response and no peripheral access initiates.
10546 * - 0 - Accesses from an untrusted master are allowed.
10547 * - 1 - Accesses from an untrusted master are not allowed.
10550 #define BP_AIPS_PACRN_TP2 (20U) /*!< Bit position for AIPS_PACRN_TP2. */
10551 #define BM_AIPS_PACRN_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRN_TP2. */
10552 #define BS_AIPS_PACRN_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRN_TP2. */
10554 /*! @brief Read current value of the AIPS_PACRN_TP2 field. */
10555 #define BR_AIPS_PACRN_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP2))
10557 /*! @brief Format value for bitfield AIPS_PACRN_TP2. */
10558 #define BF_AIPS_PACRN_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_TP2) & BM_AIPS_PACRN_TP2)
10560 /*! @brief Set the TP2 field to a new value. */
10561 #define BW_AIPS_PACRN_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP2) = (v))
10565 * @name Register AIPS_PACRN, field WP2[21] (RW)
10567 * Determines whether the peripheral allows write accesses. When this field is
10568 * set and a write access is attempted, access terminates with an error response
10569 * and no peripheral access initiates.
10572 * - 0 - This peripheral allows write accesses.
10573 * - 1 - This peripheral is write protected.
10576 #define BP_AIPS_PACRN_WP2 (21U) /*!< Bit position for AIPS_PACRN_WP2. */
10577 #define BM_AIPS_PACRN_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRN_WP2. */
10578 #define BS_AIPS_PACRN_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRN_WP2. */
10580 /*! @brief Read current value of the AIPS_PACRN_WP2 field. */
10581 #define BR_AIPS_PACRN_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP2))
10583 /*! @brief Format value for bitfield AIPS_PACRN_WP2. */
10584 #define BF_AIPS_PACRN_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_WP2) & BM_AIPS_PACRN_WP2)
10586 /*! @brief Set the WP2 field to a new value. */
10587 #define BW_AIPS_PACRN_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP2) = (v))
10591 * @name Register AIPS_PACRN, field SP2[22] (RW)
10593 * Determines whether the peripheral requires supervisor privilege level for
10594 * access. When this bit is set, the master privilege level must indicate the
10595 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
10596 * set. If not, access terminates with an error response and no peripheral access
10600 * - 0 - This peripheral does not require supervisor privilege level for
10602 * - 1 - This peripheral requires supervisor privilege level for accesses.
10605 #define BP_AIPS_PACRN_SP2 (22U) /*!< Bit position for AIPS_PACRN_SP2. */
10606 #define BM_AIPS_PACRN_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRN_SP2. */
10607 #define BS_AIPS_PACRN_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRN_SP2. */
10609 /*! @brief Read current value of the AIPS_PACRN_SP2 field. */
10610 #define BR_AIPS_PACRN_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP2))
10612 /*! @brief Format value for bitfield AIPS_PACRN_SP2. */
10613 #define BF_AIPS_PACRN_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_SP2) & BM_AIPS_PACRN_SP2)
10615 /*! @brief Set the SP2 field to a new value. */
10616 #define BW_AIPS_PACRN_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP2) = (v))
10620 * @name Register AIPS_PACRN, field TP1[24] (RW)
10622 * Determines whether the peripheral allows accesses from an untrusted master.
10623 * When this field is set and an access is attempted by an untrusted master, the
10624 * access terminates with an error response and no peripheral access initiates.
10627 * - 0 - Accesses from an untrusted master are allowed.
10628 * - 1 - Accesses from an untrusted master are not allowed.
10631 #define BP_AIPS_PACRN_TP1 (24U) /*!< Bit position for AIPS_PACRN_TP1. */
10632 #define BM_AIPS_PACRN_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRN_TP1. */
10633 #define BS_AIPS_PACRN_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRN_TP1. */
10635 /*! @brief Read current value of the AIPS_PACRN_TP1 field. */
10636 #define BR_AIPS_PACRN_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP1))
10638 /*! @brief Format value for bitfield AIPS_PACRN_TP1. */
10639 #define BF_AIPS_PACRN_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_TP1) & BM_AIPS_PACRN_TP1)
10641 /*! @brief Set the TP1 field to a new value. */
10642 #define BW_AIPS_PACRN_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP1) = (v))
10646 * @name Register AIPS_PACRN, field WP1[25] (RW)
10648 * Determines whether the peripheral allows write accesses. When this field is
10649 * set and a write access is attempted, access terminates with an error response
10650 * and no peripheral access initiates.
10653 * - 0 - This peripheral allows write accesses.
10654 * - 1 - This peripheral is write protected.
10657 #define BP_AIPS_PACRN_WP1 (25U) /*!< Bit position for AIPS_PACRN_WP1. */
10658 #define BM_AIPS_PACRN_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRN_WP1. */
10659 #define BS_AIPS_PACRN_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRN_WP1. */
10661 /*! @brief Read current value of the AIPS_PACRN_WP1 field. */
10662 #define BR_AIPS_PACRN_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP1))
10664 /*! @brief Format value for bitfield AIPS_PACRN_WP1. */
10665 #define BF_AIPS_PACRN_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_WP1) & BM_AIPS_PACRN_WP1)
10667 /*! @brief Set the WP1 field to a new value. */
10668 #define BW_AIPS_PACRN_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP1) = (v))
10672 * @name Register AIPS_PACRN, field SP1[26] (RW)
10674 * Determines whether the peripheral requires supervisor privilege level for
10675 * access. When this field is set, the master privilege level must indicate the
10676 * supervisor access attribute, and the MPRx[MPLn] control field for the master must
10677 * be set. If not, access terminates with an error response and no peripheral
10678 * access initiates.
10681 * - 0 - This peripheral does not require supervisor privilege level for
10683 * - 1 - This peripheral requires supervisor privilege level for accesses.
10686 #define BP_AIPS_PACRN_SP1 (26U) /*!< Bit position for AIPS_PACRN_SP1. */
10687 #define BM_AIPS_PACRN_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRN_SP1. */
10688 #define BS_AIPS_PACRN_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRN_SP1. */
10690 /*! @brief Read current value of the AIPS_PACRN_SP1 field. */
10691 #define BR_AIPS_PACRN_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP1))
10693 /*! @brief Format value for bitfield AIPS_PACRN_SP1. */
10694 #define BF_AIPS_PACRN_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_SP1) & BM_AIPS_PACRN_SP1)
10696 /*! @brief Set the SP1 field to a new value. */
10697 #define BW_AIPS_PACRN_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP1) = (v))
10701 * @name Register AIPS_PACRN, field TP0[28] (RW)
10703 * Determines whether the peripheral allows accesses from an untrusted master.
10704 * When this bit is set and an access is attempted by an untrusted master, the
10705 * access terminates with an error response and no peripheral access initiates.
10708 * - 0 - Accesses from an untrusted master are allowed.
10709 * - 1 - Accesses from an untrusted master are not allowed.
10712 #define BP_AIPS_PACRN_TP0 (28U) /*!< Bit position for AIPS_PACRN_TP0. */
10713 #define BM_AIPS_PACRN_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRN_TP0. */
10714 #define BS_AIPS_PACRN_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRN_TP0. */
10716 /*! @brief Read current value of the AIPS_PACRN_TP0 field. */
10717 #define BR_AIPS_PACRN_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP0))
10719 /*! @brief Format value for bitfield AIPS_PACRN_TP0. */
10720 #define BF_AIPS_PACRN_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_TP0) & BM_AIPS_PACRN_TP0)
10722 /*! @brief Set the TP0 field to a new value. */
10723 #define BW_AIPS_PACRN_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP0) = (v))
10727 * @name Register AIPS_PACRN, field WP0[29] (RW)
10729 * Determines whether the peripheral allows write accesses. When this field is
10730 * set and a write access is attempted, access terminates with an error response
10731 * and no peripheral access initiates.
10734 * - 0 - This peripheral allows write accesses.
10735 * - 1 - This peripheral is write protected.
10738 #define BP_AIPS_PACRN_WP0 (29U) /*!< Bit position for AIPS_PACRN_WP0. */
10739 #define BM_AIPS_PACRN_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRN_WP0. */
10740 #define BS_AIPS_PACRN_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRN_WP0. */
10742 /*! @brief Read current value of the AIPS_PACRN_WP0 field. */
10743 #define BR_AIPS_PACRN_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP0))
10745 /*! @brief Format value for bitfield AIPS_PACRN_WP0. */
10746 #define BF_AIPS_PACRN_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_WP0) & BM_AIPS_PACRN_WP0)
10748 /*! @brief Set the WP0 field to a new value. */
10749 #define BW_AIPS_PACRN_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP0) = (v))
10753 * @name Register AIPS_PACRN, field SP0[30] (RW)
10755 * Determines whether the peripheral requires supervisor privilege level for
10756 * accesses. When this field is set, the master privilege level must indicate the
10757 * supervisor access attribute, and the MPRx[MPLn] control field for the master
10758 * must be set. If not, access terminates with an error response and no peripheral
10759 * access initiates.
10762 * - 0 - This peripheral does not require supervisor privilege level for
10764 * - 1 - This peripheral requires supervisor privilege level for accesses.
10767 #define BP_AIPS_PACRN_SP0 (30U) /*!< Bit position for AIPS_PACRN_SP0. */
10768 #define BM_AIPS_PACRN_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRN_SP0. */
10769 #define BS_AIPS_PACRN_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRN_SP0. */
10771 /*! @brief Read current value of the AIPS_PACRN_SP0 field. */
10772 #define BR_AIPS_PACRN_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP0))
10774 /*! @brief Format value for bitfield AIPS_PACRN_SP0. */
10775 #define BF_AIPS_PACRN_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_SP0) & BM_AIPS_PACRN_SP0)
10777 /*! @brief Set the SP0 field to a new value. */
10778 #define BW_AIPS_PACRN_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP0) = (v))
10781 /*******************************************************************************
10782 * HW_AIPS_PACRO - Peripheral Access Control Register
10783 ******************************************************************************/
10786 * @brief HW_AIPS_PACRO - Peripheral Access Control Register (RW)
10788 * Reset value: 0x44444444U
10790 * This section describes PACR registers E-P, which control peripheral slots
10791 * 32-127. See PACRPeripheral Access Control Register for the description of these
10794 typedef union _hw_aips_pacro
10797 struct _hw_aips_pacro_bitfields
10799 uint32_t TP7
: 1; /*!< [0] Trusted Protect */
10800 uint32_t WP7
: 1; /*!< [1] Write Protect */
10801 uint32_t SP7
: 1; /*!< [2] Supervisor Protect */
10802 uint32_t RESERVED0
: 1; /*!< [3] */
10803 uint32_t TP6
: 1; /*!< [4] Trusted Protect */
10804 uint32_t WP6
: 1; /*!< [5] Write Protect */
10805 uint32_t SP6
: 1; /*!< [6] Supervisor Protect */
10806 uint32_t RESERVED1
: 1; /*!< [7] */
10807 uint32_t TP5
: 1; /*!< [8] Trusted Protect */
10808 uint32_t WP5
: 1; /*!< [9] Write Protect */
10809 uint32_t SP5
: 1; /*!< [10] Supervisor Protect */
10810 uint32_t RESERVED2
: 1; /*!< [11] */
10811 uint32_t TP4
: 1; /*!< [12] Trusted Protect */
10812 uint32_t WP4
: 1; /*!< [13] Write Protect */
10813 uint32_t SP4
: 1; /*!< [14] Supervisor Protect */
10814 uint32_t RESERVED3
: 1; /*!< [15] */
10815 uint32_t TP3
: 1; /*!< [16] Trusted Protect */
10816 uint32_t WP3
: 1; /*!< [17] Write Protect */
10817 uint32_t SP3
: 1; /*!< [18] Supervisor Protect */
10818 uint32_t RESERVED4
: 1; /*!< [19] */
10819 uint32_t TP2
: 1; /*!< [20] Trusted Protect */
10820 uint32_t WP2
: 1; /*!< [21] Write Protect */
10821 uint32_t SP2
: 1; /*!< [22] Supervisor Protect */
10822 uint32_t RESERVED5
: 1; /*!< [23] */
10823 uint32_t TP1
: 1; /*!< [24] Trusted Protect */
10824 uint32_t WP1
: 1; /*!< [25] Write Protect */
10825 uint32_t SP1
: 1; /*!< [26] Supervisor Protect */
10826 uint32_t RESERVED6
: 1; /*!< [27] */
10827 uint32_t TP0
: 1; /*!< [28] Trusted Protect */
10828 uint32_t WP0
: 1; /*!< [29] Write Protect */
10829 uint32_t SP0
: 1; /*!< [30] Supervisor Protect */
10830 uint32_t RESERVED7
: 1; /*!< [31] */
10835 * @name Constants and macros for entire AIPS_PACRO register
10838 #define HW_AIPS_PACRO_ADDR(x) ((x) + 0x68U)
10840 #define HW_AIPS_PACRO(x) (*(__IO hw_aips_pacro_t *) HW_AIPS_PACRO_ADDR(x))
10841 #define HW_AIPS_PACRO_RD(x) (HW_AIPS_PACRO(x).U)
10842 #define HW_AIPS_PACRO_WR(x, v) (HW_AIPS_PACRO(x).U = (v))
10843 #define HW_AIPS_PACRO_SET(x, v) (HW_AIPS_PACRO_WR(x, HW_AIPS_PACRO_RD(x) | (v)))
10844 #define HW_AIPS_PACRO_CLR(x, v) (HW_AIPS_PACRO_WR(x, HW_AIPS_PACRO_RD(x) & ~(v)))
10845 #define HW_AIPS_PACRO_TOG(x, v) (HW_AIPS_PACRO_WR(x, HW_AIPS_PACRO_RD(x) ^ (v)))
10849 * Constants & macros for individual AIPS_PACRO bitfields
10853 * @name Register AIPS_PACRO, field TP7[0] (RW)
10855 * Determines whether the peripheral allows accesses from an untrusted master.
10856 * When this field is set and an access is attempted by an untrusted master, the
10857 * access terminates with an error response and no peripheral access initiates.
10860 * - 0 - Accesses from an untrusted master are allowed.
10861 * - 1 - Accesses from an untrusted master are not allowed.
10864 #define BP_AIPS_PACRO_TP7 (0U) /*!< Bit position for AIPS_PACRO_TP7. */
10865 #define BM_AIPS_PACRO_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRO_TP7. */
10866 #define BS_AIPS_PACRO_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRO_TP7. */
10868 /*! @brief Read current value of the AIPS_PACRO_TP7 field. */
10869 #define BR_AIPS_PACRO_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP7))
10871 /*! @brief Format value for bitfield AIPS_PACRO_TP7. */
10872 #define BF_AIPS_PACRO_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_TP7) & BM_AIPS_PACRO_TP7)
10874 /*! @brief Set the TP7 field to a new value. */
10875 #define BW_AIPS_PACRO_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP7) = (v))
10879 * @name Register AIPS_PACRO, field WP7[1] (RW)
10881 * Determines whether the peripheral allows write accesses. When this field is
10882 * set and a write access is attempted, access terminates with an error response
10883 * and no peripheral access initiates.
10886 * - 0 - This peripheral allows write accesses.
10887 * - 1 - This peripheral is write protected.
10890 #define BP_AIPS_PACRO_WP7 (1U) /*!< Bit position for AIPS_PACRO_WP7. */
10891 #define BM_AIPS_PACRO_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRO_WP7. */
10892 #define BS_AIPS_PACRO_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRO_WP7. */
10894 /*! @brief Read current value of the AIPS_PACRO_WP7 field. */
10895 #define BR_AIPS_PACRO_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP7))
10897 /*! @brief Format value for bitfield AIPS_PACRO_WP7. */
10898 #define BF_AIPS_PACRO_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_WP7) & BM_AIPS_PACRO_WP7)
10900 /*! @brief Set the WP7 field to a new value. */
10901 #define BW_AIPS_PACRO_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP7) = (v))
10905 * @name Register AIPS_PACRO, field SP7[2] (RW)
10907 * Determines whether the peripheral requires supervisor privilege level for
10908 * accesses. When this field is set, the master privilege level must indicate the
10909 * supervisor access attribute, and the MPRx[MPLn] control field for the master
10910 * must be set. If not, access terminates with an error response and no peripheral
10911 * access initiates.
10914 * - 0 - This peripheral does not require supervisor privilege level for
10916 * - 1 - This peripheral requires supervisor privilege level for accesses.
10919 #define BP_AIPS_PACRO_SP7 (2U) /*!< Bit position for AIPS_PACRO_SP7. */
10920 #define BM_AIPS_PACRO_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRO_SP7. */
10921 #define BS_AIPS_PACRO_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRO_SP7. */
10923 /*! @brief Read current value of the AIPS_PACRO_SP7 field. */
10924 #define BR_AIPS_PACRO_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP7))
10926 /*! @brief Format value for bitfield AIPS_PACRO_SP7. */
10927 #define BF_AIPS_PACRO_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_SP7) & BM_AIPS_PACRO_SP7)
10929 /*! @brief Set the SP7 field to a new value. */
10930 #define BW_AIPS_PACRO_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP7) = (v))
10934 * @name Register AIPS_PACRO, field TP6[4] (RW)
10936 * Determines whether the peripheral allows accesses from an untrusted master.
10937 * When this field is set and an access is attempted by an untrusted master, the
10938 * access terminates with an error response and no peripheral access initiates.
10941 * - 0 - Accesses from an untrusted master are allowed.
10942 * - 1 - Accesses from an untrusted master are not allowed.
10945 #define BP_AIPS_PACRO_TP6 (4U) /*!< Bit position for AIPS_PACRO_TP6. */
10946 #define BM_AIPS_PACRO_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRO_TP6. */
10947 #define BS_AIPS_PACRO_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRO_TP6. */
10949 /*! @brief Read current value of the AIPS_PACRO_TP6 field. */
10950 #define BR_AIPS_PACRO_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP6))
10952 /*! @brief Format value for bitfield AIPS_PACRO_TP6. */
10953 #define BF_AIPS_PACRO_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_TP6) & BM_AIPS_PACRO_TP6)
10955 /*! @brief Set the TP6 field to a new value. */
10956 #define BW_AIPS_PACRO_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP6) = (v))
10960 * @name Register AIPS_PACRO, field WP6[5] (RW)
10962 * Determines whether the peripheral allows write accesses. When this field is
10963 * set and a write access is attempted, access terminates with an error response
10964 * and no peripheral access initiates.
10967 * - 0 - This peripheral allows write accesses.
10968 * - 1 - This peripheral is write protected.
10971 #define BP_AIPS_PACRO_WP6 (5U) /*!< Bit position for AIPS_PACRO_WP6. */
10972 #define BM_AIPS_PACRO_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRO_WP6. */
10973 #define BS_AIPS_PACRO_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRO_WP6. */
10975 /*! @brief Read current value of the AIPS_PACRO_WP6 field. */
10976 #define BR_AIPS_PACRO_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP6))
10978 /*! @brief Format value for bitfield AIPS_PACRO_WP6. */
10979 #define BF_AIPS_PACRO_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_WP6) & BM_AIPS_PACRO_WP6)
10981 /*! @brief Set the WP6 field to a new value. */
10982 #define BW_AIPS_PACRO_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP6) = (v))
10986 * @name Register AIPS_PACRO, field SP6[6] (RW)
10988 * Determines whether the peripheral requires supervisor privilege level for
10989 * accesses. When this field is set, the master privilege level must indicate the
10990 * supervisor access attribute, and the MPRx[MPLn] control field for the master
10991 * must be set. If not, access terminates with an error response and no peripheral
10992 * access initiates.
10995 * - 0 - This peripheral does not require supervisor privilege level for
10997 * - 1 - This peripheral requires supervisor privilege level for accesses.
11000 #define BP_AIPS_PACRO_SP6 (6U) /*!< Bit position for AIPS_PACRO_SP6. */
11001 #define BM_AIPS_PACRO_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRO_SP6. */
11002 #define BS_AIPS_PACRO_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRO_SP6. */
11004 /*! @brief Read current value of the AIPS_PACRO_SP6 field. */
11005 #define BR_AIPS_PACRO_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP6))
11007 /*! @brief Format value for bitfield AIPS_PACRO_SP6. */
11008 #define BF_AIPS_PACRO_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_SP6) & BM_AIPS_PACRO_SP6)
11010 /*! @brief Set the SP6 field to a new value. */
11011 #define BW_AIPS_PACRO_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP6) = (v))
11015 * @name Register AIPS_PACRO, field TP5[8] (RW)
11017 * Determines whether the peripheral allows accesses from an untrusted master.
11018 * When this field is set and an access is attempted by an untrusted master, the
11019 * access terminates with an error response and no peripheral access initiates.
11022 * - 0 - Accesses from an untrusted master are allowed.
11023 * - 1 - Accesses from an untrusted master are not allowed.
11026 #define BP_AIPS_PACRO_TP5 (8U) /*!< Bit position for AIPS_PACRO_TP5. */
11027 #define BM_AIPS_PACRO_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRO_TP5. */
11028 #define BS_AIPS_PACRO_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRO_TP5. */
11030 /*! @brief Read current value of the AIPS_PACRO_TP5 field. */
11031 #define BR_AIPS_PACRO_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP5))
11033 /*! @brief Format value for bitfield AIPS_PACRO_TP5. */
11034 #define BF_AIPS_PACRO_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_TP5) & BM_AIPS_PACRO_TP5)
11036 /*! @brief Set the TP5 field to a new value. */
11037 #define BW_AIPS_PACRO_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP5) = (v))
11041 * @name Register AIPS_PACRO, field WP5[9] (RW)
11043 * Determines whether the peripheral allows write accesses. When this field is
11044 * set and a write access is attempted, access terminates with an error response
11045 * and no peripheral access initiates.
11048 * - 0 - This peripheral allows write accesses.
11049 * - 1 - This peripheral is write protected.
11052 #define BP_AIPS_PACRO_WP5 (9U) /*!< Bit position for AIPS_PACRO_WP5. */
11053 #define BM_AIPS_PACRO_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRO_WP5. */
11054 #define BS_AIPS_PACRO_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRO_WP5. */
11056 /*! @brief Read current value of the AIPS_PACRO_WP5 field. */
11057 #define BR_AIPS_PACRO_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP5))
11059 /*! @brief Format value for bitfield AIPS_PACRO_WP5. */
11060 #define BF_AIPS_PACRO_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_WP5) & BM_AIPS_PACRO_WP5)
11062 /*! @brief Set the WP5 field to a new value. */
11063 #define BW_AIPS_PACRO_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP5) = (v))
11067 * @name Register AIPS_PACRO, field SP5[10] (RW)
11069 * Determines whether the peripheral requires supervisor privilege level for
11070 * accesses. When this field is set, the master privilege level must indicate the
11071 * supervisor access attribute, and the MPRx[MPLn] control field for the master
11072 * must be set. If not, access terminates with an error response and no peripheral
11073 * access initiates.
11076 * - 0 - This peripheral does not require supervisor privilege level for
11078 * - 1 - This peripheral requires supervisor privilege level for accesses.
11081 #define BP_AIPS_PACRO_SP5 (10U) /*!< Bit position for AIPS_PACRO_SP5. */
11082 #define BM_AIPS_PACRO_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRO_SP5. */
11083 #define BS_AIPS_PACRO_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRO_SP5. */
11085 /*! @brief Read current value of the AIPS_PACRO_SP5 field. */
11086 #define BR_AIPS_PACRO_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP5))
11088 /*! @brief Format value for bitfield AIPS_PACRO_SP5. */
11089 #define BF_AIPS_PACRO_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_SP5) & BM_AIPS_PACRO_SP5)
11091 /*! @brief Set the SP5 field to a new value. */
11092 #define BW_AIPS_PACRO_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP5) = (v))
11096 * @name Register AIPS_PACRO, field TP4[12] (RW)
11098 * Determines whether the peripheral allows accesses from an untrusted master.
11099 * When this bit is set and an access is attempted by an untrusted master, the
11100 * access terminates with an error response and no peripheral access initiates.
11103 * - 0 - Accesses from an untrusted master are allowed.
11104 * - 1 - Accesses from an untrusted master are not allowed.
11107 #define BP_AIPS_PACRO_TP4 (12U) /*!< Bit position for AIPS_PACRO_TP4. */
11108 #define BM_AIPS_PACRO_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRO_TP4. */
11109 #define BS_AIPS_PACRO_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRO_TP4. */
11111 /*! @brief Read current value of the AIPS_PACRO_TP4 field. */
11112 #define BR_AIPS_PACRO_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP4))
11114 /*! @brief Format value for bitfield AIPS_PACRO_TP4. */
11115 #define BF_AIPS_PACRO_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_TP4) & BM_AIPS_PACRO_TP4)
11117 /*! @brief Set the TP4 field to a new value. */
11118 #define BW_AIPS_PACRO_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP4) = (v))
11122 * @name Register AIPS_PACRO, field WP4[13] (RW)
11124 * Determines whether the peripheral allows write accesses. When this field is
11125 * set and a write access is attempted, access terminates with an error response
11126 * and no peripheral access initiates.
11129 * - 0 - This peripheral allows write accesses.
11130 * - 1 - This peripheral is write protected.
11133 #define BP_AIPS_PACRO_WP4 (13U) /*!< Bit position for AIPS_PACRO_WP4. */
11134 #define BM_AIPS_PACRO_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRO_WP4. */
11135 #define BS_AIPS_PACRO_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRO_WP4. */
11137 /*! @brief Read current value of the AIPS_PACRO_WP4 field. */
11138 #define BR_AIPS_PACRO_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP4))
11140 /*! @brief Format value for bitfield AIPS_PACRO_WP4. */
11141 #define BF_AIPS_PACRO_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_WP4) & BM_AIPS_PACRO_WP4)
11143 /*! @brief Set the WP4 field to a new value. */
11144 #define BW_AIPS_PACRO_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP4) = (v))
11148 * @name Register AIPS_PACRO, field SP4[14] (RW)
11150 * Determines whether the peripheral requires supervisor privilege level for
11151 * access. When this bit is set, the master privilege level must indicate the
11152 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
11153 * set. If not, access terminates with an error response and no peripheral access
11157 * - 0 - This peripheral does not require supervisor privilege level for
11159 * - 1 - This peripheral requires supervisor privilege level for accesses.
11162 #define BP_AIPS_PACRO_SP4 (14U) /*!< Bit position for AIPS_PACRO_SP4. */
11163 #define BM_AIPS_PACRO_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRO_SP4. */
11164 #define BS_AIPS_PACRO_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRO_SP4. */
11166 /*! @brief Read current value of the AIPS_PACRO_SP4 field. */
11167 #define BR_AIPS_PACRO_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP4))
11169 /*! @brief Format value for bitfield AIPS_PACRO_SP4. */
11170 #define BF_AIPS_PACRO_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_SP4) & BM_AIPS_PACRO_SP4)
11172 /*! @brief Set the SP4 field to a new value. */
11173 #define BW_AIPS_PACRO_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP4) = (v))
11177 * @name Register AIPS_PACRO, field TP3[16] (RW)
11179 * Determines whether the peripheral allows accesses from an untrusted master.
11180 * When this field is set and an access is attempted by an untrusted master, the
11181 * access terminates with an error response and no peripheral access initiates.
11184 * - 0 - Accesses from an untrusted master are allowed.
11185 * - 1 - Accesses from an untrusted master are not allowed.
11188 #define BP_AIPS_PACRO_TP3 (16U) /*!< Bit position for AIPS_PACRO_TP3. */
11189 #define BM_AIPS_PACRO_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRO_TP3. */
11190 #define BS_AIPS_PACRO_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRO_TP3. */
11192 /*! @brief Read current value of the AIPS_PACRO_TP3 field. */
11193 #define BR_AIPS_PACRO_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP3))
11195 /*! @brief Format value for bitfield AIPS_PACRO_TP3. */
11196 #define BF_AIPS_PACRO_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_TP3) & BM_AIPS_PACRO_TP3)
11198 /*! @brief Set the TP3 field to a new value. */
11199 #define BW_AIPS_PACRO_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP3) = (v))
11203 * @name Register AIPS_PACRO, field WP3[17] (RW)
11205 * Determines whether the peripheral allows write accesss. When this bit is set
11206 * and a write access is attempted, access terminates with an error response and
11207 * no peripheral access initiates.
11210 * - 0 - This peripheral allows write accesses.
11211 * - 1 - This peripheral is write protected.
11214 #define BP_AIPS_PACRO_WP3 (17U) /*!< Bit position for AIPS_PACRO_WP3. */
11215 #define BM_AIPS_PACRO_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRO_WP3. */
11216 #define BS_AIPS_PACRO_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRO_WP3. */
11218 /*! @brief Read current value of the AIPS_PACRO_WP3 field. */
11219 #define BR_AIPS_PACRO_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP3))
11221 /*! @brief Format value for bitfield AIPS_PACRO_WP3. */
11222 #define BF_AIPS_PACRO_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_WP3) & BM_AIPS_PACRO_WP3)
11224 /*! @brief Set the WP3 field to a new value. */
11225 #define BW_AIPS_PACRO_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP3) = (v))
11229 * @name Register AIPS_PACRO, field SP3[18] (RW)
11231 * Determines whether the peripheral requires supervisor privilege level for
11232 * accesses. When this field is set, the master privilege level must indicate the
11233 * supervisor access attribute, and the MPRx[MPLn] control field for the master
11234 * must be set. If not, access terminates with an error response and no peripheral
11235 * access initiates.
11238 * - 0 - This peripheral does not require supervisor privilege level for
11240 * - 1 - This peripheral requires supervisor privilege level for accesses.
11243 #define BP_AIPS_PACRO_SP3 (18U) /*!< Bit position for AIPS_PACRO_SP3. */
11244 #define BM_AIPS_PACRO_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRO_SP3. */
11245 #define BS_AIPS_PACRO_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRO_SP3. */
11247 /*! @brief Read current value of the AIPS_PACRO_SP3 field. */
11248 #define BR_AIPS_PACRO_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP3))
11250 /*! @brief Format value for bitfield AIPS_PACRO_SP3. */
11251 #define BF_AIPS_PACRO_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_SP3) & BM_AIPS_PACRO_SP3)
11253 /*! @brief Set the SP3 field to a new value. */
11254 #define BW_AIPS_PACRO_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP3) = (v))
11258 * @name Register AIPS_PACRO, field TP2[20] (RW)
11260 * Determines whether the peripheral allows accesses from an untrusted master.
11261 * When this bit is set and an access is attempted by an untrusted master, the
11262 * access terminates with an error response and no peripheral access initiates.
11265 * - 0 - Accesses from an untrusted master are allowed.
11266 * - 1 - Accesses from an untrusted master are not allowed.
11269 #define BP_AIPS_PACRO_TP2 (20U) /*!< Bit position for AIPS_PACRO_TP2. */
11270 #define BM_AIPS_PACRO_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRO_TP2. */
11271 #define BS_AIPS_PACRO_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRO_TP2. */
11273 /*! @brief Read current value of the AIPS_PACRO_TP2 field. */
11274 #define BR_AIPS_PACRO_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP2))
11276 /*! @brief Format value for bitfield AIPS_PACRO_TP2. */
11277 #define BF_AIPS_PACRO_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_TP2) & BM_AIPS_PACRO_TP2)
11279 /*! @brief Set the TP2 field to a new value. */
11280 #define BW_AIPS_PACRO_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP2) = (v))
11284 * @name Register AIPS_PACRO, field WP2[21] (RW)
11286 * Determines whether the peripheral allows write accesses. When this field is
11287 * set and a write access is attempted, access terminates with an error response
11288 * and no peripheral access initiates.
11291 * - 0 - This peripheral allows write accesses.
11292 * - 1 - This peripheral is write protected.
11295 #define BP_AIPS_PACRO_WP2 (21U) /*!< Bit position for AIPS_PACRO_WP2. */
11296 #define BM_AIPS_PACRO_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRO_WP2. */
11297 #define BS_AIPS_PACRO_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRO_WP2. */
11299 /*! @brief Read current value of the AIPS_PACRO_WP2 field. */
11300 #define BR_AIPS_PACRO_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP2))
11302 /*! @brief Format value for bitfield AIPS_PACRO_WP2. */
11303 #define BF_AIPS_PACRO_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_WP2) & BM_AIPS_PACRO_WP2)
11305 /*! @brief Set the WP2 field to a new value. */
11306 #define BW_AIPS_PACRO_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP2) = (v))
11310 * @name Register AIPS_PACRO, field SP2[22] (RW)
11312 * Determines whether the peripheral requires supervisor privilege level for
11313 * access. When this bit is set, the master privilege level must indicate the
11314 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
11315 * set. If not, access terminates with an error response and no peripheral access
11319 * - 0 - This peripheral does not require supervisor privilege level for
11321 * - 1 - This peripheral requires supervisor privilege level for accesses.
11324 #define BP_AIPS_PACRO_SP2 (22U) /*!< Bit position for AIPS_PACRO_SP2. */
11325 #define BM_AIPS_PACRO_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRO_SP2. */
11326 #define BS_AIPS_PACRO_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRO_SP2. */
11328 /*! @brief Read current value of the AIPS_PACRO_SP2 field. */
11329 #define BR_AIPS_PACRO_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP2))
11331 /*! @brief Format value for bitfield AIPS_PACRO_SP2. */
11332 #define BF_AIPS_PACRO_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_SP2) & BM_AIPS_PACRO_SP2)
11334 /*! @brief Set the SP2 field to a new value. */
11335 #define BW_AIPS_PACRO_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP2) = (v))
11339 * @name Register AIPS_PACRO, field TP1[24] (RW)
11341 * Determines whether the peripheral allows accesses from an untrusted master.
11342 * When this field is set and an access is attempted by an untrusted master, the
11343 * access terminates with an error response and no peripheral access initiates.
11346 * - 0 - Accesses from an untrusted master are allowed.
11347 * - 1 - Accesses from an untrusted master are not allowed.
11350 #define BP_AIPS_PACRO_TP1 (24U) /*!< Bit position for AIPS_PACRO_TP1. */
11351 #define BM_AIPS_PACRO_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRO_TP1. */
11352 #define BS_AIPS_PACRO_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRO_TP1. */
11354 /*! @brief Read current value of the AIPS_PACRO_TP1 field. */
11355 #define BR_AIPS_PACRO_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP1))
11357 /*! @brief Format value for bitfield AIPS_PACRO_TP1. */
11358 #define BF_AIPS_PACRO_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_TP1) & BM_AIPS_PACRO_TP1)
11360 /*! @brief Set the TP1 field to a new value. */
11361 #define BW_AIPS_PACRO_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP1) = (v))
11365 * @name Register AIPS_PACRO, field WP1[25] (RW)
11367 * Determines whether the peripheral allows write accesses. When this field is
11368 * set and a write access is attempted, access terminates with an error response
11369 * and no peripheral access initiates.
11372 * - 0 - This peripheral allows write accesses.
11373 * - 1 - This peripheral is write protected.
11376 #define BP_AIPS_PACRO_WP1 (25U) /*!< Bit position for AIPS_PACRO_WP1. */
11377 #define BM_AIPS_PACRO_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRO_WP1. */
11378 #define BS_AIPS_PACRO_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRO_WP1. */
11380 /*! @brief Read current value of the AIPS_PACRO_WP1 field. */
11381 #define BR_AIPS_PACRO_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP1))
11383 /*! @brief Format value for bitfield AIPS_PACRO_WP1. */
11384 #define BF_AIPS_PACRO_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_WP1) & BM_AIPS_PACRO_WP1)
11386 /*! @brief Set the WP1 field to a new value. */
11387 #define BW_AIPS_PACRO_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP1) = (v))
11391 * @name Register AIPS_PACRO, field SP1[26] (RW)
11393 * Determines whether the peripheral requires supervisor privilege level for
11394 * access. When this field is set, the master privilege level must indicate the
11395 * supervisor access attribute, and the MPRx[MPLn] control field for the master must
11396 * be set. If not, access terminates with an error response and no peripheral
11397 * access initiates.
11400 * - 0 - This peripheral does not require supervisor privilege level for
11402 * - 1 - This peripheral requires supervisor privilege level for accesses.
11405 #define BP_AIPS_PACRO_SP1 (26U) /*!< Bit position for AIPS_PACRO_SP1. */
11406 #define BM_AIPS_PACRO_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRO_SP1. */
11407 #define BS_AIPS_PACRO_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRO_SP1. */
11409 /*! @brief Read current value of the AIPS_PACRO_SP1 field. */
11410 #define BR_AIPS_PACRO_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP1))
11412 /*! @brief Format value for bitfield AIPS_PACRO_SP1. */
11413 #define BF_AIPS_PACRO_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_SP1) & BM_AIPS_PACRO_SP1)
11415 /*! @brief Set the SP1 field to a new value. */
11416 #define BW_AIPS_PACRO_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP1) = (v))
11420 * @name Register AIPS_PACRO, field TP0[28] (RW)
11422 * Determines whether the peripheral allows accesses from an untrusted master.
11423 * When this bit is set and an access is attempted by an untrusted master, the
11424 * access terminates with an error response and no peripheral access initiates.
11427 * - 0 - Accesses from an untrusted master are allowed.
11428 * - 1 - Accesses from an untrusted master are not allowed.
11431 #define BP_AIPS_PACRO_TP0 (28U) /*!< Bit position for AIPS_PACRO_TP0. */
11432 #define BM_AIPS_PACRO_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRO_TP0. */
11433 #define BS_AIPS_PACRO_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRO_TP0. */
11435 /*! @brief Read current value of the AIPS_PACRO_TP0 field. */
11436 #define BR_AIPS_PACRO_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP0))
11438 /*! @brief Format value for bitfield AIPS_PACRO_TP0. */
11439 #define BF_AIPS_PACRO_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_TP0) & BM_AIPS_PACRO_TP0)
11441 /*! @brief Set the TP0 field to a new value. */
11442 #define BW_AIPS_PACRO_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP0) = (v))
11446 * @name Register AIPS_PACRO, field WP0[29] (RW)
11448 * Determines whether the peripheral allows write accesses. When this field is
11449 * set and a write access is attempted, access terminates with an error response
11450 * and no peripheral access initiates.
11453 * - 0 - This peripheral allows write accesses.
11454 * - 1 - This peripheral is write protected.
11457 #define BP_AIPS_PACRO_WP0 (29U) /*!< Bit position for AIPS_PACRO_WP0. */
11458 #define BM_AIPS_PACRO_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRO_WP0. */
11459 #define BS_AIPS_PACRO_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRO_WP0. */
11461 /*! @brief Read current value of the AIPS_PACRO_WP0 field. */
11462 #define BR_AIPS_PACRO_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP0))
11464 /*! @brief Format value for bitfield AIPS_PACRO_WP0. */
11465 #define BF_AIPS_PACRO_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_WP0) & BM_AIPS_PACRO_WP0)
11467 /*! @brief Set the WP0 field to a new value. */
11468 #define BW_AIPS_PACRO_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP0) = (v))
11472 * @name Register AIPS_PACRO, field SP0[30] (RW)
11474 * Determines whether the peripheral requires supervisor privilege level for
11475 * accesses. When this field is set, the master privilege level must indicate the
11476 * supervisor access attribute, and the MPRx[MPLn] control field for the master
11477 * must be set. If not, access terminates with an error response and no peripheral
11478 * access initiates.
11481 * - 0 - This peripheral does not require supervisor privilege level for
11483 * - 1 - This peripheral requires supervisor privilege level for accesses.
11486 #define BP_AIPS_PACRO_SP0 (30U) /*!< Bit position for AIPS_PACRO_SP0. */
11487 #define BM_AIPS_PACRO_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRO_SP0. */
11488 #define BS_AIPS_PACRO_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRO_SP0. */
11490 /*! @brief Read current value of the AIPS_PACRO_SP0 field. */
11491 #define BR_AIPS_PACRO_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP0))
11493 /*! @brief Format value for bitfield AIPS_PACRO_SP0. */
11494 #define BF_AIPS_PACRO_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_SP0) & BM_AIPS_PACRO_SP0)
11496 /*! @brief Set the SP0 field to a new value. */
11497 #define BW_AIPS_PACRO_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP0) = (v))
11500 /*******************************************************************************
11501 * HW_AIPS_PACRP - Peripheral Access Control Register
11502 ******************************************************************************/
11505 * @brief HW_AIPS_PACRP - Peripheral Access Control Register (RW)
11507 * Reset value: 0x44444444U
11509 * This section describes PACR registers E-P, which control peripheral slots
11510 * 32-127. See PACRPeripheral Access Control Register for the description of these
11513 typedef union _hw_aips_pacrp
11516 struct _hw_aips_pacrp_bitfields
11518 uint32_t TP7
: 1; /*!< [0] Trusted Protect */
11519 uint32_t WP7
: 1; /*!< [1] Write Protect */
11520 uint32_t SP7
: 1; /*!< [2] Supervisor Protect */
11521 uint32_t RESERVED0
: 1; /*!< [3] */
11522 uint32_t TP6
: 1; /*!< [4] Trusted Protect */
11523 uint32_t WP6
: 1; /*!< [5] Write Protect */
11524 uint32_t SP6
: 1; /*!< [6] Supervisor Protect */
11525 uint32_t RESERVED1
: 1; /*!< [7] */
11526 uint32_t TP5
: 1; /*!< [8] Trusted Protect */
11527 uint32_t WP5
: 1; /*!< [9] Write Protect */
11528 uint32_t SP5
: 1; /*!< [10] Supervisor Protect */
11529 uint32_t RESERVED2
: 1; /*!< [11] */
11530 uint32_t TP4
: 1; /*!< [12] Trusted Protect */
11531 uint32_t WP4
: 1; /*!< [13] Write Protect */
11532 uint32_t SP4
: 1; /*!< [14] Supervisor Protect */
11533 uint32_t RESERVED3
: 1; /*!< [15] */
11534 uint32_t TP3
: 1; /*!< [16] Trusted Protect */
11535 uint32_t WP3
: 1; /*!< [17] Write Protect */
11536 uint32_t SP3
: 1; /*!< [18] Supervisor Protect */
11537 uint32_t RESERVED4
: 1; /*!< [19] */
11538 uint32_t TP2
: 1; /*!< [20] Trusted Protect */
11539 uint32_t WP2
: 1; /*!< [21] Write Protect */
11540 uint32_t SP2
: 1; /*!< [22] Supervisor Protect */
11541 uint32_t RESERVED5
: 1; /*!< [23] */
11542 uint32_t TP1
: 1; /*!< [24] Trusted Protect */
11543 uint32_t WP1
: 1; /*!< [25] Write Protect */
11544 uint32_t SP1
: 1; /*!< [26] Supervisor Protect */
11545 uint32_t RESERVED6
: 1; /*!< [27] */
11546 uint32_t TP0
: 1; /*!< [28] Trusted Protect */
11547 uint32_t WP0
: 1; /*!< [29] Write Protect */
11548 uint32_t SP0
: 1; /*!< [30] Supervisor Protect */
11549 uint32_t RESERVED7
: 1; /*!< [31] */
11554 * @name Constants and macros for entire AIPS_PACRP register
11557 #define HW_AIPS_PACRP_ADDR(x) ((x) + 0x6CU)
11559 #define HW_AIPS_PACRP(x) (*(__IO hw_aips_pacrp_t *) HW_AIPS_PACRP_ADDR(x))
11560 #define HW_AIPS_PACRP_RD(x) (HW_AIPS_PACRP(x).U)
11561 #define HW_AIPS_PACRP_WR(x, v) (HW_AIPS_PACRP(x).U = (v))
11562 #define HW_AIPS_PACRP_SET(x, v) (HW_AIPS_PACRP_WR(x, HW_AIPS_PACRP_RD(x) | (v)))
11563 #define HW_AIPS_PACRP_CLR(x, v) (HW_AIPS_PACRP_WR(x, HW_AIPS_PACRP_RD(x) & ~(v)))
11564 #define HW_AIPS_PACRP_TOG(x, v) (HW_AIPS_PACRP_WR(x, HW_AIPS_PACRP_RD(x) ^ (v)))
11568 * Constants & macros for individual AIPS_PACRP bitfields
11572 * @name Register AIPS_PACRP, field TP7[0] (RW)
11574 * Determines whether the peripheral allows accesses from an untrusted master.
11575 * When this field is set and an access is attempted by an untrusted master, the
11576 * access terminates with an error response and no peripheral access initiates.
11579 * - 0 - Accesses from an untrusted master are allowed.
11580 * - 1 - Accesses from an untrusted master are not allowed.
11583 #define BP_AIPS_PACRP_TP7 (0U) /*!< Bit position for AIPS_PACRP_TP7. */
11584 #define BM_AIPS_PACRP_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRP_TP7. */
11585 #define BS_AIPS_PACRP_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRP_TP7. */
11587 /*! @brief Read current value of the AIPS_PACRP_TP7 field. */
11588 #define BR_AIPS_PACRP_TP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP7))
11590 /*! @brief Format value for bitfield AIPS_PACRP_TP7. */
11591 #define BF_AIPS_PACRP_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_TP7) & BM_AIPS_PACRP_TP7)
11593 /*! @brief Set the TP7 field to a new value. */
11594 #define BW_AIPS_PACRP_TP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP7) = (v))
11598 * @name Register AIPS_PACRP, field WP7[1] (RW)
11600 * Determines whether the peripheral allows write accesses. When this field is
11601 * set and a write access is attempted, access terminates with an error response
11602 * and no peripheral access initiates.
11605 * - 0 - This peripheral allows write accesses.
11606 * - 1 - This peripheral is write protected.
11609 #define BP_AIPS_PACRP_WP7 (1U) /*!< Bit position for AIPS_PACRP_WP7. */
11610 #define BM_AIPS_PACRP_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRP_WP7. */
11611 #define BS_AIPS_PACRP_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRP_WP7. */
11613 /*! @brief Read current value of the AIPS_PACRP_WP7 field. */
11614 #define BR_AIPS_PACRP_WP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP7))
11616 /*! @brief Format value for bitfield AIPS_PACRP_WP7. */
11617 #define BF_AIPS_PACRP_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_WP7) & BM_AIPS_PACRP_WP7)
11619 /*! @brief Set the WP7 field to a new value. */
11620 #define BW_AIPS_PACRP_WP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP7) = (v))
11624 * @name Register AIPS_PACRP, field SP7[2] (RW)
11626 * Determines whether the peripheral requires supervisor privilege level for
11627 * accesses. When this field is set, the master privilege level must indicate the
11628 * supervisor access attribute, and the MPRx[MPLn] control field for the master
11629 * must be set. If not, access terminates with an error response and no peripheral
11630 * access initiates.
11633 * - 0 - This peripheral does not require supervisor privilege level for
11635 * - 1 - This peripheral requires supervisor privilege level for accesses.
11638 #define BP_AIPS_PACRP_SP7 (2U) /*!< Bit position for AIPS_PACRP_SP7. */
11639 #define BM_AIPS_PACRP_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRP_SP7. */
11640 #define BS_AIPS_PACRP_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRP_SP7. */
11642 /*! @brief Read current value of the AIPS_PACRP_SP7 field. */
11643 #define BR_AIPS_PACRP_SP7(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP7))
11645 /*! @brief Format value for bitfield AIPS_PACRP_SP7. */
11646 #define BF_AIPS_PACRP_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_SP7) & BM_AIPS_PACRP_SP7)
11648 /*! @brief Set the SP7 field to a new value. */
11649 #define BW_AIPS_PACRP_SP7(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP7) = (v))
11653 * @name Register AIPS_PACRP, field TP6[4] (RW)
11655 * Determines whether the peripheral allows accesses from an untrusted master.
11656 * When this field is set and an access is attempted by an untrusted master, the
11657 * access terminates with an error response and no peripheral access initiates.
11660 * - 0 - Accesses from an untrusted master are allowed.
11661 * - 1 - Accesses from an untrusted master are not allowed.
11664 #define BP_AIPS_PACRP_TP6 (4U) /*!< Bit position for AIPS_PACRP_TP6. */
11665 #define BM_AIPS_PACRP_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRP_TP6. */
11666 #define BS_AIPS_PACRP_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRP_TP6. */
11668 /*! @brief Read current value of the AIPS_PACRP_TP6 field. */
11669 #define BR_AIPS_PACRP_TP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP6))
11671 /*! @brief Format value for bitfield AIPS_PACRP_TP6. */
11672 #define BF_AIPS_PACRP_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_TP6) & BM_AIPS_PACRP_TP6)
11674 /*! @brief Set the TP6 field to a new value. */
11675 #define BW_AIPS_PACRP_TP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP6) = (v))
11679 * @name Register AIPS_PACRP, field WP6[5] (RW)
11681 * Determines whether the peripheral allows write accesses. When this field is
11682 * set and a write access is attempted, access terminates with an error response
11683 * and no peripheral access initiates.
11686 * - 0 - This peripheral allows write accesses.
11687 * - 1 - This peripheral is write protected.
11690 #define BP_AIPS_PACRP_WP6 (5U) /*!< Bit position for AIPS_PACRP_WP6. */
11691 #define BM_AIPS_PACRP_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRP_WP6. */
11692 #define BS_AIPS_PACRP_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRP_WP6. */
11694 /*! @brief Read current value of the AIPS_PACRP_WP6 field. */
11695 #define BR_AIPS_PACRP_WP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP6))
11697 /*! @brief Format value for bitfield AIPS_PACRP_WP6. */
11698 #define BF_AIPS_PACRP_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_WP6) & BM_AIPS_PACRP_WP6)
11700 /*! @brief Set the WP6 field to a new value. */
11701 #define BW_AIPS_PACRP_WP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP6) = (v))
11705 * @name Register AIPS_PACRP, field SP6[6] (RW)
11707 * Determines whether the peripheral requires supervisor privilege level for
11708 * accesses. When this field is set, the master privilege level must indicate the
11709 * supervisor access attribute, and the MPRx[MPLn] control field for the master
11710 * must be set. If not, access terminates with an error response and no peripheral
11711 * access initiates.
11714 * - 0 - This peripheral does not require supervisor privilege level for
11716 * - 1 - This peripheral requires supervisor privilege level for accesses.
11719 #define BP_AIPS_PACRP_SP6 (6U) /*!< Bit position for AIPS_PACRP_SP6. */
11720 #define BM_AIPS_PACRP_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRP_SP6. */
11721 #define BS_AIPS_PACRP_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRP_SP6. */
11723 /*! @brief Read current value of the AIPS_PACRP_SP6 field. */
11724 #define BR_AIPS_PACRP_SP6(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP6))
11726 /*! @brief Format value for bitfield AIPS_PACRP_SP6. */
11727 #define BF_AIPS_PACRP_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_SP6) & BM_AIPS_PACRP_SP6)
11729 /*! @brief Set the SP6 field to a new value. */
11730 #define BW_AIPS_PACRP_SP6(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP6) = (v))
11734 * @name Register AIPS_PACRP, field TP5[8] (RW)
11736 * Determines whether the peripheral allows accesses from an untrusted master.
11737 * When this field is set and an access is attempted by an untrusted master, the
11738 * access terminates with an error response and no peripheral access initiates.
11741 * - 0 - Accesses from an untrusted master are allowed.
11742 * - 1 - Accesses from an untrusted master are not allowed.
11745 #define BP_AIPS_PACRP_TP5 (8U) /*!< Bit position for AIPS_PACRP_TP5. */
11746 #define BM_AIPS_PACRP_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRP_TP5. */
11747 #define BS_AIPS_PACRP_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRP_TP5. */
11749 /*! @brief Read current value of the AIPS_PACRP_TP5 field. */
11750 #define BR_AIPS_PACRP_TP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP5))
11752 /*! @brief Format value for bitfield AIPS_PACRP_TP5. */
11753 #define BF_AIPS_PACRP_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_TP5) & BM_AIPS_PACRP_TP5)
11755 /*! @brief Set the TP5 field to a new value. */
11756 #define BW_AIPS_PACRP_TP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP5) = (v))
11760 * @name Register AIPS_PACRP, field WP5[9] (RW)
11762 * Determines whether the peripheral allows write accesses. When this field is
11763 * set and a write access is attempted, access terminates with an error response
11764 * and no peripheral access initiates.
11767 * - 0 - This peripheral allows write accesses.
11768 * - 1 - This peripheral is write protected.
11771 #define BP_AIPS_PACRP_WP5 (9U) /*!< Bit position for AIPS_PACRP_WP5. */
11772 #define BM_AIPS_PACRP_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRP_WP5. */
11773 #define BS_AIPS_PACRP_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRP_WP5. */
11775 /*! @brief Read current value of the AIPS_PACRP_WP5 field. */
11776 #define BR_AIPS_PACRP_WP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP5))
11778 /*! @brief Format value for bitfield AIPS_PACRP_WP5. */
11779 #define BF_AIPS_PACRP_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_WP5) & BM_AIPS_PACRP_WP5)
11781 /*! @brief Set the WP5 field to a new value. */
11782 #define BW_AIPS_PACRP_WP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP5) = (v))
11786 * @name Register AIPS_PACRP, field SP5[10] (RW)
11788 * Determines whether the peripheral requires supervisor privilege level for
11789 * accesses. When this field is set, the master privilege level must indicate the
11790 * supervisor access attribute, and the MPRx[MPLn] control field for the master
11791 * must be set. If not, access terminates with an error response and no peripheral
11792 * access initiates.
11795 * - 0 - This peripheral does not require supervisor privilege level for
11797 * - 1 - This peripheral requires supervisor privilege level for accesses.
11800 #define BP_AIPS_PACRP_SP5 (10U) /*!< Bit position for AIPS_PACRP_SP5. */
11801 #define BM_AIPS_PACRP_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRP_SP5. */
11802 #define BS_AIPS_PACRP_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRP_SP5. */
11804 /*! @brief Read current value of the AIPS_PACRP_SP5 field. */
11805 #define BR_AIPS_PACRP_SP5(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP5))
11807 /*! @brief Format value for bitfield AIPS_PACRP_SP5. */
11808 #define BF_AIPS_PACRP_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_SP5) & BM_AIPS_PACRP_SP5)
11810 /*! @brief Set the SP5 field to a new value. */
11811 #define BW_AIPS_PACRP_SP5(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP5) = (v))
11815 * @name Register AIPS_PACRP, field TP4[12] (RW)
11817 * Determines whether the peripheral allows accesses from an untrusted master.
11818 * When this bit is set and an access is attempted by an untrusted master, the
11819 * access terminates with an error response and no peripheral access initiates.
11822 * - 0 - Accesses from an untrusted master are allowed.
11823 * - 1 - Accesses from an untrusted master are not allowed.
11826 #define BP_AIPS_PACRP_TP4 (12U) /*!< Bit position for AIPS_PACRP_TP4. */
11827 #define BM_AIPS_PACRP_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRP_TP4. */
11828 #define BS_AIPS_PACRP_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRP_TP4. */
11830 /*! @brief Read current value of the AIPS_PACRP_TP4 field. */
11831 #define BR_AIPS_PACRP_TP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP4))
11833 /*! @brief Format value for bitfield AIPS_PACRP_TP4. */
11834 #define BF_AIPS_PACRP_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_TP4) & BM_AIPS_PACRP_TP4)
11836 /*! @brief Set the TP4 field to a new value. */
11837 #define BW_AIPS_PACRP_TP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP4) = (v))
11841 * @name Register AIPS_PACRP, field WP4[13] (RW)
11843 * Determines whether the peripheral allows write accesses. When this field is
11844 * set and a write access is attempted, access terminates with an error response
11845 * and no peripheral access initiates.
11848 * - 0 - This peripheral allows write accesses.
11849 * - 1 - This peripheral is write protected.
11852 #define BP_AIPS_PACRP_WP4 (13U) /*!< Bit position for AIPS_PACRP_WP4. */
11853 #define BM_AIPS_PACRP_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRP_WP4. */
11854 #define BS_AIPS_PACRP_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRP_WP4. */
11856 /*! @brief Read current value of the AIPS_PACRP_WP4 field. */
11857 #define BR_AIPS_PACRP_WP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP4))
11859 /*! @brief Format value for bitfield AIPS_PACRP_WP4. */
11860 #define BF_AIPS_PACRP_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_WP4) & BM_AIPS_PACRP_WP4)
11862 /*! @brief Set the WP4 field to a new value. */
11863 #define BW_AIPS_PACRP_WP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP4) = (v))
11867 * @name Register AIPS_PACRP, field SP4[14] (RW)
11869 * Determines whether the peripheral requires supervisor privilege level for
11870 * access. When this bit is set, the master privilege level must indicate the
11871 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
11872 * set. If not, access terminates with an error response and no peripheral access
11876 * - 0 - This peripheral does not require supervisor privilege level for
11878 * - 1 - This peripheral requires supervisor privilege level for accesses.
11881 #define BP_AIPS_PACRP_SP4 (14U) /*!< Bit position for AIPS_PACRP_SP4. */
11882 #define BM_AIPS_PACRP_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRP_SP4. */
11883 #define BS_AIPS_PACRP_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRP_SP4. */
11885 /*! @brief Read current value of the AIPS_PACRP_SP4 field. */
11886 #define BR_AIPS_PACRP_SP4(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP4))
11888 /*! @brief Format value for bitfield AIPS_PACRP_SP4. */
11889 #define BF_AIPS_PACRP_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_SP4) & BM_AIPS_PACRP_SP4)
11891 /*! @brief Set the SP4 field to a new value. */
11892 #define BW_AIPS_PACRP_SP4(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP4) = (v))
11896 * @name Register AIPS_PACRP, field TP3[16] (RW)
11898 * Determines whether the peripheral allows accesses from an untrusted master.
11899 * When this field is set and an access is attempted by an untrusted master, the
11900 * access terminates with an error response and no peripheral access initiates.
11903 * - 0 - Accesses from an untrusted master are allowed.
11904 * - 1 - Accesses from an untrusted master are not allowed.
11907 #define BP_AIPS_PACRP_TP3 (16U) /*!< Bit position for AIPS_PACRP_TP3. */
11908 #define BM_AIPS_PACRP_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRP_TP3. */
11909 #define BS_AIPS_PACRP_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRP_TP3. */
11911 /*! @brief Read current value of the AIPS_PACRP_TP3 field. */
11912 #define BR_AIPS_PACRP_TP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP3))
11914 /*! @brief Format value for bitfield AIPS_PACRP_TP3. */
11915 #define BF_AIPS_PACRP_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_TP3) & BM_AIPS_PACRP_TP3)
11917 /*! @brief Set the TP3 field to a new value. */
11918 #define BW_AIPS_PACRP_TP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP3) = (v))
11922 * @name Register AIPS_PACRP, field WP3[17] (RW)
11924 * Determines whether the peripheral allows write accesss. When this bit is set
11925 * and a write access is attempted, access terminates with an error response and
11926 * no peripheral access initiates.
11929 * - 0 - This peripheral allows write accesses.
11930 * - 1 - This peripheral is write protected.
11933 #define BP_AIPS_PACRP_WP3 (17U) /*!< Bit position for AIPS_PACRP_WP3. */
11934 #define BM_AIPS_PACRP_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRP_WP3. */
11935 #define BS_AIPS_PACRP_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRP_WP3. */
11937 /*! @brief Read current value of the AIPS_PACRP_WP3 field. */
11938 #define BR_AIPS_PACRP_WP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP3))
11940 /*! @brief Format value for bitfield AIPS_PACRP_WP3. */
11941 #define BF_AIPS_PACRP_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_WP3) & BM_AIPS_PACRP_WP3)
11943 /*! @brief Set the WP3 field to a new value. */
11944 #define BW_AIPS_PACRP_WP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP3) = (v))
11948 * @name Register AIPS_PACRP, field SP3[18] (RW)
11950 * Determines whether the peripheral requires supervisor privilege level for
11951 * accesses. When this field is set, the master privilege level must indicate the
11952 * supervisor access attribute, and the MPRx[MPLn] control field for the master
11953 * must be set. If not, access terminates with an error response and no peripheral
11954 * access initiates.
11957 * - 0 - This peripheral does not require supervisor privilege level for
11959 * - 1 - This peripheral requires supervisor privilege level for accesses.
11962 #define BP_AIPS_PACRP_SP3 (18U) /*!< Bit position for AIPS_PACRP_SP3. */
11963 #define BM_AIPS_PACRP_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRP_SP3. */
11964 #define BS_AIPS_PACRP_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRP_SP3. */
11966 /*! @brief Read current value of the AIPS_PACRP_SP3 field. */
11967 #define BR_AIPS_PACRP_SP3(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP3))
11969 /*! @brief Format value for bitfield AIPS_PACRP_SP3. */
11970 #define BF_AIPS_PACRP_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_SP3) & BM_AIPS_PACRP_SP3)
11972 /*! @brief Set the SP3 field to a new value. */
11973 #define BW_AIPS_PACRP_SP3(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP3) = (v))
11977 * @name Register AIPS_PACRP, field TP2[20] (RW)
11979 * Determines whether the peripheral allows accesses from an untrusted master.
11980 * When this bit is set and an access is attempted by an untrusted master, the
11981 * access terminates with an error response and no peripheral access initiates.
11984 * - 0 - Accesses from an untrusted master are allowed.
11985 * - 1 - Accesses from an untrusted master are not allowed.
11988 #define BP_AIPS_PACRP_TP2 (20U) /*!< Bit position for AIPS_PACRP_TP2. */
11989 #define BM_AIPS_PACRP_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRP_TP2. */
11990 #define BS_AIPS_PACRP_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRP_TP2. */
11992 /*! @brief Read current value of the AIPS_PACRP_TP2 field. */
11993 #define BR_AIPS_PACRP_TP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP2))
11995 /*! @brief Format value for bitfield AIPS_PACRP_TP2. */
11996 #define BF_AIPS_PACRP_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_TP2) & BM_AIPS_PACRP_TP2)
11998 /*! @brief Set the TP2 field to a new value. */
11999 #define BW_AIPS_PACRP_TP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP2) = (v))
12003 * @name Register AIPS_PACRP, field WP2[21] (RW)
12005 * Determines whether the peripheral allows write accesses. When this field is
12006 * set and a write access is attempted, access terminates with an error response
12007 * and no peripheral access initiates.
12010 * - 0 - This peripheral allows write accesses.
12011 * - 1 - This peripheral is write protected.
12014 #define BP_AIPS_PACRP_WP2 (21U) /*!< Bit position for AIPS_PACRP_WP2. */
12015 #define BM_AIPS_PACRP_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRP_WP2. */
12016 #define BS_AIPS_PACRP_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRP_WP2. */
12018 /*! @brief Read current value of the AIPS_PACRP_WP2 field. */
12019 #define BR_AIPS_PACRP_WP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP2))
12021 /*! @brief Format value for bitfield AIPS_PACRP_WP2. */
12022 #define BF_AIPS_PACRP_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_WP2) & BM_AIPS_PACRP_WP2)
12024 /*! @brief Set the WP2 field to a new value. */
12025 #define BW_AIPS_PACRP_WP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP2) = (v))
12029 * @name Register AIPS_PACRP, field SP2[22] (RW)
12031 * Determines whether the peripheral requires supervisor privilege level for
12032 * access. When this bit is set, the master privilege level must indicate the
12033 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
12034 * set. If not, access terminates with an error response and no peripheral access
12038 * - 0 - This peripheral does not require supervisor privilege level for
12040 * - 1 - This peripheral requires supervisor privilege level for accesses.
12043 #define BP_AIPS_PACRP_SP2 (22U) /*!< Bit position for AIPS_PACRP_SP2. */
12044 #define BM_AIPS_PACRP_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRP_SP2. */
12045 #define BS_AIPS_PACRP_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRP_SP2. */
12047 /*! @brief Read current value of the AIPS_PACRP_SP2 field. */
12048 #define BR_AIPS_PACRP_SP2(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP2))
12050 /*! @brief Format value for bitfield AIPS_PACRP_SP2. */
12051 #define BF_AIPS_PACRP_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_SP2) & BM_AIPS_PACRP_SP2)
12053 /*! @brief Set the SP2 field to a new value. */
12054 #define BW_AIPS_PACRP_SP2(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP2) = (v))
12058 * @name Register AIPS_PACRP, field TP1[24] (RW)
12060 * Determines whether the peripheral allows accesses from an untrusted master.
12061 * When this field is set and an access is attempted by an untrusted master, the
12062 * access terminates with an error response and no peripheral access initiates.
12065 * - 0 - Accesses from an untrusted master are allowed.
12066 * - 1 - Accesses from an untrusted master are not allowed.
12069 #define BP_AIPS_PACRP_TP1 (24U) /*!< Bit position for AIPS_PACRP_TP1. */
12070 #define BM_AIPS_PACRP_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRP_TP1. */
12071 #define BS_AIPS_PACRP_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRP_TP1. */
12073 /*! @brief Read current value of the AIPS_PACRP_TP1 field. */
12074 #define BR_AIPS_PACRP_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP1))
12076 /*! @brief Format value for bitfield AIPS_PACRP_TP1. */
12077 #define BF_AIPS_PACRP_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_TP1) & BM_AIPS_PACRP_TP1)
12079 /*! @brief Set the TP1 field to a new value. */
12080 #define BW_AIPS_PACRP_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP1) = (v))
12084 * @name Register AIPS_PACRP, field WP1[25] (RW)
12086 * Determines whether the peripheral allows write accesses. When this field is
12087 * set and a write access is attempted, access terminates with an error response
12088 * and no peripheral access initiates.
12091 * - 0 - This peripheral allows write accesses.
12092 * - 1 - This peripheral is write protected.
12095 #define BP_AIPS_PACRP_WP1 (25U) /*!< Bit position for AIPS_PACRP_WP1. */
12096 #define BM_AIPS_PACRP_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRP_WP1. */
12097 #define BS_AIPS_PACRP_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRP_WP1. */
12099 /*! @brief Read current value of the AIPS_PACRP_WP1 field. */
12100 #define BR_AIPS_PACRP_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP1))
12102 /*! @brief Format value for bitfield AIPS_PACRP_WP1. */
12103 #define BF_AIPS_PACRP_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_WP1) & BM_AIPS_PACRP_WP1)
12105 /*! @brief Set the WP1 field to a new value. */
12106 #define BW_AIPS_PACRP_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP1) = (v))
12110 * @name Register AIPS_PACRP, field SP1[26] (RW)
12112 * Determines whether the peripheral requires supervisor privilege level for
12113 * access. When this field is set, the master privilege level must indicate the
12114 * supervisor access attribute, and the MPRx[MPLn] control field for the master must
12115 * be set. If not, access terminates with an error response and no peripheral
12116 * access initiates.
12119 * - 0 - This peripheral does not require supervisor privilege level for
12121 * - 1 - This peripheral requires supervisor privilege level for accesses.
12124 #define BP_AIPS_PACRP_SP1 (26U) /*!< Bit position for AIPS_PACRP_SP1. */
12125 #define BM_AIPS_PACRP_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRP_SP1. */
12126 #define BS_AIPS_PACRP_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRP_SP1. */
12128 /*! @brief Read current value of the AIPS_PACRP_SP1 field. */
12129 #define BR_AIPS_PACRP_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP1))
12131 /*! @brief Format value for bitfield AIPS_PACRP_SP1. */
12132 #define BF_AIPS_PACRP_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_SP1) & BM_AIPS_PACRP_SP1)
12134 /*! @brief Set the SP1 field to a new value. */
12135 #define BW_AIPS_PACRP_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP1) = (v))
12139 * @name Register AIPS_PACRP, field TP0[28] (RW)
12141 * Determines whether the peripheral allows accesses from an untrusted master.
12142 * When this bit is set and an access is attempted by an untrusted master, the
12143 * access terminates with an error response and no peripheral access initiates.
12146 * - 0 - Accesses from an untrusted master are allowed.
12147 * - 1 - Accesses from an untrusted master are not allowed.
12150 #define BP_AIPS_PACRP_TP0 (28U) /*!< Bit position for AIPS_PACRP_TP0. */
12151 #define BM_AIPS_PACRP_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRP_TP0. */
12152 #define BS_AIPS_PACRP_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRP_TP0. */
12154 /*! @brief Read current value of the AIPS_PACRP_TP0 field. */
12155 #define BR_AIPS_PACRP_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP0))
12157 /*! @brief Format value for bitfield AIPS_PACRP_TP0. */
12158 #define BF_AIPS_PACRP_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_TP0) & BM_AIPS_PACRP_TP0)
12160 /*! @brief Set the TP0 field to a new value. */
12161 #define BW_AIPS_PACRP_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP0) = (v))
12165 * @name Register AIPS_PACRP, field WP0[29] (RW)
12167 * Determines whether the peripheral allows write accesses. When this field is
12168 * set and a write access is attempted, access terminates with an error response
12169 * and no peripheral access initiates.
12172 * - 0 - This peripheral allows write accesses.
12173 * - 1 - This peripheral is write protected.
12176 #define BP_AIPS_PACRP_WP0 (29U) /*!< Bit position for AIPS_PACRP_WP0. */
12177 #define BM_AIPS_PACRP_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRP_WP0. */
12178 #define BS_AIPS_PACRP_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRP_WP0. */
12180 /*! @brief Read current value of the AIPS_PACRP_WP0 field. */
12181 #define BR_AIPS_PACRP_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP0))
12183 /*! @brief Format value for bitfield AIPS_PACRP_WP0. */
12184 #define BF_AIPS_PACRP_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_WP0) & BM_AIPS_PACRP_WP0)
12186 /*! @brief Set the WP0 field to a new value. */
12187 #define BW_AIPS_PACRP_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP0) = (v))
12191 * @name Register AIPS_PACRP, field SP0[30] (RW)
12193 * Determines whether the peripheral requires supervisor privilege level for
12194 * accesses. When this field is set, the master privilege level must indicate the
12195 * supervisor access attribute, and the MPRx[MPLn] control field for the master
12196 * must be set. If not, access terminates with an error response and no peripheral
12197 * access initiates.
12200 * - 0 - This peripheral does not require supervisor privilege level for
12202 * - 1 - This peripheral requires supervisor privilege level for accesses.
12205 #define BP_AIPS_PACRP_SP0 (30U) /*!< Bit position for AIPS_PACRP_SP0. */
12206 #define BM_AIPS_PACRP_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRP_SP0. */
12207 #define BS_AIPS_PACRP_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRP_SP0. */
12209 /*! @brief Read current value of the AIPS_PACRP_SP0 field. */
12210 #define BR_AIPS_PACRP_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP0))
12212 /*! @brief Format value for bitfield AIPS_PACRP_SP0. */
12213 #define BF_AIPS_PACRP_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_SP0) & BM_AIPS_PACRP_SP0)
12215 /*! @brief Set the SP0 field to a new value. */
12216 #define BW_AIPS_PACRP_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP0) = (v))
12219 /*******************************************************************************
12220 * HW_AIPS_PACRU - Peripheral Access Control Register
12221 ******************************************************************************/
12224 * @brief HW_AIPS_PACRU - Peripheral Access Control Register (RW)
12226 * Reset value: 0x44000000U
12228 * PACRU defines the access levels for the two global spaces.
12230 typedef union _hw_aips_pacru
12233 struct _hw_aips_pacru_bitfields
12235 uint32_t RESERVED0
: 24; /*!< [23:0] */
12236 uint32_t TP1
: 1; /*!< [24] Trusted Protect */
12237 uint32_t WP1
: 1; /*!< [25] Write Protect */
12238 uint32_t SP1
: 1; /*!< [26] Supervisor Protect */
12239 uint32_t RESERVED1
: 1; /*!< [27] */
12240 uint32_t TP0
: 1; /*!< [28] Trusted Protect */
12241 uint32_t WP0
: 1; /*!< [29] Write Protect */
12242 uint32_t SP0
: 1; /*!< [30] Supervisor Protect */
12243 uint32_t RESERVED2
: 1; /*!< [31] */
12248 * @name Constants and macros for entire AIPS_PACRU register
12251 #define HW_AIPS_PACRU_ADDR(x) ((x) + 0x80U)
12253 #define HW_AIPS_PACRU(x) (*(__IO hw_aips_pacru_t *) HW_AIPS_PACRU_ADDR(x))
12254 #define HW_AIPS_PACRU_RD(x) (HW_AIPS_PACRU(x).U)
12255 #define HW_AIPS_PACRU_WR(x, v) (HW_AIPS_PACRU(x).U = (v))
12256 #define HW_AIPS_PACRU_SET(x, v) (HW_AIPS_PACRU_WR(x, HW_AIPS_PACRU_RD(x) | (v)))
12257 #define HW_AIPS_PACRU_CLR(x, v) (HW_AIPS_PACRU_WR(x, HW_AIPS_PACRU_RD(x) & ~(v)))
12258 #define HW_AIPS_PACRU_TOG(x, v) (HW_AIPS_PACRU_WR(x, HW_AIPS_PACRU_RD(x) ^ (v)))
12262 * Constants & macros for individual AIPS_PACRU bitfields
12266 * @name Register AIPS_PACRU, field TP1[24] (RW)
12268 * Determines whether the peripheral allows accesses from an untrusted master.
12269 * When this field is set and an access is attempted by an untrusted master, the
12270 * access terminates with an error response and no peripheral access initiates.
12273 * - 0 - Accesses from an untrusted master are allowed.
12274 * - 1 - Accesses from an untrusted master are not allowed.
12277 #define BP_AIPS_PACRU_TP1 (24U) /*!< Bit position for AIPS_PACRU_TP1. */
12278 #define BM_AIPS_PACRU_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRU_TP1. */
12279 #define BS_AIPS_PACRU_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRU_TP1. */
12281 /*! @brief Read current value of the AIPS_PACRU_TP1 field. */
12282 #define BR_AIPS_PACRU_TP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP1))
12284 /*! @brief Format value for bitfield AIPS_PACRU_TP1. */
12285 #define BF_AIPS_PACRU_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRU_TP1) & BM_AIPS_PACRU_TP1)
12287 /*! @brief Set the TP1 field to a new value. */
12288 #define BW_AIPS_PACRU_TP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP1) = (v))
12292 * @name Register AIPS_PACRU, field WP1[25] (RW)
12294 * Determines whether the peripheral allows write accesss. When this bit is set
12295 * and a write access is attempted, access terminates with an error response and
12296 * no peripheral access initiates.
12299 * - 0 - This peripheral allows write accesses.
12300 * - 1 - This peripheral is write protected.
12303 #define BP_AIPS_PACRU_WP1 (25U) /*!< Bit position for AIPS_PACRU_WP1. */
12304 #define BM_AIPS_PACRU_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRU_WP1. */
12305 #define BS_AIPS_PACRU_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRU_WP1. */
12307 /*! @brief Read current value of the AIPS_PACRU_WP1 field. */
12308 #define BR_AIPS_PACRU_WP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP1))
12310 /*! @brief Format value for bitfield AIPS_PACRU_WP1. */
12311 #define BF_AIPS_PACRU_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRU_WP1) & BM_AIPS_PACRU_WP1)
12313 /*! @brief Set the WP1 field to a new value. */
12314 #define BW_AIPS_PACRU_WP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP1) = (v))
12318 * @name Register AIPS_PACRU, field SP1[26] (RW)
12320 * Determines whether the peripheral requires supervisor privilege level for
12321 * accesses. When this field is set, the master privilege level must indicate the
12322 * supervisor access attribute, and the MPRx[MPLn] control field for the master
12323 * must be set. If not, access terminates with an error response and no peripheral
12324 * access initiates.
12327 * - 0 - This peripheral does not require supervisor privilege level for
12329 * - 1 - This peripheral requires supervisor privilege level for accesses.
12332 #define BP_AIPS_PACRU_SP1 (26U) /*!< Bit position for AIPS_PACRU_SP1. */
12333 #define BM_AIPS_PACRU_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRU_SP1. */
12334 #define BS_AIPS_PACRU_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRU_SP1. */
12336 /*! @brief Read current value of the AIPS_PACRU_SP1 field. */
12337 #define BR_AIPS_PACRU_SP1(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP1))
12339 /*! @brief Format value for bitfield AIPS_PACRU_SP1. */
12340 #define BF_AIPS_PACRU_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRU_SP1) & BM_AIPS_PACRU_SP1)
12342 /*! @brief Set the SP1 field to a new value. */
12343 #define BW_AIPS_PACRU_SP1(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP1) = (v))
12347 * @name Register AIPS_PACRU, field TP0[28] (RW)
12349 * Determines whether the peripheral allows accesses from an untrusted master.
12350 * When this field is set and an access is attempted by an untrusted master, the
12351 * access terminates with an error response and no peripheral access initiates.
12354 * - 0 - Accesses from an untrusted master are allowed.
12355 * - 1 - Accesses from an untrusted master are not allowed.
12358 #define BP_AIPS_PACRU_TP0 (28U) /*!< Bit position for AIPS_PACRU_TP0. */
12359 #define BM_AIPS_PACRU_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRU_TP0. */
12360 #define BS_AIPS_PACRU_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRU_TP0. */
12362 /*! @brief Read current value of the AIPS_PACRU_TP0 field. */
12363 #define BR_AIPS_PACRU_TP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP0))
12365 /*! @brief Format value for bitfield AIPS_PACRU_TP0. */
12366 #define BF_AIPS_PACRU_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRU_TP0) & BM_AIPS_PACRU_TP0)
12368 /*! @brief Set the TP0 field to a new value. */
12369 #define BW_AIPS_PACRU_TP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP0) = (v))
12373 * @name Register AIPS_PACRU, field WP0[29] (RW)
12375 * Determines whether the peripheral allows write accesses. When this field is
12376 * set and a write access is attempted, access terminates with an error response
12377 * and no peripheral access initiates.
12380 * - 0 - This peripheral allows write accesses.
12381 * - 1 - This peripheral is write protected.
12384 #define BP_AIPS_PACRU_WP0 (29U) /*!< Bit position for AIPS_PACRU_WP0. */
12385 #define BM_AIPS_PACRU_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRU_WP0. */
12386 #define BS_AIPS_PACRU_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRU_WP0. */
12388 /*! @brief Read current value of the AIPS_PACRU_WP0 field. */
12389 #define BR_AIPS_PACRU_WP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP0))
12391 /*! @brief Format value for bitfield AIPS_PACRU_WP0. */
12392 #define BF_AIPS_PACRU_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRU_WP0) & BM_AIPS_PACRU_WP0)
12394 /*! @brief Set the WP0 field to a new value. */
12395 #define BW_AIPS_PACRU_WP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP0) = (v))
12399 * @name Register AIPS_PACRU, field SP0[30] (RW)
12401 * Determines whether the peripheral requires supervisor privilege level for
12402 * access. When this bit is set, the master privilege level must indicate the
12403 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
12404 * set. If not, access terminates with an error response and no peripheral access
12408 * - 0 - This peripheral does not require supervisor privilege level for
12410 * - 1 - This peripheral requires supervisor privilege level for accesses.
12413 #define BP_AIPS_PACRU_SP0 (30U) /*!< Bit position for AIPS_PACRU_SP0. */
12414 #define BM_AIPS_PACRU_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRU_SP0. */
12415 #define BS_AIPS_PACRU_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRU_SP0. */
12417 /*! @brief Read current value of the AIPS_PACRU_SP0 field. */
12418 #define BR_AIPS_PACRU_SP0(x) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP0))
12420 /*! @brief Format value for bitfield AIPS_PACRU_SP0. */
12421 #define BF_AIPS_PACRU_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRU_SP0) & BM_AIPS_PACRU_SP0)
12423 /*! @brief Set the SP0 field to a new value. */
12424 #define BW_AIPS_PACRU_SP0(x, v) (BITBAND_ACCESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP0) = (v))
12427 /*******************************************************************************
12428 * hw_aips_t - module struct
12429 ******************************************************************************/
12431 * @brief All AIPS module registers.
12434 typedef struct _hw_aips
12436 __IO hw_aips_mpra_t MPRA
; /*!< [0x0] Master Privilege Register A */
12437 uint8_t _reserved0
[28];
12438 __IO hw_aips_pacra_t PACRA
; /*!< [0x20] Peripheral Access Control Register */
12439 __IO hw_aips_pacrb_t PACRB
; /*!< [0x24] Peripheral Access Control Register */
12440 __IO hw_aips_pacrc_t PACRC
; /*!< [0x28] Peripheral Access Control Register */
12441 __IO hw_aips_pacrd_t PACRD
; /*!< [0x2C] Peripheral Access Control Register */
12442 uint8_t _reserved1
[16];
12443 __IO hw_aips_pacre_t PACRE
; /*!< [0x40] Peripheral Access Control Register */
12444 __IO hw_aips_pacrf_t PACRF
; /*!< [0x44] Peripheral Access Control Register */
12445 __IO hw_aips_pacrg_t PACRG
; /*!< [0x48] Peripheral Access Control Register */
12446 __IO hw_aips_pacrh_t PACRH
; /*!< [0x4C] Peripheral Access Control Register */
12447 __IO hw_aips_pacri_t PACRI
; /*!< [0x50] Peripheral Access Control Register */
12448 __IO hw_aips_pacrj_t PACRJ
; /*!< [0x54] Peripheral Access Control Register */
12449 __IO hw_aips_pacrk_t PACRK
; /*!< [0x58] Peripheral Access Control Register */
12450 __IO hw_aips_pacrl_t PACRL
; /*!< [0x5C] Peripheral Access Control Register */
12451 __IO hw_aips_pacrm_t PACRM
; /*!< [0x60] Peripheral Access Control Register */
12452 __IO hw_aips_pacrn_t PACRN
; /*!< [0x64] Peripheral Access Control Register */
12453 __IO hw_aips_pacro_t PACRO
; /*!< [0x68] Peripheral Access Control Register */
12454 __IO hw_aips_pacrp_t PACRP
; /*!< [0x6C] Peripheral Access Control Register */
12455 uint8_t _reserved2
[16];
12456 __IO hw_aips_pacru_t PACRU
; /*!< [0x80] Peripheral Access Control Register */
12460 /*! @brief Macro to access all AIPS registers. */
12461 /*! @param x AIPS module instance base address. */
12462 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
12463 * use the '&' operator, like <code>&HW_AIPS(AIPS0_BASE)</code>. */
12464 #define HW_AIPS(x) (*(hw_aips_t *)(x))
12466 #endif /* __HW_AIPS_REGISTERS_H__ */