2 ** ###################################################################
3 ** Compilers: Keil ARM C/C++ Compiler
4 ** Freescale C/C++ for Embedded ARM
6 ** IAR ANSI C/C++ Compiler for ARM
8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
9 ** Version: rev. 2.5, 2014-02-10
13 ** Extension to the CMSIS register access layer header.
15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
16 ** All rights reserved.
18 ** Redistribution and use in source and binary forms, with or without modification,
19 ** are permitted provided that the following conditions are met:
21 ** o Redistributions of source code must retain the above copyright notice, this list
22 ** of conditions and the following disclaimer.
24 ** o Redistributions in binary form must reproduce the above copyright notice, this
25 ** list of conditions and the following disclaimer in the documentation and/or
26 ** other materials provided with the distribution.
28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
29 ** contributors may be used to endorse or promote products derived from this
30 ** software without specific prior written permission.
32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ** http: www.freescale.com
44 ** mail: support@freescale.com
47 ** - rev. 1.0 (2013-08-12)
49 ** - rev. 2.0 (2013-10-29)
50 ** Register accessor macros added to the memory map.
51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
52 ** Startup file for gcc has been updated according to CMSIS 3.2.
53 ** System initialization updated.
54 ** MCG - registers updated.
55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
56 ** - rev. 2.1 (2013-10-30)
57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
58 ** - rev. 2.2 (2013-12-09)
59 ** DMA - EARS register removed.
60 ** AIPS0, AIPS1 - MPRA register updated.
61 ** - rev. 2.3 (2014-01-24)
62 ** Update according to reference manual rev. 2
63 ** ENET, MCG, MCM, SIM, USB - registers updated
64 ** - rev. 2.4 (2014-02-10)
65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
67 ** - rev. 2.5 (2014-02-10)
68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
72 ** ###################################################################
76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
78 * This file was generated automatically and any changes may be lost.
80 #ifndef __HW_CAN_REGISTERS_H__
81 #define __HW_CAN_REGISTERS_H__
84 #include "fsl_bitaccess.h"
89 * Flex Controller Area Network module
91 * Registers defined in this header file:
92 * - HW_CAN_MCR - Module Configuration Register
93 * - HW_CAN_CTRL1 - Control 1 register
94 * - HW_CAN_TIMER - Free Running Timer
95 * - HW_CAN_RXMGMASK - Rx Mailboxes Global Mask Register
96 * - HW_CAN_RX14MASK - Rx 14 Mask register
97 * - HW_CAN_RX15MASK - Rx 15 Mask register
98 * - HW_CAN_ECR - Error Counter
99 * - HW_CAN_ESR1 - Error and Status 1 register
100 * - HW_CAN_IMASK1 - Interrupt Masks 1 register
101 * - HW_CAN_IFLAG1 - Interrupt Flags 1 register
102 * - HW_CAN_CTRL2 - Control 2 register
103 * - HW_CAN_ESR2 - Error and Status 2 register
104 * - HW_CAN_CRCR - CRC Register
105 * - HW_CAN_RXFGMASK - Rx FIFO Global Mask register
106 * - HW_CAN_RXFIR - Rx FIFO Information Register
107 * - HW_CAN_CSn - Message Buffer 0 CS Register
108 * - HW_CAN_IDn - Message Buffer 0 ID Register
109 * - HW_CAN_WORD0n - Message Buffer 0 WORD0 Register
110 * - HW_CAN_WORD1n - Message Buffer 0 WORD1 Register
111 * - HW_CAN_RXIMRn - Rx Individual Mask Registers
113 * - hw_can_t - Struct containing all module registers.
116 #define HW_CAN_INSTANCE_COUNT (1U) /*!< Number of instances of the CAN module. */
118 /*******************************************************************************
119 * HW_CAN_MCR - Module Configuration Register
120 ******************************************************************************/
123 * @brief HW_CAN_MCR - Module Configuration Register (RW)
125 * Reset value: 0xD890000FU
127 * This register defines global system configurations, such as the module
128 * operation modes and the maximum message buffer configuration.
130 typedef union _hw_can_mcr
133 struct _hw_can_mcr_bitfields
135 uint32_t MAXMB
: 7; /*!< [6:0] Number Of The Last Message Buffer */
136 uint32_t RESERVED0
: 1; /*!< [7] */
137 uint32_t IDAM
: 2; /*!< [9:8] ID Acceptance Mode */
138 uint32_t RESERVED1
: 2; /*!< [11:10] */
139 uint32_t AEN
: 1; /*!< [12] Abort Enable */
140 uint32_t LPRIOEN
: 1; /*!< [13] Local Priority Enable */
141 uint32_t RESERVED2
: 2; /*!< [15:14] */
142 uint32_t IRMQ
: 1; /*!< [16] Individual Rx Masking And Queue Enable */
143 uint32_t SRXDIS
: 1; /*!< [17] Self Reception Disable */
144 uint32_t RESERVED3
: 1; /*!< [18] */
145 uint32_t WAKSRC
: 1; /*!< [19] Wake Up Source */
146 uint32_t LPMACK
: 1; /*!< [20] Low-Power Mode Acknowledge */
147 uint32_t WRNEN
: 1; /*!< [21] Warning Interrupt Enable */
148 uint32_t SLFWAK
: 1; /*!< [22] Self Wake Up */
149 uint32_t SUPV
: 1; /*!< [23] Supervisor Mode */
150 uint32_t FRZACK
: 1; /*!< [24] Freeze Mode Acknowledge */
151 uint32_t SOFTRST
: 1; /*!< [25] Soft Reset */
152 uint32_t WAKMSK
: 1; /*!< [26] Wake Up Interrupt Mask */
153 uint32_t NOTRDY
: 1; /*!< [27] FlexCAN Not Ready */
154 uint32_t HALT
: 1; /*!< [28] Halt FlexCAN */
155 uint32_t RFEN
: 1; /*!< [29] Rx FIFO Enable */
156 uint32_t FRZ
: 1; /*!< [30] Freeze Enable */
157 uint32_t MDIS
: 1; /*!< [31] Module Disable */
162 * @name Constants and macros for entire CAN_MCR register
165 #define HW_CAN_MCR_ADDR(x) ((x) + 0x0U)
167 #define HW_CAN_MCR(x) (*(__IO hw_can_mcr_t *) HW_CAN_MCR_ADDR(x))
168 #define HW_CAN_MCR_RD(x) (HW_CAN_MCR(x).U)
169 #define HW_CAN_MCR_WR(x, v) (HW_CAN_MCR(x).U = (v))
170 #define HW_CAN_MCR_SET(x, v) (HW_CAN_MCR_WR(x, HW_CAN_MCR_RD(x) | (v)))
171 #define HW_CAN_MCR_CLR(x, v) (HW_CAN_MCR_WR(x, HW_CAN_MCR_RD(x) & ~(v)))
172 #define HW_CAN_MCR_TOG(x, v) (HW_CAN_MCR_WR(x, HW_CAN_MCR_RD(x) ^ (v)))
176 * Constants & macros for individual CAN_MCR bitfields
180 * @name Register CAN_MCR, field MAXMB[6:0] (RW)
182 * This 7-bit field defines the number of the last Message Buffers that will
183 * take part in the matching and arbitration processes. The reset value (0x0F) is
184 * equivalent to a 16 MB configuration. This field can be written only in Freeze
185 * mode because it is blocked by hardware in other modes. Number of the last MB =
186 * MAXMB MAXMB must be programmed with a value smaller than the parameter
187 * NUMBER_OF_MB, otherwise the number of the last effective Message Buffer will be:
188 * (NUMBER_OF_MB - 1) Additionally, the value of MAXMB must encompass the FIFO size
189 * defined by CTRL2[RFFN]. MAXMB also impacts the definition of the minimum number
190 * of peripheral clocks per CAN bit as described in Table "Minimum Ratio Between
191 * Peripheral Clock Frequency and CAN Bit Rate" (in Section "Arbitration and
195 #define BP_CAN_MCR_MAXMB (0U) /*!< Bit position for CAN_MCR_MAXMB. */
196 #define BM_CAN_MCR_MAXMB (0x0000007FU) /*!< Bit mask for CAN_MCR_MAXMB. */
197 #define BS_CAN_MCR_MAXMB (7U) /*!< Bit field size in bits for CAN_MCR_MAXMB. */
199 /*! @brief Read current value of the CAN_MCR_MAXMB field. */
200 #define BR_CAN_MCR_MAXMB(x) (HW_CAN_MCR(x).B.MAXMB)
202 /*! @brief Format value for bitfield CAN_MCR_MAXMB. */
203 #define BF_CAN_MCR_MAXMB(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_MAXMB) & BM_CAN_MCR_MAXMB)
205 /*! @brief Set the MAXMB field to a new value. */
206 #define BW_CAN_MCR_MAXMB(x, v) (HW_CAN_MCR_WR(x, (HW_CAN_MCR_RD(x) & ~BM_CAN_MCR_MAXMB) | BF_CAN_MCR_MAXMB(v)))
210 * @name Register CAN_MCR, field IDAM[9:8] (RW)
212 * This 2-bit field identifies the format of the Rx FIFO ID Filter Table
213 * elements. Note that all elements of the table are configured at the same time by this
214 * field (they are all the same format). See Section "Rx FIFO Structure". This
215 * field can be written only in Freeze mode because it is blocked by hardware in
219 * - 00 - Format A: One full ID (standard and extended) per ID Filter Table
221 * - 01 - Format B: Two full standard IDs or two partial 14-bit (standard and
222 * extended) IDs per ID Filter Table element.
223 * - 10 - Format C: Four partial 8-bit Standard IDs per ID Filter Table element.
224 * - 11 - Format D: All frames rejected.
227 #define BP_CAN_MCR_IDAM (8U) /*!< Bit position for CAN_MCR_IDAM. */
228 #define BM_CAN_MCR_IDAM (0x00000300U) /*!< Bit mask for CAN_MCR_IDAM. */
229 #define BS_CAN_MCR_IDAM (2U) /*!< Bit field size in bits for CAN_MCR_IDAM. */
231 /*! @brief Read current value of the CAN_MCR_IDAM field. */
232 #define BR_CAN_MCR_IDAM(x) (HW_CAN_MCR(x).B.IDAM)
234 /*! @brief Format value for bitfield CAN_MCR_IDAM. */
235 #define BF_CAN_MCR_IDAM(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_IDAM) & BM_CAN_MCR_IDAM)
237 /*! @brief Set the IDAM field to a new value. */
238 #define BW_CAN_MCR_IDAM(x, v) (HW_CAN_MCR_WR(x, (HW_CAN_MCR_RD(x) & ~BM_CAN_MCR_IDAM) | BF_CAN_MCR_IDAM(v)))
242 * @name Register CAN_MCR, field AEN[12] (RW)
244 * This bit is supplied for backwards compatibility with legacy applications.
245 * When asserted, it enables the Tx abort mechanism. This mechanism guarantees a
246 * safe procedure for aborting a pending transmission, so that no frame is sent in
247 * the CAN bus without notification. This bit can be written only in Freeze mode
248 * because it is blocked by hardware in other modes. When MCR[AEN] is asserted,
249 * only the abort mechanism (see Section "Transmission Abort Mechanism") must be
250 * used for updating Mailboxes configured for transmission. Writing the Abort code
251 * into Rx Mailboxes can cause unpredictable results when the MCR[AEN] is
255 * - 0 - Abort disabled.
256 * - 1 - Abort enabled.
259 #define BP_CAN_MCR_AEN (12U) /*!< Bit position for CAN_MCR_AEN. */
260 #define BM_CAN_MCR_AEN (0x00001000U) /*!< Bit mask for CAN_MCR_AEN. */
261 #define BS_CAN_MCR_AEN (1U) /*!< Bit field size in bits for CAN_MCR_AEN. */
263 /*! @brief Read current value of the CAN_MCR_AEN field. */
264 #define BR_CAN_MCR_AEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_AEN))
266 /*! @brief Format value for bitfield CAN_MCR_AEN. */
267 #define BF_CAN_MCR_AEN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_AEN) & BM_CAN_MCR_AEN)
269 /*! @brief Set the AEN field to a new value. */
270 #define BW_CAN_MCR_AEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_AEN) = (v))
274 * @name Register CAN_MCR, field LPRIOEN[13] (RW)
276 * This bit is provided for backwards compatibility with legacy applications. It
277 * controls whether the local priority feature is enabled or not. It is used to
278 * expand the ID used during the arbitration process. With this expanded ID
279 * concept, the arbitration process is done based on the full 32-bit word, but the
280 * actual transmitted ID still has 11-bit for standard frames and 29-bit for
281 * extended frames. This bit can be written only in Freeze mode because it is blocked by
282 * hardware in other modes.
285 * - 0 - Local Priority disabled.
286 * - 1 - Local Priority enabled.
289 #define BP_CAN_MCR_LPRIOEN (13U) /*!< Bit position for CAN_MCR_LPRIOEN. */
290 #define BM_CAN_MCR_LPRIOEN (0x00002000U) /*!< Bit mask for CAN_MCR_LPRIOEN. */
291 #define BS_CAN_MCR_LPRIOEN (1U) /*!< Bit field size in bits for CAN_MCR_LPRIOEN. */
293 /*! @brief Read current value of the CAN_MCR_LPRIOEN field. */
294 #define BR_CAN_MCR_LPRIOEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_LPRIOEN))
296 /*! @brief Format value for bitfield CAN_MCR_LPRIOEN. */
297 #define BF_CAN_MCR_LPRIOEN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_LPRIOEN) & BM_CAN_MCR_LPRIOEN)
299 /*! @brief Set the LPRIOEN field to a new value. */
300 #define BW_CAN_MCR_LPRIOEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_LPRIOEN) = (v))
304 * @name Register CAN_MCR, field IRMQ[16] (RW)
306 * This bit indicates whether Rx matching process will be based either on
307 * individual masking and queue or on masking scheme with RXMGMASK, RX14MASK and
308 * RX15MASK, RXFGMASK. This bit can be written only in Freeze mode because it is
309 * blocked by hardware in other modes.
312 * - 0 - Individual Rx masking and queue feature are disabled. For backward
313 * compatibility with legacy applications, the reading of C/S word locks the MB
314 * even if it is EMPTY.
315 * - 1 - Individual Rx masking and queue feature are enabled.
318 #define BP_CAN_MCR_IRMQ (16U) /*!< Bit position for CAN_MCR_IRMQ. */
319 #define BM_CAN_MCR_IRMQ (0x00010000U) /*!< Bit mask for CAN_MCR_IRMQ. */
320 #define BS_CAN_MCR_IRMQ (1U) /*!< Bit field size in bits for CAN_MCR_IRMQ. */
322 /*! @brief Read current value of the CAN_MCR_IRMQ field. */
323 #define BR_CAN_MCR_IRMQ(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_IRMQ))
325 /*! @brief Format value for bitfield CAN_MCR_IRMQ. */
326 #define BF_CAN_MCR_IRMQ(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_IRMQ) & BM_CAN_MCR_IRMQ)
328 /*! @brief Set the IRMQ field to a new value. */
329 #define BW_CAN_MCR_IRMQ(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_IRMQ) = (v))
333 * @name Register CAN_MCR, field SRXDIS[17] (RW)
335 * This bit defines whether FlexCAN is allowed to receive frames transmitted by
336 * itself. If this bit is asserted, frames transmitted by the module will not be
337 * stored in any MB, regardless if the MB is programmed with an ID that matches
338 * the transmitted frame, and no interrupt flag or interrupt signal will be
339 * generated due to the frame reception. This bit can be written only in Freeze mode
340 * because it is blocked by hardware in other modes.
343 * - 0 - Self reception enabled.
344 * - 1 - Self reception disabled.
347 #define BP_CAN_MCR_SRXDIS (17U) /*!< Bit position for CAN_MCR_SRXDIS. */
348 #define BM_CAN_MCR_SRXDIS (0x00020000U) /*!< Bit mask for CAN_MCR_SRXDIS. */
349 #define BS_CAN_MCR_SRXDIS (1U) /*!< Bit field size in bits for CAN_MCR_SRXDIS. */
351 /*! @brief Read current value of the CAN_MCR_SRXDIS field. */
352 #define BR_CAN_MCR_SRXDIS(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SRXDIS))
354 /*! @brief Format value for bitfield CAN_MCR_SRXDIS. */
355 #define BF_CAN_MCR_SRXDIS(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_SRXDIS) & BM_CAN_MCR_SRXDIS)
357 /*! @brief Set the SRXDIS field to a new value. */
358 #define BW_CAN_MCR_SRXDIS(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SRXDIS) = (v))
362 * @name Register CAN_MCR, field WAKSRC[19] (RW)
364 * This bit defines whether the integrated low-pass filter is applied to protect
365 * the Rx CAN input from spurious wake up. This bit can be written only in
366 * Freeze mode because it is blocked by hardware in other modes.
369 * - 0 - FlexCAN uses the unfiltered Rx input to detect recessive to dominant
370 * edges on the CAN bus.
371 * - 1 - FlexCAN uses the filtered Rx input to detect recessive to dominant
372 * edges on the CAN bus.
375 #define BP_CAN_MCR_WAKSRC (19U) /*!< Bit position for CAN_MCR_WAKSRC. */
376 #define BM_CAN_MCR_WAKSRC (0x00080000U) /*!< Bit mask for CAN_MCR_WAKSRC. */
377 #define BS_CAN_MCR_WAKSRC (1U) /*!< Bit field size in bits for CAN_MCR_WAKSRC. */
379 /*! @brief Read current value of the CAN_MCR_WAKSRC field. */
380 #define BR_CAN_MCR_WAKSRC(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKSRC))
382 /*! @brief Format value for bitfield CAN_MCR_WAKSRC. */
383 #define BF_CAN_MCR_WAKSRC(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_WAKSRC) & BM_CAN_MCR_WAKSRC)
385 /*! @brief Set the WAKSRC field to a new value. */
386 #define BW_CAN_MCR_WAKSRC(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKSRC) = (v))
390 * @name Register CAN_MCR, field LPMACK[20] (RO)
392 * This read-only bit indicates that FlexCAN is in a low-power mode (Disable
393 * mode , Stop mode ). A low-power mode cannot be entered until all current
394 * transmission or reception processes have finished, so the CPU can poll the LPMACK bit
395 * to know when FlexCAN has actually entered low power mode. LPMACK will be
396 * asserted within 180 CAN bits from the low-power mode request by the CPU, and
397 * negated within 2 CAN bits after the low-power mode request removal (see Section
398 * "Protocol Timing").
401 * - 0 - FlexCAN is not in a low-power mode.
402 * - 1 - FlexCAN is in a low-power mode.
405 #define BP_CAN_MCR_LPMACK (20U) /*!< Bit position for CAN_MCR_LPMACK. */
406 #define BM_CAN_MCR_LPMACK (0x00100000U) /*!< Bit mask for CAN_MCR_LPMACK. */
407 #define BS_CAN_MCR_LPMACK (1U) /*!< Bit field size in bits for CAN_MCR_LPMACK. */
409 /*! @brief Read current value of the CAN_MCR_LPMACK field. */
410 #define BR_CAN_MCR_LPMACK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_LPMACK))
414 * @name Register CAN_MCR, field WRNEN[21] (RW)
416 * When asserted, this bit enables the generation of the TWRNINT and RWRNINT
417 * flags in the Error and Status Register. If WRNEN is negated, the TWRNINT and
418 * RWRNINT flags will always be zero, independent of the values of the error
419 * counters, and no warning interrupt will ever be generated. This bit can be written
420 * only in Freeze mode because it is blocked by hardware in other modes.
423 * - 0 - TWRNINT and RWRNINT bits are zero, independent of the values in the
425 * - 1 - TWRNINT and RWRNINT bits are set when the respective error counter
426 * transitions from less than 96 to greater than or equal to 96.
429 #define BP_CAN_MCR_WRNEN (21U) /*!< Bit position for CAN_MCR_WRNEN. */
430 #define BM_CAN_MCR_WRNEN (0x00200000U) /*!< Bit mask for CAN_MCR_WRNEN. */
431 #define BS_CAN_MCR_WRNEN (1U) /*!< Bit field size in bits for CAN_MCR_WRNEN. */
433 /*! @brief Read current value of the CAN_MCR_WRNEN field. */
434 #define BR_CAN_MCR_WRNEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WRNEN))
436 /*! @brief Format value for bitfield CAN_MCR_WRNEN. */
437 #define BF_CAN_MCR_WRNEN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_WRNEN) & BM_CAN_MCR_WRNEN)
439 /*! @brief Set the WRNEN field to a new value. */
440 #define BW_CAN_MCR_WRNEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WRNEN) = (v))
444 * @name Register CAN_MCR, field SLFWAK[22] (RW)
446 * This bit enables the Self Wake Up feature when FlexCAN is in a low-power mode
447 * other than Disable mode. When this feature is enabled, the FlexCAN module
448 * monitors the bus for wake up event, that is, a recessive-to-dominant transition.
449 * If a wake up event is detected during Stop mode, then FlexCAN generates, if
450 * enabled to do so, a Wake Up interrupt to the CPU so that it can exit Stop mode
451 * globally and FlexCAN can request to resume the clocks. When FlexCAN is in a
452 * low-power mode other than Disable mode, this bit cannot be written as it is
453 * blocked by hardware.
456 * - 0 - FlexCAN Self Wake Up feature is disabled.
457 * - 1 - FlexCAN Self Wake Up feature is enabled.
460 #define BP_CAN_MCR_SLFWAK (22U) /*!< Bit position for CAN_MCR_SLFWAK. */
461 #define BM_CAN_MCR_SLFWAK (0x00400000U) /*!< Bit mask for CAN_MCR_SLFWAK. */
462 #define BS_CAN_MCR_SLFWAK (1U) /*!< Bit field size in bits for CAN_MCR_SLFWAK. */
464 /*! @brief Read current value of the CAN_MCR_SLFWAK field. */
465 #define BR_CAN_MCR_SLFWAK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SLFWAK))
467 /*! @brief Format value for bitfield CAN_MCR_SLFWAK. */
468 #define BF_CAN_MCR_SLFWAK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_SLFWAK) & BM_CAN_MCR_SLFWAK)
470 /*! @brief Set the SLFWAK field to a new value. */
471 #define BW_CAN_MCR_SLFWAK(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SLFWAK) = (v))
475 * @name Register CAN_MCR, field SUPV[23] (RW)
477 * This bit configures the FlexCAN to be either in Supervisor or User mode. The
478 * registers affected by this bit are marked as S/U in the Access Type column of
479 * the module memory map. Reset value of this bit is 1, so the affected registers
480 * start with Supervisor access allowance only . This bit can be written only in
481 * Freeze mode because it is blocked by hardware in other modes.
484 * - 0 - FlexCAN is in User mode. Affected registers allow both Supervisor and
485 * Unrestricted accesses .
486 * - 1 - FlexCAN is in Supervisor mode. Affected registers allow only Supervisor
487 * access. Unrestricted access behaves as though the access was done to an
488 * unimplemented register location .
491 #define BP_CAN_MCR_SUPV (23U) /*!< Bit position for CAN_MCR_SUPV. */
492 #define BM_CAN_MCR_SUPV (0x00800000U) /*!< Bit mask for CAN_MCR_SUPV. */
493 #define BS_CAN_MCR_SUPV (1U) /*!< Bit field size in bits for CAN_MCR_SUPV. */
495 /*! @brief Read current value of the CAN_MCR_SUPV field. */
496 #define BR_CAN_MCR_SUPV(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SUPV))
498 /*! @brief Format value for bitfield CAN_MCR_SUPV. */
499 #define BF_CAN_MCR_SUPV(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_SUPV) & BM_CAN_MCR_SUPV)
501 /*! @brief Set the SUPV field to a new value. */
502 #define BW_CAN_MCR_SUPV(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SUPV) = (v))
506 * @name Register CAN_MCR, field FRZACK[24] (RO)
508 * This read-only bit indicates that FlexCAN is in Freeze mode and its prescaler
509 * is stopped. The Freeze mode request cannot be granted until current
510 * transmission or reception processes have finished. Therefore the software can poll the
511 * FRZACK bit to know when FlexCAN has actually entered Freeze mode. If Freeze
512 * Mode request is negated, then this bit is negated after the FlexCAN prescaler is
513 * running again. If Freeze mode is requested while FlexCAN is in a low power
514 * mode, then the FRZACK bit will be set only when the low-power mode is exited.
515 * See Section "Freeze Mode". FRZACK will be asserted within 178 CAN bits from the
516 * freeze mode request by the CPU, and negated within 2 CAN bits after the freeze
517 * mode request removal (see Section "Protocol Timing").
520 * - 0 - FlexCAN not in Freeze mode, prescaler running.
521 * - 1 - FlexCAN in Freeze mode, prescaler stopped.
524 #define BP_CAN_MCR_FRZACK (24U) /*!< Bit position for CAN_MCR_FRZACK. */
525 #define BM_CAN_MCR_FRZACK (0x01000000U) /*!< Bit mask for CAN_MCR_FRZACK. */
526 #define BS_CAN_MCR_FRZACK (1U) /*!< Bit field size in bits for CAN_MCR_FRZACK. */
528 /*! @brief Read current value of the CAN_MCR_FRZACK field. */
529 #define BR_CAN_MCR_FRZACK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_FRZACK))
533 * @name Register CAN_MCR, field SOFTRST[25] (RW)
535 * When this bit is asserted, FlexCAN resets its internal state machines and
536 * some of the memory mapped registers. The following registers are reset: MCR
537 * (except the MDIS bit), TIMER , ECR, ESR1, ESR2, IMASK1, IMASK2, IFLAG1, IFLAG2 and
538 * CRCR. Configuration registers that control the interface to the CAN bus are
539 * not affected by soft reset. The following registers are unaffected: CTRL1,
540 * CTRL2, all RXIMR registers, RXMGMASK, RX14MASK, RX15MASK, RXFGMASK, RXFIR, all
541 * Message Buffers . The SOFTRST bit can be asserted directly by the CPU when it
542 * writes to the MCR Register, but it is also asserted when global soft reset is
543 * requested at MCU level . Because soft reset is synchronous and has to follow a
544 * request/acknowledge procedure across clock domains, it may take some time to
545 * fully propagate its effect. The SOFTRST bit remains asserted while reset is
546 * pending, and is automatically negated when reset completes. Therefore, software can
547 * poll this bit to know when the soft reset has completed. Soft reset cannot be
548 * applied while clocks are shut down in a low power mode. The module should be
549 * first removed from low power mode, and then soft reset can be applied.
552 * - 0 - No reset request.
553 * - 1 - Resets the registers affected by soft reset.
556 #define BP_CAN_MCR_SOFTRST (25U) /*!< Bit position for CAN_MCR_SOFTRST. */
557 #define BM_CAN_MCR_SOFTRST (0x02000000U) /*!< Bit mask for CAN_MCR_SOFTRST. */
558 #define BS_CAN_MCR_SOFTRST (1U) /*!< Bit field size in bits for CAN_MCR_SOFTRST. */
560 /*! @brief Read current value of the CAN_MCR_SOFTRST field. */
561 #define BR_CAN_MCR_SOFTRST(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SOFTRST))
563 /*! @brief Format value for bitfield CAN_MCR_SOFTRST. */
564 #define BF_CAN_MCR_SOFTRST(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_SOFTRST) & BM_CAN_MCR_SOFTRST)
566 /*! @brief Set the SOFTRST field to a new value. */
567 #define BW_CAN_MCR_SOFTRST(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SOFTRST) = (v))
571 * @name Register CAN_MCR, field WAKMSK[26] (RW)
573 * This bit enables the Wake Up Interrupt generation under Self Wake Up
577 * - 0 - Wake Up Interrupt is disabled.
578 * - 1 - Wake Up Interrupt is enabled.
581 #define BP_CAN_MCR_WAKMSK (26U) /*!< Bit position for CAN_MCR_WAKMSK. */
582 #define BM_CAN_MCR_WAKMSK (0x04000000U) /*!< Bit mask for CAN_MCR_WAKMSK. */
583 #define BS_CAN_MCR_WAKMSK (1U) /*!< Bit field size in bits for CAN_MCR_WAKMSK. */
585 /*! @brief Read current value of the CAN_MCR_WAKMSK field. */
586 #define BR_CAN_MCR_WAKMSK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKMSK))
588 /*! @brief Format value for bitfield CAN_MCR_WAKMSK. */
589 #define BF_CAN_MCR_WAKMSK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_WAKMSK) & BM_CAN_MCR_WAKMSK)
591 /*! @brief Set the WAKMSK field to a new value. */
592 #define BW_CAN_MCR_WAKMSK(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKMSK) = (v))
596 * @name Register CAN_MCR, field NOTRDY[27] (RO)
598 * This read-only bit indicates that FlexCAN is either in Disable mode , Stop
599 * mode or Freeze mode. It is negated once FlexCAN has exited these modes.
602 * - 0 - FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back
604 * - 1 - FlexCAN module is either in Disable mode , Stop mode or Freeze mode.
607 #define BP_CAN_MCR_NOTRDY (27U) /*!< Bit position for CAN_MCR_NOTRDY. */
608 #define BM_CAN_MCR_NOTRDY (0x08000000U) /*!< Bit mask for CAN_MCR_NOTRDY. */
609 #define BS_CAN_MCR_NOTRDY (1U) /*!< Bit field size in bits for CAN_MCR_NOTRDY. */
611 /*! @brief Read current value of the CAN_MCR_NOTRDY field. */
612 #define BR_CAN_MCR_NOTRDY(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_NOTRDY))
616 * @name Register CAN_MCR, field HALT[28] (RW)
618 * Assertion of this bit puts the FlexCAN module into Freeze mode. The CPU
619 * should clear it after initializing the Message Buffers and Control Register. No
620 * reception or transmission is performed by FlexCAN before this bit is cleared.
621 * Freeze mode cannot be entered while FlexCAN is in a low power mode.
624 * - 0 - No Freeze mode request.
625 * - 1 - Enters Freeze mode if the FRZ bit is asserted.
628 #define BP_CAN_MCR_HALT (28U) /*!< Bit position for CAN_MCR_HALT. */
629 #define BM_CAN_MCR_HALT (0x10000000U) /*!< Bit mask for CAN_MCR_HALT. */
630 #define BS_CAN_MCR_HALT (1U) /*!< Bit field size in bits for CAN_MCR_HALT. */
632 /*! @brief Read current value of the CAN_MCR_HALT field. */
633 #define BR_CAN_MCR_HALT(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_HALT))
635 /*! @brief Format value for bitfield CAN_MCR_HALT. */
636 #define BF_CAN_MCR_HALT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_HALT) & BM_CAN_MCR_HALT)
638 /*! @brief Set the HALT field to a new value. */
639 #define BW_CAN_MCR_HALT(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_HALT) = (v))
643 * @name Register CAN_MCR, field RFEN[29] (RW)
645 * This bit controls whether the Rx FIFO feature is enabled or not. When RFEN is
646 * set, MBs 0 to 5 cannot be used for normal reception and transmission because
647 * the corresponding memory region (0x80-0xDC) is used by the FIFO engine as well
648 * as additional MBs (up to 32, depending on CTRL2[RFFN] setting) which are used
649 * as Rx FIFO ID Filter Table elements. RFEN also impacts the definition of the
650 * minimum number of peripheral clocks per CAN bit as described in the table
651 * "Minimum Ratio Between Peripheral Clock Frequency and CAN Bit Rate" (in section
652 * "Arbitration and Matching Timing"). This bit can be written only in Freeze mode
653 * because it is blocked by hardware in other modes.
656 * - 0 - Rx FIFO not enabled.
657 * - 1 - Rx FIFO enabled.
660 #define BP_CAN_MCR_RFEN (29U) /*!< Bit position for CAN_MCR_RFEN. */
661 #define BM_CAN_MCR_RFEN (0x20000000U) /*!< Bit mask for CAN_MCR_RFEN. */
662 #define BS_CAN_MCR_RFEN (1U) /*!< Bit field size in bits for CAN_MCR_RFEN. */
664 /*! @brief Read current value of the CAN_MCR_RFEN field. */
665 #define BR_CAN_MCR_RFEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_RFEN))
667 /*! @brief Format value for bitfield CAN_MCR_RFEN. */
668 #define BF_CAN_MCR_RFEN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_RFEN) & BM_CAN_MCR_RFEN)
670 /*! @brief Set the RFEN field to a new value. */
671 #define BW_CAN_MCR_RFEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_RFEN) = (v))
675 * @name Register CAN_MCR, field FRZ[30] (RW)
677 * The FRZ bit specifies the FlexCAN behavior when the HALT bit in the MCR
678 * Register is set or when Debug mode is requested at MCU level . When FRZ is
679 * asserted, FlexCAN is enabled to enter Freeze mode. Negation of this bit field causes
680 * FlexCAN to exit from Freeze mode.
683 * - 0 - Not enabled to enter Freeze mode.
684 * - 1 - Enabled to enter Freeze mode.
687 #define BP_CAN_MCR_FRZ (30U) /*!< Bit position for CAN_MCR_FRZ. */
688 #define BM_CAN_MCR_FRZ (0x40000000U) /*!< Bit mask for CAN_MCR_FRZ. */
689 #define BS_CAN_MCR_FRZ (1U) /*!< Bit field size in bits for CAN_MCR_FRZ. */
691 /*! @brief Read current value of the CAN_MCR_FRZ field. */
692 #define BR_CAN_MCR_FRZ(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_FRZ))
694 /*! @brief Format value for bitfield CAN_MCR_FRZ. */
695 #define BF_CAN_MCR_FRZ(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_FRZ) & BM_CAN_MCR_FRZ)
697 /*! @brief Set the FRZ field to a new value. */
698 #define BW_CAN_MCR_FRZ(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_FRZ) = (v))
702 * @name Register CAN_MCR, field MDIS[31] (RW)
704 * This bit controls whether FlexCAN is enabled or not. When disabled, FlexCAN
705 * disables the clocks to the CAN Protocol Engine and Controller Host Interface
706 * sub-modules. This is the only bit within this register not affected by soft
710 * - 0 - Enable the FlexCAN module.
711 * - 1 - Disable the FlexCAN module.
714 #define BP_CAN_MCR_MDIS (31U) /*!< Bit position for CAN_MCR_MDIS. */
715 #define BM_CAN_MCR_MDIS (0x80000000U) /*!< Bit mask for CAN_MCR_MDIS. */
716 #define BS_CAN_MCR_MDIS (1U) /*!< Bit field size in bits for CAN_MCR_MDIS. */
718 /*! @brief Read current value of the CAN_MCR_MDIS field. */
719 #define BR_CAN_MCR_MDIS(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_MDIS))
721 /*! @brief Format value for bitfield CAN_MCR_MDIS. */
722 #define BF_CAN_MCR_MDIS(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_MDIS) & BM_CAN_MCR_MDIS)
724 /*! @brief Set the MDIS field to a new value. */
725 #define BW_CAN_MCR_MDIS(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_MDIS) = (v))
728 /*******************************************************************************
729 * HW_CAN_CTRL1 - Control 1 register
730 ******************************************************************************/
733 * @brief HW_CAN_CTRL1 - Control 1 register (RW)
735 * Reset value: 0x00000000U
737 * This register is defined for specific FlexCAN control features related to the
738 * CAN bus, such as bit-rate, programmable sampling point within an Rx bit, Loop
739 * Back mode, Listen-Only mode, Bus Off recovery behavior and interrupt enabling
740 * (Bus-Off, Error, Warning). It also determines the Division Factor for the
743 typedef union _hw_can_ctrl1
746 struct _hw_can_ctrl1_bitfields
748 uint32_t PROPSEG
: 3; /*!< [2:0] Propagation Segment */
749 uint32_t LOM
: 1; /*!< [3] Listen-Only Mode */
750 uint32_t LBUF
: 1; /*!< [4] Lowest Buffer Transmitted First */
751 uint32_t TSYN
: 1; /*!< [5] Timer Sync */
752 uint32_t BOFFREC
: 1; /*!< [6] Bus Off Recovery */
753 uint32_t SMP
: 1; /*!< [7] CAN Bit Sampling */
754 uint32_t RESERVED0
: 2; /*!< [9:8] */
755 uint32_t RWRNMSK
: 1; /*!< [10] Rx Warning Interrupt Mask */
756 uint32_t TWRNMSK
: 1; /*!< [11] Tx Warning Interrupt Mask */
757 uint32_t LPB
: 1; /*!< [12] Loop Back Mode */
758 uint32_t CLKSRC
: 1; /*!< [13] CAN Engine Clock Source */
759 uint32_t ERRMSK
: 1; /*!< [14] Error Mask */
760 uint32_t BOFFMSK
: 1; /*!< [15] Bus Off Mask */
761 uint32_t PSEG2
: 3; /*!< [18:16] Phase Segment 2 */
762 uint32_t PSEG1
: 3; /*!< [21:19] Phase Segment 1 */
763 uint32_t RJW
: 2; /*!< [23:22] Resync Jump Width */
764 uint32_t PRESDIV
: 8; /*!< [31:24] Prescaler Division Factor */
769 * @name Constants and macros for entire CAN_CTRL1 register
772 #define HW_CAN_CTRL1_ADDR(x) ((x) + 0x4U)
774 #define HW_CAN_CTRL1(x) (*(__IO hw_can_ctrl1_t *) HW_CAN_CTRL1_ADDR(x))
775 #define HW_CAN_CTRL1_RD(x) (HW_CAN_CTRL1(x).U)
776 #define HW_CAN_CTRL1_WR(x, v) (HW_CAN_CTRL1(x).U = (v))
777 #define HW_CAN_CTRL1_SET(x, v) (HW_CAN_CTRL1_WR(x, HW_CAN_CTRL1_RD(x) | (v)))
778 #define HW_CAN_CTRL1_CLR(x, v) (HW_CAN_CTRL1_WR(x, HW_CAN_CTRL1_RD(x) & ~(v)))
779 #define HW_CAN_CTRL1_TOG(x, v) (HW_CAN_CTRL1_WR(x, HW_CAN_CTRL1_RD(x) ^ (v)))
783 * Constants & macros for individual CAN_CTRL1 bitfields
787 * @name Register CAN_CTRL1, field PROPSEG[2:0] (RW)
789 * This 3-bit field defines the length of the Propagation Segment in the bit
790 * time. The valid programmable values are 0-7. This field can be written only in
791 * Freeze mode because it is blocked by hardware in other modes. Propagation
792 * Segment Time = (PROPSEG + 1) * Time-Quanta. Time-Quantum = one Sclock period.
795 #define BP_CAN_CTRL1_PROPSEG (0U) /*!< Bit position for CAN_CTRL1_PROPSEG. */
796 #define BM_CAN_CTRL1_PROPSEG (0x00000007U) /*!< Bit mask for CAN_CTRL1_PROPSEG. */
797 #define BS_CAN_CTRL1_PROPSEG (3U) /*!< Bit field size in bits for CAN_CTRL1_PROPSEG. */
799 /*! @brief Read current value of the CAN_CTRL1_PROPSEG field. */
800 #define BR_CAN_CTRL1_PROPSEG(x) (HW_CAN_CTRL1(x).B.PROPSEG)
802 /*! @brief Format value for bitfield CAN_CTRL1_PROPSEG. */
803 #define BF_CAN_CTRL1_PROPSEG(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_PROPSEG) & BM_CAN_CTRL1_PROPSEG)
805 /*! @brief Set the PROPSEG field to a new value. */
806 #define BW_CAN_CTRL1_PROPSEG(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PROPSEG) | BF_CAN_CTRL1_PROPSEG(v)))
810 * @name Register CAN_CTRL1, field LOM[3] (RW)
812 * This bit configures FlexCAN to operate in Listen-Only mode. In this mode,
813 * transmission is disabled, all error counters are frozen and the module operates
814 * in a CAN Error Passive mode. Only messages acknowledged by another CAN station
815 * will be received. If FlexCAN detects a message that has not been acknowledged,
816 * it will flag a BIT0 error without changing the REC, as if it was trying to
817 * acknowledge the message. Listen-Only mode acknowledgement can be obtained by the
818 * state of ESR1[FLTCONF] field which is Passive Error when Listen-Only mode is
819 * entered. There can be some delay between the Listen-Only mode request and
820 * acknowledge. This bit can be written only in Freeze mode because it is blocked by
821 * hardware in other modes.
824 * - 0 - Listen-Only mode is deactivated.
825 * - 1 - FlexCAN module operates in Listen-Only mode.
828 #define BP_CAN_CTRL1_LOM (3U) /*!< Bit position for CAN_CTRL1_LOM. */
829 #define BM_CAN_CTRL1_LOM (0x00000008U) /*!< Bit mask for CAN_CTRL1_LOM. */
830 #define BS_CAN_CTRL1_LOM (1U) /*!< Bit field size in bits for CAN_CTRL1_LOM. */
832 /*! @brief Read current value of the CAN_CTRL1_LOM field. */
833 #define BR_CAN_CTRL1_LOM(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LOM))
835 /*! @brief Format value for bitfield CAN_CTRL1_LOM. */
836 #define BF_CAN_CTRL1_LOM(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_LOM) & BM_CAN_CTRL1_LOM)
838 /*! @brief Set the LOM field to a new value. */
839 #define BW_CAN_CTRL1_LOM(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LOM) = (v))
843 * @name Register CAN_CTRL1, field LBUF[4] (RW)
845 * This bit defines the ordering mechanism for Message Buffer transmission. When
846 * asserted, the LPRIOEN bit does not affect the priority arbitration. This bit
847 * can be written only in Freeze mode because it is blocked by hardware in other
851 * - 0 - Buffer with highest priority is transmitted first.
852 * - 1 - Lowest number buffer is transmitted first.
855 #define BP_CAN_CTRL1_LBUF (4U) /*!< Bit position for CAN_CTRL1_LBUF. */
856 #define BM_CAN_CTRL1_LBUF (0x00000010U) /*!< Bit mask for CAN_CTRL1_LBUF. */
857 #define BS_CAN_CTRL1_LBUF (1U) /*!< Bit field size in bits for CAN_CTRL1_LBUF. */
859 /*! @brief Read current value of the CAN_CTRL1_LBUF field. */
860 #define BR_CAN_CTRL1_LBUF(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LBUF))
862 /*! @brief Format value for bitfield CAN_CTRL1_LBUF. */
863 #define BF_CAN_CTRL1_LBUF(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_LBUF) & BM_CAN_CTRL1_LBUF)
865 /*! @brief Set the LBUF field to a new value. */
866 #define BW_CAN_CTRL1_LBUF(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LBUF) = (v))
870 * @name Register CAN_CTRL1, field TSYN[5] (RW)
872 * This bit enables a mechanism that resets the free-running timer each time a
873 * message is received in Message Buffer 0. This feature provides means to
874 * synchronize multiple FlexCAN stations with a special "SYNC" message, that is, global
875 * network time. If the RFEN bit in MCR is set (Rx FIFO enabled), the first
876 * available Mailbox, according to CTRL2[RFFN] setting, is used for timer
877 * synchronization instead of MB0. This bit can be written only in Freeze mode because it is
878 * blocked by hardware in other modes.
881 * - 0 - Timer Sync feature disabled
882 * - 1 - Timer Sync feature enabled
885 #define BP_CAN_CTRL1_TSYN (5U) /*!< Bit position for CAN_CTRL1_TSYN. */
886 #define BM_CAN_CTRL1_TSYN (0x00000020U) /*!< Bit mask for CAN_CTRL1_TSYN. */
887 #define BS_CAN_CTRL1_TSYN (1U) /*!< Bit field size in bits for CAN_CTRL1_TSYN. */
889 /*! @brief Read current value of the CAN_CTRL1_TSYN field. */
890 #define BR_CAN_CTRL1_TSYN(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TSYN))
892 /*! @brief Format value for bitfield CAN_CTRL1_TSYN. */
893 #define BF_CAN_CTRL1_TSYN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_TSYN) & BM_CAN_CTRL1_TSYN)
895 /*! @brief Set the TSYN field to a new value. */
896 #define BW_CAN_CTRL1_TSYN(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TSYN) = (v))
900 * @name Register CAN_CTRL1, field BOFFREC[6] (RW)
902 * This bit defines how FlexCAN recovers from Bus Off state. If this bit is
903 * negated, automatic recovering from Bus Off state occurs according to the CAN
904 * Specification 2.0B. If the bit is asserted, automatic recovering from Bus Off is
905 * disabled and the module remains in Bus Off state until the bit is negated by the
906 * user. If the negation occurs before 128 sequences of 11 recessive bits are
907 * detected on the CAN bus, then Bus Off recovery happens as if the BOFFREC bit had
908 * never been asserted. If the negation occurs after 128 sequences of 11
909 * recessive bits occurred, then FlexCAN will re-synchronize to the bus by waiting for
910 * 11 recessive bits before joining the bus. After negation, the BOFFREC bit can
911 * be re-asserted again during Bus Off, but it will be effective only the next
912 * time the module enters Bus Off. If BOFFREC was negated when the module entered
913 * Bus Off, asserting it during Bus Off will not be effective for the current Bus
917 * - 0 - Automatic recovering from Bus Off state enabled, according to CAN Spec
919 * - 1 - Automatic recovering from Bus Off state disabled.
922 #define BP_CAN_CTRL1_BOFFREC (6U) /*!< Bit position for CAN_CTRL1_BOFFREC. */
923 #define BM_CAN_CTRL1_BOFFREC (0x00000040U) /*!< Bit mask for CAN_CTRL1_BOFFREC. */
924 #define BS_CAN_CTRL1_BOFFREC (1U) /*!< Bit field size in bits for CAN_CTRL1_BOFFREC. */
926 /*! @brief Read current value of the CAN_CTRL1_BOFFREC field. */
927 #define BR_CAN_CTRL1_BOFFREC(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFREC))
929 /*! @brief Format value for bitfield CAN_CTRL1_BOFFREC. */
930 #define BF_CAN_CTRL1_BOFFREC(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_BOFFREC) & BM_CAN_CTRL1_BOFFREC)
932 /*! @brief Set the BOFFREC field to a new value. */
933 #define BW_CAN_CTRL1_BOFFREC(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFREC) = (v))
937 * @name Register CAN_CTRL1, field SMP[7] (RW)
939 * This bit defines the sampling mode of CAN bits at the Rx input. This bit can
940 * be written only in Freeze mode because it is blocked by hardware in other
944 * - 0 - Just one sample is used to determine the bit value.
945 * - 1 - Three samples are used to determine the value of the received bit: the
946 * regular one (sample point) and 2 preceding samples; a majority rule is
950 #define BP_CAN_CTRL1_SMP (7U) /*!< Bit position for CAN_CTRL1_SMP. */
951 #define BM_CAN_CTRL1_SMP (0x00000080U) /*!< Bit mask for CAN_CTRL1_SMP. */
952 #define BS_CAN_CTRL1_SMP (1U) /*!< Bit field size in bits for CAN_CTRL1_SMP. */
954 /*! @brief Read current value of the CAN_CTRL1_SMP field. */
955 #define BR_CAN_CTRL1_SMP(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_SMP))
957 /*! @brief Format value for bitfield CAN_CTRL1_SMP. */
958 #define BF_CAN_CTRL1_SMP(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_SMP) & BM_CAN_CTRL1_SMP)
960 /*! @brief Set the SMP field to a new value. */
961 #define BW_CAN_CTRL1_SMP(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_SMP) = (v))
965 * @name Register CAN_CTRL1, field RWRNMSK[10] (RW)
967 * This bit provides a mask for the Rx Warning Interrupt associated with the
968 * RWRNINT flag in the Error and Status Register. This bit is read as zero when
969 * MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is
973 * - 0 - Rx Warning Interrupt disabled.
974 * - 1 - Rx Warning Interrupt enabled.
977 #define BP_CAN_CTRL1_RWRNMSK (10U) /*!< Bit position for CAN_CTRL1_RWRNMSK. */
978 #define BM_CAN_CTRL1_RWRNMSK (0x00000400U) /*!< Bit mask for CAN_CTRL1_RWRNMSK. */
979 #define BS_CAN_CTRL1_RWRNMSK (1U) /*!< Bit field size in bits for CAN_CTRL1_RWRNMSK. */
981 /*! @brief Read current value of the CAN_CTRL1_RWRNMSK field. */
982 #define BR_CAN_CTRL1_RWRNMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_RWRNMSK))
984 /*! @brief Format value for bitfield CAN_CTRL1_RWRNMSK. */
985 #define BF_CAN_CTRL1_RWRNMSK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_RWRNMSK) & BM_CAN_CTRL1_RWRNMSK)
987 /*! @brief Set the RWRNMSK field to a new value. */
988 #define BW_CAN_CTRL1_RWRNMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_RWRNMSK) = (v))
992 * @name Register CAN_CTRL1, field TWRNMSK[11] (RW)
994 * This bit provides a mask for the Tx Warning Interrupt associated with the
995 * TWRNINT flag in the Error and Status Register. This bit is read as zero when
996 * MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is
1000 * - 0 - Tx Warning Interrupt disabled.
1001 * - 1 - Tx Warning Interrupt enabled.
1004 #define BP_CAN_CTRL1_TWRNMSK (11U) /*!< Bit position for CAN_CTRL1_TWRNMSK. */
1005 #define BM_CAN_CTRL1_TWRNMSK (0x00000800U) /*!< Bit mask for CAN_CTRL1_TWRNMSK. */
1006 #define BS_CAN_CTRL1_TWRNMSK (1U) /*!< Bit field size in bits for CAN_CTRL1_TWRNMSK. */
1008 /*! @brief Read current value of the CAN_CTRL1_TWRNMSK field. */
1009 #define BR_CAN_CTRL1_TWRNMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TWRNMSK))
1011 /*! @brief Format value for bitfield CAN_CTRL1_TWRNMSK. */
1012 #define BF_CAN_CTRL1_TWRNMSK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_TWRNMSK) & BM_CAN_CTRL1_TWRNMSK)
1014 /*! @brief Set the TWRNMSK field to a new value. */
1015 #define BW_CAN_CTRL1_TWRNMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TWRNMSK) = (v))
1019 * @name Register CAN_CTRL1, field LPB[12] (RW)
1021 * This bit configures FlexCAN to operate in Loop-Back mode. In this mode,
1022 * FlexCAN performs an internal loop back that can be used for self test operation.
1023 * The bit stream output of the transmitter is fed back internally to the receiver
1024 * input. The Rx CAN input pin is ignored and the Tx CAN output goes to the
1025 * recessive state (logic 1). FlexCAN behaves as it normally does when transmitting,
1026 * and treats its own transmitted message as a message received from a remote
1027 * node. In this mode, FlexCAN ignores the bit sent during the ACK slot in the CAN
1028 * frame acknowledge field, generating an internal acknowledge bit to ensure proper
1029 * reception of its own message. Both transmit and receive interrupts are
1030 * generated. This bit can be written only in Freeze mode because it is blocked by
1031 * hardware in other modes. In this mode, the MCR[SRXDIS] cannot be asserted because
1032 * this will impede the self reception of a transmitted message.
1035 * - 0 - Loop Back disabled.
1036 * - 1 - Loop Back enabled.
1039 #define BP_CAN_CTRL1_LPB (12U) /*!< Bit position for CAN_CTRL1_LPB. */
1040 #define BM_CAN_CTRL1_LPB (0x00001000U) /*!< Bit mask for CAN_CTRL1_LPB. */
1041 #define BS_CAN_CTRL1_LPB (1U) /*!< Bit field size in bits for CAN_CTRL1_LPB. */
1043 /*! @brief Read current value of the CAN_CTRL1_LPB field. */
1044 #define BR_CAN_CTRL1_LPB(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LPB))
1046 /*! @brief Format value for bitfield CAN_CTRL1_LPB. */
1047 #define BF_CAN_CTRL1_LPB(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_LPB) & BM_CAN_CTRL1_LPB)
1049 /*! @brief Set the LPB field to a new value. */
1050 #define BW_CAN_CTRL1_LPB(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LPB) = (v))
1054 * @name Register CAN_CTRL1, field CLKSRC[13] (RW)
1056 * This bit selects the clock source to the CAN Protocol Engine (PE) to be
1057 * either the peripheral clock (driven by the PLL) or the crystal oscillator clock.
1058 * The selected clock is the one fed to the prescaler to generate the Serial Clock
1059 * (Sclock). In order to guarantee reliable operation, this bit can be written
1060 * only in Disable mode because it is blocked by hardware in other modes. See
1061 * Section "Protocol Timing".
1064 * - 0 - The CAN engine clock source is the oscillator clock. Under this
1065 * condition, the oscillator clock frequency must be lower than the bus clock.
1066 * - 1 - The CAN engine clock source is the peripheral clock.
1069 #define BP_CAN_CTRL1_CLKSRC (13U) /*!< Bit position for CAN_CTRL1_CLKSRC. */
1070 #define BM_CAN_CTRL1_CLKSRC (0x00002000U) /*!< Bit mask for CAN_CTRL1_CLKSRC. */
1071 #define BS_CAN_CTRL1_CLKSRC (1U) /*!< Bit field size in bits for CAN_CTRL1_CLKSRC. */
1073 /*! @brief Read current value of the CAN_CTRL1_CLKSRC field. */
1074 #define BR_CAN_CTRL1_CLKSRC(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_CLKSRC))
1076 /*! @brief Format value for bitfield CAN_CTRL1_CLKSRC. */
1077 #define BF_CAN_CTRL1_CLKSRC(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_CLKSRC) & BM_CAN_CTRL1_CLKSRC)
1079 /*! @brief Set the CLKSRC field to a new value. */
1080 #define BW_CAN_CTRL1_CLKSRC(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_CLKSRC) = (v))
1084 * @name Register CAN_CTRL1, field ERRMSK[14] (RW)
1086 * This bit provides a mask for the Error Interrupt.
1089 * - 0 - Error interrupt disabled.
1090 * - 1 - Error interrupt enabled.
1093 #define BP_CAN_CTRL1_ERRMSK (14U) /*!< Bit position for CAN_CTRL1_ERRMSK. */
1094 #define BM_CAN_CTRL1_ERRMSK (0x00004000U) /*!< Bit mask for CAN_CTRL1_ERRMSK. */
1095 #define BS_CAN_CTRL1_ERRMSK (1U) /*!< Bit field size in bits for CAN_CTRL1_ERRMSK. */
1097 /*! @brief Read current value of the CAN_CTRL1_ERRMSK field. */
1098 #define BR_CAN_CTRL1_ERRMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_ERRMSK))
1100 /*! @brief Format value for bitfield CAN_CTRL1_ERRMSK. */
1101 #define BF_CAN_CTRL1_ERRMSK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_ERRMSK) & BM_CAN_CTRL1_ERRMSK)
1103 /*! @brief Set the ERRMSK field to a new value. */
1104 #define BW_CAN_CTRL1_ERRMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_ERRMSK) = (v))
1108 * @name Register CAN_CTRL1, field BOFFMSK[15] (RW)
1110 * This bit provides a mask for the Bus Off Interrupt.
1113 * - 0 - Bus Off interrupt disabled.
1114 * - 1 - Bus Off interrupt enabled.
1117 #define BP_CAN_CTRL1_BOFFMSK (15U) /*!< Bit position for CAN_CTRL1_BOFFMSK. */
1118 #define BM_CAN_CTRL1_BOFFMSK (0x00008000U) /*!< Bit mask for CAN_CTRL1_BOFFMSK. */
1119 #define BS_CAN_CTRL1_BOFFMSK (1U) /*!< Bit field size in bits for CAN_CTRL1_BOFFMSK. */
1121 /*! @brief Read current value of the CAN_CTRL1_BOFFMSK field. */
1122 #define BR_CAN_CTRL1_BOFFMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFMSK))
1124 /*! @brief Format value for bitfield CAN_CTRL1_BOFFMSK. */
1125 #define BF_CAN_CTRL1_BOFFMSK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_BOFFMSK) & BM_CAN_CTRL1_BOFFMSK)
1127 /*! @brief Set the BOFFMSK field to a new value. */
1128 #define BW_CAN_CTRL1_BOFFMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFMSK) = (v))
1132 * @name Register CAN_CTRL1, field PSEG2[18:16] (RW)
1134 * This 3-bit field defines the length of Phase Buffer Segment 2 in the bit
1135 * time. The valid programmable values are 1-7. This field can be written only in
1136 * Freeze mode because it is blocked by hardware in other modes. Phase Buffer
1137 * Segment 2 = (PSEG2 + 1) * Time-Quanta.
1140 #define BP_CAN_CTRL1_PSEG2 (16U) /*!< Bit position for CAN_CTRL1_PSEG2. */
1141 #define BM_CAN_CTRL1_PSEG2 (0x00070000U) /*!< Bit mask for CAN_CTRL1_PSEG2. */
1142 #define BS_CAN_CTRL1_PSEG2 (3U) /*!< Bit field size in bits for CAN_CTRL1_PSEG2. */
1144 /*! @brief Read current value of the CAN_CTRL1_PSEG2 field. */
1145 #define BR_CAN_CTRL1_PSEG2(x) (HW_CAN_CTRL1(x).B.PSEG2)
1147 /*! @brief Format value for bitfield CAN_CTRL1_PSEG2. */
1148 #define BF_CAN_CTRL1_PSEG2(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_PSEG2) & BM_CAN_CTRL1_PSEG2)
1150 /*! @brief Set the PSEG2 field to a new value. */
1151 #define BW_CAN_CTRL1_PSEG2(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PSEG2) | BF_CAN_CTRL1_PSEG2(v)))
1155 * @name Register CAN_CTRL1, field PSEG1[21:19] (RW)
1157 * This 3-bit field defines the length of Phase Buffer Segment 1 in the bit
1158 * time. The valid programmable values are 0-7. This field can be written only in
1159 * Freeze mode because it is blocked by hardware in other modes. Phase Buffer
1160 * Segment 1 = (PSEG1 + 1) * Time-Quanta.
1163 #define BP_CAN_CTRL1_PSEG1 (19U) /*!< Bit position for CAN_CTRL1_PSEG1. */
1164 #define BM_CAN_CTRL1_PSEG1 (0x00380000U) /*!< Bit mask for CAN_CTRL1_PSEG1. */
1165 #define BS_CAN_CTRL1_PSEG1 (3U) /*!< Bit field size in bits for CAN_CTRL1_PSEG1. */
1167 /*! @brief Read current value of the CAN_CTRL1_PSEG1 field. */
1168 #define BR_CAN_CTRL1_PSEG1(x) (HW_CAN_CTRL1(x).B.PSEG1)
1170 /*! @brief Format value for bitfield CAN_CTRL1_PSEG1. */
1171 #define BF_CAN_CTRL1_PSEG1(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_PSEG1) & BM_CAN_CTRL1_PSEG1)
1173 /*! @brief Set the PSEG1 field to a new value. */
1174 #define BW_CAN_CTRL1_PSEG1(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PSEG1) | BF_CAN_CTRL1_PSEG1(v)))
1178 * @name Register CAN_CTRL1, field RJW[23:22] (RW)
1180 * This 2-bit field defines the maximum number of time quanta that a bit time
1181 * can be changed by one re-synchronization. One time quantum is equal to the
1182 * Sclock period. The valid programmable values are 0-3. This field can be written
1183 * only in Freeze mode because it is blocked by hardware in other modes. Resync Jump
1187 #define BP_CAN_CTRL1_RJW (22U) /*!< Bit position for CAN_CTRL1_RJW. */
1188 #define BM_CAN_CTRL1_RJW (0x00C00000U) /*!< Bit mask for CAN_CTRL1_RJW. */
1189 #define BS_CAN_CTRL1_RJW (2U) /*!< Bit field size in bits for CAN_CTRL1_RJW. */
1191 /*! @brief Read current value of the CAN_CTRL1_RJW field. */
1192 #define BR_CAN_CTRL1_RJW(x) (HW_CAN_CTRL1(x).B.RJW)
1194 /*! @brief Format value for bitfield CAN_CTRL1_RJW. */
1195 #define BF_CAN_CTRL1_RJW(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_RJW) & BM_CAN_CTRL1_RJW)
1197 /*! @brief Set the RJW field to a new value. */
1198 #define BW_CAN_CTRL1_RJW(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_RJW) | BF_CAN_CTRL1_RJW(v)))
1202 * @name Register CAN_CTRL1, field PRESDIV[31:24] (RW)
1204 * This 8-bit field defines the ratio between the PE clock frequency and the
1205 * Serial Clock (Sclock) frequency. The Sclock period defines the time quantum of
1206 * the CAN protocol. For the reset value, the Sclock frequency is equal to the PE
1207 * clock frequency. The Maximum value of this field is 0xFF, that gives a minimum
1208 * Sclock frequency equal to the PE clock frequency divided by 256. See Section
1209 * "Protocol Timing". This field can be written only in Freeze mode because it is
1210 * blocked by hardware in other modes. Sclock frequency = PE clock frequency /
1214 #define BP_CAN_CTRL1_PRESDIV (24U) /*!< Bit position for CAN_CTRL1_PRESDIV. */
1215 #define BM_CAN_CTRL1_PRESDIV (0xFF000000U) /*!< Bit mask for CAN_CTRL1_PRESDIV. */
1216 #define BS_CAN_CTRL1_PRESDIV (8U) /*!< Bit field size in bits for CAN_CTRL1_PRESDIV. */
1218 /*! @brief Read current value of the CAN_CTRL1_PRESDIV field. */
1219 #define BR_CAN_CTRL1_PRESDIV(x) (HW_CAN_CTRL1(x).B.PRESDIV)
1221 /*! @brief Format value for bitfield CAN_CTRL1_PRESDIV. */
1222 #define BF_CAN_CTRL1_PRESDIV(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_PRESDIV) & BM_CAN_CTRL1_PRESDIV)
1224 /*! @brief Set the PRESDIV field to a new value. */
1225 #define BW_CAN_CTRL1_PRESDIV(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PRESDIV) | BF_CAN_CTRL1_PRESDIV(v)))
1228 /*******************************************************************************
1229 * HW_CAN_TIMER - Free Running Timer
1230 ******************************************************************************/
1233 * @brief HW_CAN_TIMER - Free Running Timer (RW)
1235 * Reset value: 0x00000000U
1237 * This register represents a 16-bit free running counter that can be read and
1238 * written by the CPU. The timer starts from 0x0 after Reset, counts linearly to
1239 * 0xFFFF, and wraps around. The timer is clocked by the FlexCAN bit-clock, which
1240 * defines the baud rate on the CAN bus. During a message transmission/reception,
1241 * it increments by one for each bit that is received or transmitted. When there
1242 * is no message on the bus, it counts using the previously programmed baud
1243 * rate. The timer is not incremented during Disable , Stop, and Freeze modes. The
1244 * timer value is captured when the second bit of the identifier field of any frame
1245 * is on the CAN bus. This captured value is written into the Time Stamp entry
1246 * in a message buffer after a successful reception or transmission of a message.
1247 * If bit CTRL1[TSYN] is asserted, the Timer is reset whenever a message is
1248 * received in the first available Mailbox, according to CTRL2[RFFN] setting. The CPU
1249 * can write to this register anytime. However, if the write occurs at the same
1250 * time that the Timer is being reset by a reception in the first Mailbox, then
1251 * the write value is discarded. Reading this register affects the Mailbox
1252 * Unlocking procedure; see Section "Mailbox Lock Mechanism".
1254 typedef union _hw_can_timer
1257 struct _hw_can_timer_bitfields
1259 uint32_t TIMER
: 16; /*!< [15:0] Timer Value */
1260 uint32_t RESERVED0
: 16; /*!< [31:16] */
1265 * @name Constants and macros for entire CAN_TIMER register
1268 #define HW_CAN_TIMER_ADDR(x) ((x) + 0x8U)
1270 #define HW_CAN_TIMER(x) (*(__IO hw_can_timer_t *) HW_CAN_TIMER_ADDR(x))
1271 #define HW_CAN_TIMER_RD(x) (HW_CAN_TIMER(x).U)
1272 #define HW_CAN_TIMER_WR(x, v) (HW_CAN_TIMER(x).U = (v))
1273 #define HW_CAN_TIMER_SET(x, v) (HW_CAN_TIMER_WR(x, HW_CAN_TIMER_RD(x) | (v)))
1274 #define HW_CAN_TIMER_CLR(x, v) (HW_CAN_TIMER_WR(x, HW_CAN_TIMER_RD(x) & ~(v)))
1275 #define HW_CAN_TIMER_TOG(x, v) (HW_CAN_TIMER_WR(x, HW_CAN_TIMER_RD(x) ^ (v)))
1279 * Constants & macros for individual CAN_TIMER bitfields
1283 * @name Register CAN_TIMER, field TIMER[15:0] (RW)
1285 * Contains the free-running counter value.
1288 #define BP_CAN_TIMER_TIMER (0U) /*!< Bit position for CAN_TIMER_TIMER. */
1289 #define BM_CAN_TIMER_TIMER (0x0000FFFFU) /*!< Bit mask for CAN_TIMER_TIMER. */
1290 #define BS_CAN_TIMER_TIMER (16U) /*!< Bit field size in bits for CAN_TIMER_TIMER. */
1292 /*! @brief Read current value of the CAN_TIMER_TIMER field. */
1293 #define BR_CAN_TIMER_TIMER(x) (HW_CAN_TIMER(x).B.TIMER)
1295 /*! @brief Format value for bitfield CAN_TIMER_TIMER. */
1296 #define BF_CAN_TIMER_TIMER(v) ((uint32_t)((uint32_t)(v) << BP_CAN_TIMER_TIMER) & BM_CAN_TIMER_TIMER)
1298 /*! @brief Set the TIMER field to a new value. */
1299 #define BW_CAN_TIMER_TIMER(x, v) (HW_CAN_TIMER_WR(x, (HW_CAN_TIMER_RD(x) & ~BM_CAN_TIMER_TIMER) | BF_CAN_TIMER_TIMER(v)))
1302 /*******************************************************************************
1303 * HW_CAN_RXMGMASK - Rx Mailboxes Global Mask Register
1304 ******************************************************************************/
1307 * @brief HW_CAN_RXMGMASK - Rx Mailboxes Global Mask Register (RW)
1309 * Reset value: 0xFFFFFFFFU
1311 * This register is located in RAM. RXMGMASK is provided for legacy application
1312 * support. When the MCR[IRMQ] bit is negated, RXMGMASK is always in effect. When
1313 * the MCR[IRMQ] bit is asserted, RXMGMASK has no effect. RXMGMASK is used to
1314 * mask the filter fields of all Rx MBs, excluding MBs 14-15, which have individual
1315 * mask registers. This register can only be written in Freeze mode as it is
1316 * blocked by hardware in other modes.
1318 typedef union _hw_can_rxmgmask
1321 struct _hw_can_rxmgmask_bitfields
1323 uint32_t MG
: 32; /*!< [31:0] Rx Mailboxes Global Mask Bits */
1325 } hw_can_rxmgmask_t
;
1328 * @name Constants and macros for entire CAN_RXMGMASK register
1331 #define HW_CAN_RXMGMASK_ADDR(x) ((x) + 0x10U)
1333 #define HW_CAN_RXMGMASK(x) (*(__IO hw_can_rxmgmask_t *) HW_CAN_RXMGMASK_ADDR(x))
1334 #define HW_CAN_RXMGMASK_RD(x) (HW_CAN_RXMGMASK(x).U)
1335 #define HW_CAN_RXMGMASK_WR(x, v) (HW_CAN_RXMGMASK(x).U = (v))
1336 #define HW_CAN_RXMGMASK_SET(x, v) (HW_CAN_RXMGMASK_WR(x, HW_CAN_RXMGMASK_RD(x) | (v)))
1337 #define HW_CAN_RXMGMASK_CLR(x, v) (HW_CAN_RXMGMASK_WR(x, HW_CAN_RXMGMASK_RD(x) & ~(v)))
1338 #define HW_CAN_RXMGMASK_TOG(x, v) (HW_CAN_RXMGMASK_WR(x, HW_CAN_RXMGMASK_RD(x) ^ (v)))
1342 * Constants & macros for individual CAN_RXMGMASK bitfields
1346 * @name Register CAN_RXMGMASK, field MG[31:0] (RW)
1348 * These bits mask the Mailbox filter bits. Note that the alignment with the ID
1349 * word of the Mailbox is not perfect as the two most significant MG bits affect
1350 * the fields RTR and IDE, which are located in the Control and Status word of
1351 * the Mailbox. The following table shows in detail which MG bits mask each Mailbox
1352 * filter field. SMB[RTR] RTR bit of the Incoming Frame. It is saved into an
1353 * auxiliary MB called Rx Serial Message Buffer (Rx SMB). CTRL2[RRS] CTRL2[EACEN]
1354 * Mailbox filter fields MB[RTR] MB[IDE] MB[ID] Reserved 0 - 0 note If the
1355 * CTRL2[EACEN] bit is negated, the RTR bit of Mailbox is never compared with the RTR bit
1356 * of the incoming frame. note If the CTRL2[EACEN] bit is negated, the IDE bit
1357 * of Mailbox is always compared with the IDE bit of the incoming frame. MG[28:0]
1358 * MG[31:29] 0 - 1 MG[31] MG[30] MG[28:0] MG[29] 1 0 - - - - MG[31:0] 1 1 0 - -
1359 * MG[28:0] MG[31:29] 1 1 1 MG[31] MG[30] MG[28:0] MG[29]
1362 * - 0 - The corresponding bit in the filter is "don't care."
1363 * - 1 - The corresponding bit in the filter is checked.
1366 #define BP_CAN_RXMGMASK_MG (0U) /*!< Bit position for CAN_RXMGMASK_MG. */
1367 #define BM_CAN_RXMGMASK_MG (0xFFFFFFFFU) /*!< Bit mask for CAN_RXMGMASK_MG. */
1368 #define BS_CAN_RXMGMASK_MG (32U) /*!< Bit field size in bits for CAN_RXMGMASK_MG. */
1370 /*! @brief Read current value of the CAN_RXMGMASK_MG field. */
1371 #define BR_CAN_RXMGMASK_MG(x) (HW_CAN_RXMGMASK(x).U)
1373 /*! @brief Format value for bitfield CAN_RXMGMASK_MG. */
1374 #define BF_CAN_RXMGMASK_MG(v) ((uint32_t)((uint32_t)(v) << BP_CAN_RXMGMASK_MG) & BM_CAN_RXMGMASK_MG)
1376 /*! @brief Set the MG field to a new value. */
1377 #define BW_CAN_RXMGMASK_MG(x, v) (HW_CAN_RXMGMASK_WR(x, v))
1380 /*******************************************************************************
1381 * HW_CAN_RX14MASK - Rx 14 Mask register
1382 ******************************************************************************/
1385 * @brief HW_CAN_RX14MASK - Rx 14 Mask register (RW)
1387 * Reset value: 0xFFFFFFFFU
1389 * This register is located in RAM. RX14MASK is provided for legacy application
1390 * support. When the MCR[IRMQ] bit is asserted, RX14MASK has no effect. RX14MASK
1391 * is used to mask the filter fields of Message Buffer 14. This register can only
1392 * be programmed while the module is in Freeze mode as it is blocked by hardware
1395 typedef union _hw_can_rx14mask
1398 struct _hw_can_rx14mask_bitfields
1400 uint32_t RX14M
: 32; /*!< [31:0] Rx Buffer 14 Mask Bits */
1402 } hw_can_rx14mask_t
;
1405 * @name Constants and macros for entire CAN_RX14MASK register
1408 #define HW_CAN_RX14MASK_ADDR(x) ((x) + 0x14U)
1410 #define HW_CAN_RX14MASK(x) (*(__IO hw_can_rx14mask_t *) HW_CAN_RX14MASK_ADDR(x))
1411 #define HW_CAN_RX14MASK_RD(x) (HW_CAN_RX14MASK(x).U)
1412 #define HW_CAN_RX14MASK_WR(x, v) (HW_CAN_RX14MASK(x).U = (v))
1413 #define HW_CAN_RX14MASK_SET(x, v) (HW_CAN_RX14MASK_WR(x, HW_CAN_RX14MASK_RD(x) | (v)))
1414 #define HW_CAN_RX14MASK_CLR(x, v) (HW_CAN_RX14MASK_WR(x, HW_CAN_RX14MASK_RD(x) & ~(v)))
1415 #define HW_CAN_RX14MASK_TOG(x, v) (HW_CAN_RX14MASK_WR(x, HW_CAN_RX14MASK_RD(x) ^ (v)))
1419 * Constants & macros for individual CAN_RX14MASK bitfields
1423 * @name Register CAN_RX14MASK, field RX14M[31:0] (RW)
1425 * Each mask bit masks the corresponding Mailbox 14 filter field in the same way
1426 * that RXMGMASK masks other Mailboxes' filters. See the description of the
1427 * CAN_RXMGMASK register.
1430 * - 0 - The corresponding bit in the filter is "don't care."
1431 * - 1 - The corresponding bit in the filter is checked.
1434 #define BP_CAN_RX14MASK_RX14M (0U) /*!< Bit position for CAN_RX14MASK_RX14M. */
1435 #define BM_CAN_RX14MASK_RX14M (0xFFFFFFFFU) /*!< Bit mask for CAN_RX14MASK_RX14M. */
1436 #define BS_CAN_RX14MASK_RX14M (32U) /*!< Bit field size in bits for CAN_RX14MASK_RX14M. */
1438 /*! @brief Read current value of the CAN_RX14MASK_RX14M field. */
1439 #define BR_CAN_RX14MASK_RX14M(x) (HW_CAN_RX14MASK(x).U)
1441 /*! @brief Format value for bitfield CAN_RX14MASK_RX14M. */
1442 #define BF_CAN_RX14MASK_RX14M(v) ((uint32_t)((uint32_t)(v) << BP_CAN_RX14MASK_RX14M) & BM_CAN_RX14MASK_RX14M)
1444 /*! @brief Set the RX14M field to a new value. */
1445 #define BW_CAN_RX14MASK_RX14M(x, v) (HW_CAN_RX14MASK_WR(x, v))
1448 /*******************************************************************************
1449 * HW_CAN_RX15MASK - Rx 15 Mask register
1450 ******************************************************************************/
1453 * @brief HW_CAN_RX15MASK - Rx 15 Mask register (RW)
1455 * Reset value: 0xFFFFFFFFU
1457 * This register is located in RAM. RX15MASK is provided for legacy application
1458 * support. When the MCR[IRMQ] bit is asserted, RX15MASK has no effect. RX15MASK
1459 * is used to mask the filter fields of Message Buffer 15. This register can be
1460 * programmed only while the module is in Freeze mode because it is blocked by
1461 * hardware in other modes.
1463 typedef union _hw_can_rx15mask
1466 struct _hw_can_rx15mask_bitfields
1468 uint32_t RX15M
: 32; /*!< [31:0] Rx Buffer 15 Mask Bits */
1470 } hw_can_rx15mask_t
;
1473 * @name Constants and macros for entire CAN_RX15MASK register
1476 #define HW_CAN_RX15MASK_ADDR(x) ((x) + 0x18U)
1478 #define HW_CAN_RX15MASK(x) (*(__IO hw_can_rx15mask_t *) HW_CAN_RX15MASK_ADDR(x))
1479 #define HW_CAN_RX15MASK_RD(x) (HW_CAN_RX15MASK(x).U)
1480 #define HW_CAN_RX15MASK_WR(x, v) (HW_CAN_RX15MASK(x).U = (v))
1481 #define HW_CAN_RX15MASK_SET(x, v) (HW_CAN_RX15MASK_WR(x, HW_CAN_RX15MASK_RD(x) | (v)))
1482 #define HW_CAN_RX15MASK_CLR(x, v) (HW_CAN_RX15MASK_WR(x, HW_CAN_RX15MASK_RD(x) & ~(v)))
1483 #define HW_CAN_RX15MASK_TOG(x, v) (HW_CAN_RX15MASK_WR(x, HW_CAN_RX15MASK_RD(x) ^ (v)))
1487 * Constants & macros for individual CAN_RX15MASK bitfields
1491 * @name Register CAN_RX15MASK, field RX15M[31:0] (RW)
1493 * Each mask bit masks the corresponding Mailbox 15 filter field in the same way
1494 * that RXMGMASK masks other Mailboxes' filters. See the description of the
1495 * CAN_RXMGMASK register.
1498 * - 0 - The corresponding bit in the filter is "don't care."
1499 * - 1 - The corresponding bit in the filter is checked.
1502 #define BP_CAN_RX15MASK_RX15M (0U) /*!< Bit position for CAN_RX15MASK_RX15M. */
1503 #define BM_CAN_RX15MASK_RX15M (0xFFFFFFFFU) /*!< Bit mask for CAN_RX15MASK_RX15M. */
1504 #define BS_CAN_RX15MASK_RX15M (32U) /*!< Bit field size in bits for CAN_RX15MASK_RX15M. */
1506 /*! @brief Read current value of the CAN_RX15MASK_RX15M field. */
1507 #define BR_CAN_RX15MASK_RX15M(x) (HW_CAN_RX15MASK(x).U)
1509 /*! @brief Format value for bitfield CAN_RX15MASK_RX15M. */
1510 #define BF_CAN_RX15MASK_RX15M(v) ((uint32_t)((uint32_t)(v) << BP_CAN_RX15MASK_RX15M) & BM_CAN_RX15MASK_RX15M)
1512 /*! @brief Set the RX15M field to a new value. */
1513 #define BW_CAN_RX15MASK_RX15M(x, v) (HW_CAN_RX15MASK_WR(x, v))
1516 /*******************************************************************************
1517 * HW_CAN_ECR - Error Counter
1518 ******************************************************************************/
1521 * @brief HW_CAN_ECR - Error Counter (RW)
1523 * Reset value: 0x00000000U
1525 * This register has two 8-bit fields reflecting the value of two FlexCAN error
1526 * counters: Transmit Error Counter (TXERRCNT field) and Receive Error Counter
1527 * (RXERRCNT field). The rules for increasing and decreasing these counters are
1528 * described in the CAN protocol and are completely implemented in the FlexCAN
1529 * module. Both counters are read-only except in Freeze mode, where they can be
1530 * written by the CPU. FlexCAN responds to any bus state as described in the protocol,
1531 * for example, transmit Error Active or Error Passive flag, delay its
1532 * transmission start time (Error Passive) and avoid any influence on the bus when in Bus
1533 * Off state. The following are the basic rules for FlexCAN bus state transitions:
1534 * If the value of TXERRCNT or RXERRCNT increases to be greater than or equal to
1535 * 128, the FLTCONF field in the Error and Status Register is updated to reflect
1536 * 'Error Passive' state. If the FlexCAN state is 'Error Passive', and either
1537 * TXERRCNT or RXERRCNT decrements to a value less than or equal to 127 while the
1538 * other already satisfies this condition, the FLTCONF field in the Error and
1539 * Status Register is updated to reflect 'Error Active' state. If the value of
1540 * TXERRCNT increases to be greater than 255, the FLTCONF field in the Error and Status
1541 * Register is updated to reflect 'Bus Off' state, and an interrupt may be
1542 * issued. The value of TXERRCNT is then reset to zero. If FlexCAN is in 'Bus Off'
1543 * state, then TXERRCNT is cascaded together with another internal counter to count
1544 * the 128th occurrences of 11 consecutive recessive bits on the bus. Hence,
1545 * TXERRCNT is reset to zero and counts in a manner where the internal counter counts
1546 * 11 such bits and then wraps around while incrementing the TXERRCNT. When
1547 * TXERRCNT reaches the value of 128, the FLTCONF field in the Error and Status
1548 * Register is updated to be 'Error Active' and both error counters are reset to zero.
1549 * At any instance of dominant bit following a stream of less than 11
1550 * consecutive recessive bits, the internal counter resets itself to zero without affecting
1551 * the TXERRCNT value. If during system start-up, only one node is operating,
1552 * then its TXERRCNT increases in each message it is trying to transmit, as a
1553 * result of acknowledge errors (indicated by the ACKERR bit in the Error and Status
1554 * Register). After the transition to 'Error Passive' state, the TXERRCNT does not
1555 * increment anymore by acknowledge errors. Therefore the device never goes to
1556 * the 'Bus Off' state. If the RXERRCNT increases to a value greater than 127, it
1557 * is not incremented further, even if more errors are detected while being a
1558 * receiver. At the next successful message reception, the counter is set to a value
1559 * between 119 and 127 to resume to 'Error Active' state.
1561 typedef union _hw_can_ecr
1564 struct _hw_can_ecr_bitfields
1566 uint32_t TXERRCNT
: 8; /*!< [7:0] Transmit Error Counter */
1567 uint32_t RXERRCNT
: 8; /*!< [15:8] Receive Error Counter */
1568 uint32_t RESERVED0
: 16; /*!< [31:16] */
1573 * @name Constants and macros for entire CAN_ECR register
1576 #define HW_CAN_ECR_ADDR(x) ((x) + 0x1CU)
1578 #define HW_CAN_ECR(x) (*(__IO hw_can_ecr_t *) HW_CAN_ECR_ADDR(x))
1579 #define HW_CAN_ECR_RD(x) (HW_CAN_ECR(x).U)
1580 #define HW_CAN_ECR_WR(x, v) (HW_CAN_ECR(x).U = (v))
1581 #define HW_CAN_ECR_SET(x, v) (HW_CAN_ECR_WR(x, HW_CAN_ECR_RD(x) | (v)))
1582 #define HW_CAN_ECR_CLR(x, v) (HW_CAN_ECR_WR(x, HW_CAN_ECR_RD(x) & ~(v)))
1583 #define HW_CAN_ECR_TOG(x, v) (HW_CAN_ECR_WR(x, HW_CAN_ECR_RD(x) ^ (v)))
1587 * Constants & macros for individual CAN_ECR bitfields
1591 * @name Register CAN_ECR, field TXERRCNT[7:0] (RW)
1594 #define BP_CAN_ECR_TXERRCNT (0U) /*!< Bit position for CAN_ECR_TXERRCNT. */
1595 #define BM_CAN_ECR_TXERRCNT (0x000000FFU) /*!< Bit mask for CAN_ECR_TXERRCNT. */
1596 #define BS_CAN_ECR_TXERRCNT (8U) /*!< Bit field size in bits for CAN_ECR_TXERRCNT. */
1598 /*! @brief Read current value of the CAN_ECR_TXERRCNT field. */
1599 #define BR_CAN_ECR_TXERRCNT(x) (HW_CAN_ECR(x).B.TXERRCNT)
1601 /*! @brief Format value for bitfield CAN_ECR_TXERRCNT. */
1602 #define BF_CAN_ECR_TXERRCNT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ECR_TXERRCNT) & BM_CAN_ECR_TXERRCNT)
1604 /*! @brief Set the TXERRCNT field to a new value. */
1605 #define BW_CAN_ECR_TXERRCNT(x, v) (HW_CAN_ECR_WR(x, (HW_CAN_ECR_RD(x) & ~BM_CAN_ECR_TXERRCNT) | BF_CAN_ECR_TXERRCNT(v)))
1609 * @name Register CAN_ECR, field RXERRCNT[15:8] (RW)
1612 #define BP_CAN_ECR_RXERRCNT (8U) /*!< Bit position for CAN_ECR_RXERRCNT. */
1613 #define BM_CAN_ECR_RXERRCNT (0x0000FF00U) /*!< Bit mask for CAN_ECR_RXERRCNT. */
1614 #define BS_CAN_ECR_RXERRCNT (8U) /*!< Bit field size in bits for CAN_ECR_RXERRCNT. */
1616 /*! @brief Read current value of the CAN_ECR_RXERRCNT field. */
1617 #define BR_CAN_ECR_RXERRCNT(x) (HW_CAN_ECR(x).B.RXERRCNT)
1619 /*! @brief Format value for bitfield CAN_ECR_RXERRCNT. */
1620 #define BF_CAN_ECR_RXERRCNT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ECR_RXERRCNT) & BM_CAN_ECR_RXERRCNT)
1622 /*! @brief Set the RXERRCNT field to a new value. */
1623 #define BW_CAN_ECR_RXERRCNT(x, v) (HW_CAN_ECR_WR(x, (HW_CAN_ECR_RD(x) & ~BM_CAN_ECR_RXERRCNT) | BF_CAN_ECR_RXERRCNT(v)))
1626 /*******************************************************************************
1627 * HW_CAN_ESR1 - Error and Status 1 register
1628 ******************************************************************************/
1631 * @brief HW_CAN_ESR1 - Error and Status 1 register (RW)
1633 * Reset value: 0x00000000U
1635 * This register reflects various error conditions, some general status of the
1636 * device and it is the source of interrupts to the CPU. The CPU read action
1637 * clears bits 15-10. Therefore the reported error conditions (bits 15-10) are those
1638 * that occurred since the last time the CPU read this register. Bits 9-3 are
1639 * status bits. The following table shows the FlexCAN state variables and their
1640 * meanings. Other combinations not shown in the table are reserved. SYNCH IDLE TX RX
1641 * FlexCAN State 0 0 0 0 Not synchronized to CAN bus 1 1 x x Idle 1 0 1 0
1642 * Transmitting 1 0 0 1 Receiving
1644 typedef union _hw_can_esr1
1647 struct _hw_can_esr1_bitfields
1649 uint32_t WAKINT
: 1; /*!< [0] Wake-Up Interrupt */
1650 uint32_t ERRINT
: 1; /*!< [1] Error Interrupt */
1651 uint32_t BOFFINT
: 1; /*!< [2] Bus Off Interrupt */
1652 uint32_t RX
: 1; /*!< [3] FlexCAN In Reception */
1653 uint32_t FLTCONF
: 2; /*!< [5:4] Fault Confinement State */
1654 uint32_t TX
: 1; /*!< [6] FlexCAN In Transmission */
1655 uint32_t IDLE
: 1; /*!< [7] */
1656 uint32_t RXWRN
: 1; /*!< [8] Rx Error Warning */
1657 uint32_t TXWRN
: 1; /*!< [9] TX Error Warning */
1658 uint32_t STFERR
: 1; /*!< [10] Stuffing Error */
1659 uint32_t FRMERR
: 1; /*!< [11] Form Error */
1660 uint32_t CRCERR
: 1; /*!< [12] Cyclic Redundancy Check Error */
1661 uint32_t ACKERR
: 1; /*!< [13] Acknowledge Error */
1662 uint32_t BIT0ERR
: 1; /*!< [14] Bit0 Error */
1663 uint32_t BIT1ERR
: 1; /*!< [15] Bit1 Error */
1664 uint32_t RWRNINT
: 1; /*!< [16] Rx Warning Interrupt Flag */
1665 uint32_t TWRNINT
: 1; /*!< [17] Tx Warning Interrupt Flag */
1666 uint32_t SYNCH
: 1; /*!< [18] CAN Synchronization Status */
1667 uint32_t RESERVED0
: 13; /*!< [31:19] */
1672 * @name Constants and macros for entire CAN_ESR1 register
1675 #define HW_CAN_ESR1_ADDR(x) ((x) + 0x20U)
1677 #define HW_CAN_ESR1(x) (*(__IO hw_can_esr1_t *) HW_CAN_ESR1_ADDR(x))
1678 #define HW_CAN_ESR1_RD(x) (HW_CAN_ESR1(x).U)
1679 #define HW_CAN_ESR1_WR(x, v) (HW_CAN_ESR1(x).U = (v))
1680 #define HW_CAN_ESR1_SET(x, v) (HW_CAN_ESR1_WR(x, HW_CAN_ESR1_RD(x) | (v)))
1681 #define HW_CAN_ESR1_CLR(x, v) (HW_CAN_ESR1_WR(x, HW_CAN_ESR1_RD(x) & ~(v)))
1682 #define HW_CAN_ESR1_TOG(x, v) (HW_CAN_ESR1_WR(x, HW_CAN_ESR1_RD(x) ^ (v)))
1686 * Constants & macros for individual CAN_ESR1 bitfields
1690 * @name Register CAN_ESR1, field WAKINT[0] (W1C)
1692 * This field applies when FlexCAN is in low-power mode under Self Wake Up
1693 * mechanism: Stop mode When a recessive-to-dominant transition is detected on the CAN
1694 * bus and if the MCR[WAKMSK] bit is set, an interrupt is generated to the CPU.
1695 * This bit is cleared by writing it to 1. When MCR[SLFWAK] is negated, this flag
1696 * is masked. The CPU must clear this flag before disabling the bit. Otherwise
1697 * it will be set when the SLFWAK is set again. Writing 0 has no effect.
1700 * - 0 - No such occurrence.
1701 * - 1 - Indicates a recessive to dominant transition was received on the CAN
1705 #define BP_CAN_ESR1_WAKINT (0U) /*!< Bit position for CAN_ESR1_WAKINT. */
1706 #define BM_CAN_ESR1_WAKINT (0x00000001U) /*!< Bit mask for CAN_ESR1_WAKINT. */
1707 #define BS_CAN_ESR1_WAKINT (1U) /*!< Bit field size in bits for CAN_ESR1_WAKINT. */
1709 /*! @brief Read current value of the CAN_ESR1_WAKINT field. */
1710 #define BR_CAN_ESR1_WAKINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_WAKINT))
1712 /*! @brief Format value for bitfield CAN_ESR1_WAKINT. */
1713 #define BF_CAN_ESR1_WAKINT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ESR1_WAKINT) & BM_CAN_ESR1_WAKINT)
1715 /*! @brief Set the WAKINT field to a new value. */
1716 #define BW_CAN_ESR1_WAKINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_WAKINT) = (v))
1720 * @name Register CAN_ESR1, field ERRINT[1] (W1C)
1722 * This bit indicates that at least one of the Error Bits (bits 15-10) is set.
1723 * If the corresponding mask bit CTRL1[ERRMSK] is set, an interrupt is generated
1724 * to the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
1727 * - 0 - No such occurrence.
1728 * - 1 - Indicates setting of any Error Bit in the Error and Status Register.
1731 #define BP_CAN_ESR1_ERRINT (1U) /*!< Bit position for CAN_ESR1_ERRINT. */
1732 #define BM_CAN_ESR1_ERRINT (0x00000002U) /*!< Bit mask for CAN_ESR1_ERRINT. */
1733 #define BS_CAN_ESR1_ERRINT (1U) /*!< Bit field size in bits for CAN_ESR1_ERRINT. */
1735 /*! @brief Read current value of the CAN_ESR1_ERRINT field. */
1736 #define BR_CAN_ESR1_ERRINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_ERRINT))
1738 /*! @brief Format value for bitfield CAN_ESR1_ERRINT. */
1739 #define BF_CAN_ESR1_ERRINT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ESR1_ERRINT) & BM_CAN_ESR1_ERRINT)
1741 /*! @brief Set the ERRINT field to a new value. */
1742 #define BW_CAN_ESR1_ERRINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_ERRINT) = (v))
1746 * @name Register CAN_ESR1, field BOFFINT[2] (W1C)
1748 * This bit is set when FlexCAN enters 'Bus Off' state. If the corresponding
1749 * mask bit in the Control Register (BOFFMSK) is set, an interrupt is generated to
1750 * the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
1753 * - 0 - No such occurrence.
1754 * - 1 - FlexCAN module entered Bus Off state.
1757 #define BP_CAN_ESR1_BOFFINT (2U) /*!< Bit position for CAN_ESR1_BOFFINT. */
1758 #define BM_CAN_ESR1_BOFFINT (0x00000004U) /*!< Bit mask for CAN_ESR1_BOFFINT. */
1759 #define BS_CAN_ESR1_BOFFINT (1U) /*!< Bit field size in bits for CAN_ESR1_BOFFINT. */
1761 /*! @brief Read current value of the CAN_ESR1_BOFFINT field. */
1762 #define BR_CAN_ESR1_BOFFINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BOFFINT))
1764 /*! @brief Format value for bitfield CAN_ESR1_BOFFINT. */
1765 #define BF_CAN_ESR1_BOFFINT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ESR1_BOFFINT) & BM_CAN_ESR1_BOFFINT)
1767 /*! @brief Set the BOFFINT field to a new value. */
1768 #define BW_CAN_ESR1_BOFFINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BOFFINT) = (v))
1772 * @name Register CAN_ESR1, field RX[3] (RO)
1774 * This bit indicates if FlexCAN is receiving a message. See the table in the
1775 * overall CAN_ESR1 register description.
1778 * - 0 - FlexCAN is not receiving a message.
1779 * - 1 - FlexCAN is receiving a message.
1782 #define BP_CAN_ESR1_RX (3U) /*!< Bit position for CAN_ESR1_RX. */
1783 #define BM_CAN_ESR1_RX (0x00000008U) /*!< Bit mask for CAN_ESR1_RX. */
1784 #define BS_CAN_ESR1_RX (1U) /*!< Bit field size in bits for CAN_ESR1_RX. */
1786 /*! @brief Read current value of the CAN_ESR1_RX field. */
1787 #define BR_CAN_ESR1_RX(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RX))
1791 * @name Register CAN_ESR1, field FLTCONF[5:4] (RO)
1793 * This 2-bit field indicates the Confinement State of the FlexCAN module. If
1794 * the LOM bit in the Control Register is asserted, after some delay that depends
1795 * on the CAN bit timing the FLTCONF field will indicate "Error Passive". The very
1796 * same delay affects the way how FLTCONF reflects an update to ECR register by
1797 * the CPU. It may be necessary up to one CAN bit time to get them coherent
1798 * again. Because the Control Register is not affected by soft reset, the FLTCONF
1799 * field will not be affected by soft reset if the LOM bit is asserted.
1802 * - 00 - Error Active
1803 * - 01 - Error Passive
1807 #define BP_CAN_ESR1_FLTCONF (4U) /*!< Bit position for CAN_ESR1_FLTCONF. */
1808 #define BM_CAN_ESR1_FLTCONF (0x00000030U) /*!< Bit mask for CAN_ESR1_FLTCONF. */
1809 #define BS_CAN_ESR1_FLTCONF (2U) /*!< Bit field size in bits for CAN_ESR1_FLTCONF. */
1811 /*! @brief Read current value of the CAN_ESR1_FLTCONF field. */
1812 #define BR_CAN_ESR1_FLTCONF(x) (HW_CAN_ESR1(x).B.FLTCONF)
1816 * @name Register CAN_ESR1, field TX[6] (RO)
1818 * This bit indicates if FlexCAN is transmitting a message. See the table in the
1819 * overall CAN_ESR1 register description.
1822 * - 0 - FlexCAN is not transmitting a message.
1823 * - 1 - FlexCAN is transmitting a message.
1826 #define BP_CAN_ESR1_TX (6U) /*!< Bit position for CAN_ESR1_TX. */
1827 #define BM_CAN_ESR1_TX (0x00000040U) /*!< Bit mask for CAN_ESR1_TX. */
1828 #define BS_CAN_ESR1_TX (1U) /*!< Bit field size in bits for CAN_ESR1_TX. */
1830 /*! @brief Read current value of the CAN_ESR1_TX field. */
1831 #define BR_CAN_ESR1_TX(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TX))
1835 * @name Register CAN_ESR1, field IDLE[7] (RO)
1837 * This bit indicates when CAN bus is in IDLE state. See the table in the
1838 * overall CAN_ESR1 register description.
1841 * - 0 - No such occurrence.
1842 * - 1 - CAN bus is now IDLE.
1845 #define BP_CAN_ESR1_IDLE (7U) /*!< Bit position for CAN_ESR1_IDLE. */
1846 #define BM_CAN_ESR1_IDLE (0x00000080U) /*!< Bit mask for CAN_ESR1_IDLE. */
1847 #define BS_CAN_ESR1_IDLE (1U) /*!< Bit field size in bits for CAN_ESR1_IDLE. */
1849 /*! @brief Read current value of the CAN_ESR1_IDLE field. */
1850 #define BR_CAN_ESR1_IDLE(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_IDLE))
1854 * @name Register CAN_ESR1, field RXWRN[8] (RO)
1856 * This bit indicates when repetitive errors are occurring during message
1857 * reception. This bit is not updated during Freeze mode.
1860 * - 0 - No such occurrence.
1861 * - 1 - RXERRCNT is greater than or equal to 96.
1864 #define BP_CAN_ESR1_RXWRN (8U) /*!< Bit position for CAN_ESR1_RXWRN. */
1865 #define BM_CAN_ESR1_RXWRN (0x00000100U) /*!< Bit mask for CAN_ESR1_RXWRN. */
1866 #define BS_CAN_ESR1_RXWRN (1U) /*!< Bit field size in bits for CAN_ESR1_RXWRN. */
1868 /*! @brief Read current value of the CAN_ESR1_RXWRN field. */
1869 #define BR_CAN_ESR1_RXWRN(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RXWRN))
1873 * @name Register CAN_ESR1, field TXWRN[9] (RO)
1875 * This bit indicates when repetitive errors are occurring during message
1876 * transmission. This bit is not updated during Freeze mode.
1879 * - 0 - No such occurrence.
1880 * - 1 - TXERRCNT is greater than or equal to 96.
1883 #define BP_CAN_ESR1_TXWRN (9U) /*!< Bit position for CAN_ESR1_TXWRN. */
1884 #define BM_CAN_ESR1_TXWRN (0x00000200U) /*!< Bit mask for CAN_ESR1_TXWRN. */
1885 #define BS_CAN_ESR1_TXWRN (1U) /*!< Bit field size in bits for CAN_ESR1_TXWRN. */
1887 /*! @brief Read current value of the CAN_ESR1_TXWRN field. */
1888 #define BR_CAN_ESR1_TXWRN(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TXWRN))
1892 * @name Register CAN_ESR1, field STFERR[10] (RO)
1894 * This bit indicates that a Stuffing Error has been etected.
1897 * - 0 - No such occurrence.
1898 * - 1 - A Stuffing Error occurred since last read of this register.
1901 #define BP_CAN_ESR1_STFERR (10U) /*!< Bit position for CAN_ESR1_STFERR. */
1902 #define BM_CAN_ESR1_STFERR (0x00000400U) /*!< Bit mask for CAN_ESR1_STFERR. */
1903 #define BS_CAN_ESR1_STFERR (1U) /*!< Bit field size in bits for CAN_ESR1_STFERR. */
1905 /*! @brief Read current value of the CAN_ESR1_STFERR field. */
1906 #define BR_CAN_ESR1_STFERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_STFERR))
1910 * @name Register CAN_ESR1, field FRMERR[11] (RO)
1912 * This bit indicates that a Form Error has been detected by the receiver node,
1913 * that is, a fixed-form bit field contains at least one illegal bit.
1916 * - 0 - No such occurrence.
1917 * - 1 - A Form Error occurred since last read of this register.
1920 #define BP_CAN_ESR1_FRMERR (11U) /*!< Bit position for CAN_ESR1_FRMERR. */
1921 #define BM_CAN_ESR1_FRMERR (0x00000800U) /*!< Bit mask for CAN_ESR1_FRMERR. */
1922 #define BS_CAN_ESR1_FRMERR (1U) /*!< Bit field size in bits for CAN_ESR1_FRMERR. */
1924 /*! @brief Read current value of the CAN_ESR1_FRMERR field. */
1925 #define BR_CAN_ESR1_FRMERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_FRMERR))
1929 * @name Register CAN_ESR1, field CRCERR[12] (RO)
1931 * This bit indicates that a CRC Error has been detected by the receiver node,
1932 * that is, the calculated CRC is different from the received.
1935 * - 0 - No such occurrence.
1936 * - 1 - A CRC error occurred since last read of this register.
1939 #define BP_CAN_ESR1_CRCERR (12U) /*!< Bit position for CAN_ESR1_CRCERR. */
1940 #define BM_CAN_ESR1_CRCERR (0x00001000U) /*!< Bit mask for CAN_ESR1_CRCERR. */
1941 #define BS_CAN_ESR1_CRCERR (1U) /*!< Bit field size in bits for CAN_ESR1_CRCERR. */
1943 /*! @brief Read current value of the CAN_ESR1_CRCERR field. */
1944 #define BR_CAN_ESR1_CRCERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_CRCERR))
1948 * @name Register CAN_ESR1, field ACKERR[13] (RO)
1950 * This bit indicates that an Acknowledge Error has been detected by the
1951 * transmitter node, that is, a dominant bit has not been detected during the ACK SLOT.
1954 * - 0 - No such occurrence.
1955 * - 1 - An ACK error occurred since last read of this register.
1958 #define BP_CAN_ESR1_ACKERR (13U) /*!< Bit position for CAN_ESR1_ACKERR. */
1959 #define BM_CAN_ESR1_ACKERR (0x00002000U) /*!< Bit mask for CAN_ESR1_ACKERR. */
1960 #define BS_CAN_ESR1_ACKERR (1U) /*!< Bit field size in bits for CAN_ESR1_ACKERR. */
1962 /*! @brief Read current value of the CAN_ESR1_ACKERR field. */
1963 #define BR_CAN_ESR1_ACKERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_ACKERR))
1967 * @name Register CAN_ESR1, field BIT0ERR[14] (RO)
1969 * This bit indicates when an inconsistency occurs between the transmitted and
1970 * the received bit in a message.
1973 * - 0 - No such occurrence.
1974 * - 1 - At least one bit sent as dominant is received as recessive.
1977 #define BP_CAN_ESR1_BIT0ERR (14U) /*!< Bit position for CAN_ESR1_BIT0ERR. */
1978 #define BM_CAN_ESR1_BIT0ERR (0x00004000U) /*!< Bit mask for CAN_ESR1_BIT0ERR. */
1979 #define BS_CAN_ESR1_BIT0ERR (1U) /*!< Bit field size in bits for CAN_ESR1_BIT0ERR. */
1981 /*! @brief Read current value of the CAN_ESR1_BIT0ERR field. */
1982 #define BR_CAN_ESR1_BIT0ERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BIT0ERR))
1986 * @name Register CAN_ESR1, field BIT1ERR[15] (RO)
1988 * This bit indicates when an inconsistency occurs between the transmitted and
1989 * the received bit in a message. This bit is not set by a transmitter in case of
1990 * arbitration field or ACK slot, or in case of a node sending a passive error
1991 * flag that detects dominant bits.
1994 * - 0 - No such occurrence.
1995 * - 1 - At least one bit sent as recessive is received as dominant.
1998 #define BP_CAN_ESR1_BIT1ERR (15U) /*!< Bit position for CAN_ESR1_BIT1ERR. */
1999 #define BM_CAN_ESR1_BIT1ERR (0x00008000U) /*!< Bit mask for CAN_ESR1_BIT1ERR. */
2000 #define BS_CAN_ESR1_BIT1ERR (1U) /*!< Bit field size in bits for CAN_ESR1_BIT1ERR. */
2002 /*! @brief Read current value of the CAN_ESR1_BIT1ERR field. */
2003 #define BR_CAN_ESR1_BIT1ERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BIT1ERR))
2007 * @name Register CAN_ESR1, field RWRNINT[16] (W1C)
2009 * If the WRNEN bit in MCR is asserted, the RWRNINT bit is set when the RXWRN
2010 * flag transitions from 0 to 1, meaning that the Rx error counters reached 96. If
2011 * the corresponding mask bit in the Control Register (RWRNMSK) is set, an
2012 * interrupt is generated to the CPU. This bit is cleared by writing it to 1. When
2013 * WRNEN is negated, this flag is masked. CPU must clear this flag before disabling
2014 * the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no
2015 * effect. This bit is not updated during Freeze mode.
2018 * - 0 - No such occurrence.
2019 * - 1 - The Rx error counter transitioned from less than 96 to greater than or
2023 #define BP_CAN_ESR1_RWRNINT (16U) /*!< Bit position for CAN_ESR1_RWRNINT. */
2024 #define BM_CAN_ESR1_RWRNINT (0x00010000U) /*!< Bit mask for CAN_ESR1_RWRNINT. */
2025 #define BS_CAN_ESR1_RWRNINT (1U) /*!< Bit field size in bits for CAN_ESR1_RWRNINT. */
2027 /*! @brief Read current value of the CAN_ESR1_RWRNINT field. */
2028 #define BR_CAN_ESR1_RWRNINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RWRNINT))
2030 /*! @brief Format value for bitfield CAN_ESR1_RWRNINT. */
2031 #define BF_CAN_ESR1_RWRNINT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ESR1_RWRNINT) & BM_CAN_ESR1_RWRNINT)
2033 /*! @brief Set the RWRNINT field to a new value. */
2034 #define BW_CAN_ESR1_RWRNINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RWRNINT) = (v))
2038 * @name Register CAN_ESR1, field TWRNINT[17] (W1C)
2040 * If the WRNEN bit in MCR is asserted, the TWRNINT bit is set when the TXWRN
2041 * flag transitions from 0 to 1, meaning that the Tx error counter reached 96. If
2042 * the corresponding mask bit in the Control Register (TWRNMSK) is set, an
2043 * interrupt is generated to the CPU. This bit is cleared by writing it to 1. When WRNEN
2044 * is negated, this flag is masked. CPU must clear this flag before disabling
2045 * the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no
2046 * effect. This flag is not generated during Bus Off state. This bit is not
2047 * updated during Freeze mode.
2050 * - 0 - No such occurrence.
2051 * - 1 - The Tx error counter transitioned from less than 96 to greater than or
2055 #define BP_CAN_ESR1_TWRNINT (17U) /*!< Bit position for CAN_ESR1_TWRNINT. */
2056 #define BM_CAN_ESR1_TWRNINT (0x00020000U) /*!< Bit mask for CAN_ESR1_TWRNINT. */
2057 #define BS_CAN_ESR1_TWRNINT (1U) /*!< Bit field size in bits for CAN_ESR1_TWRNINT. */
2059 /*! @brief Read current value of the CAN_ESR1_TWRNINT field. */
2060 #define BR_CAN_ESR1_TWRNINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TWRNINT))
2062 /*! @brief Format value for bitfield CAN_ESR1_TWRNINT. */
2063 #define BF_CAN_ESR1_TWRNINT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ESR1_TWRNINT) & BM_CAN_ESR1_TWRNINT)
2065 /*! @brief Set the TWRNINT field to a new value. */
2066 #define BW_CAN_ESR1_TWRNINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TWRNINT) = (v))
2070 * @name Register CAN_ESR1, field SYNCH[18] (RO)
2072 * This read-only flag indicates whether the FlexCAN is synchronized to the CAN
2073 * bus and able to participate in the communication process. It is set and
2074 * cleared by the FlexCAN. See the table in the overall CAN_ESR1 register description.
2077 * - 0 - FlexCAN is not synchronized to the CAN bus.
2078 * - 1 - FlexCAN is synchronized to the CAN bus.
2081 #define BP_CAN_ESR1_SYNCH (18U) /*!< Bit position for CAN_ESR1_SYNCH. */
2082 #define BM_CAN_ESR1_SYNCH (0x00040000U) /*!< Bit mask for CAN_ESR1_SYNCH. */
2083 #define BS_CAN_ESR1_SYNCH (1U) /*!< Bit field size in bits for CAN_ESR1_SYNCH. */
2085 /*! @brief Read current value of the CAN_ESR1_SYNCH field. */
2086 #define BR_CAN_ESR1_SYNCH(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_SYNCH))
2089 /*******************************************************************************
2090 * HW_CAN_IMASK1 - Interrupt Masks 1 register
2091 ******************************************************************************/
2094 * @brief HW_CAN_IMASK1 - Interrupt Masks 1 register (RW)
2096 * Reset value: 0x00000000U
2098 * This register allows any number of a range of the 32 Message Buffer
2099 * Interrupts to be enabled or disabled for MB31 to MB0. It contains one interrupt mask
2100 * bit per buffer, enabling the CPU to determine which buffer generates an
2101 * interrupt after a successful transmission or reception, that is, when the
2102 * corresponding IFLAG1 bit is set.
2104 typedef union _hw_can_imask1
2107 struct _hw_can_imask1_bitfields
2109 uint32_t BUFLM
: 32; /*!< [31:0] Buffer MB i Mask */
2114 * @name Constants and macros for entire CAN_IMASK1 register
2117 #define HW_CAN_IMASK1_ADDR(x) ((x) + 0x28U)
2119 #define HW_CAN_IMASK1(x) (*(__IO hw_can_imask1_t *) HW_CAN_IMASK1_ADDR(x))
2120 #define HW_CAN_IMASK1_RD(x) (HW_CAN_IMASK1(x).U)
2121 #define HW_CAN_IMASK1_WR(x, v) (HW_CAN_IMASK1(x).U = (v))
2122 #define HW_CAN_IMASK1_SET(x, v) (HW_CAN_IMASK1_WR(x, HW_CAN_IMASK1_RD(x) | (v)))
2123 #define HW_CAN_IMASK1_CLR(x, v) (HW_CAN_IMASK1_WR(x, HW_CAN_IMASK1_RD(x) & ~(v)))
2124 #define HW_CAN_IMASK1_TOG(x, v) (HW_CAN_IMASK1_WR(x, HW_CAN_IMASK1_RD(x) ^ (v)))
2128 * Constants & macros for individual CAN_IMASK1 bitfields
2132 * @name Register CAN_IMASK1, field BUFLM[31:0] (RW)
2134 * Each bit enables or disables the corresponding FlexCAN Message Buffer
2135 * Interrupt for MB31 to MB0. Setting or clearing a bit in the IMASK1 Register can
2136 * assert or negate an interrupt request, if the corresponding IFLAG1 bit is set.
2139 * - 0 - The corresponding buffer Interrupt is disabled.
2140 * - 1 - The corresponding buffer Interrupt is enabled.
2143 #define BP_CAN_IMASK1_BUFLM (0U) /*!< Bit position for CAN_IMASK1_BUFLM. */
2144 #define BM_CAN_IMASK1_BUFLM (0xFFFFFFFFU) /*!< Bit mask for CAN_IMASK1_BUFLM. */
2145 #define BS_CAN_IMASK1_BUFLM (32U) /*!< Bit field size in bits for CAN_IMASK1_BUFLM. */
2147 /*! @brief Read current value of the CAN_IMASK1_BUFLM field. */
2148 #define BR_CAN_IMASK1_BUFLM(x) (HW_CAN_IMASK1(x).U)
2150 /*! @brief Format value for bitfield CAN_IMASK1_BUFLM. */
2151 #define BF_CAN_IMASK1_BUFLM(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IMASK1_BUFLM) & BM_CAN_IMASK1_BUFLM)
2153 /*! @brief Set the BUFLM field to a new value. */
2154 #define BW_CAN_IMASK1_BUFLM(x, v) (HW_CAN_IMASK1_WR(x, v))
2157 /*******************************************************************************
2158 * HW_CAN_IFLAG1 - Interrupt Flags 1 register
2159 ******************************************************************************/
2162 * @brief HW_CAN_IFLAG1 - Interrupt Flags 1 register (W1C)
2164 * Reset value: 0x00000000U
2166 * This register defines the flags for the 32 Message Buffer interrupts for MB31
2167 * to MB0. It contains one interrupt flag bit per buffer. Each successful
2168 * transmission or reception sets the corresponding IFLAG1 bit. If the corresponding
2169 * IMASK1 bit is set, an interrupt will be generated. The interrupt flag must be
2170 * cleared by writing 1 to it. Writing 0 has no effect. The BUF7I to BUF5I flags
2171 * are also used to represent FIFO interrupts when the Rx FIFO is enabled. When the
2172 * bit MCR[RFEN] is set, the function of the 8 least significant interrupt flags
2173 * BUF[7:0]I changes: BUF7I, BUF6I and BUF5I indicate operating conditions of
2174 * the FIFO, and the BUF4TO0I field is reserved. Before enabling the RFEN, the CPU
2175 * must service the IFLAG bits asserted in the Rx FIFO region; see Section "Rx
2176 * FIFO". Otherwise, these IFLAG bits will mistakenly show the related MBs now
2177 * belonging to FIFO as having contents to be serviced. When the RFEN bit is negated,
2178 * the FIFO flags must be cleared. The same care must be taken when an RFFN
2179 * value is selected extending Rx FIFO filters beyond MB7. For example, when RFFN is
2180 * 0x8, the MB0-23 range is occupied by Rx FIFO filters and related IFLAG bits
2181 * must be cleared. Before updating MCR[MAXMB] field, CPU must service the IFLAG1
2182 * bits whose MB value is greater than the MCR[MAXMB] to be updated; otherwise,
2183 * they will remain set and be inconsistent with the number of MBs available.
2185 typedef union _hw_can_iflag1
2188 struct _hw_can_iflag1_bitfields
2190 uint32_t BUF0I
: 1; /*!< [0] Buffer MB0 Interrupt Or "reserved" */
2191 uint32_t BUF4TO1I
: 4; /*!< [4:1] Buffer MB i Interrupt Or "reserved"
2193 uint32_t BUF5I
: 1; /*!< [5] Buffer MB5 Interrupt Or "Frames
2194 * available in Rx FIFO" */
2195 uint32_t BUF6I
: 1; /*!< [6] Buffer MB6 Interrupt Or "Rx FIFO
2197 uint32_t BUF7I
: 1; /*!< [7] Buffer MB7 Interrupt Or "Rx FIFO
2199 uint32_t BUF31TO8I
: 24; /*!< [31:8] Buffer MBi Interrupt */
2204 * @name Constants and macros for entire CAN_IFLAG1 register
2207 #define HW_CAN_IFLAG1_ADDR(x) ((x) + 0x30U)
2209 #define HW_CAN_IFLAG1(x) (*(__IO hw_can_iflag1_t *) HW_CAN_IFLAG1_ADDR(x))
2210 #define HW_CAN_IFLAG1_RD(x) (HW_CAN_IFLAG1(x).U)
2211 #define HW_CAN_IFLAG1_WR(x, v) (HW_CAN_IFLAG1(x).U = (v))
2212 #define HW_CAN_IFLAG1_SET(x, v) (HW_CAN_IFLAG1_WR(x, HW_CAN_IFLAG1_RD(x) | (v)))
2213 #define HW_CAN_IFLAG1_CLR(x, v) (HW_CAN_IFLAG1_WR(x, HW_CAN_IFLAG1_RD(x) & ~(v)))
2214 #define HW_CAN_IFLAG1_TOG(x, v) (HW_CAN_IFLAG1_WR(x, HW_CAN_IFLAG1_RD(x) ^ (v)))
2218 * Constants & macros for individual CAN_IFLAG1 bitfields
2222 * @name Register CAN_IFLAG1, field BUF0I[0] (W1C)
2224 * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
2225 * the interrupt for MB0. This flag is cleared by the FlexCAN whenever the bit
2226 * MCR[RFEN] is changed by CPU writes. The BUF0I flag is reserved when MCR[RFEN] is
2230 * - 0 - The corresponding buffer has no occurrence of successfully completed
2231 * transmission or reception when MCR[RFEN]=0.
2232 * - 1 - The corresponding buffer has successfully completed transmission or
2233 * reception when MCR[RFEN]=0.
2236 #define BP_CAN_IFLAG1_BUF0I (0U) /*!< Bit position for CAN_IFLAG1_BUF0I. */
2237 #define BM_CAN_IFLAG1_BUF0I (0x00000001U) /*!< Bit mask for CAN_IFLAG1_BUF0I. */
2238 #define BS_CAN_IFLAG1_BUF0I (1U) /*!< Bit field size in bits for CAN_IFLAG1_BUF0I. */
2240 /*! @brief Read current value of the CAN_IFLAG1_BUF0I field. */
2241 #define BR_CAN_IFLAG1_BUF0I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF0I))
2243 /*! @brief Format value for bitfield CAN_IFLAG1_BUF0I. */
2244 #define BF_CAN_IFLAG1_BUF0I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF0I) & BM_CAN_IFLAG1_BUF0I)
2246 /*! @brief Set the BUF0I field to a new value. */
2247 #define BW_CAN_IFLAG1_BUF0I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF0I) = (v))
2251 * @name Register CAN_IFLAG1, field BUF4TO1I[4:1] (W1C)
2253 * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), these bits flag
2254 * the interrupts for MB4 to MB1. These flags are cleared by the FlexCAN whenever
2255 * the bit MCR[RFEN] is changed by CPU writes. The BUF4TO1I flags are reserved
2256 * when MCR[RFEN] is set.
2259 * - 0 - The corresponding buffer has no occurrence of successfully completed
2260 * transmission or reception when MCR[RFEN]=0.
2261 * - 1 - The corresponding buffer has successfully completed transmission or
2262 * reception when MCR[RFEN]=0.
2265 #define BP_CAN_IFLAG1_BUF4TO1I (1U) /*!< Bit position for CAN_IFLAG1_BUF4TO1I. */
2266 #define BM_CAN_IFLAG1_BUF4TO1I (0x0000001EU) /*!< Bit mask for CAN_IFLAG1_BUF4TO1I. */
2267 #define BS_CAN_IFLAG1_BUF4TO1I (4U) /*!< Bit field size in bits for CAN_IFLAG1_BUF4TO1I. */
2269 /*! @brief Read current value of the CAN_IFLAG1_BUF4TO1I field. */
2270 #define BR_CAN_IFLAG1_BUF4TO1I(x) (HW_CAN_IFLAG1(x).B.BUF4TO1I)
2272 /*! @brief Format value for bitfield CAN_IFLAG1_BUF4TO1I. */
2273 #define BF_CAN_IFLAG1_BUF4TO1I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF4TO1I) & BM_CAN_IFLAG1_BUF4TO1I)
2275 /*! @brief Set the BUF4TO1I field to a new value. */
2276 #define BW_CAN_IFLAG1_BUF4TO1I(x, v) (HW_CAN_IFLAG1_WR(x, (HW_CAN_IFLAG1_RD(x) & ~BM_CAN_IFLAG1_BUF4TO1I) | BF_CAN_IFLAG1_BUF4TO1I(v)))
2280 * @name Register CAN_IFLAG1, field BUF5I[5] (W1C)
2282 * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
2283 * the interrupt for MB5. This flag is cleared by the FlexCAN whenever the bit
2284 * MCR[RFEN] is changed by CPU writes. The BUF5I flag represents "Frames available in
2285 * Rx FIFO" when MCR[RFEN] is set. In this case, the flag indicates that at
2286 * least one frame is available to be read from the Rx FIFO.
2289 * - 0 - No occurrence of MB5 completing transmission/reception when
2290 * MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1
2291 * - 1 - MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s)
2292 * available in the Rx FIFO when MCR[RFEN]=1
2295 #define BP_CAN_IFLAG1_BUF5I (5U) /*!< Bit position for CAN_IFLAG1_BUF5I. */
2296 #define BM_CAN_IFLAG1_BUF5I (0x00000020U) /*!< Bit mask for CAN_IFLAG1_BUF5I. */
2297 #define BS_CAN_IFLAG1_BUF5I (1U) /*!< Bit field size in bits for CAN_IFLAG1_BUF5I. */
2299 /*! @brief Read current value of the CAN_IFLAG1_BUF5I field. */
2300 #define BR_CAN_IFLAG1_BUF5I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF5I))
2302 /*! @brief Format value for bitfield CAN_IFLAG1_BUF5I. */
2303 #define BF_CAN_IFLAG1_BUF5I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF5I) & BM_CAN_IFLAG1_BUF5I)
2305 /*! @brief Set the BUF5I field to a new value. */
2306 #define BW_CAN_IFLAG1_BUF5I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF5I) = (v))
2310 * @name Register CAN_IFLAG1, field BUF6I[6] (W1C)
2312 * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
2313 * the interrupt for MB6. This flag is cleared by the FlexCAN whenever the bit
2314 * MCR[RFEN] is changed by CPU writes. The BUF6I flag represents "Rx FIFO Warning"
2315 * when MCR[RFEN] is set. In this case, the flag indicates when the number of
2316 * unread messages within the Rx FIFO is increased to 5 from 4 due to the reception of
2317 * a new one, meaning that the Rx FIFO is almost full. Note that if the flag is
2318 * cleared while the number of unread messages is greater than 4, it does not
2319 * assert again until the number of unread messages within the Rx FIFO is decreased
2320 * to be equal to or less than 4.
2323 * - 0 - No occurrence of MB6 completing transmission/reception when
2324 * MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1
2325 * - 1 - MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO
2326 * almost full when MCR[RFEN]=1
2329 #define BP_CAN_IFLAG1_BUF6I (6U) /*!< Bit position for CAN_IFLAG1_BUF6I. */
2330 #define BM_CAN_IFLAG1_BUF6I (0x00000040U) /*!< Bit mask for CAN_IFLAG1_BUF6I. */
2331 #define BS_CAN_IFLAG1_BUF6I (1U) /*!< Bit field size in bits for CAN_IFLAG1_BUF6I. */
2333 /*! @brief Read current value of the CAN_IFLAG1_BUF6I field. */
2334 #define BR_CAN_IFLAG1_BUF6I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF6I))
2336 /*! @brief Format value for bitfield CAN_IFLAG1_BUF6I. */
2337 #define BF_CAN_IFLAG1_BUF6I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF6I) & BM_CAN_IFLAG1_BUF6I)
2339 /*! @brief Set the BUF6I field to a new value. */
2340 #define BW_CAN_IFLAG1_BUF6I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF6I) = (v))
2344 * @name Register CAN_IFLAG1, field BUF7I[7] (W1C)
2346 * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
2347 * the interrupt for MB7. This flag is cleared by the FlexCAN whenever the bit
2348 * MCR[RFEN] is changed by CPU writes. The BUF7I flag represents "Rx FIFO Overflow"
2349 * when MCR[RFEN] is set. In this case, the flag indicates that a message was lost
2350 * because the Rx FIFO is full. Note that the flag will not be asserted when the
2351 * Rx FIFO is full and the message was captured by a Mailbox.
2354 * - 0 - No occurrence of MB7 completing transmission/reception when
2355 * MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1
2356 * - 1 - MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO
2357 * overflow when MCR[RFEN]=1
2360 #define BP_CAN_IFLAG1_BUF7I (7U) /*!< Bit position for CAN_IFLAG1_BUF7I. */
2361 #define BM_CAN_IFLAG1_BUF7I (0x00000080U) /*!< Bit mask for CAN_IFLAG1_BUF7I. */
2362 #define BS_CAN_IFLAG1_BUF7I (1U) /*!< Bit field size in bits for CAN_IFLAG1_BUF7I. */
2364 /*! @brief Read current value of the CAN_IFLAG1_BUF7I field. */
2365 #define BR_CAN_IFLAG1_BUF7I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF7I))
2367 /*! @brief Format value for bitfield CAN_IFLAG1_BUF7I. */
2368 #define BF_CAN_IFLAG1_BUF7I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF7I) & BM_CAN_IFLAG1_BUF7I)
2370 /*! @brief Set the BUF7I field to a new value. */
2371 #define BW_CAN_IFLAG1_BUF7I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF7I) = (v))
2375 * @name Register CAN_IFLAG1, field BUF31TO8I[31:8] (W1C)
2377 * Each bit flags the corresponding FlexCAN Message Buffer interrupt for MB31 to
2381 * - 0 - The corresponding buffer has no occurrence of successfully completed
2382 * transmission or reception.
2383 * - 1 - The corresponding buffer has successfully completed transmission or
2387 #define BP_CAN_IFLAG1_BUF31TO8I (8U) /*!< Bit position for CAN_IFLAG1_BUF31TO8I. */
2388 #define BM_CAN_IFLAG1_BUF31TO8I (0xFFFFFF00U) /*!< Bit mask for CAN_IFLAG1_BUF31TO8I. */
2389 #define BS_CAN_IFLAG1_BUF31TO8I (24U) /*!< Bit field size in bits for CAN_IFLAG1_BUF31TO8I. */
2391 /*! @brief Read current value of the CAN_IFLAG1_BUF31TO8I field. */
2392 #define BR_CAN_IFLAG1_BUF31TO8I(x) (HW_CAN_IFLAG1(x).B.BUF31TO8I)
2394 /*! @brief Format value for bitfield CAN_IFLAG1_BUF31TO8I. */
2395 #define BF_CAN_IFLAG1_BUF31TO8I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF31TO8I) & BM_CAN_IFLAG1_BUF31TO8I)
2397 /*! @brief Set the BUF31TO8I field to a new value. */
2398 #define BW_CAN_IFLAG1_BUF31TO8I(x, v) (HW_CAN_IFLAG1_WR(x, (HW_CAN_IFLAG1_RD(x) & ~BM_CAN_IFLAG1_BUF31TO8I) | BF_CAN_IFLAG1_BUF31TO8I(v)))
2401 /*******************************************************************************
2402 * HW_CAN_CTRL2 - Control 2 register
2403 ******************************************************************************/
2406 * @brief HW_CAN_CTRL2 - Control 2 register (RW)
2408 * Reset value: 0x00B00000U
2410 * This register contains control bits for CAN errors, FIFO features, and mode
2413 typedef union _hw_can_ctrl2
2416 struct _hw_can_ctrl2_bitfields
2418 uint32_t RESERVED0
: 16; /*!< [15:0] */
2419 uint32_t EACEN
: 1; /*!< [16] Entire Frame Arbitration Field
2420 * Comparison Enable For Rx Mailboxes */
2421 uint32_t RRS
: 1; /*!< [17] Remote Request Storing */
2422 uint32_t MRP
: 1; /*!< [18] Mailboxes Reception Priority */
2423 uint32_t TASD
: 5; /*!< [23:19] Tx Arbitration Start Delay */
2424 uint32_t RFFN
: 4; /*!< [27:24] Number Of Rx FIFO Filters */
2425 uint32_t WRMFRZ
: 1; /*!< [28] Write-Access To Memory In Freeze Mode
2427 uint32_t RESERVED1
: 3; /*!< [31:29] */
2432 * @name Constants and macros for entire CAN_CTRL2 register
2435 #define HW_CAN_CTRL2_ADDR(x) ((x) + 0x34U)
2437 #define HW_CAN_CTRL2(x) (*(__IO hw_can_ctrl2_t *) HW_CAN_CTRL2_ADDR(x))
2438 #define HW_CAN_CTRL2_RD(x) (HW_CAN_CTRL2(x).U)
2439 #define HW_CAN_CTRL2_WR(x, v) (HW_CAN_CTRL2(x).U = (v))
2440 #define HW_CAN_CTRL2_SET(x, v) (HW_CAN_CTRL2_WR(x, HW_CAN_CTRL2_RD(x) | (v)))
2441 #define HW_CAN_CTRL2_CLR(x, v) (HW_CAN_CTRL2_WR(x, HW_CAN_CTRL2_RD(x) & ~(v)))
2442 #define HW_CAN_CTRL2_TOG(x, v) (HW_CAN_CTRL2_WR(x, HW_CAN_CTRL2_RD(x) ^ (v)))
2446 * Constants & macros for individual CAN_CTRL2 bitfields
2450 * @name Register CAN_CTRL2, field EACEN[16] (RW)
2452 * This bit controls the comparison of IDE and RTR bits whithin Rx Mailboxes
2453 * filters with their corresponding bits in the incoming frame by the matching
2454 * process. This bit does not affect matching for Rx FIFO. This bit can be written
2455 * only in Freeze mode because it is blocked by hardware in other modes.
2458 * - 0 - Rx Mailbox filter's IDE bit is always compared and RTR is never
2459 * compared despite mask bits.
2460 * - 1 - Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with
2461 * their corresponding bits within the incoming frame. Mask bits do apply.
2464 #define BP_CAN_CTRL2_EACEN (16U) /*!< Bit position for CAN_CTRL2_EACEN. */
2465 #define BM_CAN_CTRL2_EACEN (0x00010000U) /*!< Bit mask for CAN_CTRL2_EACEN. */
2466 #define BS_CAN_CTRL2_EACEN (1U) /*!< Bit field size in bits for CAN_CTRL2_EACEN. */
2468 /*! @brief Read current value of the CAN_CTRL2_EACEN field. */
2469 #define BR_CAN_CTRL2_EACEN(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_EACEN))
2471 /*! @brief Format value for bitfield CAN_CTRL2_EACEN. */
2472 #define BF_CAN_CTRL2_EACEN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_EACEN) & BM_CAN_CTRL2_EACEN)
2474 /*! @brief Set the EACEN field to a new value. */
2475 #define BW_CAN_CTRL2_EACEN(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_EACEN) = (v))
2479 * @name Register CAN_CTRL2, field RRS[17] (RW)
2481 * If this bit is asserted Remote Request Frame is submitted to a matching
2482 * process and stored in the corresponding Message Buffer in the same fashion of a
2483 * Data Frame. No automatic Remote Response Frame will be generated. If this bit is
2484 * negated the Remote Request Frame is submitted to a matching process and an
2485 * automatic Remote Response Frame is generated if a Message Buffer with CODE=0b1010
2486 * is found with the same ID. This bit can be written only in Freeze mode
2487 * because it is blocked by hardware in other modes.
2490 * - 0 - Remote Response Frame is generated.
2491 * - 1 - Remote Request Frame is stored.
2494 #define BP_CAN_CTRL2_RRS (17U) /*!< Bit position for CAN_CTRL2_RRS. */
2495 #define BM_CAN_CTRL2_RRS (0x00020000U) /*!< Bit mask for CAN_CTRL2_RRS. */
2496 #define BS_CAN_CTRL2_RRS (1U) /*!< Bit field size in bits for CAN_CTRL2_RRS. */
2498 /*! @brief Read current value of the CAN_CTRL2_RRS field. */
2499 #define BR_CAN_CTRL2_RRS(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_RRS))
2501 /*! @brief Format value for bitfield CAN_CTRL2_RRS. */
2502 #define BF_CAN_CTRL2_RRS(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_RRS) & BM_CAN_CTRL2_RRS)
2504 /*! @brief Set the RRS field to a new value. */
2505 #define BW_CAN_CTRL2_RRS(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_RRS) = (v))
2509 * @name Register CAN_CTRL2, field MRP[18] (RW)
2511 * If this bit is set the matching process starts from the Mailboxes and if no
2512 * match occurs the matching continues on the Rx FIFO. This bit can be written
2513 * only in Freeze mode because it is blocked by hardware in other modes.
2516 * - 0 - Matching starts from Rx FIFO and continues on Mailboxes.
2517 * - 1 - Matching starts from Mailboxes and continues on Rx FIFO.
2520 #define BP_CAN_CTRL2_MRP (18U) /*!< Bit position for CAN_CTRL2_MRP. */
2521 #define BM_CAN_CTRL2_MRP (0x00040000U) /*!< Bit mask for CAN_CTRL2_MRP. */
2522 #define BS_CAN_CTRL2_MRP (1U) /*!< Bit field size in bits for CAN_CTRL2_MRP. */
2524 /*! @brief Read current value of the CAN_CTRL2_MRP field. */
2525 #define BR_CAN_CTRL2_MRP(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_MRP))
2527 /*! @brief Format value for bitfield CAN_CTRL2_MRP. */
2528 #define BF_CAN_CTRL2_MRP(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_MRP) & BM_CAN_CTRL2_MRP)
2530 /*! @brief Set the MRP field to a new value. */
2531 #define BW_CAN_CTRL2_MRP(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_MRP) = (v))
2535 * @name Register CAN_CTRL2, field TASD[23:19] (RW)
2537 * This 5-bit field indicates how many CAN bits the Tx arbitration process start
2538 * point can be delayed from the first bit of CRC field on CAN bus. This field
2539 * can be written only in Freeze mode because it is blocked by hardware in other
2540 * modes. This field is useful to optimize the transmit performance based on
2541 * factors such as: peripheral/serial clock ratio, CAN bit timing and number of MBs.
2542 * The duration of an arbitration process, in terms of CAN bits, is directly
2543 * proportional to the number of available MBs and CAN baud rate and inversely
2544 * proportional to the peripheral clock frequency. The optimal arbitration timing is
2545 * that in which the last MB is scanned right before the first bit of the
2546 * Intermission field of a CAN frame. Therefore, if there are few MBs and the system/serial
2547 * clock ratio is high and the CAN baud rate is low then the arbitration can be
2548 * delayed and vice-versa. If TASD is 0 then the arbitration start is not
2549 * delayed, thus the CPU has less time to configure a Tx MB for the next arbitration,
2550 * but more time is reserved for arbitration. On the other hand, if TASD is 24 then
2551 * the CPU can configure a Tx MB later and less time is reserved for
2552 * arbitration. If too little time is reserved for arbitration the FlexCAN may be not able
2553 * to find winner MBs in time to compete with other nodes for the CAN bus. If the
2554 * arbitration ends too much time before the first bit of Intermission field then
2555 * there is a chance that the CPU reconfigures some Tx MBs and the winner MB is
2556 * not the best to be transmitted. The optimal configuration for TASD can be
2557 * calculated as: TASD = 25 - {f CANCLK * [MAXMB + 3 - (RFEN * 8) - (RFEN * RFFN *
2558 * 2)] * 2} / {f SYS * [1+(PSEG1+1)+(PSEG2+1)+(PROPSEG+1)] * (PRESDIV+1)} where: f
2559 * CANCLK is the Protocol Engine (PE) Clock (see section "Protocol Timing"), in
2560 * Hz f SYS is the peripheral clock, in Hz MAXMB is the value in CTRL1[MAXMB]
2561 * field RFEN is the value in CTRL1[RFEN] bit RFFN is the value in CTRL2[RFFN] field
2562 * PSEG1 is the value in CTRL1[PSEG1] field PSEG2 is the value in CTRL1[PSEG2]
2563 * field PROPSEG is the value in CTRL1[PROPSEG] field PRESDIV is the value in
2564 * CTRL1[PRESDIV] field See Section "Arbitration process" and Section "Protocol
2565 * Timing" for more details.
2568 #define BP_CAN_CTRL2_TASD (19U) /*!< Bit position for CAN_CTRL2_TASD. */
2569 #define BM_CAN_CTRL2_TASD (0x00F80000U) /*!< Bit mask for CAN_CTRL2_TASD. */
2570 #define BS_CAN_CTRL2_TASD (5U) /*!< Bit field size in bits for CAN_CTRL2_TASD. */
2572 /*! @brief Read current value of the CAN_CTRL2_TASD field. */
2573 #define BR_CAN_CTRL2_TASD(x) (HW_CAN_CTRL2(x).B.TASD)
2575 /*! @brief Format value for bitfield CAN_CTRL2_TASD. */
2576 #define BF_CAN_CTRL2_TASD(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_TASD) & BM_CAN_CTRL2_TASD)
2578 /*! @brief Set the TASD field to a new value. */
2579 #define BW_CAN_CTRL2_TASD(x, v) (HW_CAN_CTRL2_WR(x, (HW_CAN_CTRL2_RD(x) & ~BM_CAN_CTRL2_TASD) | BF_CAN_CTRL2_TASD(v)))
2583 * @name Register CAN_CTRL2, field RFFN[27:24] (RW)
2585 * This 4-bit field defines the number of Rx FIFO filters, as shown in the
2586 * following table. The maximum selectable number of filters is determined by the MCU.
2587 * This field can only be written in Freeze mode as it is blocked by hardware in
2588 * other modes. This field must not be programmed with values that make the
2589 * number of Message Buffers occupied by Rx FIFO and ID Filter exceed the number of
2590 * Mailboxes present, defined by MCR[MAXMB]. Each group of eight filters occupies
2591 * a memory space equivalent to two Message Buffers which means that the more
2592 * filters are implemented the less Mailboxes will be available. Considering that
2593 * the Rx FIFO occupies the memory space originally reserved for MB0-5, RFFN should
2594 * be programmed with a value correponding to a number of filters not greater
2595 * than the number of available memory words which can be calculated as follows:
2596 * (SETUP_MB - 6) * 4 where SETUP_MB is the least between NUMBER_OF_MB and MAXMB.
2597 * The number of remaining Mailboxes available will be: (SETUP_MB - 8) - (RFFN *
2598 * 2) If the Number of Rx FIFO Filters programmed through RFFN exceeds the
2599 * SETUP_MB value (memory space available) the exceeding ones will not be functional.
2600 * RFFN[3:0] Number of Rx FIFO filters Message Buffers occupied by Rx FIFO and ID
2601 * Filter Table Remaining Available MailboxesThe number of the last remaining
2602 * available mailboxes is defined by the least value between the parameter
2603 * NUMBER_OF_MB minus 1 and the MCR[MAXMB] field. Rx FIFO ID Filter Table Elements Affected
2604 * by Rx Individual MasksIf Rx Individual Mask Registers are not enabled then
2605 * all Rx FIFO filters are affected by the Rx FIFO Global Mask. Rx FIFO ID Filter
2606 * Table Elements Affected by Rx FIFO Global Mask #rxfgmask-note 0x0 8 MB 0-7 MB
2607 * 8-63 Elements 0-7 none 0x1 16 MB 0-9 MB 10-63 Elements 0-9 Elements 10-15 0x2
2608 * 24 MB 0-11 MB 12-63 Elements 0-11 Elements 12-23 0x3 32 MB 0-13 MB 14-63
2609 * Elements 0-13 Elements 14-31 0x4 40 MB 0-15 MB 16-63 Elements 0-15 Elements 16-39
2610 * 0x5 48 MB 0-17 MB 18-63 Elements 0-17 Elements 18-47 0x6 56 MB 0-19 MB 20-63
2611 * Elements 0-19 Elements 20-55 0x7 64 MB 0-21 MB 22-63 Elements 0-21 Elements 22-63
2612 * 0x8 72 MB 0-23 MB 24-63 Elements 0-23 Elements 24-71 0x9 80 MB 0-25 MB 26-63
2613 * Elements 0-25 Elements 26-79 0xA 88 MB 0-27 MB 28-63 Elements 0-27 Elements
2614 * 28-87 0xB 96 MB 0-29 MB 30-63 Elements 0-29 Elements 30-95 0xC 104 MB 0-31 MB
2615 * 32-63 Elements 0-31 Elements 32-103 0xD 112 MB 0-33 MB 34-63 Elements 0-31
2616 * Elements 32-111 0xE 120 MB 0-35 MB 36-63 Elements 0-31 Elements 32-119 0xF 128 MB
2617 * 0-37 MB 38-63 Elements 0-31 Elements 32-127
2620 #define BP_CAN_CTRL2_RFFN (24U) /*!< Bit position for CAN_CTRL2_RFFN. */
2621 #define BM_CAN_CTRL2_RFFN (0x0F000000U) /*!< Bit mask for CAN_CTRL2_RFFN. */
2622 #define BS_CAN_CTRL2_RFFN (4U) /*!< Bit field size in bits for CAN_CTRL2_RFFN. */
2624 /*! @brief Read current value of the CAN_CTRL2_RFFN field. */
2625 #define BR_CAN_CTRL2_RFFN(x) (HW_CAN_CTRL2(x).B.RFFN)
2627 /*! @brief Format value for bitfield CAN_CTRL2_RFFN. */
2628 #define BF_CAN_CTRL2_RFFN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_RFFN) & BM_CAN_CTRL2_RFFN)
2630 /*! @brief Set the RFFN field to a new value. */
2631 #define BW_CAN_CTRL2_RFFN(x, v) (HW_CAN_CTRL2_WR(x, (HW_CAN_CTRL2_RD(x) & ~BM_CAN_CTRL2_RFFN) | BF_CAN_CTRL2_RFFN(v)))
2635 * @name Register CAN_CTRL2, field WRMFRZ[28] (RW)
2637 * Enable unrestricted write access to FlexCAN memory in Freeze mode. This bit
2638 * can only be written in Freeze mode and has no effect out of Freeze mode.
2641 * - 0 - Maintain the write access restrictions.
2642 * - 1 - Enable unrestricted write access to FlexCAN memory.
2645 #define BP_CAN_CTRL2_WRMFRZ (28U) /*!< Bit position for CAN_CTRL2_WRMFRZ. */
2646 #define BM_CAN_CTRL2_WRMFRZ (0x10000000U) /*!< Bit mask for CAN_CTRL2_WRMFRZ. */
2647 #define BS_CAN_CTRL2_WRMFRZ (1U) /*!< Bit field size in bits for CAN_CTRL2_WRMFRZ. */
2649 /*! @brief Read current value of the CAN_CTRL2_WRMFRZ field. */
2650 #define BR_CAN_CTRL2_WRMFRZ(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_WRMFRZ))
2652 /*! @brief Format value for bitfield CAN_CTRL2_WRMFRZ. */
2653 #define BF_CAN_CTRL2_WRMFRZ(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_WRMFRZ) & BM_CAN_CTRL2_WRMFRZ)
2655 /*! @brief Set the WRMFRZ field to a new value. */
2656 #define BW_CAN_CTRL2_WRMFRZ(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_WRMFRZ) = (v))
2659 /*******************************************************************************
2660 * HW_CAN_ESR2 - Error and Status 2 register
2661 ******************************************************************************/
2664 * @brief HW_CAN_ESR2 - Error and Status 2 register (RO)
2666 * Reset value: 0x00000000U
2668 * This register reflects various interrupt flags and some general status.
2670 typedef union _hw_can_esr2
2673 struct _hw_can_esr2_bitfields
2675 uint32_t RESERVED0
: 13; /*!< [12:0] */
2676 uint32_t IMB
: 1; /*!< [13] Inactive Mailbox */
2677 uint32_t VPS
: 1; /*!< [14] Valid Priority Status */
2678 uint32_t RESERVED1
: 1; /*!< [15] */
2679 uint32_t LPTM
: 7; /*!< [22:16] Lowest Priority Tx Mailbox */
2680 uint32_t RESERVED2
: 9; /*!< [31:23] */
2685 * @name Constants and macros for entire CAN_ESR2 register
2688 #define HW_CAN_ESR2_ADDR(x) ((x) + 0x38U)
2690 #define HW_CAN_ESR2(x) (*(__I hw_can_esr2_t *) HW_CAN_ESR2_ADDR(x))
2691 #define HW_CAN_ESR2_RD(x) (HW_CAN_ESR2(x).U)
2695 * Constants & macros for individual CAN_ESR2 bitfields
2699 * @name Register CAN_ESR2, field IMB[13] (RO)
2701 * If ESR2[VPS] is asserted, this bit indicates whether there is any inactive
2702 * Mailbox (CODE field is either 0b1000 or 0b0000). This bit is asserted in the
2703 * following cases: During arbitration, if an LPTM is found and it is inactive. If
2704 * IMB is not asserted and a frame is transmitted successfully. This bit is
2705 * cleared in all start of arbitration (see Section "Arbitration process"). LPTM
2706 * mechanism have the following behavior: if an MB is successfully transmitted and
2707 * ESR2[IMB]=0 (no inactive Mailbox), then ESR2[VPS] and ESR2[IMB] are asserted and
2708 * the index related to the MB just transmitted is loaded into ESR2[LPTM].
2711 * - 0 - If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox.
2712 * - 1 - If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM
2713 * content is the number of the first one.
2716 #define BP_CAN_ESR2_IMB (13U) /*!< Bit position for CAN_ESR2_IMB. */
2717 #define BM_CAN_ESR2_IMB (0x00002000U) /*!< Bit mask for CAN_ESR2_IMB. */
2718 #define BS_CAN_ESR2_IMB (1U) /*!< Bit field size in bits for CAN_ESR2_IMB. */
2720 /*! @brief Read current value of the CAN_ESR2_IMB field. */
2721 #define BR_CAN_ESR2_IMB(x) (BITBAND_ACCESS32(HW_CAN_ESR2_ADDR(x), BP_CAN_ESR2_IMB))
2725 * @name Register CAN_ESR2, field VPS[14] (RO)
2727 * This bit indicates whether IMB and LPTM contents are currently valid or not.
2728 * VPS is asserted upon every complete Tx arbitration process unless the CPU
2729 * writes to Control and Status word of a Mailbox that has already been scanned, that
2730 * is, it is behind Tx Arbitration Pointer, during the Tx arbitration process.
2731 * If there is no inactive Mailbox and only one Tx Mailbox that is being
2732 * transmitted then VPS is not asserted. VPS is negated upon the start of every Tx
2733 * arbitration process or upon a write to Control and Status word of any Mailbox.
2734 * ESR2[VPS] is not affected by any CPU write into Control Status (C/S) of a MB that is
2735 * blocked by abort mechanism. When MCR[AEN] is asserted, the abort code write
2736 * in C/S of a MB that is being transmitted (pending abort), or any write attempt
2737 * into a Tx MB with IFLAG set is blocked.
2740 * - 0 - Contents of IMB and LPTM are invalid.
2741 * - 1 - Contents of IMB and LPTM are valid.
2744 #define BP_CAN_ESR2_VPS (14U) /*!< Bit position for CAN_ESR2_VPS. */
2745 #define BM_CAN_ESR2_VPS (0x00004000U) /*!< Bit mask for CAN_ESR2_VPS. */
2746 #define BS_CAN_ESR2_VPS (1U) /*!< Bit field size in bits for CAN_ESR2_VPS. */
2748 /*! @brief Read current value of the CAN_ESR2_VPS field. */
2749 #define BR_CAN_ESR2_VPS(x) (BITBAND_ACCESS32(HW_CAN_ESR2_ADDR(x), BP_CAN_ESR2_VPS))
2753 * @name Register CAN_ESR2, field LPTM[22:16] (RO)
2755 * If ESR2[VPS] is asserted, this field indicates the lowest number inactive
2756 * Mailbox (see the IMB bit description). If there is no inactive Mailbox then the
2757 * Mailbox indicated depends on CTRL1[LBUF] bit value. If CTRL1[LBUF] bit is
2758 * negated then the Mailbox indicated is the one that has the greatest arbitration
2759 * value (see the "Highest priority Mailbox first" section). If CTRL1[LBUF] bit is
2760 * asserted then the Mailbox indicated is the highest number active Tx Mailbox. If
2761 * a Tx Mailbox is being transmitted it is not considered in LPTM calculation.
2762 * If ESR2[IMB] is not asserted and a frame is transmitted successfully, LPTM is
2763 * updated with its Mailbox number.
2766 #define BP_CAN_ESR2_LPTM (16U) /*!< Bit position for CAN_ESR2_LPTM. */
2767 #define BM_CAN_ESR2_LPTM (0x007F0000U) /*!< Bit mask for CAN_ESR2_LPTM. */
2768 #define BS_CAN_ESR2_LPTM (7U) /*!< Bit field size in bits for CAN_ESR2_LPTM. */
2770 /*! @brief Read current value of the CAN_ESR2_LPTM field. */
2771 #define BR_CAN_ESR2_LPTM(x) (HW_CAN_ESR2(x).B.LPTM)
2774 /*******************************************************************************
2775 * HW_CAN_CRCR - CRC Register
2776 ******************************************************************************/
2779 * @brief HW_CAN_CRCR - CRC Register (RO)
2781 * Reset value: 0x00000000U
2783 * This register provides information about the CRC of transmitted messages.
2785 typedef union _hw_can_crcr
2788 struct _hw_can_crcr_bitfields
2790 uint32_t TXCRC
: 15; /*!< [14:0] CRC Transmitted */
2791 uint32_t RESERVED0
: 1; /*!< [15] */
2792 uint32_t MBCRC
: 7; /*!< [22:16] CRC Mailbox */
2793 uint32_t RESERVED1
: 9; /*!< [31:23] */
2798 * @name Constants and macros for entire CAN_CRCR register
2801 #define HW_CAN_CRCR_ADDR(x) ((x) + 0x44U)
2803 #define HW_CAN_CRCR(x) (*(__I hw_can_crcr_t *) HW_CAN_CRCR_ADDR(x))
2804 #define HW_CAN_CRCR_RD(x) (HW_CAN_CRCR(x).U)
2808 * Constants & macros for individual CAN_CRCR bitfields
2812 * @name Register CAN_CRCR, field TXCRC[14:0] (RO)
2814 * This field indicates the CRC value of the last message transmitted. This
2815 * field is updated at the same time the Tx Interrupt Flag is asserted.
2818 #define BP_CAN_CRCR_TXCRC (0U) /*!< Bit position for CAN_CRCR_TXCRC. */
2819 #define BM_CAN_CRCR_TXCRC (0x00007FFFU) /*!< Bit mask for CAN_CRCR_TXCRC. */
2820 #define BS_CAN_CRCR_TXCRC (15U) /*!< Bit field size in bits for CAN_CRCR_TXCRC. */
2822 /*! @brief Read current value of the CAN_CRCR_TXCRC field. */
2823 #define BR_CAN_CRCR_TXCRC(x) (HW_CAN_CRCR(x).B.TXCRC)
2827 * @name Register CAN_CRCR, field MBCRC[22:16] (RO)
2829 * This field indicates the number of the Mailbox corresponding to the value in
2833 #define BP_CAN_CRCR_MBCRC (16U) /*!< Bit position for CAN_CRCR_MBCRC. */
2834 #define BM_CAN_CRCR_MBCRC (0x007F0000U) /*!< Bit mask for CAN_CRCR_MBCRC. */
2835 #define BS_CAN_CRCR_MBCRC (7U) /*!< Bit field size in bits for CAN_CRCR_MBCRC. */
2837 /*! @brief Read current value of the CAN_CRCR_MBCRC field. */
2838 #define BR_CAN_CRCR_MBCRC(x) (HW_CAN_CRCR(x).B.MBCRC)
2841 /*******************************************************************************
2842 * HW_CAN_RXFGMASK - Rx FIFO Global Mask register
2843 ******************************************************************************/
2846 * @brief HW_CAN_RXFGMASK - Rx FIFO Global Mask register (RW)
2848 * Reset value: 0xFFFFFFFFU
2850 * This register is located in RAM. If Rx FIFO is enabled RXFGMASK is used to
2851 * mask the Rx FIFO ID Filter Table elements that do not have a corresponding RXIMR
2852 * according to CTRL2[RFFN] field setting. This register can only be written in
2853 * Freeze mode as it is blocked by hardware in other modes.
2855 typedef union _hw_can_rxfgmask
2858 struct _hw_can_rxfgmask_bitfields
2860 uint32_t FGM
: 32; /*!< [31:0] Rx FIFO Global Mask Bits */
2862 } hw_can_rxfgmask_t
;
2865 * @name Constants and macros for entire CAN_RXFGMASK register
2868 #define HW_CAN_RXFGMASK_ADDR(x) ((x) + 0x48U)
2870 #define HW_CAN_RXFGMASK(x) (*(__IO hw_can_rxfgmask_t *) HW_CAN_RXFGMASK_ADDR(x))
2871 #define HW_CAN_RXFGMASK_RD(x) (HW_CAN_RXFGMASK(x).U)
2872 #define HW_CAN_RXFGMASK_WR(x, v) (HW_CAN_RXFGMASK(x).U = (v))
2873 #define HW_CAN_RXFGMASK_SET(x, v) (HW_CAN_RXFGMASK_WR(x, HW_CAN_RXFGMASK_RD(x) | (v)))
2874 #define HW_CAN_RXFGMASK_CLR(x, v) (HW_CAN_RXFGMASK_WR(x, HW_CAN_RXFGMASK_RD(x) & ~(v)))
2875 #define HW_CAN_RXFGMASK_TOG(x, v) (HW_CAN_RXFGMASK_WR(x, HW_CAN_RXFGMASK_RD(x) ^ (v)))
2879 * Constants & macros for individual CAN_RXFGMASK bitfields
2883 * @name Register CAN_RXFGMASK, field FGM[31:0] (RW)
2885 * These bits mask the ID Filter Table elements bits in a perfect alignment. The
2886 * following table shows how the FGM bits correspond to each IDAF field. Rx FIFO
2887 * ID Filter Table Elements Format (MCR[IDAM]) Identifier Acceptance Filter
2888 * Fields RTR IDE RXIDA RXIDB If MCR[IDAM] field is equivalent to the format B only
2889 * the fourteen most significant bits of the Identifier of the incoming frame are
2890 * compared with the Rx FIFO filter. RXIDC If MCR[IDAM] field is equivalent to
2891 * the format C only the eight most significant bits of the Identifier of the
2892 * incoming frame are compared with the Rx FIFO filter. Reserved A FGM[31] FGM[30]
2893 * FGM[29:1] - - FGM[0] B FGM[31], FGM[15] FGM[30], FGM[14] - FGM[29:16], FGM[13:0]
2894 * - C - - - FGM[31:24], FGM[23:16], FGM[15:8], FGM[7:0]
2897 * - 0 - The corresponding bit in the filter is "don't care."
2898 * - 1 - The corresponding bit in the filter is checked.
2901 #define BP_CAN_RXFGMASK_FGM (0U) /*!< Bit position for CAN_RXFGMASK_FGM. */
2902 #define BM_CAN_RXFGMASK_FGM (0xFFFFFFFFU) /*!< Bit mask for CAN_RXFGMASK_FGM. */
2903 #define BS_CAN_RXFGMASK_FGM (32U) /*!< Bit field size in bits for CAN_RXFGMASK_FGM. */
2905 /*! @brief Read current value of the CAN_RXFGMASK_FGM field. */
2906 #define BR_CAN_RXFGMASK_FGM(x) (HW_CAN_RXFGMASK(x).U)
2908 /*! @brief Format value for bitfield CAN_RXFGMASK_FGM. */
2909 #define BF_CAN_RXFGMASK_FGM(v) ((uint32_t)((uint32_t)(v) << BP_CAN_RXFGMASK_FGM) & BM_CAN_RXFGMASK_FGM)
2911 /*! @brief Set the FGM field to a new value. */
2912 #define BW_CAN_RXFGMASK_FGM(x, v) (HW_CAN_RXFGMASK_WR(x, v))
2915 /*******************************************************************************
2916 * HW_CAN_RXFIR - Rx FIFO Information Register
2917 ******************************************************************************/
2920 * @brief HW_CAN_RXFIR - Rx FIFO Information Register (RO)
2922 * Reset value: 0x00000000U
2924 * RXFIR provides information on Rx FIFO. This register is the port through
2925 * which the CPU accesses the output of the RXFIR FIFO located in RAM. The RXFIR FIFO
2926 * is written by the FlexCAN whenever a new message is moved into the Rx FIFO as
2927 * well as its output is updated whenever the output of the Rx FIFO is updated
2928 * with the next message. See Section "Rx FIFO" for instructions on reading this
2931 typedef union _hw_can_rxfir
2934 struct _hw_can_rxfir_bitfields
2936 uint32_t IDHIT
: 9; /*!< [8:0] Identifier Acceptance Filter Hit
2938 uint32_t RESERVED0
: 23; /*!< [31:9] */
2943 * @name Constants and macros for entire CAN_RXFIR register
2946 #define HW_CAN_RXFIR_ADDR(x) ((x) + 0x4CU)
2948 #define HW_CAN_RXFIR(x) (*(__I hw_can_rxfir_t *) HW_CAN_RXFIR_ADDR(x))
2949 #define HW_CAN_RXFIR_RD(x) (HW_CAN_RXFIR(x).U)
2953 * Constants & macros for individual CAN_RXFIR bitfields
2957 * @name Register CAN_RXFIR, field IDHIT[8:0] (RO)
2959 * This field indicates which Identifier Acceptance Filter was hit by the
2960 * received message that is in the output of the Rx FIFO. If multiple filters match the
2961 * incoming message ID then the first matching IDAF found (lowest number) by the
2962 * matching process is indicated. This field is valid only while the
2963 * IFLAG[BUF5I] is asserted.
2966 #define BP_CAN_RXFIR_IDHIT (0U) /*!< Bit position for CAN_RXFIR_IDHIT. */
2967 #define BM_CAN_RXFIR_IDHIT (0x000001FFU) /*!< Bit mask for CAN_RXFIR_IDHIT. */
2968 #define BS_CAN_RXFIR_IDHIT (9U) /*!< Bit field size in bits for CAN_RXFIR_IDHIT. */
2970 /*! @brief Read current value of the CAN_RXFIR_IDHIT field. */
2971 #define BR_CAN_RXFIR_IDHIT(x) (HW_CAN_RXFIR(x).B.IDHIT)
2974 /*******************************************************************************
2975 * HW_CAN_CSn - Message Buffer 0 CS Register
2976 ******************************************************************************/
2979 * @brief HW_CAN_CSn - Message Buffer 0 CS Register (RW)
2981 * Reset value: 0x00000000U
2983 typedef union _hw_can_csn
2986 struct _hw_can_csn_bitfields
2988 uint32_t TIME_STAMP
: 16; /*!< [15:0] Free-Running Counter Time
2989 * stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx
2990 * and Rx frames at the time when the beginning of the Identifier field
2991 * appears on the CAN bus. */
2992 uint32_t DLC
: 4; /*!< [19:16] Length of the data to be
2993 * stored/transmitted. */
2994 uint32_t RTR
: 1; /*!< [20] Remote Transmission Request. One/zero for
2995 * remote/data frame. */
2996 uint32_t IDE
: 1; /*!< [21] ID Extended. One/zero for
2997 * extended/standard format frame. */
2998 uint32_t SRR
: 1; /*!< [22] Substitute Remote Request. Contains a
2999 * fixed recessive bit. */
3000 uint32_t RESERVED0
: 1; /*!< [23] Reserved */
3001 uint32_t CODE
: 4; /*!< [27:24] Reserved */
3002 uint32_t RESERVED1
: 4; /*!< [31:28] Reserved */
3007 * @name Constants and macros for entire CAN_CSn register
3010 #define HW_CAN_CSn_COUNT (16U)
3012 #define HW_CAN_CSn_ADDR(x, n) ((x) + 0x80U + (0x10U * (n)))
3014 #define HW_CAN_CSn(x, n) (*(__IO hw_can_csn_t *) HW_CAN_CSn_ADDR(x, n))
3015 #define HW_CAN_CSn_RD(x, n) (HW_CAN_CSn(x, n).U)
3016 #define HW_CAN_CSn_WR(x, n, v) (HW_CAN_CSn(x, n).U = (v))
3017 #define HW_CAN_CSn_SET(x, n, v) (HW_CAN_CSn_WR(x, n, HW_CAN_CSn_RD(x, n) | (v)))
3018 #define HW_CAN_CSn_CLR(x, n, v) (HW_CAN_CSn_WR(x, n, HW_CAN_CSn_RD(x, n) & ~(v)))
3019 #define HW_CAN_CSn_TOG(x, n, v) (HW_CAN_CSn_WR(x, n, HW_CAN_CSn_RD(x, n) ^ (v)))
3023 * Constants & macros for individual CAN_CSn bitfields
3027 * @name Register CAN_CSn, field TIME_STAMP[15:0] (RW)
3030 #define BP_CAN_CSn_TIME_STAMP (0U) /*!< Bit position for CAN_CSn_TIME_STAMP. */
3031 #define BM_CAN_CSn_TIME_STAMP (0x0000FFFFU) /*!< Bit mask for CAN_CSn_TIME_STAMP. */
3032 #define BS_CAN_CSn_TIME_STAMP (16U) /*!< Bit field size in bits for CAN_CSn_TIME_STAMP. */
3034 /*! @brief Read current value of the CAN_CSn_TIME_STAMP field. */
3035 #define BR_CAN_CSn_TIME_STAMP(x, n) (HW_CAN_CSn(x, n).B.TIME_STAMP)
3037 /*! @brief Format value for bitfield CAN_CSn_TIME_STAMP. */
3038 #define BF_CAN_CSn_TIME_STAMP(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_TIME_STAMP) & BM_CAN_CSn_TIME_STAMP)
3040 /*! @brief Set the TIME_STAMP field to a new value. */
3041 #define BW_CAN_CSn_TIME_STAMP(x, n, v) (HW_CAN_CSn_WR(x, n, (HW_CAN_CSn_RD(x, n) & ~BM_CAN_CSn_TIME_STAMP) | BF_CAN_CSn_TIME_STAMP(v)))
3045 * @name Register CAN_CSn, field DLC[19:16] (RW)
3048 #define BP_CAN_CSn_DLC (16U) /*!< Bit position for CAN_CSn_DLC. */
3049 #define BM_CAN_CSn_DLC (0x000F0000U) /*!< Bit mask for CAN_CSn_DLC. */
3050 #define BS_CAN_CSn_DLC (4U) /*!< Bit field size in bits for CAN_CSn_DLC. */
3052 /*! @brief Read current value of the CAN_CSn_DLC field. */
3053 #define BR_CAN_CSn_DLC(x, n) (HW_CAN_CSn(x, n).B.DLC)
3055 /*! @brief Format value for bitfield CAN_CSn_DLC. */
3056 #define BF_CAN_CSn_DLC(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_DLC) & BM_CAN_CSn_DLC)
3058 /*! @brief Set the DLC field to a new value. */
3059 #define BW_CAN_CSn_DLC(x, n, v) (HW_CAN_CSn_WR(x, n, (HW_CAN_CSn_RD(x, n) & ~BM_CAN_CSn_DLC) | BF_CAN_CSn_DLC(v)))
3063 * @name Register CAN_CSn, field RTR[20] (RW)
3066 #define BP_CAN_CSn_RTR (20U) /*!< Bit position for CAN_CSn_RTR. */
3067 #define BM_CAN_CSn_RTR (0x00100000U) /*!< Bit mask for CAN_CSn_RTR. */
3068 #define BS_CAN_CSn_RTR (1U) /*!< Bit field size in bits for CAN_CSn_RTR. */
3070 /*! @brief Read current value of the CAN_CSn_RTR field. */
3071 #define BR_CAN_CSn_RTR(x, n) (BITBAND_ACCESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_RTR))
3073 /*! @brief Format value for bitfield CAN_CSn_RTR. */
3074 #define BF_CAN_CSn_RTR(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_RTR) & BM_CAN_CSn_RTR)
3076 /*! @brief Set the RTR field to a new value. */
3077 #define BW_CAN_CSn_RTR(x, n, v) (BITBAND_ACCESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_RTR) = (v))
3081 * @name Register CAN_CSn, field IDE[21] (RW)
3084 #define BP_CAN_CSn_IDE (21U) /*!< Bit position for CAN_CSn_IDE. */
3085 #define BM_CAN_CSn_IDE (0x00200000U) /*!< Bit mask for CAN_CSn_IDE. */
3086 #define BS_CAN_CSn_IDE (1U) /*!< Bit field size in bits for CAN_CSn_IDE. */
3088 /*! @brief Read current value of the CAN_CSn_IDE field. */
3089 #define BR_CAN_CSn_IDE(x, n) (BITBAND_ACCESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_IDE))
3091 /*! @brief Format value for bitfield CAN_CSn_IDE. */
3092 #define BF_CAN_CSn_IDE(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_IDE) & BM_CAN_CSn_IDE)
3094 /*! @brief Set the IDE field to a new value. */
3095 #define BW_CAN_CSn_IDE(x, n, v) (BITBAND_ACCESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_IDE) = (v))
3099 * @name Register CAN_CSn, field SRR[22] (RW)
3102 #define BP_CAN_CSn_SRR (22U) /*!< Bit position for CAN_CSn_SRR. */
3103 #define BM_CAN_CSn_SRR (0x00400000U) /*!< Bit mask for CAN_CSn_SRR. */
3104 #define BS_CAN_CSn_SRR (1U) /*!< Bit field size in bits for CAN_CSn_SRR. */
3106 /*! @brief Read current value of the CAN_CSn_SRR field. */
3107 #define BR_CAN_CSn_SRR(x, n) (BITBAND_ACCESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_SRR))
3109 /*! @brief Format value for bitfield CAN_CSn_SRR. */
3110 #define BF_CAN_CSn_SRR(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_SRR) & BM_CAN_CSn_SRR)
3112 /*! @brief Set the SRR field to a new value. */
3113 #define BW_CAN_CSn_SRR(x, n, v) (BITBAND_ACCESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_SRR) = (v))
3117 * @name Register CAN_CSn, field CODE[27:24] (RW)
3120 #define BP_CAN_CSn_CODE (24U) /*!< Bit position for CAN_CSn_CODE. */
3121 #define BM_CAN_CSn_CODE (0x0F000000U) /*!< Bit mask for CAN_CSn_CODE. */
3122 #define BS_CAN_CSn_CODE (4U) /*!< Bit field size in bits for CAN_CSn_CODE. */
3124 /*! @brief Read current value of the CAN_CSn_CODE field. */
3125 #define BR_CAN_CSn_CODE(x, n) (HW_CAN_CSn(x, n).B.CODE)
3127 /*! @brief Format value for bitfield CAN_CSn_CODE. */
3128 #define BF_CAN_CSn_CODE(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_CODE) & BM_CAN_CSn_CODE)
3130 /*! @brief Set the CODE field to a new value. */
3131 #define BW_CAN_CSn_CODE(x, n, v) (HW_CAN_CSn_WR(x, n, (HW_CAN_CSn_RD(x, n) & ~BM_CAN_CSn_CODE) | BF_CAN_CSn_CODE(v)))
3133 /*******************************************************************************
3134 * HW_CAN_IDn - Message Buffer 0 ID Register
3135 ******************************************************************************/
3138 * @brief HW_CAN_IDn - Message Buffer 0 ID Register (RW)
3140 * Reset value: 0x00000000U
3142 typedef union _hw_can_idn
3145 struct _hw_can_idn_bitfields
3147 uint32_t EXT
: 18; /*!< [17:0] Contains extended (LOW word)
3148 * identifier of message buffer. */
3149 uint32_t STD
: 11; /*!< [28:18] Contains standard/extended (HIGH
3150 * word) identifier of message buffer. */
3151 uint32_t PRIO
: 3; /*!< [31:29] Local priority. This 3-bit fieldis
3152 * only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx
3153 * buffers. These bits are not transmitted. They are appended to the regular
3154 * ID to define the transmission priority. */
3159 * @name Constants and macros for entire CAN_IDn register
3162 #define HW_CAN_IDn_COUNT (16U)
3164 #define HW_CAN_IDn_ADDR(x, n) ((x) + 0x84U + (0x10U * (n)))
3166 #define HW_CAN_IDn(x, n) (*(__IO hw_can_idn_t *) HW_CAN_IDn_ADDR(x, n))
3167 #define HW_CAN_IDn_RD(x, n) (HW_CAN_IDn(x, n).U)
3168 #define HW_CAN_IDn_WR(x, n, v) (HW_CAN_IDn(x, n).U = (v))
3169 #define HW_CAN_IDn_SET(x, n, v) (HW_CAN_IDn_WR(x, n, HW_CAN_IDn_RD(x, n) | (v)))
3170 #define HW_CAN_IDn_CLR(x, n, v) (HW_CAN_IDn_WR(x, n, HW_CAN_IDn_RD(x, n) & ~(v)))
3171 #define HW_CAN_IDn_TOG(x, n, v) (HW_CAN_IDn_WR(x, n, HW_CAN_IDn_RD(x, n) ^ (v)))
3175 * Constants & macros for individual CAN_IDn bitfields
3179 * @name Register CAN_IDn, field EXT[17:0] (RW)
3182 #define BP_CAN_IDn_EXT (0U) /*!< Bit position for CAN_IDn_EXT. */
3183 #define BM_CAN_IDn_EXT (0x0003FFFFU) /*!< Bit mask for CAN_IDn_EXT. */
3184 #define BS_CAN_IDn_EXT (18U) /*!< Bit field size in bits for CAN_IDn_EXT. */
3186 /*! @brief Read current value of the CAN_IDn_EXT field. */
3187 #define BR_CAN_IDn_EXT(x, n) (HW_CAN_IDn(x, n).B.EXT)
3189 /*! @brief Format value for bitfield CAN_IDn_EXT. */
3190 #define BF_CAN_IDn_EXT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IDn_EXT) & BM_CAN_IDn_EXT)
3192 /*! @brief Set the EXT field to a new value. */
3193 #define BW_CAN_IDn_EXT(x, n, v) (HW_CAN_IDn_WR(x, n, (HW_CAN_IDn_RD(x, n) & ~BM_CAN_IDn_EXT) | BF_CAN_IDn_EXT(v)))
3197 * @name Register CAN_IDn, field STD[28:18] (RW)
3200 #define BP_CAN_IDn_STD (18U) /*!< Bit position for CAN_IDn_STD. */
3201 #define BM_CAN_IDn_STD (0x1FFC0000U) /*!< Bit mask for CAN_IDn_STD. */
3202 #define BS_CAN_IDn_STD (11U) /*!< Bit field size in bits for CAN_IDn_STD. */
3204 /*! @brief Read current value of the CAN_IDn_STD field. */
3205 #define BR_CAN_IDn_STD(x, n) (HW_CAN_IDn(x, n).B.STD)
3207 /*! @brief Format value for bitfield CAN_IDn_STD. */
3208 #define BF_CAN_IDn_STD(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IDn_STD) & BM_CAN_IDn_STD)
3210 /*! @brief Set the STD field to a new value. */
3211 #define BW_CAN_IDn_STD(x, n, v) (HW_CAN_IDn_WR(x, n, (HW_CAN_IDn_RD(x, n) & ~BM_CAN_IDn_STD) | BF_CAN_IDn_STD(v)))
3215 * @name Register CAN_IDn, field PRIO[31:29] (RW)
3218 #define BP_CAN_IDn_PRIO (29U) /*!< Bit position for CAN_IDn_PRIO. */
3219 #define BM_CAN_IDn_PRIO (0xE0000000U) /*!< Bit mask for CAN_IDn_PRIO. */
3220 #define BS_CAN_IDn_PRIO (3U) /*!< Bit field size in bits for CAN_IDn_PRIO. */
3222 /*! @brief Read current value of the CAN_IDn_PRIO field. */
3223 #define BR_CAN_IDn_PRIO(x, n) (HW_CAN_IDn(x, n).B.PRIO)
3225 /*! @brief Format value for bitfield CAN_IDn_PRIO. */
3226 #define BF_CAN_IDn_PRIO(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IDn_PRIO) & BM_CAN_IDn_PRIO)
3228 /*! @brief Set the PRIO field to a new value. */
3229 #define BW_CAN_IDn_PRIO(x, n, v) (HW_CAN_IDn_WR(x, n, (HW_CAN_IDn_RD(x, n) & ~BM_CAN_IDn_PRIO) | BF_CAN_IDn_PRIO(v)))
3231 /*******************************************************************************
3232 * HW_CAN_WORD0n - Message Buffer 0 WORD0 Register
3233 ******************************************************************************/
3236 * @brief HW_CAN_WORD0n - Message Buffer 0 WORD0 Register (RW)
3238 * Reset value: 0x00000000U
3240 typedef union _hw_can_word0n
3243 struct _hw_can_word0n_bitfields
3245 uint32_t DATA_BYTE_3
: 8; /*!< [7:0] Data byte 3 of Rx/Tx frame. */
3246 uint32_t DATA_BYTE_2
: 8; /*!< [15:8] Data byte 2 of Rx/Tx frame. */
3247 uint32_t DATA_BYTE_1
: 8; /*!< [23:16] Data byte 1 of Rx/Tx frame. */
3248 uint32_t DATA_BYTE_0
: 8; /*!< [31:24] Data byte 0 of Rx/Tx frame. */
3253 * @name Constants and macros for entire CAN_WORD0n register
3256 #define HW_CAN_WORD0n_COUNT (16U)
3258 #define HW_CAN_WORD0n_ADDR(x, n) ((x) + 0x88U + (0x10U * (n)))
3260 #define HW_CAN_WORD0n(x, n) (*(__IO hw_can_word0n_t *) HW_CAN_WORD0n_ADDR(x, n))
3261 #define HW_CAN_WORD0n_RD(x, n) (HW_CAN_WORD0n(x, n).U)
3262 #define HW_CAN_WORD0n_WR(x, n, v) (HW_CAN_WORD0n(x, n).U = (v))
3263 #define HW_CAN_WORD0n_SET(x, n, v) (HW_CAN_WORD0n_WR(x, n, HW_CAN_WORD0n_RD(x, n) | (v)))
3264 #define HW_CAN_WORD0n_CLR(x, n, v) (HW_CAN_WORD0n_WR(x, n, HW_CAN_WORD0n_RD(x, n) & ~(v)))
3265 #define HW_CAN_WORD0n_TOG(x, n, v) (HW_CAN_WORD0n_WR(x, n, HW_CAN_WORD0n_RD(x, n) ^ (v)))
3269 * Constants & macros for individual CAN_WORD0n bitfields
3273 * @name Register CAN_WORD0n, field DATA_BYTE_3[7:0] (RW)
3276 #define BP_CAN_WORD0n_DATA_BYTE_3 (0U) /*!< Bit position for CAN_WORD0n_DATA_BYTE_3. */
3277 #define BM_CAN_WORD0n_DATA_BYTE_3 (0x000000FFU) /*!< Bit mask for CAN_WORD0n_DATA_BYTE_3. */
3278 #define BS_CAN_WORD0n_DATA_BYTE_3 (8U) /*!< Bit field size in bits for CAN_WORD0n_DATA_BYTE_3. */
3280 /*! @brief Read current value of the CAN_WORD0n_DATA_BYTE_3 field. */
3281 #define BR_CAN_WORD0n_DATA_BYTE_3(x, n) (HW_CAN_WORD0n(x, n).B.DATA_BYTE_3)
3283 /*! @brief Format value for bitfield CAN_WORD0n_DATA_BYTE_3. */
3284 #define BF_CAN_WORD0n_DATA_BYTE_3(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD0n_DATA_BYTE_3) & BM_CAN_WORD0n_DATA_BYTE_3)
3286 /*! @brief Set the DATA_BYTE_3 field to a new value. */
3287 #define BW_CAN_WORD0n_DATA_BYTE_3(x, n, v) (HW_CAN_WORD0n_WR(x, n, (HW_CAN_WORD0n_RD(x, n) & ~BM_CAN_WORD0n_DATA_BYTE_3) | BF_CAN_WORD0n_DATA_BYTE_3(v)))
3291 * @name Register CAN_WORD0n, field DATA_BYTE_2[15:8] (RW)
3294 #define BP_CAN_WORD0n_DATA_BYTE_2 (8U) /*!< Bit position for CAN_WORD0n_DATA_BYTE_2. */
3295 #define BM_CAN_WORD0n_DATA_BYTE_2 (0x0000FF00U) /*!< Bit mask for CAN_WORD0n_DATA_BYTE_2. */
3296 #define BS_CAN_WORD0n_DATA_BYTE_2 (8U) /*!< Bit field size in bits for CAN_WORD0n_DATA_BYTE_2. */
3298 /*! @brief Read current value of the CAN_WORD0n_DATA_BYTE_2 field. */
3299 #define BR_CAN_WORD0n_DATA_BYTE_2(x, n) (HW_CAN_WORD0n(x, n).B.DATA_BYTE_2)
3301 /*! @brief Format value for bitfield CAN_WORD0n_DATA_BYTE_2. */
3302 #define BF_CAN_WORD0n_DATA_BYTE_2(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD0n_DATA_BYTE_2) & BM_CAN_WORD0n_DATA_BYTE_2)
3304 /*! @brief Set the DATA_BYTE_2 field to a new value. */
3305 #define BW_CAN_WORD0n_DATA_BYTE_2(x, n, v) (HW_CAN_WORD0n_WR(x, n, (HW_CAN_WORD0n_RD(x, n) & ~BM_CAN_WORD0n_DATA_BYTE_2) | BF_CAN_WORD0n_DATA_BYTE_2(v)))
3309 * @name Register CAN_WORD0n, field DATA_BYTE_1[23:16] (RW)
3312 #define BP_CAN_WORD0n_DATA_BYTE_1 (16U) /*!< Bit position for CAN_WORD0n_DATA_BYTE_1. */
3313 #define BM_CAN_WORD0n_DATA_BYTE_1 (0x00FF0000U) /*!< Bit mask for CAN_WORD0n_DATA_BYTE_1. */
3314 #define BS_CAN_WORD0n_DATA_BYTE_1 (8U) /*!< Bit field size in bits for CAN_WORD0n_DATA_BYTE_1. */
3316 /*! @brief Read current value of the CAN_WORD0n_DATA_BYTE_1 field. */
3317 #define BR_CAN_WORD0n_DATA_BYTE_1(x, n) (HW_CAN_WORD0n(x, n).B.DATA_BYTE_1)
3319 /*! @brief Format value for bitfield CAN_WORD0n_DATA_BYTE_1. */
3320 #define BF_CAN_WORD0n_DATA_BYTE_1(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD0n_DATA_BYTE_1) & BM_CAN_WORD0n_DATA_BYTE_1)
3322 /*! @brief Set the DATA_BYTE_1 field to a new value. */
3323 #define BW_CAN_WORD0n_DATA_BYTE_1(x, n, v) (HW_CAN_WORD0n_WR(x, n, (HW_CAN_WORD0n_RD(x, n) & ~BM_CAN_WORD0n_DATA_BYTE_1) | BF_CAN_WORD0n_DATA_BYTE_1(v)))
3327 * @name Register CAN_WORD0n, field DATA_BYTE_0[31:24] (RW)
3330 #define BP_CAN_WORD0n_DATA_BYTE_0 (24U) /*!< Bit position for CAN_WORD0n_DATA_BYTE_0. */
3331 #define BM_CAN_WORD0n_DATA_BYTE_0 (0xFF000000U) /*!< Bit mask for CAN_WORD0n_DATA_BYTE_0. */
3332 #define BS_CAN_WORD0n_DATA_BYTE_0 (8U) /*!< Bit field size in bits for CAN_WORD0n_DATA_BYTE_0. */
3334 /*! @brief Read current value of the CAN_WORD0n_DATA_BYTE_0 field. */
3335 #define BR_CAN_WORD0n_DATA_BYTE_0(x, n) (HW_CAN_WORD0n(x, n).B.DATA_BYTE_0)
3337 /*! @brief Format value for bitfield CAN_WORD0n_DATA_BYTE_0. */
3338 #define BF_CAN_WORD0n_DATA_BYTE_0(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD0n_DATA_BYTE_0) & BM_CAN_WORD0n_DATA_BYTE_0)
3340 /*! @brief Set the DATA_BYTE_0 field to a new value. */
3341 #define BW_CAN_WORD0n_DATA_BYTE_0(x, n, v) (HW_CAN_WORD0n_WR(x, n, (HW_CAN_WORD0n_RD(x, n) & ~BM_CAN_WORD0n_DATA_BYTE_0) | BF_CAN_WORD0n_DATA_BYTE_0(v)))
3343 /*******************************************************************************
3344 * HW_CAN_WORD1n - Message Buffer 0 WORD1 Register
3345 ******************************************************************************/
3348 * @brief HW_CAN_WORD1n - Message Buffer 0 WORD1 Register (RW)
3350 * Reset value: 0x00000000U
3352 typedef union _hw_can_word1n
3355 struct _hw_can_word1n_bitfields
3357 uint32_t DATA_BYTE_7
: 8; /*!< [7:0] Data byte 7 of Rx/Tx frame. */
3358 uint32_t DATA_BYTE_6
: 8; /*!< [15:8] Data byte 6 of Rx/Tx frame. */
3359 uint32_t DATA_BYTE_5
: 8; /*!< [23:16] Data byte 5 of Rx/Tx frame. */
3360 uint32_t DATA_BYTE_4
: 8; /*!< [31:24] Data byte 4 of Rx/Tx frame. */
3365 * @name Constants and macros for entire CAN_WORD1n register
3368 #define HW_CAN_WORD1n_COUNT (16U)
3370 #define HW_CAN_WORD1n_ADDR(x, n) ((x) + 0x8CU + (0x10U * (n)))
3372 #define HW_CAN_WORD1n(x, n) (*(__IO hw_can_word1n_t *) HW_CAN_WORD1n_ADDR(x, n))
3373 #define HW_CAN_WORD1n_RD(x, n) (HW_CAN_WORD1n(x, n).U)
3374 #define HW_CAN_WORD1n_WR(x, n, v) (HW_CAN_WORD1n(x, n).U = (v))
3375 #define HW_CAN_WORD1n_SET(x, n, v) (HW_CAN_WORD1n_WR(x, n, HW_CAN_WORD1n_RD(x, n) | (v)))
3376 #define HW_CAN_WORD1n_CLR(x, n, v) (HW_CAN_WORD1n_WR(x, n, HW_CAN_WORD1n_RD(x, n) & ~(v)))
3377 #define HW_CAN_WORD1n_TOG(x, n, v) (HW_CAN_WORD1n_WR(x, n, HW_CAN_WORD1n_RD(x, n) ^ (v)))
3381 * Constants & macros for individual CAN_WORD1n bitfields
3385 * @name Register CAN_WORD1n, field DATA_BYTE_7[7:0] (RW)
3388 #define BP_CAN_WORD1n_DATA_BYTE_7 (0U) /*!< Bit position for CAN_WORD1n_DATA_BYTE_7. */
3389 #define BM_CAN_WORD1n_DATA_BYTE_7 (0x000000FFU) /*!< Bit mask for CAN_WORD1n_DATA_BYTE_7. */
3390 #define BS_CAN_WORD1n_DATA_BYTE_7 (8U) /*!< Bit field size in bits for CAN_WORD1n_DATA_BYTE_7. */
3392 /*! @brief Read current value of the CAN_WORD1n_DATA_BYTE_7 field. */
3393 #define BR_CAN_WORD1n_DATA_BYTE_7(x, n) (HW_CAN_WORD1n(x, n).B.DATA_BYTE_7)
3395 /*! @brief Format value for bitfield CAN_WORD1n_DATA_BYTE_7. */
3396 #define BF_CAN_WORD1n_DATA_BYTE_7(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD1n_DATA_BYTE_7) & BM_CAN_WORD1n_DATA_BYTE_7)
3398 /*! @brief Set the DATA_BYTE_7 field to a new value. */
3399 #define BW_CAN_WORD1n_DATA_BYTE_7(x, n, v) (HW_CAN_WORD1n_WR(x, n, (HW_CAN_WORD1n_RD(x, n) & ~BM_CAN_WORD1n_DATA_BYTE_7) | BF_CAN_WORD1n_DATA_BYTE_7(v)))
3403 * @name Register CAN_WORD1n, field DATA_BYTE_6[15:8] (RW)
3406 #define BP_CAN_WORD1n_DATA_BYTE_6 (8U) /*!< Bit position for CAN_WORD1n_DATA_BYTE_6. */
3407 #define BM_CAN_WORD1n_DATA_BYTE_6 (0x0000FF00U) /*!< Bit mask for CAN_WORD1n_DATA_BYTE_6. */
3408 #define BS_CAN_WORD1n_DATA_BYTE_6 (8U) /*!< Bit field size in bits for CAN_WORD1n_DATA_BYTE_6. */
3410 /*! @brief Read current value of the CAN_WORD1n_DATA_BYTE_6 field. */
3411 #define BR_CAN_WORD1n_DATA_BYTE_6(x, n) (HW_CAN_WORD1n(x, n).B.DATA_BYTE_6)
3413 /*! @brief Format value for bitfield CAN_WORD1n_DATA_BYTE_6. */
3414 #define BF_CAN_WORD1n_DATA_BYTE_6(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD1n_DATA_BYTE_6) & BM_CAN_WORD1n_DATA_BYTE_6)
3416 /*! @brief Set the DATA_BYTE_6 field to a new value. */
3417 #define BW_CAN_WORD1n_DATA_BYTE_6(x, n, v) (HW_CAN_WORD1n_WR(x, n, (HW_CAN_WORD1n_RD(x, n) & ~BM_CAN_WORD1n_DATA_BYTE_6) | BF_CAN_WORD1n_DATA_BYTE_6(v)))
3421 * @name Register CAN_WORD1n, field DATA_BYTE_5[23:16] (RW)
3424 #define BP_CAN_WORD1n_DATA_BYTE_5 (16U) /*!< Bit position for CAN_WORD1n_DATA_BYTE_5. */
3425 #define BM_CAN_WORD1n_DATA_BYTE_5 (0x00FF0000U) /*!< Bit mask for CAN_WORD1n_DATA_BYTE_5. */
3426 #define BS_CAN_WORD1n_DATA_BYTE_5 (8U) /*!< Bit field size in bits for CAN_WORD1n_DATA_BYTE_5. */
3428 /*! @brief Read current value of the CAN_WORD1n_DATA_BYTE_5 field. */
3429 #define BR_CAN_WORD1n_DATA_BYTE_5(x, n) (HW_CAN_WORD1n(x, n).B.DATA_BYTE_5)
3431 /*! @brief Format value for bitfield CAN_WORD1n_DATA_BYTE_5. */
3432 #define BF_CAN_WORD1n_DATA_BYTE_5(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD1n_DATA_BYTE_5) & BM_CAN_WORD1n_DATA_BYTE_5)
3434 /*! @brief Set the DATA_BYTE_5 field to a new value. */
3435 #define BW_CAN_WORD1n_DATA_BYTE_5(x, n, v) (HW_CAN_WORD1n_WR(x, n, (HW_CAN_WORD1n_RD(x, n) & ~BM_CAN_WORD1n_DATA_BYTE_5) | BF_CAN_WORD1n_DATA_BYTE_5(v)))
3439 * @name Register CAN_WORD1n, field DATA_BYTE_4[31:24] (RW)
3442 #define BP_CAN_WORD1n_DATA_BYTE_4 (24U) /*!< Bit position for CAN_WORD1n_DATA_BYTE_4. */
3443 #define BM_CAN_WORD1n_DATA_BYTE_4 (0xFF000000U) /*!< Bit mask for CAN_WORD1n_DATA_BYTE_4. */
3444 #define BS_CAN_WORD1n_DATA_BYTE_4 (8U) /*!< Bit field size in bits for CAN_WORD1n_DATA_BYTE_4. */
3446 /*! @brief Read current value of the CAN_WORD1n_DATA_BYTE_4 field. */
3447 #define BR_CAN_WORD1n_DATA_BYTE_4(x, n) (HW_CAN_WORD1n(x, n).B.DATA_BYTE_4)
3449 /*! @brief Format value for bitfield CAN_WORD1n_DATA_BYTE_4. */
3450 #define BF_CAN_WORD1n_DATA_BYTE_4(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD1n_DATA_BYTE_4) & BM_CAN_WORD1n_DATA_BYTE_4)
3452 /*! @brief Set the DATA_BYTE_4 field to a new value. */
3453 #define BW_CAN_WORD1n_DATA_BYTE_4(x, n, v) (HW_CAN_WORD1n_WR(x, n, (HW_CAN_WORD1n_RD(x, n) & ~BM_CAN_WORD1n_DATA_BYTE_4) | BF_CAN_WORD1n_DATA_BYTE_4(v)))
3456 /*******************************************************************************
3457 * HW_CAN_RXIMRn - Rx Individual Mask Registers
3458 ******************************************************************************/
3461 * @brief HW_CAN_RXIMRn - Rx Individual Mask Registers (RW)
3463 * Reset value: 0x00000000U
3465 * These registers are located in RAM. RXIMR are used as acceptance masks for ID
3466 * filtering in Rx MBs and the Rx FIFO. If the Rx FIFO is not enabled, one mask
3467 * register is provided for each available Mailbox, providing ID masking
3468 * capability on a per Mailbox basis. When the Rx FIFO is enabled (MCR[RFEN] bit is
3469 * asserted), up to 32 Rx Individual Mask Registers can apply to the Rx FIFO ID Filter
3470 * Table elements on a one-to-one correspondence depending on the setting of
3471 * CTRL2[RFFN]. RXIMR can only be written by the CPU while the module is in Freeze
3472 * mode; otherwise, they are blocked by hardware. The Individual Rx Mask Registers
3473 * are not affected by reset and must be explicitly initialized prior to any
3476 typedef union _hw_can_rximrn
3479 struct _hw_can_rximrn_bitfields
3481 uint32_t MI
: 32; /*!< [31:0] Individual Mask Bits */
3486 * @name Constants and macros for entire CAN_RXIMRn register
3489 #define HW_CAN_RXIMRn_COUNT (16U)
3491 #define HW_CAN_RXIMRn_ADDR(x, n) ((x) + 0x880U + (0x4U * (n)))
3493 #define HW_CAN_RXIMRn(x, n) (*(__IO hw_can_rximrn_t *) HW_CAN_RXIMRn_ADDR(x, n))
3494 #define HW_CAN_RXIMRn_RD(x, n) (HW_CAN_RXIMRn(x, n).U)
3495 #define HW_CAN_RXIMRn_WR(x, n, v) (HW_CAN_RXIMRn(x, n).U = (v))
3496 #define HW_CAN_RXIMRn_SET(x, n, v) (HW_CAN_RXIMRn_WR(x, n, HW_CAN_RXIMRn_RD(x, n) | (v)))
3497 #define HW_CAN_RXIMRn_CLR(x, n, v) (HW_CAN_RXIMRn_WR(x, n, HW_CAN_RXIMRn_RD(x, n) & ~(v)))
3498 #define HW_CAN_RXIMRn_TOG(x, n, v) (HW_CAN_RXIMRn_WR(x, n, HW_CAN_RXIMRn_RD(x, n) ^ (v)))
3502 * Constants & macros for individual CAN_RXIMRn bitfields
3506 * @name Register CAN_RXIMRn, field MI[31:0] (RW)
3508 * Each Individual Mask Bit masks the corresponding bit in both the Mailbox
3509 * filter and Rx FIFO ID Filter Table element in distinct ways. For Mailbox filters,
3510 * see the RXMGMASK register description. For Rx FIFO ID Filter Table elements,
3511 * see the RXFGMASK register description.
3514 * - 0 - The corresponding bit in the filter is "don't care."
3515 * - 1 - The corresponding bit in the filter is checked.
3518 #define BP_CAN_RXIMRn_MI (0U) /*!< Bit position for CAN_RXIMRn_MI. */
3519 #define BM_CAN_RXIMRn_MI (0xFFFFFFFFU) /*!< Bit mask for CAN_RXIMRn_MI. */
3520 #define BS_CAN_RXIMRn_MI (32U) /*!< Bit field size in bits for CAN_RXIMRn_MI. */
3522 /*! @brief Read current value of the CAN_RXIMRn_MI field. */
3523 #define BR_CAN_RXIMRn_MI(x, n) (HW_CAN_RXIMRn(x, n).U)
3525 /*! @brief Format value for bitfield CAN_RXIMRn_MI. */
3526 #define BF_CAN_RXIMRn_MI(v) ((uint32_t)((uint32_t)(v) << BP_CAN_RXIMRn_MI) & BM_CAN_RXIMRn_MI)
3528 /*! @brief Set the MI field to a new value. */
3529 #define BW_CAN_RXIMRn_MI(x, n, v) (HW_CAN_RXIMRn_WR(x, n, v))
3532 /*******************************************************************************
3533 * hw_can_t - module struct
3534 ******************************************************************************/
3536 * @brief All CAN module registers.
3539 typedef struct _hw_can
3541 __IO hw_can_mcr_t MCR
; /*!< [0x0] Module Configuration Register */
3542 __IO hw_can_ctrl1_t CTRL1
; /*!< [0x4] Control 1 register */
3543 __IO hw_can_timer_t TIMER
; /*!< [0x8] Free Running Timer */
3544 uint8_t _reserved0
[4];
3545 __IO hw_can_rxmgmask_t RXMGMASK
; /*!< [0x10] Rx Mailboxes Global Mask Register */
3546 __IO hw_can_rx14mask_t RX14MASK
; /*!< [0x14] Rx 14 Mask register */
3547 __IO hw_can_rx15mask_t RX15MASK
; /*!< [0x18] Rx 15 Mask register */
3548 __IO hw_can_ecr_t ECR
; /*!< [0x1C] Error Counter */
3549 __IO hw_can_esr1_t ESR1
; /*!< [0x20] Error and Status 1 register */
3550 uint8_t _reserved1
[4];
3551 __IO hw_can_imask1_t IMASK1
; /*!< [0x28] Interrupt Masks 1 register */
3552 uint8_t _reserved2
[4];
3553 __IO hw_can_iflag1_t IFLAG1
; /*!< [0x30] Interrupt Flags 1 register */
3554 __IO hw_can_ctrl2_t CTRL2
; /*!< [0x34] Control 2 register */
3555 __I hw_can_esr2_t ESR2
; /*!< [0x38] Error and Status 2 register */
3556 uint8_t _reserved3
[8];
3557 __I hw_can_crcr_t CRCR
; /*!< [0x44] CRC Register */
3558 __IO hw_can_rxfgmask_t RXFGMASK
; /*!< [0x48] Rx FIFO Global Mask register */
3559 __I hw_can_rxfir_t RXFIR
; /*!< [0x4C] Rx FIFO Information Register */
3560 uint8_t _reserved4
[48];
3562 __IO hw_can_csn_t CSn
; /*!< [0x80] Message Buffer 0 CS Register */
3563 __IO hw_can_idn_t IDn
; /*!< [0x84] Message Buffer 0 ID Register */
3564 __IO hw_can_word0n_t WORD0n
; /*!< [0x88] Message Buffer 0 WORD0 Register */
3565 __IO hw_can_word1n_t WORD1n
; /*!< [0x8C] Message Buffer 0 WORD1 Register */
3567 uint8_t _reserved5
[1792];
3568 __IO hw_can_rximrn_t RXIMRn
[16]; /*!< [0x880] Rx Individual Mask Registers */
3572 /*! @brief Macro to access all CAN registers. */
3573 /*! @param x CAN module instance base address. */
3574 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
3575 * use the '&' operator, like <code>&HW_CAN(CAN0_BASE)</code>. */
3576 #define HW_CAN(x) (*(hw_can_t *)(x))
3578 #endif /* __HW_CAN_REGISTERS_H__ */