2 ** ###################################################################
3 ** Compilers: Keil ARM C/C++ Compiler
4 ** Freescale C/C++ for Embedded ARM
6 ** IAR ANSI C/C++ Compiler for ARM
8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
9 ** Version: rev. 2.5, 2014-02-10
13 ** Extension to the CMSIS register access layer header.
15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
16 ** All rights reserved.
18 ** Redistribution and use in source and binary forms, with or without modification,
19 ** are permitted provided that the following conditions are met:
21 ** o Redistributions of source code must retain the above copyright notice, this list
22 ** of conditions and the following disclaimer.
24 ** o Redistributions in binary form must reproduce the above copyright notice, this
25 ** list of conditions and the following disclaimer in the documentation and/or
26 ** other materials provided with the distribution.
28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
29 ** contributors may be used to endorse or promote products derived from this
30 ** software without specific prior written permission.
32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ** http: www.freescale.com
44 ** mail: support@freescale.com
47 ** - rev. 1.0 (2013-08-12)
49 ** - rev. 2.0 (2013-10-29)
50 ** Register accessor macros added to the memory map.
51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
52 ** Startup file for gcc has been updated according to CMSIS 3.2.
53 ** System initialization updated.
54 ** MCG - registers updated.
55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
56 ** - rev. 2.1 (2013-10-30)
57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
58 ** - rev. 2.2 (2013-12-09)
59 ** DMA - EARS register removed.
60 ** AIPS0, AIPS1 - MPRA register updated.
61 ** - rev. 2.3 (2014-01-24)
62 ** Update according to reference manual rev. 2
63 ** ENET, MCG, MCM, SIM, USB - registers updated
64 ** - rev. 2.4 (2014-02-10)
65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
67 ** - rev. 2.5 (2014-02-10)
68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
72 ** ###################################################################
76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
78 * This file was generated automatically and any changes may be lost.
80 #ifndef __HW_CAU_REGISTERS_H__
81 #define __HW_CAU_REGISTERS_H__
84 #include "fsl_bitaccess.h"
89 * Memory Mapped Cryptographic Acceleration Unit (MMCAU)
91 * Registers defined in this header file:
92 * - HW_CAU_DIRECT0 - Direct access register 0
93 * - HW_CAU_DIRECT1 - Direct access register 1
94 * - HW_CAU_DIRECT2 - Direct access register 2
95 * - HW_CAU_DIRECT3 - Direct access register 3
96 * - HW_CAU_DIRECT4 - Direct access register 4
97 * - HW_CAU_DIRECT5 - Direct access register 5
98 * - HW_CAU_DIRECT6 - Direct access register 6
99 * - HW_CAU_DIRECT7 - Direct access register 7
100 * - HW_CAU_DIRECT8 - Direct access register 8
101 * - HW_CAU_DIRECT9 - Direct access register 9
102 * - HW_CAU_DIRECT10 - Direct access register 10
103 * - HW_CAU_DIRECT11 - Direct access register 11
104 * - HW_CAU_DIRECT12 - Direct access register 12
105 * - HW_CAU_DIRECT13 - Direct access register 13
106 * - HW_CAU_DIRECT14 - Direct access register 14
107 * - HW_CAU_DIRECT15 - Direct access register 15
108 * - HW_CAU_LDR_CASR - Status register - Load Register command
109 * - HW_CAU_LDR_CAA - Accumulator register - Load Register command
110 * - HW_CAU_LDR_CA0 - General Purpose Register 0 - Load Register command
111 * - HW_CAU_LDR_CA1 - General Purpose Register 1 - Load Register command
112 * - HW_CAU_LDR_CA2 - General Purpose Register 2 - Load Register command
113 * - HW_CAU_LDR_CA3 - General Purpose Register 3 - Load Register command
114 * - HW_CAU_LDR_CA4 - General Purpose Register 4 - Load Register command
115 * - HW_CAU_LDR_CA5 - General Purpose Register 5 - Load Register command
116 * - HW_CAU_LDR_CA6 - General Purpose Register 6 - Load Register command
117 * - HW_CAU_LDR_CA7 - General Purpose Register 7 - Load Register command
118 * - HW_CAU_LDR_CA8 - General Purpose Register 8 - Load Register command
119 * - HW_CAU_STR_CASR - Status register - Store Register command
120 * - HW_CAU_STR_CAA - Accumulator register - Store Register command
121 * - HW_CAU_STR_CA0 - General Purpose Register 0 - Store Register command
122 * - HW_CAU_STR_CA1 - General Purpose Register 1 - Store Register command
123 * - HW_CAU_STR_CA2 - General Purpose Register 2 - Store Register command
124 * - HW_CAU_STR_CA3 - General Purpose Register 3 - Store Register command
125 * - HW_CAU_STR_CA4 - General Purpose Register 4 - Store Register command
126 * - HW_CAU_STR_CA5 - General Purpose Register 5 - Store Register command
127 * - HW_CAU_STR_CA6 - General Purpose Register 6 - Store Register command
128 * - HW_CAU_STR_CA7 - General Purpose Register 7 - Store Register command
129 * - HW_CAU_STR_CA8 - General Purpose Register 8 - Store Register command
130 * - HW_CAU_ADR_CASR - Status register - Add Register command
131 * - HW_CAU_ADR_CAA - Accumulator register - Add to register command
132 * - HW_CAU_ADR_CA0 - General Purpose Register 0 - Add to register command
133 * - HW_CAU_ADR_CA1 - General Purpose Register 1 - Add to register command
134 * - HW_CAU_ADR_CA2 - General Purpose Register 2 - Add to register command
135 * - HW_CAU_ADR_CA3 - General Purpose Register 3 - Add to register command
136 * - HW_CAU_ADR_CA4 - General Purpose Register 4 - Add to register command
137 * - HW_CAU_ADR_CA5 - General Purpose Register 5 - Add to register command
138 * - HW_CAU_ADR_CA6 - General Purpose Register 6 - Add to register command
139 * - HW_CAU_ADR_CA7 - General Purpose Register 7 - Add to register command
140 * - HW_CAU_ADR_CA8 - General Purpose Register 8 - Add to register command
141 * - HW_CAU_RADR_CASR - Status register - Reverse and Add to Register command
142 * - HW_CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command
143 * - HW_CAU_RADR_CA0 - General Purpose Register 0 - Reverse and Add to Register command
144 * - HW_CAU_RADR_CA1 - General Purpose Register 1 - Reverse and Add to Register command
145 * - HW_CAU_RADR_CA2 - General Purpose Register 2 - Reverse and Add to Register command
146 * - HW_CAU_RADR_CA3 - General Purpose Register 3 - Reverse and Add to Register command
147 * - HW_CAU_RADR_CA4 - General Purpose Register 4 - Reverse and Add to Register command
148 * - HW_CAU_RADR_CA5 - General Purpose Register 5 - Reverse and Add to Register command
149 * - HW_CAU_RADR_CA6 - General Purpose Register 6 - Reverse and Add to Register command
150 * - HW_CAU_RADR_CA7 - General Purpose Register 7 - Reverse and Add to Register command
151 * - HW_CAU_RADR_CA8 - General Purpose Register 8 - Reverse and Add to Register command
152 * - HW_CAU_XOR_CASR - Status register - Exclusive Or command
153 * - HW_CAU_XOR_CAA - Accumulator register - Exclusive Or command
154 * - HW_CAU_XOR_CA0 - General Purpose Register 0 - Exclusive Or command
155 * - HW_CAU_XOR_CA1 - General Purpose Register 1 - Exclusive Or command
156 * - HW_CAU_XOR_CA2 - General Purpose Register 2 - Exclusive Or command
157 * - HW_CAU_XOR_CA3 - General Purpose Register 3 - Exclusive Or command
158 * - HW_CAU_XOR_CA4 - General Purpose Register 4 - Exclusive Or command
159 * - HW_CAU_XOR_CA5 - General Purpose Register 5 - Exclusive Or command
160 * - HW_CAU_XOR_CA6 - General Purpose Register 6 - Exclusive Or command
161 * - HW_CAU_XOR_CA7 - General Purpose Register 7 - Exclusive Or command
162 * - HW_CAU_XOR_CA8 - General Purpose Register 8 - Exclusive Or command
163 * - HW_CAU_ROTL_CASR - Status register - Rotate Left command
164 * - HW_CAU_ROTL_CAA - Accumulator register - Rotate Left command
165 * - HW_CAU_ROTL_CA0 - General Purpose Register 0 - Rotate Left command
166 * - HW_CAU_ROTL_CA1 - General Purpose Register 1 - Rotate Left command
167 * - HW_CAU_ROTL_CA2 - General Purpose Register 2 - Rotate Left command
168 * - HW_CAU_ROTL_CA3 - General Purpose Register 3 - Rotate Left command
169 * - HW_CAU_ROTL_CA4 - General Purpose Register 4 - Rotate Left command
170 * - HW_CAU_ROTL_CA5 - General Purpose Register 5 - Rotate Left command
171 * - HW_CAU_ROTL_CA6 - General Purpose Register 6 - Rotate Left command
172 * - HW_CAU_ROTL_CA7 - General Purpose Register 7 - Rotate Left command
173 * - HW_CAU_ROTL_CA8 - General Purpose Register 8 - Rotate Left command
174 * - HW_CAU_AESC_CASR - Status register - AES Column Operation command
175 * - HW_CAU_AESC_CAA - Accumulator register - AES Column Operation command
176 * - HW_CAU_AESC_CA0 - General Purpose Register 0 - AES Column Operation command
177 * - HW_CAU_AESC_CA1 - General Purpose Register 1 - AES Column Operation command
178 * - HW_CAU_AESC_CA2 - General Purpose Register 2 - AES Column Operation command
179 * - HW_CAU_AESC_CA3 - General Purpose Register 3 - AES Column Operation command
180 * - HW_CAU_AESC_CA4 - General Purpose Register 4 - AES Column Operation command
181 * - HW_CAU_AESC_CA5 - General Purpose Register 5 - AES Column Operation command
182 * - HW_CAU_AESC_CA6 - General Purpose Register 6 - AES Column Operation command
183 * - HW_CAU_AESC_CA7 - General Purpose Register 7 - AES Column Operation command
184 * - HW_CAU_AESC_CA8 - General Purpose Register 8 - AES Column Operation command
185 * - HW_CAU_AESIC_CASR - Status register - AES Inverse Column Operation command
186 * - HW_CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command
187 * - HW_CAU_AESIC_CA0 - General Purpose Register 0 - AES Inverse Column Operation command
188 * - HW_CAU_AESIC_CA1 - General Purpose Register 1 - AES Inverse Column Operation command
189 * - HW_CAU_AESIC_CA2 - General Purpose Register 2 - AES Inverse Column Operation command
190 * - HW_CAU_AESIC_CA3 - General Purpose Register 3 - AES Inverse Column Operation command
191 * - HW_CAU_AESIC_CA4 - General Purpose Register 4 - AES Inverse Column Operation command
192 * - HW_CAU_AESIC_CA5 - General Purpose Register 5 - AES Inverse Column Operation command
193 * - HW_CAU_AESIC_CA6 - General Purpose Register 6 - AES Inverse Column Operation command
194 * - HW_CAU_AESIC_CA7 - General Purpose Register 7 - AES Inverse Column Operation command
195 * - HW_CAU_AESIC_CA8 - General Purpose Register 8 - AES Inverse Column Operation command
197 * - hw_cau_t - Struct containing all module registers.
200 #define HW_CAU_INSTANCE_COUNT (1U) /*!< Number of instances of the CAU module. */
202 /*******************************************************************************
203 * HW_CAU_DIRECT0 - Direct access register 0
204 ******************************************************************************/
207 * @brief HW_CAU_DIRECT0 - Direct access register 0 (WO)
209 * Reset value: 0x00000000U
211 typedef union _hw_cau_direct0
214 struct _hw_cau_direct0_bitfields
216 uint32_t CAU_DIRECT0b
: 32; /*!< [31:0] Direct register 0 */
221 * @name Constants and macros for entire CAU_DIRECT0 register
224 #define HW_CAU_DIRECT0_ADDR(x) ((x) + 0x0U)
226 #define HW_CAU_DIRECT0(x) (*(__O hw_cau_direct0_t *) HW_CAU_DIRECT0_ADDR(x))
227 #define HW_CAU_DIRECT0_WR(x, v) (HW_CAU_DIRECT0(x).U = (v))
231 * Constants & macros for individual CAU_DIRECT0 bitfields
235 * @name Register CAU_DIRECT0, field CAU_DIRECT0[31:0] (WO)
238 #define BP_CAU_DIRECT0_CAU_DIRECT0 (0U) /*!< Bit position for CAU_DIRECT0_CAU_DIRECT0. */
239 #define BM_CAU_DIRECT0_CAU_DIRECT0 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT0_CAU_DIRECT0. */
240 #define BS_CAU_DIRECT0_CAU_DIRECT0 (32U) /*!< Bit field size in bits for CAU_DIRECT0_CAU_DIRECT0. */
242 /*! @brief Format value for bitfield CAU_DIRECT0_CAU_DIRECT0. */
243 #define BF_CAU_DIRECT0_CAU_DIRECT0(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT0_CAU_DIRECT0) & BM_CAU_DIRECT0_CAU_DIRECT0)
246 /*******************************************************************************
247 * HW_CAU_DIRECT1 - Direct access register 1
248 ******************************************************************************/
251 * @brief HW_CAU_DIRECT1 - Direct access register 1 (WO)
253 * Reset value: 0x00000000U
255 typedef union _hw_cau_direct1
258 struct _hw_cau_direct1_bitfields
260 uint32_t CAU_DIRECT1b
: 32; /*!< [31:0] Direct register 1 */
265 * @name Constants and macros for entire CAU_DIRECT1 register
268 #define HW_CAU_DIRECT1_ADDR(x) ((x) + 0x4U)
270 #define HW_CAU_DIRECT1(x) (*(__O hw_cau_direct1_t *) HW_CAU_DIRECT1_ADDR(x))
271 #define HW_CAU_DIRECT1_WR(x, v) (HW_CAU_DIRECT1(x).U = (v))
275 * Constants & macros for individual CAU_DIRECT1 bitfields
279 * @name Register CAU_DIRECT1, field CAU_DIRECT1[31:0] (WO)
282 #define BP_CAU_DIRECT1_CAU_DIRECT1 (0U) /*!< Bit position for CAU_DIRECT1_CAU_DIRECT1. */
283 #define BM_CAU_DIRECT1_CAU_DIRECT1 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT1_CAU_DIRECT1. */
284 #define BS_CAU_DIRECT1_CAU_DIRECT1 (32U) /*!< Bit field size in bits for CAU_DIRECT1_CAU_DIRECT1. */
286 /*! @brief Format value for bitfield CAU_DIRECT1_CAU_DIRECT1. */
287 #define BF_CAU_DIRECT1_CAU_DIRECT1(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT1_CAU_DIRECT1) & BM_CAU_DIRECT1_CAU_DIRECT1)
290 /*******************************************************************************
291 * HW_CAU_DIRECT2 - Direct access register 2
292 ******************************************************************************/
295 * @brief HW_CAU_DIRECT2 - Direct access register 2 (WO)
297 * Reset value: 0x00000000U
299 typedef union _hw_cau_direct2
302 struct _hw_cau_direct2_bitfields
304 uint32_t CAU_DIRECT2b
: 32; /*!< [31:0] Direct register 2 */
309 * @name Constants and macros for entire CAU_DIRECT2 register
312 #define HW_CAU_DIRECT2_ADDR(x) ((x) + 0x8U)
314 #define HW_CAU_DIRECT2(x) (*(__O hw_cau_direct2_t *) HW_CAU_DIRECT2_ADDR(x))
315 #define HW_CAU_DIRECT2_WR(x, v) (HW_CAU_DIRECT2(x).U = (v))
319 * Constants & macros for individual CAU_DIRECT2 bitfields
323 * @name Register CAU_DIRECT2, field CAU_DIRECT2[31:0] (WO)
326 #define BP_CAU_DIRECT2_CAU_DIRECT2 (0U) /*!< Bit position for CAU_DIRECT2_CAU_DIRECT2. */
327 #define BM_CAU_DIRECT2_CAU_DIRECT2 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT2_CAU_DIRECT2. */
328 #define BS_CAU_DIRECT2_CAU_DIRECT2 (32U) /*!< Bit field size in bits for CAU_DIRECT2_CAU_DIRECT2. */
330 /*! @brief Format value for bitfield CAU_DIRECT2_CAU_DIRECT2. */
331 #define BF_CAU_DIRECT2_CAU_DIRECT2(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT2_CAU_DIRECT2) & BM_CAU_DIRECT2_CAU_DIRECT2)
334 /*******************************************************************************
335 * HW_CAU_DIRECT3 - Direct access register 3
336 ******************************************************************************/
339 * @brief HW_CAU_DIRECT3 - Direct access register 3 (WO)
341 * Reset value: 0x00000000U
343 typedef union _hw_cau_direct3
346 struct _hw_cau_direct3_bitfields
348 uint32_t CAU_DIRECT3b
: 32; /*!< [31:0] Direct register 3 */
353 * @name Constants and macros for entire CAU_DIRECT3 register
356 #define HW_CAU_DIRECT3_ADDR(x) ((x) + 0xCU)
358 #define HW_CAU_DIRECT3(x) (*(__O hw_cau_direct3_t *) HW_CAU_DIRECT3_ADDR(x))
359 #define HW_CAU_DIRECT3_WR(x, v) (HW_CAU_DIRECT3(x).U = (v))
363 * Constants & macros for individual CAU_DIRECT3 bitfields
367 * @name Register CAU_DIRECT3, field CAU_DIRECT3[31:0] (WO)
370 #define BP_CAU_DIRECT3_CAU_DIRECT3 (0U) /*!< Bit position for CAU_DIRECT3_CAU_DIRECT3. */
371 #define BM_CAU_DIRECT3_CAU_DIRECT3 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT3_CAU_DIRECT3. */
372 #define BS_CAU_DIRECT3_CAU_DIRECT3 (32U) /*!< Bit field size in bits for CAU_DIRECT3_CAU_DIRECT3. */
374 /*! @brief Format value for bitfield CAU_DIRECT3_CAU_DIRECT3. */
375 #define BF_CAU_DIRECT3_CAU_DIRECT3(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT3_CAU_DIRECT3) & BM_CAU_DIRECT3_CAU_DIRECT3)
378 /*******************************************************************************
379 * HW_CAU_DIRECT4 - Direct access register 4
380 ******************************************************************************/
383 * @brief HW_CAU_DIRECT4 - Direct access register 4 (WO)
385 * Reset value: 0x00000000U
387 typedef union _hw_cau_direct4
390 struct _hw_cau_direct4_bitfields
392 uint32_t CAU_DIRECT4b
: 32; /*!< [31:0] Direct register 4 */
397 * @name Constants and macros for entire CAU_DIRECT4 register
400 #define HW_CAU_DIRECT4_ADDR(x) ((x) + 0x10U)
402 #define HW_CAU_DIRECT4(x) (*(__O hw_cau_direct4_t *) HW_CAU_DIRECT4_ADDR(x))
403 #define HW_CAU_DIRECT4_WR(x, v) (HW_CAU_DIRECT4(x).U = (v))
407 * Constants & macros for individual CAU_DIRECT4 bitfields
411 * @name Register CAU_DIRECT4, field CAU_DIRECT4[31:0] (WO)
414 #define BP_CAU_DIRECT4_CAU_DIRECT4 (0U) /*!< Bit position for CAU_DIRECT4_CAU_DIRECT4. */
415 #define BM_CAU_DIRECT4_CAU_DIRECT4 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT4_CAU_DIRECT4. */
416 #define BS_CAU_DIRECT4_CAU_DIRECT4 (32U) /*!< Bit field size in bits for CAU_DIRECT4_CAU_DIRECT4. */
418 /*! @brief Format value for bitfield CAU_DIRECT4_CAU_DIRECT4. */
419 #define BF_CAU_DIRECT4_CAU_DIRECT4(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT4_CAU_DIRECT4) & BM_CAU_DIRECT4_CAU_DIRECT4)
422 /*******************************************************************************
423 * HW_CAU_DIRECT5 - Direct access register 5
424 ******************************************************************************/
427 * @brief HW_CAU_DIRECT5 - Direct access register 5 (WO)
429 * Reset value: 0x00000000U
431 typedef union _hw_cau_direct5
434 struct _hw_cau_direct5_bitfields
436 uint32_t CAU_DIRECT5b
: 32; /*!< [31:0] Direct register 5 */
441 * @name Constants and macros for entire CAU_DIRECT5 register
444 #define HW_CAU_DIRECT5_ADDR(x) ((x) + 0x14U)
446 #define HW_CAU_DIRECT5(x) (*(__O hw_cau_direct5_t *) HW_CAU_DIRECT5_ADDR(x))
447 #define HW_CAU_DIRECT5_WR(x, v) (HW_CAU_DIRECT5(x).U = (v))
451 * Constants & macros for individual CAU_DIRECT5 bitfields
455 * @name Register CAU_DIRECT5, field CAU_DIRECT5[31:0] (WO)
458 #define BP_CAU_DIRECT5_CAU_DIRECT5 (0U) /*!< Bit position for CAU_DIRECT5_CAU_DIRECT5. */
459 #define BM_CAU_DIRECT5_CAU_DIRECT5 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT5_CAU_DIRECT5. */
460 #define BS_CAU_DIRECT5_CAU_DIRECT5 (32U) /*!< Bit field size in bits for CAU_DIRECT5_CAU_DIRECT5. */
462 /*! @brief Format value for bitfield CAU_DIRECT5_CAU_DIRECT5. */
463 #define BF_CAU_DIRECT5_CAU_DIRECT5(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT5_CAU_DIRECT5) & BM_CAU_DIRECT5_CAU_DIRECT5)
466 /*******************************************************************************
467 * HW_CAU_DIRECT6 - Direct access register 6
468 ******************************************************************************/
471 * @brief HW_CAU_DIRECT6 - Direct access register 6 (WO)
473 * Reset value: 0x00000000U
475 typedef union _hw_cau_direct6
478 struct _hw_cau_direct6_bitfields
480 uint32_t CAU_DIRECT6b
: 32; /*!< [31:0] Direct register 6 */
485 * @name Constants and macros for entire CAU_DIRECT6 register
488 #define HW_CAU_DIRECT6_ADDR(x) ((x) + 0x18U)
490 #define HW_CAU_DIRECT6(x) (*(__O hw_cau_direct6_t *) HW_CAU_DIRECT6_ADDR(x))
491 #define HW_CAU_DIRECT6_WR(x, v) (HW_CAU_DIRECT6(x).U = (v))
495 * Constants & macros for individual CAU_DIRECT6 bitfields
499 * @name Register CAU_DIRECT6, field CAU_DIRECT6[31:0] (WO)
502 #define BP_CAU_DIRECT6_CAU_DIRECT6 (0U) /*!< Bit position for CAU_DIRECT6_CAU_DIRECT6. */
503 #define BM_CAU_DIRECT6_CAU_DIRECT6 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT6_CAU_DIRECT6. */
504 #define BS_CAU_DIRECT6_CAU_DIRECT6 (32U) /*!< Bit field size in bits for CAU_DIRECT6_CAU_DIRECT6. */
506 /*! @brief Format value for bitfield CAU_DIRECT6_CAU_DIRECT6. */
507 #define BF_CAU_DIRECT6_CAU_DIRECT6(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT6_CAU_DIRECT6) & BM_CAU_DIRECT6_CAU_DIRECT6)
510 /*******************************************************************************
511 * HW_CAU_DIRECT7 - Direct access register 7
512 ******************************************************************************/
515 * @brief HW_CAU_DIRECT7 - Direct access register 7 (WO)
517 * Reset value: 0x00000000U
519 typedef union _hw_cau_direct7
522 struct _hw_cau_direct7_bitfields
524 uint32_t CAU_DIRECT7b
: 32; /*!< [31:0] Direct register 7 */
529 * @name Constants and macros for entire CAU_DIRECT7 register
532 #define HW_CAU_DIRECT7_ADDR(x) ((x) + 0x1CU)
534 #define HW_CAU_DIRECT7(x) (*(__O hw_cau_direct7_t *) HW_CAU_DIRECT7_ADDR(x))
535 #define HW_CAU_DIRECT7_WR(x, v) (HW_CAU_DIRECT7(x).U = (v))
539 * Constants & macros for individual CAU_DIRECT7 bitfields
543 * @name Register CAU_DIRECT7, field CAU_DIRECT7[31:0] (WO)
546 #define BP_CAU_DIRECT7_CAU_DIRECT7 (0U) /*!< Bit position for CAU_DIRECT7_CAU_DIRECT7. */
547 #define BM_CAU_DIRECT7_CAU_DIRECT7 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT7_CAU_DIRECT7. */
548 #define BS_CAU_DIRECT7_CAU_DIRECT7 (32U) /*!< Bit field size in bits for CAU_DIRECT7_CAU_DIRECT7. */
550 /*! @brief Format value for bitfield CAU_DIRECT7_CAU_DIRECT7. */
551 #define BF_CAU_DIRECT7_CAU_DIRECT7(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT7_CAU_DIRECT7) & BM_CAU_DIRECT7_CAU_DIRECT7)
554 /*******************************************************************************
555 * HW_CAU_DIRECT8 - Direct access register 8
556 ******************************************************************************/
559 * @brief HW_CAU_DIRECT8 - Direct access register 8 (WO)
561 * Reset value: 0x00000000U
563 typedef union _hw_cau_direct8
566 struct _hw_cau_direct8_bitfields
568 uint32_t CAU_DIRECT8b
: 32; /*!< [31:0] Direct register 8 */
573 * @name Constants and macros for entire CAU_DIRECT8 register
576 #define HW_CAU_DIRECT8_ADDR(x) ((x) + 0x20U)
578 #define HW_CAU_DIRECT8(x) (*(__O hw_cau_direct8_t *) HW_CAU_DIRECT8_ADDR(x))
579 #define HW_CAU_DIRECT8_WR(x, v) (HW_CAU_DIRECT8(x).U = (v))
583 * Constants & macros for individual CAU_DIRECT8 bitfields
587 * @name Register CAU_DIRECT8, field CAU_DIRECT8[31:0] (WO)
590 #define BP_CAU_DIRECT8_CAU_DIRECT8 (0U) /*!< Bit position for CAU_DIRECT8_CAU_DIRECT8. */
591 #define BM_CAU_DIRECT8_CAU_DIRECT8 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT8_CAU_DIRECT8. */
592 #define BS_CAU_DIRECT8_CAU_DIRECT8 (32U) /*!< Bit field size in bits for CAU_DIRECT8_CAU_DIRECT8. */
594 /*! @brief Format value for bitfield CAU_DIRECT8_CAU_DIRECT8. */
595 #define BF_CAU_DIRECT8_CAU_DIRECT8(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT8_CAU_DIRECT8) & BM_CAU_DIRECT8_CAU_DIRECT8)
598 /*******************************************************************************
599 * HW_CAU_DIRECT9 - Direct access register 9
600 ******************************************************************************/
603 * @brief HW_CAU_DIRECT9 - Direct access register 9 (WO)
605 * Reset value: 0x00000000U
607 typedef union _hw_cau_direct9
610 struct _hw_cau_direct9_bitfields
612 uint32_t CAU_DIRECT9b
: 32; /*!< [31:0] Direct register 9 */
617 * @name Constants and macros for entire CAU_DIRECT9 register
620 #define HW_CAU_DIRECT9_ADDR(x) ((x) + 0x24U)
622 #define HW_CAU_DIRECT9(x) (*(__O hw_cau_direct9_t *) HW_CAU_DIRECT9_ADDR(x))
623 #define HW_CAU_DIRECT9_WR(x, v) (HW_CAU_DIRECT9(x).U = (v))
627 * Constants & macros for individual CAU_DIRECT9 bitfields
631 * @name Register CAU_DIRECT9, field CAU_DIRECT9[31:0] (WO)
634 #define BP_CAU_DIRECT9_CAU_DIRECT9 (0U) /*!< Bit position for CAU_DIRECT9_CAU_DIRECT9. */
635 #define BM_CAU_DIRECT9_CAU_DIRECT9 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT9_CAU_DIRECT9. */
636 #define BS_CAU_DIRECT9_CAU_DIRECT9 (32U) /*!< Bit field size in bits for CAU_DIRECT9_CAU_DIRECT9. */
638 /*! @brief Format value for bitfield CAU_DIRECT9_CAU_DIRECT9. */
639 #define BF_CAU_DIRECT9_CAU_DIRECT9(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT9_CAU_DIRECT9) & BM_CAU_DIRECT9_CAU_DIRECT9)
642 /*******************************************************************************
643 * HW_CAU_DIRECT10 - Direct access register 10
644 ******************************************************************************/
647 * @brief HW_CAU_DIRECT10 - Direct access register 10 (WO)
649 * Reset value: 0x00000000U
651 typedef union _hw_cau_direct10
654 struct _hw_cau_direct10_bitfields
656 uint32_t CAU_DIRECT10b
: 32; /*!< [31:0] Direct register 10 */
661 * @name Constants and macros for entire CAU_DIRECT10 register
664 #define HW_CAU_DIRECT10_ADDR(x) ((x) + 0x28U)
666 #define HW_CAU_DIRECT10(x) (*(__O hw_cau_direct10_t *) HW_CAU_DIRECT10_ADDR(x))
667 #define HW_CAU_DIRECT10_WR(x, v) (HW_CAU_DIRECT10(x).U = (v))
671 * Constants & macros for individual CAU_DIRECT10 bitfields
675 * @name Register CAU_DIRECT10, field CAU_DIRECT10[31:0] (WO)
678 #define BP_CAU_DIRECT10_CAU_DIRECT10 (0U) /*!< Bit position for CAU_DIRECT10_CAU_DIRECT10. */
679 #define BM_CAU_DIRECT10_CAU_DIRECT10 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT10_CAU_DIRECT10. */
680 #define BS_CAU_DIRECT10_CAU_DIRECT10 (32U) /*!< Bit field size in bits for CAU_DIRECT10_CAU_DIRECT10. */
682 /*! @brief Format value for bitfield CAU_DIRECT10_CAU_DIRECT10. */
683 #define BF_CAU_DIRECT10_CAU_DIRECT10(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT10_CAU_DIRECT10) & BM_CAU_DIRECT10_CAU_DIRECT10)
686 /*******************************************************************************
687 * HW_CAU_DIRECT11 - Direct access register 11
688 ******************************************************************************/
691 * @brief HW_CAU_DIRECT11 - Direct access register 11 (WO)
693 * Reset value: 0x00000000U
695 typedef union _hw_cau_direct11
698 struct _hw_cau_direct11_bitfields
700 uint32_t CAU_DIRECT11b
: 32; /*!< [31:0] Direct register 11 */
705 * @name Constants and macros for entire CAU_DIRECT11 register
708 #define HW_CAU_DIRECT11_ADDR(x) ((x) + 0x2CU)
710 #define HW_CAU_DIRECT11(x) (*(__O hw_cau_direct11_t *) HW_CAU_DIRECT11_ADDR(x))
711 #define HW_CAU_DIRECT11_WR(x, v) (HW_CAU_DIRECT11(x).U = (v))
715 * Constants & macros for individual CAU_DIRECT11 bitfields
719 * @name Register CAU_DIRECT11, field CAU_DIRECT11[31:0] (WO)
722 #define BP_CAU_DIRECT11_CAU_DIRECT11 (0U) /*!< Bit position for CAU_DIRECT11_CAU_DIRECT11. */
723 #define BM_CAU_DIRECT11_CAU_DIRECT11 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT11_CAU_DIRECT11. */
724 #define BS_CAU_DIRECT11_CAU_DIRECT11 (32U) /*!< Bit field size in bits for CAU_DIRECT11_CAU_DIRECT11. */
726 /*! @brief Format value for bitfield CAU_DIRECT11_CAU_DIRECT11. */
727 #define BF_CAU_DIRECT11_CAU_DIRECT11(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT11_CAU_DIRECT11) & BM_CAU_DIRECT11_CAU_DIRECT11)
730 /*******************************************************************************
731 * HW_CAU_DIRECT12 - Direct access register 12
732 ******************************************************************************/
735 * @brief HW_CAU_DIRECT12 - Direct access register 12 (WO)
737 * Reset value: 0x00000000U
739 typedef union _hw_cau_direct12
742 struct _hw_cau_direct12_bitfields
744 uint32_t CAU_DIRECT12b
: 32; /*!< [31:0] Direct register 12 */
749 * @name Constants and macros for entire CAU_DIRECT12 register
752 #define HW_CAU_DIRECT12_ADDR(x) ((x) + 0x30U)
754 #define HW_CAU_DIRECT12(x) (*(__O hw_cau_direct12_t *) HW_CAU_DIRECT12_ADDR(x))
755 #define HW_CAU_DIRECT12_WR(x, v) (HW_CAU_DIRECT12(x).U = (v))
759 * Constants & macros for individual CAU_DIRECT12 bitfields
763 * @name Register CAU_DIRECT12, field CAU_DIRECT12[31:0] (WO)
766 #define BP_CAU_DIRECT12_CAU_DIRECT12 (0U) /*!< Bit position for CAU_DIRECT12_CAU_DIRECT12. */
767 #define BM_CAU_DIRECT12_CAU_DIRECT12 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT12_CAU_DIRECT12. */
768 #define BS_CAU_DIRECT12_CAU_DIRECT12 (32U) /*!< Bit field size in bits for CAU_DIRECT12_CAU_DIRECT12. */
770 /*! @brief Format value for bitfield CAU_DIRECT12_CAU_DIRECT12. */
771 #define BF_CAU_DIRECT12_CAU_DIRECT12(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT12_CAU_DIRECT12) & BM_CAU_DIRECT12_CAU_DIRECT12)
774 /*******************************************************************************
775 * HW_CAU_DIRECT13 - Direct access register 13
776 ******************************************************************************/
779 * @brief HW_CAU_DIRECT13 - Direct access register 13 (WO)
781 * Reset value: 0x00000000U
783 typedef union _hw_cau_direct13
786 struct _hw_cau_direct13_bitfields
788 uint32_t CAU_DIRECT13b
: 32; /*!< [31:0] Direct register 13 */
793 * @name Constants and macros for entire CAU_DIRECT13 register
796 #define HW_CAU_DIRECT13_ADDR(x) ((x) + 0x34U)
798 #define HW_CAU_DIRECT13(x) (*(__O hw_cau_direct13_t *) HW_CAU_DIRECT13_ADDR(x))
799 #define HW_CAU_DIRECT13_WR(x, v) (HW_CAU_DIRECT13(x).U = (v))
803 * Constants & macros for individual CAU_DIRECT13 bitfields
807 * @name Register CAU_DIRECT13, field CAU_DIRECT13[31:0] (WO)
810 #define BP_CAU_DIRECT13_CAU_DIRECT13 (0U) /*!< Bit position for CAU_DIRECT13_CAU_DIRECT13. */
811 #define BM_CAU_DIRECT13_CAU_DIRECT13 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT13_CAU_DIRECT13. */
812 #define BS_CAU_DIRECT13_CAU_DIRECT13 (32U) /*!< Bit field size in bits for CAU_DIRECT13_CAU_DIRECT13. */
814 /*! @brief Format value for bitfield CAU_DIRECT13_CAU_DIRECT13. */
815 #define BF_CAU_DIRECT13_CAU_DIRECT13(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT13_CAU_DIRECT13) & BM_CAU_DIRECT13_CAU_DIRECT13)
818 /*******************************************************************************
819 * HW_CAU_DIRECT14 - Direct access register 14
820 ******************************************************************************/
823 * @brief HW_CAU_DIRECT14 - Direct access register 14 (WO)
825 * Reset value: 0x00000000U
827 typedef union _hw_cau_direct14
830 struct _hw_cau_direct14_bitfields
832 uint32_t CAU_DIRECT14b
: 32; /*!< [31:0] Direct register 14 */
837 * @name Constants and macros for entire CAU_DIRECT14 register
840 #define HW_CAU_DIRECT14_ADDR(x) ((x) + 0x38U)
842 #define HW_CAU_DIRECT14(x) (*(__O hw_cau_direct14_t *) HW_CAU_DIRECT14_ADDR(x))
843 #define HW_CAU_DIRECT14_WR(x, v) (HW_CAU_DIRECT14(x).U = (v))
847 * Constants & macros for individual CAU_DIRECT14 bitfields
851 * @name Register CAU_DIRECT14, field CAU_DIRECT14[31:0] (WO)
854 #define BP_CAU_DIRECT14_CAU_DIRECT14 (0U) /*!< Bit position for CAU_DIRECT14_CAU_DIRECT14. */
855 #define BM_CAU_DIRECT14_CAU_DIRECT14 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT14_CAU_DIRECT14. */
856 #define BS_CAU_DIRECT14_CAU_DIRECT14 (32U) /*!< Bit field size in bits for CAU_DIRECT14_CAU_DIRECT14. */
858 /*! @brief Format value for bitfield CAU_DIRECT14_CAU_DIRECT14. */
859 #define BF_CAU_DIRECT14_CAU_DIRECT14(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT14_CAU_DIRECT14) & BM_CAU_DIRECT14_CAU_DIRECT14)
862 /*******************************************************************************
863 * HW_CAU_DIRECT15 - Direct access register 15
864 ******************************************************************************/
867 * @brief HW_CAU_DIRECT15 - Direct access register 15 (WO)
869 * Reset value: 0x00000000U
871 typedef union _hw_cau_direct15
874 struct _hw_cau_direct15_bitfields
876 uint32_t CAU_DIRECT15b
: 32; /*!< [31:0] Direct register 15 */
881 * @name Constants and macros for entire CAU_DIRECT15 register
884 #define HW_CAU_DIRECT15_ADDR(x) ((x) + 0x3CU)
886 #define HW_CAU_DIRECT15(x) (*(__O hw_cau_direct15_t *) HW_CAU_DIRECT15_ADDR(x))
887 #define HW_CAU_DIRECT15_WR(x, v) (HW_CAU_DIRECT15(x).U = (v))
891 * Constants & macros for individual CAU_DIRECT15 bitfields
895 * @name Register CAU_DIRECT15, field CAU_DIRECT15[31:0] (WO)
898 #define BP_CAU_DIRECT15_CAU_DIRECT15 (0U) /*!< Bit position for CAU_DIRECT15_CAU_DIRECT15. */
899 #define BM_CAU_DIRECT15_CAU_DIRECT15 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT15_CAU_DIRECT15. */
900 #define BS_CAU_DIRECT15_CAU_DIRECT15 (32U) /*!< Bit field size in bits for CAU_DIRECT15_CAU_DIRECT15. */
902 /*! @brief Format value for bitfield CAU_DIRECT15_CAU_DIRECT15. */
903 #define BF_CAU_DIRECT15_CAU_DIRECT15(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT15_CAU_DIRECT15) & BM_CAU_DIRECT15_CAU_DIRECT15)
906 /*******************************************************************************
907 * HW_CAU_LDR_CASR - Status register - Load Register command
908 ******************************************************************************/
911 * @brief HW_CAU_LDR_CASR - Status register - Load Register command (WO)
913 * Reset value: 0x20000000U
915 typedef union _hw_cau_ldr_casr
918 struct _hw_cau_ldr_casr_bitfields
920 uint32_t IC
: 1; /*!< [0] */
921 uint32_t DPE
: 1; /*!< [1] */
922 uint32_t RESERVED0
: 26; /*!< [27:2] */
923 uint32_t VER
: 4; /*!< [31:28] CAU version */
928 * @name Constants and macros for entire CAU_LDR_CASR register
931 #define HW_CAU_LDR_CASR_ADDR(x) ((x) + 0x840U)
933 #define HW_CAU_LDR_CASR(x) (*(__O hw_cau_ldr_casr_t *) HW_CAU_LDR_CASR_ADDR(x))
934 #define HW_CAU_LDR_CASR_WR(x, v) (HW_CAU_LDR_CASR(x).U = (v))
938 * Constants & macros for individual CAU_LDR_CASR bitfields
942 * @name Register CAU_LDR_CASR, field IC[0] (WO)
945 * - 0 - No illegal commands issued
946 * - 1 - Illegal command issued
949 #define BP_CAU_LDR_CASR_IC (0U) /*!< Bit position for CAU_LDR_CASR_IC. */
950 #define BM_CAU_LDR_CASR_IC (0x00000001U) /*!< Bit mask for CAU_LDR_CASR_IC. */
951 #define BS_CAU_LDR_CASR_IC (1U) /*!< Bit field size in bits for CAU_LDR_CASR_IC. */
953 /*! @brief Format value for bitfield CAU_LDR_CASR_IC. */
954 #define BF_CAU_LDR_CASR_IC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CASR_IC) & BM_CAU_LDR_CASR_IC)
958 * @name Register CAU_LDR_CASR, field DPE[1] (WO)
961 * - 0 - No error detected
962 * - 1 - DES key parity error detected
965 #define BP_CAU_LDR_CASR_DPE (1U) /*!< Bit position for CAU_LDR_CASR_DPE. */
966 #define BM_CAU_LDR_CASR_DPE (0x00000002U) /*!< Bit mask for CAU_LDR_CASR_DPE. */
967 #define BS_CAU_LDR_CASR_DPE (1U) /*!< Bit field size in bits for CAU_LDR_CASR_DPE. */
969 /*! @brief Format value for bitfield CAU_LDR_CASR_DPE. */
970 #define BF_CAU_LDR_CASR_DPE(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CASR_DPE) & BM_CAU_LDR_CASR_DPE)
974 * @name Register CAU_LDR_CASR, field VER[31:28] (WO)
977 * - 0001 - Initial CAU version
978 * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
979 * value on this device)
982 #define BP_CAU_LDR_CASR_VER (28U) /*!< Bit position for CAU_LDR_CASR_VER. */
983 #define BM_CAU_LDR_CASR_VER (0xF0000000U) /*!< Bit mask for CAU_LDR_CASR_VER. */
984 #define BS_CAU_LDR_CASR_VER (4U) /*!< Bit field size in bits for CAU_LDR_CASR_VER. */
986 /*! @brief Format value for bitfield CAU_LDR_CASR_VER. */
987 #define BF_CAU_LDR_CASR_VER(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CASR_VER) & BM_CAU_LDR_CASR_VER)
990 /*******************************************************************************
991 * HW_CAU_LDR_CAA - Accumulator register - Load Register command
992 ******************************************************************************/
995 * @brief HW_CAU_LDR_CAA - Accumulator register - Load Register command (WO)
997 * Reset value: 0x00000000U
999 typedef union _hw_cau_ldr_caa
1002 struct _hw_cau_ldr_caa_bitfields
1004 uint32_t ACC
: 32; /*!< [31:0] ACC */
1009 * @name Constants and macros for entire CAU_LDR_CAA register
1012 #define HW_CAU_LDR_CAA_ADDR(x) ((x) + 0x844U)
1014 #define HW_CAU_LDR_CAA(x) (*(__O hw_cau_ldr_caa_t *) HW_CAU_LDR_CAA_ADDR(x))
1015 #define HW_CAU_LDR_CAA_WR(x, v) (HW_CAU_LDR_CAA(x).U = (v))
1019 * Constants & macros for individual CAU_LDR_CAA bitfields
1023 * @name Register CAU_LDR_CAA, field ACC[31:0] (WO)
1026 #define BP_CAU_LDR_CAA_ACC (0U) /*!< Bit position for CAU_LDR_CAA_ACC. */
1027 #define BM_CAU_LDR_CAA_ACC (0xFFFFFFFFU) /*!< Bit mask for CAU_LDR_CAA_ACC. */
1028 #define BS_CAU_LDR_CAA_ACC (32U) /*!< Bit field size in bits for CAU_LDR_CAA_ACC. */
1030 /*! @brief Format value for bitfield CAU_LDR_CAA_ACC. */
1031 #define BF_CAU_LDR_CAA_ACC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CAA_ACC) & BM_CAU_LDR_CAA_ACC)
1034 /*******************************************************************************
1035 * HW_CAU_LDR_CA0 - General Purpose Register 0 - Load Register command
1036 ******************************************************************************/
1039 * @brief HW_CAU_LDR_CA0 - General Purpose Register 0 - Load Register command (WO)
1041 * Reset value: 0x00000000U
1043 typedef union _hw_cau_ldr_ca0
1046 struct _hw_cau_ldr_ca0_bitfields
1048 uint32_t CA0
: 32; /*!< [31:0] CA0 */
1053 * @name Constants and macros for entire CAU_LDR_CA0 register
1056 #define HW_CAU_LDR_CA0_ADDR(x) ((x) + 0x848U)
1058 #define HW_CAU_LDR_CA0(x) (*(__O hw_cau_ldr_ca0_t *) HW_CAU_LDR_CA0_ADDR(x))
1059 #define HW_CAU_LDR_CA0_WR(x, v) (HW_CAU_LDR_CA0(x).U = (v))
1063 * Constants & macros for individual CAU_LDR_CA0 bitfields
1067 * @name Register CAU_LDR_CA0, field CA0[31:0] (WO)
1070 #define BP_CAU_LDR_CA0_CA0 (0U) /*!< Bit position for CAU_LDR_CA0_CA0. */
1071 #define BM_CAU_LDR_CA0_CA0 (0xFFFFFFFFU) /*!< Bit mask for CAU_LDR_CA0_CA0. */
1072 #define BS_CAU_LDR_CA0_CA0 (32U) /*!< Bit field size in bits for CAU_LDR_CA0_CA0. */
1074 /*! @brief Format value for bitfield CAU_LDR_CA0_CA0. */
1075 #define BF_CAU_LDR_CA0_CA0(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CA0_CA0) & BM_CAU_LDR_CA0_CA0)
1078 /*******************************************************************************
1079 * HW_CAU_LDR_CA1 - General Purpose Register 1 - Load Register command
1080 ******************************************************************************/
1083 * @brief HW_CAU_LDR_CA1 - General Purpose Register 1 - Load Register command (WO)
1085 * Reset value: 0x00000000U
1087 typedef union _hw_cau_ldr_ca1
1090 struct _hw_cau_ldr_ca1_bitfields
1092 uint32_t CA1
: 32; /*!< [31:0] CA1 */
1097 * @name Constants and macros for entire CAU_LDR_CA1 register
1100 #define HW_CAU_LDR_CA1_ADDR(x) ((x) + 0x84CU)
1102 #define HW_CAU_LDR_CA1(x) (*(__O hw_cau_ldr_ca1_t *) HW_CAU_LDR_CA1_ADDR(x))
1103 #define HW_CAU_LDR_CA1_WR(x, v) (HW_CAU_LDR_CA1(x).U = (v))
1107 * Constants & macros for individual CAU_LDR_CA1 bitfields
1111 * @name Register CAU_LDR_CA1, field CA1[31:0] (WO)
1114 #define BP_CAU_LDR_CA1_CA1 (0U) /*!< Bit position for CAU_LDR_CA1_CA1. */
1115 #define BM_CAU_LDR_CA1_CA1 (0xFFFFFFFFU) /*!< Bit mask for CAU_LDR_CA1_CA1. */
1116 #define BS_CAU_LDR_CA1_CA1 (32U) /*!< Bit field size in bits for CAU_LDR_CA1_CA1. */
1118 /*! @brief Format value for bitfield CAU_LDR_CA1_CA1. */
1119 #define BF_CAU_LDR_CA1_CA1(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CA1_CA1) & BM_CAU_LDR_CA1_CA1)
1122 /*******************************************************************************
1123 * HW_CAU_LDR_CA2 - General Purpose Register 2 - Load Register command
1124 ******************************************************************************/
1127 * @brief HW_CAU_LDR_CA2 - General Purpose Register 2 - Load Register command (WO)
1129 * Reset value: 0x00000000U
1131 typedef union _hw_cau_ldr_ca2
1134 struct _hw_cau_ldr_ca2_bitfields
1136 uint32_t CA2
: 32; /*!< [31:0] CA2 */
1141 * @name Constants and macros for entire CAU_LDR_CA2 register
1144 #define HW_CAU_LDR_CA2_ADDR(x) ((x) + 0x850U)
1146 #define HW_CAU_LDR_CA2(x) (*(__O hw_cau_ldr_ca2_t *) HW_CAU_LDR_CA2_ADDR(x))
1147 #define HW_CAU_LDR_CA2_WR(x, v) (HW_CAU_LDR_CA2(x).U = (v))
1151 * Constants & macros for individual CAU_LDR_CA2 bitfields
1155 * @name Register CAU_LDR_CA2, field CA2[31:0] (WO)
1158 #define BP_CAU_LDR_CA2_CA2 (0U) /*!< Bit position for CAU_LDR_CA2_CA2. */
1159 #define BM_CAU_LDR_CA2_CA2 (0xFFFFFFFFU) /*!< Bit mask for CAU_LDR_CA2_CA2. */
1160 #define BS_CAU_LDR_CA2_CA2 (32U) /*!< Bit field size in bits for CAU_LDR_CA2_CA2. */
1162 /*! @brief Format value for bitfield CAU_LDR_CA2_CA2. */
1163 #define BF_CAU_LDR_CA2_CA2(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CA2_CA2) & BM_CAU_LDR_CA2_CA2)
1166 /*******************************************************************************
1167 * HW_CAU_LDR_CA3 - General Purpose Register 3 - Load Register command
1168 ******************************************************************************/
1171 * @brief HW_CAU_LDR_CA3 - General Purpose Register 3 - Load Register command (WO)
1173 * Reset value: 0x00000000U
1175 typedef union _hw_cau_ldr_ca3
1178 struct _hw_cau_ldr_ca3_bitfields
1180 uint32_t CA3
: 32; /*!< [31:0] CA3 */
1185 * @name Constants and macros for entire CAU_LDR_CA3 register
1188 #define HW_CAU_LDR_CA3_ADDR(x) ((x) + 0x854U)
1190 #define HW_CAU_LDR_CA3(x) (*(__O hw_cau_ldr_ca3_t *) HW_CAU_LDR_CA3_ADDR(x))
1191 #define HW_CAU_LDR_CA3_WR(x, v) (HW_CAU_LDR_CA3(x).U = (v))
1195 * Constants & macros for individual CAU_LDR_CA3 bitfields
1199 * @name Register CAU_LDR_CA3, field CA3[31:0] (WO)
1202 #define BP_CAU_LDR_CA3_CA3 (0U) /*!< Bit position for CAU_LDR_CA3_CA3. */
1203 #define BM_CAU_LDR_CA3_CA3 (0xFFFFFFFFU) /*!< Bit mask for CAU_LDR_CA3_CA3. */
1204 #define BS_CAU_LDR_CA3_CA3 (32U) /*!< Bit field size in bits for CAU_LDR_CA3_CA3. */
1206 /*! @brief Format value for bitfield CAU_LDR_CA3_CA3. */
1207 #define BF_CAU_LDR_CA3_CA3(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CA3_CA3) & BM_CAU_LDR_CA3_CA3)
1210 /*******************************************************************************
1211 * HW_CAU_LDR_CA4 - General Purpose Register 4 - Load Register command
1212 ******************************************************************************/
1215 * @brief HW_CAU_LDR_CA4 - General Purpose Register 4 - Load Register command (WO)
1217 * Reset value: 0x00000000U
1219 typedef union _hw_cau_ldr_ca4
1222 struct _hw_cau_ldr_ca4_bitfields
1224 uint32_t CA4
: 32; /*!< [31:0] CA4 */
1229 * @name Constants and macros for entire CAU_LDR_CA4 register
1232 #define HW_CAU_LDR_CA4_ADDR(x) ((x) + 0x858U)
1234 #define HW_CAU_LDR_CA4(x) (*(__O hw_cau_ldr_ca4_t *) HW_CAU_LDR_CA4_ADDR(x))
1235 #define HW_CAU_LDR_CA4_WR(x, v) (HW_CAU_LDR_CA4(x).U = (v))
1239 * Constants & macros for individual CAU_LDR_CA4 bitfields
1243 * @name Register CAU_LDR_CA4, field CA4[31:0] (WO)
1246 #define BP_CAU_LDR_CA4_CA4 (0U) /*!< Bit position for CAU_LDR_CA4_CA4. */
1247 #define BM_CAU_LDR_CA4_CA4 (0xFFFFFFFFU) /*!< Bit mask for CAU_LDR_CA4_CA4. */
1248 #define BS_CAU_LDR_CA4_CA4 (32U) /*!< Bit field size in bits for CAU_LDR_CA4_CA4. */
1250 /*! @brief Format value for bitfield CAU_LDR_CA4_CA4. */
1251 #define BF_CAU_LDR_CA4_CA4(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CA4_CA4) & BM_CAU_LDR_CA4_CA4)
1254 /*******************************************************************************
1255 * HW_CAU_LDR_CA5 - General Purpose Register 5 - Load Register command
1256 ******************************************************************************/
1259 * @brief HW_CAU_LDR_CA5 - General Purpose Register 5 - Load Register command (WO)
1261 * Reset value: 0x00000000U
1263 typedef union _hw_cau_ldr_ca5
1266 struct _hw_cau_ldr_ca5_bitfields
1268 uint32_t CA5
: 32; /*!< [31:0] CA5 */
1273 * @name Constants and macros for entire CAU_LDR_CA5 register
1276 #define HW_CAU_LDR_CA5_ADDR(x) ((x) + 0x85CU)
1278 #define HW_CAU_LDR_CA5(x) (*(__O hw_cau_ldr_ca5_t *) HW_CAU_LDR_CA5_ADDR(x))
1279 #define HW_CAU_LDR_CA5_WR(x, v) (HW_CAU_LDR_CA5(x).U = (v))
1283 * Constants & macros for individual CAU_LDR_CA5 bitfields
1287 * @name Register CAU_LDR_CA5, field CA5[31:0] (WO)
1290 #define BP_CAU_LDR_CA5_CA5 (0U) /*!< Bit position for CAU_LDR_CA5_CA5. */
1291 #define BM_CAU_LDR_CA5_CA5 (0xFFFFFFFFU) /*!< Bit mask for CAU_LDR_CA5_CA5. */
1292 #define BS_CAU_LDR_CA5_CA5 (32U) /*!< Bit field size in bits for CAU_LDR_CA5_CA5. */
1294 /*! @brief Format value for bitfield CAU_LDR_CA5_CA5. */
1295 #define BF_CAU_LDR_CA5_CA5(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CA5_CA5) & BM_CAU_LDR_CA5_CA5)
1298 /*******************************************************************************
1299 * HW_CAU_LDR_CA6 - General Purpose Register 6 - Load Register command
1300 ******************************************************************************/
1303 * @brief HW_CAU_LDR_CA6 - General Purpose Register 6 - Load Register command (WO)
1305 * Reset value: 0x00000000U
1307 typedef union _hw_cau_ldr_ca6
1310 struct _hw_cau_ldr_ca6_bitfields
1312 uint32_t CA6
: 32; /*!< [31:0] CA6 */
1317 * @name Constants and macros for entire CAU_LDR_CA6 register
1320 #define HW_CAU_LDR_CA6_ADDR(x) ((x) + 0x860U)
1322 #define HW_CAU_LDR_CA6(x) (*(__O hw_cau_ldr_ca6_t *) HW_CAU_LDR_CA6_ADDR(x))
1323 #define HW_CAU_LDR_CA6_WR(x, v) (HW_CAU_LDR_CA6(x).U = (v))
1327 * Constants & macros for individual CAU_LDR_CA6 bitfields
1331 * @name Register CAU_LDR_CA6, field CA6[31:0] (WO)
1334 #define BP_CAU_LDR_CA6_CA6 (0U) /*!< Bit position for CAU_LDR_CA6_CA6. */
1335 #define BM_CAU_LDR_CA6_CA6 (0xFFFFFFFFU) /*!< Bit mask for CAU_LDR_CA6_CA6. */
1336 #define BS_CAU_LDR_CA6_CA6 (32U) /*!< Bit field size in bits for CAU_LDR_CA6_CA6. */
1338 /*! @brief Format value for bitfield CAU_LDR_CA6_CA6. */
1339 #define BF_CAU_LDR_CA6_CA6(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CA6_CA6) & BM_CAU_LDR_CA6_CA6)
1342 /*******************************************************************************
1343 * HW_CAU_LDR_CA7 - General Purpose Register 7 - Load Register command
1344 ******************************************************************************/
1347 * @brief HW_CAU_LDR_CA7 - General Purpose Register 7 - Load Register command (WO)
1349 * Reset value: 0x00000000U
1351 typedef union _hw_cau_ldr_ca7
1354 struct _hw_cau_ldr_ca7_bitfields
1356 uint32_t CA7
: 32; /*!< [31:0] CA7 */
1361 * @name Constants and macros for entire CAU_LDR_CA7 register
1364 #define HW_CAU_LDR_CA7_ADDR(x) ((x) + 0x864U)
1366 #define HW_CAU_LDR_CA7(x) (*(__O hw_cau_ldr_ca7_t *) HW_CAU_LDR_CA7_ADDR(x))
1367 #define HW_CAU_LDR_CA7_WR(x, v) (HW_CAU_LDR_CA7(x).U = (v))
1371 * Constants & macros for individual CAU_LDR_CA7 bitfields
1375 * @name Register CAU_LDR_CA7, field CA7[31:0] (WO)
1378 #define BP_CAU_LDR_CA7_CA7 (0U) /*!< Bit position for CAU_LDR_CA7_CA7. */
1379 #define BM_CAU_LDR_CA7_CA7 (0xFFFFFFFFU) /*!< Bit mask for CAU_LDR_CA7_CA7. */
1380 #define BS_CAU_LDR_CA7_CA7 (32U) /*!< Bit field size in bits for CAU_LDR_CA7_CA7. */
1382 /*! @brief Format value for bitfield CAU_LDR_CA7_CA7. */
1383 #define BF_CAU_LDR_CA7_CA7(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CA7_CA7) & BM_CAU_LDR_CA7_CA7)
1386 /*******************************************************************************
1387 * HW_CAU_LDR_CA8 - General Purpose Register 8 - Load Register command
1388 ******************************************************************************/
1391 * @brief HW_CAU_LDR_CA8 - General Purpose Register 8 - Load Register command (WO)
1393 * Reset value: 0x00000000U
1395 typedef union _hw_cau_ldr_ca8
1398 struct _hw_cau_ldr_ca8_bitfields
1400 uint32_t CA8
: 32; /*!< [31:0] CA8 */
1405 * @name Constants and macros for entire CAU_LDR_CA8 register
1408 #define HW_CAU_LDR_CA8_ADDR(x) ((x) + 0x868U)
1410 #define HW_CAU_LDR_CA8(x) (*(__O hw_cau_ldr_ca8_t *) HW_CAU_LDR_CA8_ADDR(x))
1411 #define HW_CAU_LDR_CA8_WR(x, v) (HW_CAU_LDR_CA8(x).U = (v))
1415 * Constants & macros for individual CAU_LDR_CA8 bitfields
1419 * @name Register CAU_LDR_CA8, field CA8[31:0] (WO)
1422 #define BP_CAU_LDR_CA8_CA8 (0U) /*!< Bit position for CAU_LDR_CA8_CA8. */
1423 #define BM_CAU_LDR_CA8_CA8 (0xFFFFFFFFU) /*!< Bit mask for CAU_LDR_CA8_CA8. */
1424 #define BS_CAU_LDR_CA8_CA8 (32U) /*!< Bit field size in bits for CAU_LDR_CA8_CA8. */
1426 /*! @brief Format value for bitfield CAU_LDR_CA8_CA8. */
1427 #define BF_CAU_LDR_CA8_CA8(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CA8_CA8) & BM_CAU_LDR_CA8_CA8)
1430 /*******************************************************************************
1431 * HW_CAU_STR_CASR - Status register - Store Register command
1432 ******************************************************************************/
1435 * @brief HW_CAU_STR_CASR - Status register - Store Register command (RO)
1437 * Reset value: 0x20000000U
1439 typedef union _hw_cau_str_casr
1442 struct _hw_cau_str_casr_bitfields
1444 uint32_t IC
: 1; /*!< [0] */
1445 uint32_t DPE
: 1; /*!< [1] */
1446 uint32_t RESERVED0
: 26; /*!< [27:2] */
1447 uint32_t VER
: 4; /*!< [31:28] CAU version */
1449 } hw_cau_str_casr_t
;
1452 * @name Constants and macros for entire CAU_STR_CASR register
1455 #define HW_CAU_STR_CASR_ADDR(x) ((x) + 0x880U)
1457 #define HW_CAU_STR_CASR(x) (*(__I hw_cau_str_casr_t *) HW_CAU_STR_CASR_ADDR(x))
1458 #define HW_CAU_STR_CASR_RD(x) (HW_CAU_STR_CASR(x).U)
1462 * Constants & macros for individual CAU_STR_CASR bitfields
1466 * @name Register CAU_STR_CASR, field IC[0] (RO)
1469 * - 0 - No illegal commands issued
1470 * - 1 - Illegal command issued
1473 #define BP_CAU_STR_CASR_IC (0U) /*!< Bit position for CAU_STR_CASR_IC. */
1474 #define BM_CAU_STR_CASR_IC (0x00000001U) /*!< Bit mask for CAU_STR_CASR_IC. */
1475 #define BS_CAU_STR_CASR_IC (1U) /*!< Bit field size in bits for CAU_STR_CASR_IC. */
1477 /*! @brief Read current value of the CAU_STR_CASR_IC field. */
1478 #define BR_CAU_STR_CASR_IC(x) (HW_CAU_STR_CASR(x).B.IC)
1482 * @name Register CAU_STR_CASR, field DPE[1] (RO)
1485 * - 0 - No error detected
1486 * - 1 - DES key parity error detected
1489 #define BP_CAU_STR_CASR_DPE (1U) /*!< Bit position for CAU_STR_CASR_DPE. */
1490 #define BM_CAU_STR_CASR_DPE (0x00000002U) /*!< Bit mask for CAU_STR_CASR_DPE. */
1491 #define BS_CAU_STR_CASR_DPE (1U) /*!< Bit field size in bits for CAU_STR_CASR_DPE. */
1493 /*! @brief Read current value of the CAU_STR_CASR_DPE field. */
1494 #define BR_CAU_STR_CASR_DPE(x) (HW_CAU_STR_CASR(x).B.DPE)
1498 * @name Register CAU_STR_CASR, field VER[31:28] (RO)
1501 * - 0001 - Initial CAU version
1502 * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
1503 * value on this device)
1506 #define BP_CAU_STR_CASR_VER (28U) /*!< Bit position for CAU_STR_CASR_VER. */
1507 #define BM_CAU_STR_CASR_VER (0xF0000000U) /*!< Bit mask for CAU_STR_CASR_VER. */
1508 #define BS_CAU_STR_CASR_VER (4U) /*!< Bit field size in bits for CAU_STR_CASR_VER. */
1510 /*! @brief Read current value of the CAU_STR_CASR_VER field. */
1511 #define BR_CAU_STR_CASR_VER(x) (HW_CAU_STR_CASR(x).B.VER)
1514 /*******************************************************************************
1515 * HW_CAU_STR_CAA - Accumulator register - Store Register command
1516 ******************************************************************************/
1519 * @brief HW_CAU_STR_CAA - Accumulator register - Store Register command (RO)
1521 * Reset value: 0x00000000U
1523 typedef union _hw_cau_str_caa
1526 struct _hw_cau_str_caa_bitfields
1528 uint32_t ACC
: 32; /*!< [31:0] ACC */
1533 * @name Constants and macros for entire CAU_STR_CAA register
1536 #define HW_CAU_STR_CAA_ADDR(x) ((x) + 0x884U)
1538 #define HW_CAU_STR_CAA(x) (*(__I hw_cau_str_caa_t *) HW_CAU_STR_CAA_ADDR(x))
1539 #define HW_CAU_STR_CAA_RD(x) (HW_CAU_STR_CAA(x).U)
1543 * Constants & macros for individual CAU_STR_CAA bitfields
1547 * @name Register CAU_STR_CAA, field ACC[31:0] (RO)
1550 #define BP_CAU_STR_CAA_ACC (0U) /*!< Bit position for CAU_STR_CAA_ACC. */
1551 #define BM_CAU_STR_CAA_ACC (0xFFFFFFFFU) /*!< Bit mask for CAU_STR_CAA_ACC. */
1552 #define BS_CAU_STR_CAA_ACC (32U) /*!< Bit field size in bits for CAU_STR_CAA_ACC. */
1554 /*! @brief Read current value of the CAU_STR_CAA_ACC field. */
1555 #define BR_CAU_STR_CAA_ACC(x) (HW_CAU_STR_CAA(x).U)
1558 /*******************************************************************************
1559 * HW_CAU_STR_CA0 - General Purpose Register 0 - Store Register command
1560 ******************************************************************************/
1563 * @brief HW_CAU_STR_CA0 - General Purpose Register 0 - Store Register command (RO)
1565 * Reset value: 0x00000000U
1567 typedef union _hw_cau_str_ca0
1570 struct _hw_cau_str_ca0_bitfields
1572 uint32_t CA0
: 32; /*!< [31:0] CA0 */
1577 * @name Constants and macros for entire CAU_STR_CA0 register
1580 #define HW_CAU_STR_CA0_ADDR(x) ((x) + 0x888U)
1582 #define HW_CAU_STR_CA0(x) (*(__I hw_cau_str_ca0_t *) HW_CAU_STR_CA0_ADDR(x))
1583 #define HW_CAU_STR_CA0_RD(x) (HW_CAU_STR_CA0(x).U)
1587 * Constants & macros for individual CAU_STR_CA0 bitfields
1591 * @name Register CAU_STR_CA0, field CA0[31:0] (RO)
1594 #define BP_CAU_STR_CA0_CA0 (0U) /*!< Bit position for CAU_STR_CA0_CA0. */
1595 #define BM_CAU_STR_CA0_CA0 (0xFFFFFFFFU) /*!< Bit mask for CAU_STR_CA0_CA0. */
1596 #define BS_CAU_STR_CA0_CA0 (32U) /*!< Bit field size in bits for CAU_STR_CA0_CA0. */
1598 /*! @brief Read current value of the CAU_STR_CA0_CA0 field. */
1599 #define BR_CAU_STR_CA0_CA0(x) (HW_CAU_STR_CA0(x).U)
1602 /*******************************************************************************
1603 * HW_CAU_STR_CA1 - General Purpose Register 1 - Store Register command
1604 ******************************************************************************/
1607 * @brief HW_CAU_STR_CA1 - General Purpose Register 1 - Store Register command (RO)
1609 * Reset value: 0x00000000U
1611 typedef union _hw_cau_str_ca1
1614 struct _hw_cau_str_ca1_bitfields
1616 uint32_t CA1
: 32; /*!< [31:0] CA1 */
1621 * @name Constants and macros for entire CAU_STR_CA1 register
1624 #define HW_CAU_STR_CA1_ADDR(x) ((x) + 0x88CU)
1626 #define HW_CAU_STR_CA1(x) (*(__I hw_cau_str_ca1_t *) HW_CAU_STR_CA1_ADDR(x))
1627 #define HW_CAU_STR_CA1_RD(x) (HW_CAU_STR_CA1(x).U)
1631 * Constants & macros for individual CAU_STR_CA1 bitfields
1635 * @name Register CAU_STR_CA1, field CA1[31:0] (RO)
1638 #define BP_CAU_STR_CA1_CA1 (0U) /*!< Bit position for CAU_STR_CA1_CA1. */
1639 #define BM_CAU_STR_CA1_CA1 (0xFFFFFFFFU) /*!< Bit mask for CAU_STR_CA1_CA1. */
1640 #define BS_CAU_STR_CA1_CA1 (32U) /*!< Bit field size in bits for CAU_STR_CA1_CA1. */
1642 /*! @brief Read current value of the CAU_STR_CA1_CA1 field. */
1643 #define BR_CAU_STR_CA1_CA1(x) (HW_CAU_STR_CA1(x).U)
1646 /*******************************************************************************
1647 * HW_CAU_STR_CA2 - General Purpose Register 2 - Store Register command
1648 ******************************************************************************/
1651 * @brief HW_CAU_STR_CA2 - General Purpose Register 2 - Store Register command (RO)
1653 * Reset value: 0x00000000U
1655 typedef union _hw_cau_str_ca2
1658 struct _hw_cau_str_ca2_bitfields
1660 uint32_t CA2
: 32; /*!< [31:0] CA2 */
1665 * @name Constants and macros for entire CAU_STR_CA2 register
1668 #define HW_CAU_STR_CA2_ADDR(x) ((x) + 0x890U)
1670 #define HW_CAU_STR_CA2(x) (*(__I hw_cau_str_ca2_t *) HW_CAU_STR_CA2_ADDR(x))
1671 #define HW_CAU_STR_CA2_RD(x) (HW_CAU_STR_CA2(x).U)
1675 * Constants & macros for individual CAU_STR_CA2 bitfields
1679 * @name Register CAU_STR_CA2, field CA2[31:0] (RO)
1682 #define BP_CAU_STR_CA2_CA2 (0U) /*!< Bit position for CAU_STR_CA2_CA2. */
1683 #define BM_CAU_STR_CA2_CA2 (0xFFFFFFFFU) /*!< Bit mask for CAU_STR_CA2_CA2. */
1684 #define BS_CAU_STR_CA2_CA2 (32U) /*!< Bit field size in bits for CAU_STR_CA2_CA2. */
1686 /*! @brief Read current value of the CAU_STR_CA2_CA2 field. */
1687 #define BR_CAU_STR_CA2_CA2(x) (HW_CAU_STR_CA2(x).U)
1690 /*******************************************************************************
1691 * HW_CAU_STR_CA3 - General Purpose Register 3 - Store Register command
1692 ******************************************************************************/
1695 * @brief HW_CAU_STR_CA3 - General Purpose Register 3 - Store Register command (RO)
1697 * Reset value: 0x00000000U
1699 typedef union _hw_cau_str_ca3
1702 struct _hw_cau_str_ca3_bitfields
1704 uint32_t CA3
: 32; /*!< [31:0] CA3 */
1709 * @name Constants and macros for entire CAU_STR_CA3 register
1712 #define HW_CAU_STR_CA3_ADDR(x) ((x) + 0x894U)
1714 #define HW_CAU_STR_CA3(x) (*(__I hw_cau_str_ca3_t *) HW_CAU_STR_CA3_ADDR(x))
1715 #define HW_CAU_STR_CA3_RD(x) (HW_CAU_STR_CA3(x).U)
1719 * Constants & macros for individual CAU_STR_CA3 bitfields
1723 * @name Register CAU_STR_CA3, field CA3[31:0] (RO)
1726 #define BP_CAU_STR_CA3_CA3 (0U) /*!< Bit position for CAU_STR_CA3_CA3. */
1727 #define BM_CAU_STR_CA3_CA3 (0xFFFFFFFFU) /*!< Bit mask for CAU_STR_CA3_CA3. */
1728 #define BS_CAU_STR_CA3_CA3 (32U) /*!< Bit field size in bits for CAU_STR_CA3_CA3. */
1730 /*! @brief Read current value of the CAU_STR_CA3_CA3 field. */
1731 #define BR_CAU_STR_CA3_CA3(x) (HW_CAU_STR_CA3(x).U)
1734 /*******************************************************************************
1735 * HW_CAU_STR_CA4 - General Purpose Register 4 - Store Register command
1736 ******************************************************************************/
1739 * @brief HW_CAU_STR_CA4 - General Purpose Register 4 - Store Register command (RO)
1741 * Reset value: 0x00000000U
1743 typedef union _hw_cau_str_ca4
1746 struct _hw_cau_str_ca4_bitfields
1748 uint32_t CA4
: 32; /*!< [31:0] CA4 */
1753 * @name Constants and macros for entire CAU_STR_CA4 register
1756 #define HW_CAU_STR_CA4_ADDR(x) ((x) + 0x898U)
1758 #define HW_CAU_STR_CA4(x) (*(__I hw_cau_str_ca4_t *) HW_CAU_STR_CA4_ADDR(x))
1759 #define HW_CAU_STR_CA4_RD(x) (HW_CAU_STR_CA4(x).U)
1763 * Constants & macros for individual CAU_STR_CA4 bitfields
1767 * @name Register CAU_STR_CA4, field CA4[31:0] (RO)
1770 #define BP_CAU_STR_CA4_CA4 (0U) /*!< Bit position for CAU_STR_CA4_CA4. */
1771 #define BM_CAU_STR_CA4_CA4 (0xFFFFFFFFU) /*!< Bit mask for CAU_STR_CA4_CA4. */
1772 #define BS_CAU_STR_CA4_CA4 (32U) /*!< Bit field size in bits for CAU_STR_CA4_CA4. */
1774 /*! @brief Read current value of the CAU_STR_CA4_CA4 field. */
1775 #define BR_CAU_STR_CA4_CA4(x) (HW_CAU_STR_CA4(x).U)
1778 /*******************************************************************************
1779 * HW_CAU_STR_CA5 - General Purpose Register 5 - Store Register command
1780 ******************************************************************************/
1783 * @brief HW_CAU_STR_CA5 - General Purpose Register 5 - Store Register command (RO)
1785 * Reset value: 0x00000000U
1787 typedef union _hw_cau_str_ca5
1790 struct _hw_cau_str_ca5_bitfields
1792 uint32_t CA5
: 32; /*!< [31:0] CA5 */
1797 * @name Constants and macros for entire CAU_STR_CA5 register
1800 #define HW_CAU_STR_CA5_ADDR(x) ((x) + 0x89CU)
1802 #define HW_CAU_STR_CA5(x) (*(__I hw_cau_str_ca5_t *) HW_CAU_STR_CA5_ADDR(x))
1803 #define HW_CAU_STR_CA5_RD(x) (HW_CAU_STR_CA5(x).U)
1807 * Constants & macros for individual CAU_STR_CA5 bitfields
1811 * @name Register CAU_STR_CA5, field CA5[31:0] (RO)
1814 #define BP_CAU_STR_CA5_CA5 (0U) /*!< Bit position for CAU_STR_CA5_CA5. */
1815 #define BM_CAU_STR_CA5_CA5 (0xFFFFFFFFU) /*!< Bit mask for CAU_STR_CA5_CA5. */
1816 #define BS_CAU_STR_CA5_CA5 (32U) /*!< Bit field size in bits for CAU_STR_CA5_CA5. */
1818 /*! @brief Read current value of the CAU_STR_CA5_CA5 field. */
1819 #define BR_CAU_STR_CA5_CA5(x) (HW_CAU_STR_CA5(x).U)
1822 /*******************************************************************************
1823 * HW_CAU_STR_CA6 - General Purpose Register 6 - Store Register command
1824 ******************************************************************************/
1827 * @brief HW_CAU_STR_CA6 - General Purpose Register 6 - Store Register command (RO)
1829 * Reset value: 0x00000000U
1831 typedef union _hw_cau_str_ca6
1834 struct _hw_cau_str_ca6_bitfields
1836 uint32_t CA6
: 32; /*!< [31:0] CA6 */
1841 * @name Constants and macros for entire CAU_STR_CA6 register
1844 #define HW_CAU_STR_CA6_ADDR(x) ((x) + 0x8A0U)
1846 #define HW_CAU_STR_CA6(x) (*(__I hw_cau_str_ca6_t *) HW_CAU_STR_CA6_ADDR(x))
1847 #define HW_CAU_STR_CA6_RD(x) (HW_CAU_STR_CA6(x).U)
1851 * Constants & macros for individual CAU_STR_CA6 bitfields
1855 * @name Register CAU_STR_CA6, field CA6[31:0] (RO)
1858 #define BP_CAU_STR_CA6_CA6 (0U) /*!< Bit position for CAU_STR_CA6_CA6. */
1859 #define BM_CAU_STR_CA6_CA6 (0xFFFFFFFFU) /*!< Bit mask for CAU_STR_CA6_CA6. */
1860 #define BS_CAU_STR_CA6_CA6 (32U) /*!< Bit field size in bits for CAU_STR_CA6_CA6. */
1862 /*! @brief Read current value of the CAU_STR_CA6_CA6 field. */
1863 #define BR_CAU_STR_CA6_CA6(x) (HW_CAU_STR_CA6(x).U)
1866 /*******************************************************************************
1867 * HW_CAU_STR_CA7 - General Purpose Register 7 - Store Register command
1868 ******************************************************************************/
1871 * @brief HW_CAU_STR_CA7 - General Purpose Register 7 - Store Register command (RO)
1873 * Reset value: 0x00000000U
1875 typedef union _hw_cau_str_ca7
1878 struct _hw_cau_str_ca7_bitfields
1880 uint32_t CA7
: 32; /*!< [31:0] CA7 */
1885 * @name Constants and macros for entire CAU_STR_CA7 register
1888 #define HW_CAU_STR_CA7_ADDR(x) ((x) + 0x8A4U)
1890 #define HW_CAU_STR_CA7(x) (*(__I hw_cau_str_ca7_t *) HW_CAU_STR_CA7_ADDR(x))
1891 #define HW_CAU_STR_CA7_RD(x) (HW_CAU_STR_CA7(x).U)
1895 * Constants & macros for individual CAU_STR_CA7 bitfields
1899 * @name Register CAU_STR_CA7, field CA7[31:0] (RO)
1902 #define BP_CAU_STR_CA7_CA7 (0U) /*!< Bit position for CAU_STR_CA7_CA7. */
1903 #define BM_CAU_STR_CA7_CA7 (0xFFFFFFFFU) /*!< Bit mask for CAU_STR_CA7_CA7. */
1904 #define BS_CAU_STR_CA7_CA7 (32U) /*!< Bit field size in bits for CAU_STR_CA7_CA7. */
1906 /*! @brief Read current value of the CAU_STR_CA7_CA7 field. */
1907 #define BR_CAU_STR_CA7_CA7(x) (HW_CAU_STR_CA7(x).U)
1910 /*******************************************************************************
1911 * HW_CAU_STR_CA8 - General Purpose Register 8 - Store Register command
1912 ******************************************************************************/
1915 * @brief HW_CAU_STR_CA8 - General Purpose Register 8 - Store Register command (RO)
1917 * Reset value: 0x00000000U
1919 typedef union _hw_cau_str_ca8
1922 struct _hw_cau_str_ca8_bitfields
1924 uint32_t CA8
: 32; /*!< [31:0] CA8 */
1929 * @name Constants and macros for entire CAU_STR_CA8 register
1932 #define HW_CAU_STR_CA8_ADDR(x) ((x) + 0x8A8U)
1934 #define HW_CAU_STR_CA8(x) (*(__I hw_cau_str_ca8_t *) HW_CAU_STR_CA8_ADDR(x))
1935 #define HW_CAU_STR_CA8_RD(x) (HW_CAU_STR_CA8(x).U)
1939 * Constants & macros for individual CAU_STR_CA8 bitfields
1943 * @name Register CAU_STR_CA8, field CA8[31:0] (RO)
1946 #define BP_CAU_STR_CA8_CA8 (0U) /*!< Bit position for CAU_STR_CA8_CA8. */
1947 #define BM_CAU_STR_CA8_CA8 (0xFFFFFFFFU) /*!< Bit mask for CAU_STR_CA8_CA8. */
1948 #define BS_CAU_STR_CA8_CA8 (32U) /*!< Bit field size in bits for CAU_STR_CA8_CA8. */
1950 /*! @brief Read current value of the CAU_STR_CA8_CA8 field. */
1951 #define BR_CAU_STR_CA8_CA8(x) (HW_CAU_STR_CA8(x).U)
1954 /*******************************************************************************
1955 * HW_CAU_ADR_CASR - Status register - Add Register command
1956 ******************************************************************************/
1959 * @brief HW_CAU_ADR_CASR - Status register - Add Register command (WO)
1961 * Reset value: 0x20000000U
1963 typedef union _hw_cau_adr_casr
1966 struct _hw_cau_adr_casr_bitfields
1968 uint32_t IC
: 1; /*!< [0] */
1969 uint32_t DPE
: 1; /*!< [1] */
1970 uint32_t RESERVED0
: 26; /*!< [27:2] */
1971 uint32_t VER
: 4; /*!< [31:28] CAU version */
1973 } hw_cau_adr_casr_t
;
1976 * @name Constants and macros for entire CAU_ADR_CASR register
1979 #define HW_CAU_ADR_CASR_ADDR(x) ((x) + 0x8C0U)
1981 #define HW_CAU_ADR_CASR(x) (*(__O hw_cau_adr_casr_t *) HW_CAU_ADR_CASR_ADDR(x))
1982 #define HW_CAU_ADR_CASR_WR(x, v) (HW_CAU_ADR_CASR(x).U = (v))
1986 * Constants & macros for individual CAU_ADR_CASR bitfields
1990 * @name Register CAU_ADR_CASR, field IC[0] (WO)
1993 * - 0 - No illegal commands issued
1994 * - 1 - Illegal command issued
1997 #define BP_CAU_ADR_CASR_IC (0U) /*!< Bit position for CAU_ADR_CASR_IC. */
1998 #define BM_CAU_ADR_CASR_IC (0x00000001U) /*!< Bit mask for CAU_ADR_CASR_IC. */
1999 #define BS_CAU_ADR_CASR_IC (1U) /*!< Bit field size in bits for CAU_ADR_CASR_IC. */
2001 /*! @brief Format value for bitfield CAU_ADR_CASR_IC. */
2002 #define BF_CAU_ADR_CASR_IC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CASR_IC) & BM_CAU_ADR_CASR_IC)
2006 * @name Register CAU_ADR_CASR, field DPE[1] (WO)
2009 * - 0 - No error detected
2010 * - 1 - DES key parity error detected
2013 #define BP_CAU_ADR_CASR_DPE (1U) /*!< Bit position for CAU_ADR_CASR_DPE. */
2014 #define BM_CAU_ADR_CASR_DPE (0x00000002U) /*!< Bit mask for CAU_ADR_CASR_DPE. */
2015 #define BS_CAU_ADR_CASR_DPE (1U) /*!< Bit field size in bits for CAU_ADR_CASR_DPE. */
2017 /*! @brief Format value for bitfield CAU_ADR_CASR_DPE. */
2018 #define BF_CAU_ADR_CASR_DPE(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CASR_DPE) & BM_CAU_ADR_CASR_DPE)
2022 * @name Register CAU_ADR_CASR, field VER[31:28] (WO)
2025 * - 0001 - Initial CAU version
2026 * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
2027 * value on this device)
2030 #define BP_CAU_ADR_CASR_VER (28U) /*!< Bit position for CAU_ADR_CASR_VER. */
2031 #define BM_CAU_ADR_CASR_VER (0xF0000000U) /*!< Bit mask for CAU_ADR_CASR_VER. */
2032 #define BS_CAU_ADR_CASR_VER (4U) /*!< Bit field size in bits for CAU_ADR_CASR_VER. */
2034 /*! @brief Format value for bitfield CAU_ADR_CASR_VER. */
2035 #define BF_CAU_ADR_CASR_VER(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CASR_VER) & BM_CAU_ADR_CASR_VER)
2038 /*******************************************************************************
2039 * HW_CAU_ADR_CAA - Accumulator register - Add to register command
2040 ******************************************************************************/
2043 * @brief HW_CAU_ADR_CAA - Accumulator register - Add to register command (WO)
2045 * Reset value: 0x00000000U
2047 typedef union _hw_cau_adr_caa
2050 struct _hw_cau_adr_caa_bitfields
2052 uint32_t ACC
: 32; /*!< [31:0] ACC */
2057 * @name Constants and macros for entire CAU_ADR_CAA register
2060 #define HW_CAU_ADR_CAA_ADDR(x) ((x) + 0x8C4U)
2062 #define HW_CAU_ADR_CAA(x) (*(__O hw_cau_adr_caa_t *) HW_CAU_ADR_CAA_ADDR(x))
2063 #define HW_CAU_ADR_CAA_WR(x, v) (HW_CAU_ADR_CAA(x).U = (v))
2067 * Constants & macros for individual CAU_ADR_CAA bitfields
2071 * @name Register CAU_ADR_CAA, field ACC[31:0] (WO)
2074 #define BP_CAU_ADR_CAA_ACC (0U) /*!< Bit position for CAU_ADR_CAA_ACC. */
2075 #define BM_CAU_ADR_CAA_ACC (0xFFFFFFFFU) /*!< Bit mask for CAU_ADR_CAA_ACC. */
2076 #define BS_CAU_ADR_CAA_ACC (32U) /*!< Bit field size in bits for CAU_ADR_CAA_ACC. */
2078 /*! @brief Format value for bitfield CAU_ADR_CAA_ACC. */
2079 #define BF_CAU_ADR_CAA_ACC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CAA_ACC) & BM_CAU_ADR_CAA_ACC)
2082 /*******************************************************************************
2083 * HW_CAU_ADR_CA0 - General Purpose Register 0 - Add to register command
2084 ******************************************************************************/
2087 * @brief HW_CAU_ADR_CA0 - General Purpose Register 0 - Add to register command (WO)
2089 * Reset value: 0x00000000U
2091 typedef union _hw_cau_adr_ca0
2094 struct _hw_cau_adr_ca0_bitfields
2096 uint32_t CA0
: 32; /*!< [31:0] CA0 */
2101 * @name Constants and macros for entire CAU_ADR_CA0 register
2104 #define HW_CAU_ADR_CA0_ADDR(x) ((x) + 0x8C8U)
2106 #define HW_CAU_ADR_CA0(x) (*(__O hw_cau_adr_ca0_t *) HW_CAU_ADR_CA0_ADDR(x))
2107 #define HW_CAU_ADR_CA0_WR(x, v) (HW_CAU_ADR_CA0(x).U = (v))
2111 * Constants & macros for individual CAU_ADR_CA0 bitfields
2115 * @name Register CAU_ADR_CA0, field CA0[31:0] (WO)
2118 #define BP_CAU_ADR_CA0_CA0 (0U) /*!< Bit position for CAU_ADR_CA0_CA0. */
2119 #define BM_CAU_ADR_CA0_CA0 (0xFFFFFFFFU) /*!< Bit mask for CAU_ADR_CA0_CA0. */
2120 #define BS_CAU_ADR_CA0_CA0 (32U) /*!< Bit field size in bits for CAU_ADR_CA0_CA0. */
2122 /*! @brief Format value for bitfield CAU_ADR_CA0_CA0. */
2123 #define BF_CAU_ADR_CA0_CA0(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CA0_CA0) & BM_CAU_ADR_CA0_CA0)
2126 /*******************************************************************************
2127 * HW_CAU_ADR_CA1 - General Purpose Register 1 - Add to register command
2128 ******************************************************************************/
2131 * @brief HW_CAU_ADR_CA1 - General Purpose Register 1 - Add to register command (WO)
2133 * Reset value: 0x00000000U
2135 typedef union _hw_cau_adr_ca1
2138 struct _hw_cau_adr_ca1_bitfields
2140 uint32_t CA1
: 32; /*!< [31:0] CA1 */
2145 * @name Constants and macros for entire CAU_ADR_CA1 register
2148 #define HW_CAU_ADR_CA1_ADDR(x) ((x) + 0x8CCU)
2150 #define HW_CAU_ADR_CA1(x) (*(__O hw_cau_adr_ca1_t *) HW_CAU_ADR_CA1_ADDR(x))
2151 #define HW_CAU_ADR_CA1_WR(x, v) (HW_CAU_ADR_CA1(x).U = (v))
2155 * Constants & macros for individual CAU_ADR_CA1 bitfields
2159 * @name Register CAU_ADR_CA1, field CA1[31:0] (WO)
2162 #define BP_CAU_ADR_CA1_CA1 (0U) /*!< Bit position for CAU_ADR_CA1_CA1. */
2163 #define BM_CAU_ADR_CA1_CA1 (0xFFFFFFFFU) /*!< Bit mask for CAU_ADR_CA1_CA1. */
2164 #define BS_CAU_ADR_CA1_CA1 (32U) /*!< Bit field size in bits for CAU_ADR_CA1_CA1. */
2166 /*! @brief Format value for bitfield CAU_ADR_CA1_CA1. */
2167 #define BF_CAU_ADR_CA1_CA1(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CA1_CA1) & BM_CAU_ADR_CA1_CA1)
2170 /*******************************************************************************
2171 * HW_CAU_ADR_CA2 - General Purpose Register 2 - Add to register command
2172 ******************************************************************************/
2175 * @brief HW_CAU_ADR_CA2 - General Purpose Register 2 - Add to register command (WO)
2177 * Reset value: 0x00000000U
2179 typedef union _hw_cau_adr_ca2
2182 struct _hw_cau_adr_ca2_bitfields
2184 uint32_t CA2
: 32; /*!< [31:0] CA2 */
2189 * @name Constants and macros for entire CAU_ADR_CA2 register
2192 #define HW_CAU_ADR_CA2_ADDR(x) ((x) + 0x8D0U)
2194 #define HW_CAU_ADR_CA2(x) (*(__O hw_cau_adr_ca2_t *) HW_CAU_ADR_CA2_ADDR(x))
2195 #define HW_CAU_ADR_CA2_WR(x, v) (HW_CAU_ADR_CA2(x).U = (v))
2199 * Constants & macros for individual CAU_ADR_CA2 bitfields
2203 * @name Register CAU_ADR_CA2, field CA2[31:0] (WO)
2206 #define BP_CAU_ADR_CA2_CA2 (0U) /*!< Bit position for CAU_ADR_CA2_CA2. */
2207 #define BM_CAU_ADR_CA2_CA2 (0xFFFFFFFFU) /*!< Bit mask for CAU_ADR_CA2_CA2. */
2208 #define BS_CAU_ADR_CA2_CA2 (32U) /*!< Bit field size in bits for CAU_ADR_CA2_CA2. */
2210 /*! @brief Format value for bitfield CAU_ADR_CA2_CA2. */
2211 #define BF_CAU_ADR_CA2_CA2(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CA2_CA2) & BM_CAU_ADR_CA2_CA2)
2214 /*******************************************************************************
2215 * HW_CAU_ADR_CA3 - General Purpose Register 3 - Add to register command
2216 ******************************************************************************/
2219 * @brief HW_CAU_ADR_CA3 - General Purpose Register 3 - Add to register command (WO)
2221 * Reset value: 0x00000000U
2223 typedef union _hw_cau_adr_ca3
2226 struct _hw_cau_adr_ca3_bitfields
2228 uint32_t CA3
: 32; /*!< [31:0] CA3 */
2233 * @name Constants and macros for entire CAU_ADR_CA3 register
2236 #define HW_CAU_ADR_CA3_ADDR(x) ((x) + 0x8D4U)
2238 #define HW_CAU_ADR_CA3(x) (*(__O hw_cau_adr_ca3_t *) HW_CAU_ADR_CA3_ADDR(x))
2239 #define HW_CAU_ADR_CA3_WR(x, v) (HW_CAU_ADR_CA3(x).U = (v))
2243 * Constants & macros for individual CAU_ADR_CA3 bitfields
2247 * @name Register CAU_ADR_CA3, field CA3[31:0] (WO)
2250 #define BP_CAU_ADR_CA3_CA3 (0U) /*!< Bit position for CAU_ADR_CA3_CA3. */
2251 #define BM_CAU_ADR_CA3_CA3 (0xFFFFFFFFU) /*!< Bit mask for CAU_ADR_CA3_CA3. */
2252 #define BS_CAU_ADR_CA3_CA3 (32U) /*!< Bit field size in bits for CAU_ADR_CA3_CA3. */
2254 /*! @brief Format value for bitfield CAU_ADR_CA3_CA3. */
2255 #define BF_CAU_ADR_CA3_CA3(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CA3_CA3) & BM_CAU_ADR_CA3_CA3)
2258 /*******************************************************************************
2259 * HW_CAU_ADR_CA4 - General Purpose Register 4 - Add to register command
2260 ******************************************************************************/
2263 * @brief HW_CAU_ADR_CA4 - General Purpose Register 4 - Add to register command (WO)
2265 * Reset value: 0x00000000U
2267 typedef union _hw_cau_adr_ca4
2270 struct _hw_cau_adr_ca4_bitfields
2272 uint32_t CA4
: 32; /*!< [31:0] CA4 */
2277 * @name Constants and macros for entire CAU_ADR_CA4 register
2280 #define HW_CAU_ADR_CA4_ADDR(x) ((x) + 0x8D8U)
2282 #define HW_CAU_ADR_CA4(x) (*(__O hw_cau_adr_ca4_t *) HW_CAU_ADR_CA4_ADDR(x))
2283 #define HW_CAU_ADR_CA4_WR(x, v) (HW_CAU_ADR_CA4(x).U = (v))
2287 * Constants & macros for individual CAU_ADR_CA4 bitfields
2291 * @name Register CAU_ADR_CA4, field CA4[31:0] (WO)
2294 #define BP_CAU_ADR_CA4_CA4 (0U) /*!< Bit position for CAU_ADR_CA4_CA4. */
2295 #define BM_CAU_ADR_CA4_CA4 (0xFFFFFFFFU) /*!< Bit mask for CAU_ADR_CA4_CA4. */
2296 #define BS_CAU_ADR_CA4_CA4 (32U) /*!< Bit field size in bits for CAU_ADR_CA4_CA4. */
2298 /*! @brief Format value for bitfield CAU_ADR_CA4_CA4. */
2299 #define BF_CAU_ADR_CA4_CA4(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CA4_CA4) & BM_CAU_ADR_CA4_CA4)
2302 /*******************************************************************************
2303 * HW_CAU_ADR_CA5 - General Purpose Register 5 - Add to register command
2304 ******************************************************************************/
2307 * @brief HW_CAU_ADR_CA5 - General Purpose Register 5 - Add to register command (WO)
2309 * Reset value: 0x00000000U
2311 typedef union _hw_cau_adr_ca5
2314 struct _hw_cau_adr_ca5_bitfields
2316 uint32_t CA5
: 32; /*!< [31:0] CA5 */
2321 * @name Constants and macros for entire CAU_ADR_CA5 register
2324 #define HW_CAU_ADR_CA5_ADDR(x) ((x) + 0x8DCU)
2326 #define HW_CAU_ADR_CA5(x) (*(__O hw_cau_adr_ca5_t *) HW_CAU_ADR_CA5_ADDR(x))
2327 #define HW_CAU_ADR_CA5_WR(x, v) (HW_CAU_ADR_CA5(x).U = (v))
2331 * Constants & macros for individual CAU_ADR_CA5 bitfields
2335 * @name Register CAU_ADR_CA5, field CA5[31:0] (WO)
2338 #define BP_CAU_ADR_CA5_CA5 (0U) /*!< Bit position for CAU_ADR_CA5_CA5. */
2339 #define BM_CAU_ADR_CA5_CA5 (0xFFFFFFFFU) /*!< Bit mask for CAU_ADR_CA5_CA5. */
2340 #define BS_CAU_ADR_CA5_CA5 (32U) /*!< Bit field size in bits for CAU_ADR_CA5_CA5. */
2342 /*! @brief Format value for bitfield CAU_ADR_CA5_CA5. */
2343 #define BF_CAU_ADR_CA5_CA5(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CA5_CA5) & BM_CAU_ADR_CA5_CA5)
2346 /*******************************************************************************
2347 * HW_CAU_ADR_CA6 - General Purpose Register 6 - Add to register command
2348 ******************************************************************************/
2351 * @brief HW_CAU_ADR_CA6 - General Purpose Register 6 - Add to register command (WO)
2353 * Reset value: 0x00000000U
2355 typedef union _hw_cau_adr_ca6
2358 struct _hw_cau_adr_ca6_bitfields
2360 uint32_t CA6
: 32; /*!< [31:0] CA6 */
2365 * @name Constants and macros for entire CAU_ADR_CA6 register
2368 #define HW_CAU_ADR_CA6_ADDR(x) ((x) + 0x8E0U)
2370 #define HW_CAU_ADR_CA6(x) (*(__O hw_cau_adr_ca6_t *) HW_CAU_ADR_CA6_ADDR(x))
2371 #define HW_CAU_ADR_CA6_WR(x, v) (HW_CAU_ADR_CA6(x).U = (v))
2375 * Constants & macros for individual CAU_ADR_CA6 bitfields
2379 * @name Register CAU_ADR_CA6, field CA6[31:0] (WO)
2382 #define BP_CAU_ADR_CA6_CA6 (0U) /*!< Bit position for CAU_ADR_CA6_CA6. */
2383 #define BM_CAU_ADR_CA6_CA6 (0xFFFFFFFFU) /*!< Bit mask for CAU_ADR_CA6_CA6. */
2384 #define BS_CAU_ADR_CA6_CA6 (32U) /*!< Bit field size in bits for CAU_ADR_CA6_CA6. */
2386 /*! @brief Format value for bitfield CAU_ADR_CA6_CA6. */
2387 #define BF_CAU_ADR_CA6_CA6(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CA6_CA6) & BM_CAU_ADR_CA6_CA6)
2390 /*******************************************************************************
2391 * HW_CAU_ADR_CA7 - General Purpose Register 7 - Add to register command
2392 ******************************************************************************/
2395 * @brief HW_CAU_ADR_CA7 - General Purpose Register 7 - Add to register command (WO)
2397 * Reset value: 0x00000000U
2399 typedef union _hw_cau_adr_ca7
2402 struct _hw_cau_adr_ca7_bitfields
2404 uint32_t CA7
: 32; /*!< [31:0] CA7 */
2409 * @name Constants and macros for entire CAU_ADR_CA7 register
2412 #define HW_CAU_ADR_CA7_ADDR(x) ((x) + 0x8E4U)
2414 #define HW_CAU_ADR_CA7(x) (*(__O hw_cau_adr_ca7_t *) HW_CAU_ADR_CA7_ADDR(x))
2415 #define HW_CAU_ADR_CA7_WR(x, v) (HW_CAU_ADR_CA7(x).U = (v))
2419 * Constants & macros for individual CAU_ADR_CA7 bitfields
2423 * @name Register CAU_ADR_CA7, field CA7[31:0] (WO)
2426 #define BP_CAU_ADR_CA7_CA7 (0U) /*!< Bit position for CAU_ADR_CA7_CA7. */
2427 #define BM_CAU_ADR_CA7_CA7 (0xFFFFFFFFU) /*!< Bit mask for CAU_ADR_CA7_CA7. */
2428 #define BS_CAU_ADR_CA7_CA7 (32U) /*!< Bit field size in bits for CAU_ADR_CA7_CA7. */
2430 /*! @brief Format value for bitfield CAU_ADR_CA7_CA7. */
2431 #define BF_CAU_ADR_CA7_CA7(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CA7_CA7) & BM_CAU_ADR_CA7_CA7)
2434 /*******************************************************************************
2435 * HW_CAU_ADR_CA8 - General Purpose Register 8 - Add to register command
2436 ******************************************************************************/
2439 * @brief HW_CAU_ADR_CA8 - General Purpose Register 8 - Add to register command (WO)
2441 * Reset value: 0x00000000U
2443 typedef union _hw_cau_adr_ca8
2446 struct _hw_cau_adr_ca8_bitfields
2448 uint32_t CA8
: 32; /*!< [31:0] CA8 */
2453 * @name Constants and macros for entire CAU_ADR_CA8 register
2456 #define HW_CAU_ADR_CA8_ADDR(x) ((x) + 0x8E8U)
2458 #define HW_CAU_ADR_CA8(x) (*(__O hw_cau_adr_ca8_t *) HW_CAU_ADR_CA8_ADDR(x))
2459 #define HW_CAU_ADR_CA8_WR(x, v) (HW_CAU_ADR_CA8(x).U = (v))
2463 * Constants & macros for individual CAU_ADR_CA8 bitfields
2467 * @name Register CAU_ADR_CA8, field CA8[31:0] (WO)
2470 #define BP_CAU_ADR_CA8_CA8 (0U) /*!< Bit position for CAU_ADR_CA8_CA8. */
2471 #define BM_CAU_ADR_CA8_CA8 (0xFFFFFFFFU) /*!< Bit mask for CAU_ADR_CA8_CA8. */
2472 #define BS_CAU_ADR_CA8_CA8 (32U) /*!< Bit field size in bits for CAU_ADR_CA8_CA8. */
2474 /*! @brief Format value for bitfield CAU_ADR_CA8_CA8. */
2475 #define BF_CAU_ADR_CA8_CA8(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CA8_CA8) & BM_CAU_ADR_CA8_CA8)
2478 /*******************************************************************************
2479 * HW_CAU_RADR_CASR - Status register - Reverse and Add to Register command
2480 ******************************************************************************/
2483 * @brief HW_CAU_RADR_CASR - Status register - Reverse and Add to Register command (WO)
2485 * Reset value: 0x20000000U
2487 typedef union _hw_cau_radr_casr
2490 struct _hw_cau_radr_casr_bitfields
2492 uint32_t IC
: 1; /*!< [0] */
2493 uint32_t DPE
: 1; /*!< [1] */
2494 uint32_t RESERVED0
: 26; /*!< [27:2] */
2495 uint32_t VER
: 4; /*!< [31:28] CAU version */
2497 } hw_cau_radr_casr_t
;
2500 * @name Constants and macros for entire CAU_RADR_CASR register
2503 #define HW_CAU_RADR_CASR_ADDR(x) ((x) + 0x900U)
2505 #define HW_CAU_RADR_CASR(x) (*(__O hw_cau_radr_casr_t *) HW_CAU_RADR_CASR_ADDR(x))
2506 #define HW_CAU_RADR_CASR_WR(x, v) (HW_CAU_RADR_CASR(x).U = (v))
2510 * Constants & macros for individual CAU_RADR_CASR bitfields
2514 * @name Register CAU_RADR_CASR, field IC[0] (WO)
2517 * - 0 - No illegal commands issued
2518 * - 1 - Illegal command issued
2521 #define BP_CAU_RADR_CASR_IC (0U) /*!< Bit position for CAU_RADR_CASR_IC. */
2522 #define BM_CAU_RADR_CASR_IC (0x00000001U) /*!< Bit mask for CAU_RADR_CASR_IC. */
2523 #define BS_CAU_RADR_CASR_IC (1U) /*!< Bit field size in bits for CAU_RADR_CASR_IC. */
2525 /*! @brief Format value for bitfield CAU_RADR_CASR_IC. */
2526 #define BF_CAU_RADR_CASR_IC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CASR_IC) & BM_CAU_RADR_CASR_IC)
2530 * @name Register CAU_RADR_CASR, field DPE[1] (WO)
2533 * - 0 - No error detected
2534 * - 1 - DES key parity error detected
2537 #define BP_CAU_RADR_CASR_DPE (1U) /*!< Bit position for CAU_RADR_CASR_DPE. */
2538 #define BM_CAU_RADR_CASR_DPE (0x00000002U) /*!< Bit mask for CAU_RADR_CASR_DPE. */
2539 #define BS_CAU_RADR_CASR_DPE (1U) /*!< Bit field size in bits for CAU_RADR_CASR_DPE. */
2541 /*! @brief Format value for bitfield CAU_RADR_CASR_DPE. */
2542 #define BF_CAU_RADR_CASR_DPE(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CASR_DPE) & BM_CAU_RADR_CASR_DPE)
2546 * @name Register CAU_RADR_CASR, field VER[31:28] (WO)
2549 * - 0001 - Initial CAU version
2550 * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
2551 * value on this device)
2554 #define BP_CAU_RADR_CASR_VER (28U) /*!< Bit position for CAU_RADR_CASR_VER. */
2555 #define BM_CAU_RADR_CASR_VER (0xF0000000U) /*!< Bit mask for CAU_RADR_CASR_VER. */
2556 #define BS_CAU_RADR_CASR_VER (4U) /*!< Bit field size in bits for CAU_RADR_CASR_VER. */
2558 /*! @brief Format value for bitfield CAU_RADR_CASR_VER. */
2559 #define BF_CAU_RADR_CASR_VER(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CASR_VER) & BM_CAU_RADR_CASR_VER)
2562 /*******************************************************************************
2563 * HW_CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command
2564 ******************************************************************************/
2567 * @brief HW_CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command (WO)
2569 * Reset value: 0x00000000U
2571 typedef union _hw_cau_radr_caa
2574 struct _hw_cau_radr_caa_bitfields
2576 uint32_t ACC
: 32; /*!< [31:0] ACC */
2578 } hw_cau_radr_caa_t
;
2581 * @name Constants and macros for entire CAU_RADR_CAA register
2584 #define HW_CAU_RADR_CAA_ADDR(x) ((x) + 0x904U)
2586 #define HW_CAU_RADR_CAA(x) (*(__O hw_cau_radr_caa_t *) HW_CAU_RADR_CAA_ADDR(x))
2587 #define HW_CAU_RADR_CAA_WR(x, v) (HW_CAU_RADR_CAA(x).U = (v))
2591 * Constants & macros for individual CAU_RADR_CAA bitfields
2595 * @name Register CAU_RADR_CAA, field ACC[31:0] (WO)
2598 #define BP_CAU_RADR_CAA_ACC (0U) /*!< Bit position for CAU_RADR_CAA_ACC. */
2599 #define BM_CAU_RADR_CAA_ACC (0xFFFFFFFFU) /*!< Bit mask for CAU_RADR_CAA_ACC. */
2600 #define BS_CAU_RADR_CAA_ACC (32U) /*!< Bit field size in bits for CAU_RADR_CAA_ACC. */
2602 /*! @brief Format value for bitfield CAU_RADR_CAA_ACC. */
2603 #define BF_CAU_RADR_CAA_ACC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CAA_ACC) & BM_CAU_RADR_CAA_ACC)
2606 /*******************************************************************************
2607 * HW_CAU_RADR_CA0 - General Purpose Register 0 - Reverse and Add to Register command
2608 ******************************************************************************/
2611 * @brief HW_CAU_RADR_CA0 - General Purpose Register 0 - Reverse and Add to Register command (WO)
2613 * Reset value: 0x00000000U
2615 typedef union _hw_cau_radr_ca0
2618 struct _hw_cau_radr_ca0_bitfields
2620 uint32_t CA0
: 32; /*!< [31:0] CA0 */
2622 } hw_cau_radr_ca0_t
;
2625 * @name Constants and macros for entire CAU_RADR_CA0 register
2628 #define HW_CAU_RADR_CA0_ADDR(x) ((x) + 0x908U)
2630 #define HW_CAU_RADR_CA0(x) (*(__O hw_cau_radr_ca0_t *) HW_CAU_RADR_CA0_ADDR(x))
2631 #define HW_CAU_RADR_CA0_WR(x, v) (HW_CAU_RADR_CA0(x).U = (v))
2635 * Constants & macros for individual CAU_RADR_CA0 bitfields
2639 * @name Register CAU_RADR_CA0, field CA0[31:0] (WO)
2642 #define BP_CAU_RADR_CA0_CA0 (0U) /*!< Bit position for CAU_RADR_CA0_CA0. */
2643 #define BM_CAU_RADR_CA0_CA0 (0xFFFFFFFFU) /*!< Bit mask for CAU_RADR_CA0_CA0. */
2644 #define BS_CAU_RADR_CA0_CA0 (32U) /*!< Bit field size in bits for CAU_RADR_CA0_CA0. */
2646 /*! @brief Format value for bitfield CAU_RADR_CA0_CA0. */
2647 #define BF_CAU_RADR_CA0_CA0(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CA0_CA0) & BM_CAU_RADR_CA0_CA0)
2650 /*******************************************************************************
2651 * HW_CAU_RADR_CA1 - General Purpose Register 1 - Reverse and Add to Register command
2652 ******************************************************************************/
2655 * @brief HW_CAU_RADR_CA1 - General Purpose Register 1 - Reverse and Add to Register command (WO)
2657 * Reset value: 0x00000000U
2659 typedef union _hw_cau_radr_ca1
2662 struct _hw_cau_radr_ca1_bitfields
2664 uint32_t CA1
: 32; /*!< [31:0] CA1 */
2666 } hw_cau_radr_ca1_t
;
2669 * @name Constants and macros for entire CAU_RADR_CA1 register
2672 #define HW_CAU_RADR_CA1_ADDR(x) ((x) + 0x90CU)
2674 #define HW_CAU_RADR_CA1(x) (*(__O hw_cau_radr_ca1_t *) HW_CAU_RADR_CA1_ADDR(x))
2675 #define HW_CAU_RADR_CA1_WR(x, v) (HW_CAU_RADR_CA1(x).U = (v))
2679 * Constants & macros for individual CAU_RADR_CA1 bitfields
2683 * @name Register CAU_RADR_CA1, field CA1[31:0] (WO)
2686 #define BP_CAU_RADR_CA1_CA1 (0U) /*!< Bit position for CAU_RADR_CA1_CA1. */
2687 #define BM_CAU_RADR_CA1_CA1 (0xFFFFFFFFU) /*!< Bit mask for CAU_RADR_CA1_CA1. */
2688 #define BS_CAU_RADR_CA1_CA1 (32U) /*!< Bit field size in bits for CAU_RADR_CA1_CA1. */
2690 /*! @brief Format value for bitfield CAU_RADR_CA1_CA1. */
2691 #define BF_CAU_RADR_CA1_CA1(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CA1_CA1) & BM_CAU_RADR_CA1_CA1)
2694 /*******************************************************************************
2695 * HW_CAU_RADR_CA2 - General Purpose Register 2 - Reverse and Add to Register command
2696 ******************************************************************************/
2699 * @brief HW_CAU_RADR_CA2 - General Purpose Register 2 - Reverse and Add to Register command (WO)
2701 * Reset value: 0x00000000U
2703 typedef union _hw_cau_radr_ca2
2706 struct _hw_cau_radr_ca2_bitfields
2708 uint32_t CA2
: 32; /*!< [31:0] CA2 */
2710 } hw_cau_radr_ca2_t
;
2713 * @name Constants and macros for entire CAU_RADR_CA2 register
2716 #define HW_CAU_RADR_CA2_ADDR(x) ((x) + 0x910U)
2718 #define HW_CAU_RADR_CA2(x) (*(__O hw_cau_radr_ca2_t *) HW_CAU_RADR_CA2_ADDR(x))
2719 #define HW_CAU_RADR_CA2_WR(x, v) (HW_CAU_RADR_CA2(x).U = (v))
2723 * Constants & macros for individual CAU_RADR_CA2 bitfields
2727 * @name Register CAU_RADR_CA2, field CA2[31:0] (WO)
2730 #define BP_CAU_RADR_CA2_CA2 (0U) /*!< Bit position for CAU_RADR_CA2_CA2. */
2731 #define BM_CAU_RADR_CA2_CA2 (0xFFFFFFFFU) /*!< Bit mask for CAU_RADR_CA2_CA2. */
2732 #define BS_CAU_RADR_CA2_CA2 (32U) /*!< Bit field size in bits for CAU_RADR_CA2_CA2. */
2734 /*! @brief Format value for bitfield CAU_RADR_CA2_CA2. */
2735 #define BF_CAU_RADR_CA2_CA2(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CA2_CA2) & BM_CAU_RADR_CA2_CA2)
2738 /*******************************************************************************
2739 * HW_CAU_RADR_CA3 - General Purpose Register 3 - Reverse and Add to Register command
2740 ******************************************************************************/
2743 * @brief HW_CAU_RADR_CA3 - General Purpose Register 3 - Reverse and Add to Register command (WO)
2745 * Reset value: 0x00000000U
2747 typedef union _hw_cau_radr_ca3
2750 struct _hw_cau_radr_ca3_bitfields
2752 uint32_t CA3
: 32; /*!< [31:0] CA3 */
2754 } hw_cau_radr_ca3_t
;
2757 * @name Constants and macros for entire CAU_RADR_CA3 register
2760 #define HW_CAU_RADR_CA3_ADDR(x) ((x) + 0x914U)
2762 #define HW_CAU_RADR_CA3(x) (*(__O hw_cau_radr_ca3_t *) HW_CAU_RADR_CA3_ADDR(x))
2763 #define HW_CAU_RADR_CA3_WR(x, v) (HW_CAU_RADR_CA3(x).U = (v))
2767 * Constants & macros for individual CAU_RADR_CA3 bitfields
2771 * @name Register CAU_RADR_CA3, field CA3[31:0] (WO)
2774 #define BP_CAU_RADR_CA3_CA3 (0U) /*!< Bit position for CAU_RADR_CA3_CA3. */
2775 #define BM_CAU_RADR_CA3_CA3 (0xFFFFFFFFU) /*!< Bit mask for CAU_RADR_CA3_CA3. */
2776 #define BS_CAU_RADR_CA3_CA3 (32U) /*!< Bit field size in bits for CAU_RADR_CA3_CA3. */
2778 /*! @brief Format value for bitfield CAU_RADR_CA3_CA3. */
2779 #define BF_CAU_RADR_CA3_CA3(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CA3_CA3) & BM_CAU_RADR_CA3_CA3)
2782 /*******************************************************************************
2783 * HW_CAU_RADR_CA4 - General Purpose Register 4 - Reverse and Add to Register command
2784 ******************************************************************************/
2787 * @brief HW_CAU_RADR_CA4 - General Purpose Register 4 - Reverse and Add to Register command (WO)
2789 * Reset value: 0x00000000U
2791 typedef union _hw_cau_radr_ca4
2794 struct _hw_cau_radr_ca4_bitfields
2796 uint32_t CA4
: 32; /*!< [31:0] CA4 */
2798 } hw_cau_radr_ca4_t
;
2801 * @name Constants and macros for entire CAU_RADR_CA4 register
2804 #define HW_CAU_RADR_CA4_ADDR(x) ((x) + 0x918U)
2806 #define HW_CAU_RADR_CA4(x) (*(__O hw_cau_radr_ca4_t *) HW_CAU_RADR_CA4_ADDR(x))
2807 #define HW_CAU_RADR_CA4_WR(x, v) (HW_CAU_RADR_CA4(x).U = (v))
2811 * Constants & macros for individual CAU_RADR_CA4 bitfields
2815 * @name Register CAU_RADR_CA4, field CA4[31:0] (WO)
2818 #define BP_CAU_RADR_CA4_CA4 (0U) /*!< Bit position for CAU_RADR_CA4_CA4. */
2819 #define BM_CAU_RADR_CA4_CA4 (0xFFFFFFFFU) /*!< Bit mask for CAU_RADR_CA4_CA4. */
2820 #define BS_CAU_RADR_CA4_CA4 (32U) /*!< Bit field size in bits for CAU_RADR_CA4_CA4. */
2822 /*! @brief Format value for bitfield CAU_RADR_CA4_CA4. */
2823 #define BF_CAU_RADR_CA4_CA4(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CA4_CA4) & BM_CAU_RADR_CA4_CA4)
2826 /*******************************************************************************
2827 * HW_CAU_RADR_CA5 - General Purpose Register 5 - Reverse and Add to Register command
2828 ******************************************************************************/
2831 * @brief HW_CAU_RADR_CA5 - General Purpose Register 5 - Reverse and Add to Register command (WO)
2833 * Reset value: 0x00000000U
2835 typedef union _hw_cau_radr_ca5
2838 struct _hw_cau_radr_ca5_bitfields
2840 uint32_t CA5
: 32; /*!< [31:0] CA5 */
2842 } hw_cau_radr_ca5_t
;
2845 * @name Constants and macros for entire CAU_RADR_CA5 register
2848 #define HW_CAU_RADR_CA5_ADDR(x) ((x) + 0x91CU)
2850 #define HW_CAU_RADR_CA5(x) (*(__O hw_cau_radr_ca5_t *) HW_CAU_RADR_CA5_ADDR(x))
2851 #define HW_CAU_RADR_CA5_WR(x, v) (HW_CAU_RADR_CA5(x).U = (v))
2855 * Constants & macros for individual CAU_RADR_CA5 bitfields
2859 * @name Register CAU_RADR_CA5, field CA5[31:0] (WO)
2862 #define BP_CAU_RADR_CA5_CA5 (0U) /*!< Bit position for CAU_RADR_CA5_CA5. */
2863 #define BM_CAU_RADR_CA5_CA5 (0xFFFFFFFFU) /*!< Bit mask for CAU_RADR_CA5_CA5. */
2864 #define BS_CAU_RADR_CA5_CA5 (32U) /*!< Bit field size in bits for CAU_RADR_CA5_CA5. */
2866 /*! @brief Format value for bitfield CAU_RADR_CA5_CA5. */
2867 #define BF_CAU_RADR_CA5_CA5(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CA5_CA5) & BM_CAU_RADR_CA5_CA5)
2870 /*******************************************************************************
2871 * HW_CAU_RADR_CA6 - General Purpose Register 6 - Reverse and Add to Register command
2872 ******************************************************************************/
2875 * @brief HW_CAU_RADR_CA6 - General Purpose Register 6 - Reverse and Add to Register command (WO)
2877 * Reset value: 0x00000000U
2879 typedef union _hw_cau_radr_ca6
2882 struct _hw_cau_radr_ca6_bitfields
2884 uint32_t CA6
: 32; /*!< [31:0] CA6 */
2886 } hw_cau_radr_ca6_t
;
2889 * @name Constants and macros for entire CAU_RADR_CA6 register
2892 #define HW_CAU_RADR_CA6_ADDR(x) ((x) + 0x920U)
2894 #define HW_CAU_RADR_CA6(x) (*(__O hw_cau_radr_ca6_t *) HW_CAU_RADR_CA6_ADDR(x))
2895 #define HW_CAU_RADR_CA6_WR(x, v) (HW_CAU_RADR_CA6(x).U = (v))
2899 * Constants & macros for individual CAU_RADR_CA6 bitfields
2903 * @name Register CAU_RADR_CA6, field CA6[31:0] (WO)
2906 #define BP_CAU_RADR_CA6_CA6 (0U) /*!< Bit position for CAU_RADR_CA6_CA6. */
2907 #define BM_CAU_RADR_CA6_CA6 (0xFFFFFFFFU) /*!< Bit mask for CAU_RADR_CA6_CA6. */
2908 #define BS_CAU_RADR_CA6_CA6 (32U) /*!< Bit field size in bits for CAU_RADR_CA6_CA6. */
2910 /*! @brief Format value for bitfield CAU_RADR_CA6_CA6. */
2911 #define BF_CAU_RADR_CA6_CA6(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CA6_CA6) & BM_CAU_RADR_CA6_CA6)
2914 /*******************************************************************************
2915 * HW_CAU_RADR_CA7 - General Purpose Register 7 - Reverse and Add to Register command
2916 ******************************************************************************/
2919 * @brief HW_CAU_RADR_CA7 - General Purpose Register 7 - Reverse and Add to Register command (WO)
2921 * Reset value: 0x00000000U
2923 typedef union _hw_cau_radr_ca7
2926 struct _hw_cau_radr_ca7_bitfields
2928 uint32_t CA7
: 32; /*!< [31:0] CA7 */
2930 } hw_cau_radr_ca7_t
;
2933 * @name Constants and macros for entire CAU_RADR_CA7 register
2936 #define HW_CAU_RADR_CA7_ADDR(x) ((x) + 0x924U)
2938 #define HW_CAU_RADR_CA7(x) (*(__O hw_cau_radr_ca7_t *) HW_CAU_RADR_CA7_ADDR(x))
2939 #define HW_CAU_RADR_CA7_WR(x, v) (HW_CAU_RADR_CA7(x).U = (v))
2943 * Constants & macros for individual CAU_RADR_CA7 bitfields
2947 * @name Register CAU_RADR_CA7, field CA7[31:0] (WO)
2950 #define BP_CAU_RADR_CA7_CA7 (0U) /*!< Bit position for CAU_RADR_CA7_CA7. */
2951 #define BM_CAU_RADR_CA7_CA7 (0xFFFFFFFFU) /*!< Bit mask for CAU_RADR_CA7_CA7. */
2952 #define BS_CAU_RADR_CA7_CA7 (32U) /*!< Bit field size in bits for CAU_RADR_CA7_CA7. */
2954 /*! @brief Format value for bitfield CAU_RADR_CA7_CA7. */
2955 #define BF_CAU_RADR_CA7_CA7(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CA7_CA7) & BM_CAU_RADR_CA7_CA7)
2958 /*******************************************************************************
2959 * HW_CAU_RADR_CA8 - General Purpose Register 8 - Reverse and Add to Register command
2960 ******************************************************************************/
2963 * @brief HW_CAU_RADR_CA8 - General Purpose Register 8 - Reverse and Add to Register command (WO)
2965 * Reset value: 0x00000000U
2967 typedef union _hw_cau_radr_ca8
2970 struct _hw_cau_radr_ca8_bitfields
2972 uint32_t CA8
: 32; /*!< [31:0] CA8 */
2974 } hw_cau_radr_ca8_t
;
2977 * @name Constants and macros for entire CAU_RADR_CA8 register
2980 #define HW_CAU_RADR_CA8_ADDR(x) ((x) + 0x928U)
2982 #define HW_CAU_RADR_CA8(x) (*(__O hw_cau_radr_ca8_t *) HW_CAU_RADR_CA8_ADDR(x))
2983 #define HW_CAU_RADR_CA8_WR(x, v) (HW_CAU_RADR_CA8(x).U = (v))
2987 * Constants & macros for individual CAU_RADR_CA8 bitfields
2991 * @name Register CAU_RADR_CA8, field CA8[31:0] (WO)
2994 #define BP_CAU_RADR_CA8_CA8 (0U) /*!< Bit position for CAU_RADR_CA8_CA8. */
2995 #define BM_CAU_RADR_CA8_CA8 (0xFFFFFFFFU) /*!< Bit mask for CAU_RADR_CA8_CA8. */
2996 #define BS_CAU_RADR_CA8_CA8 (32U) /*!< Bit field size in bits for CAU_RADR_CA8_CA8. */
2998 /*! @brief Format value for bitfield CAU_RADR_CA8_CA8. */
2999 #define BF_CAU_RADR_CA8_CA8(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CA8_CA8) & BM_CAU_RADR_CA8_CA8)
3002 /*******************************************************************************
3003 * HW_CAU_XOR_CASR - Status register - Exclusive Or command
3004 ******************************************************************************/
3007 * @brief HW_CAU_XOR_CASR - Status register - Exclusive Or command (WO)
3009 * Reset value: 0x20000000U
3011 typedef union _hw_cau_xor_casr
3014 struct _hw_cau_xor_casr_bitfields
3016 uint32_t IC
: 1; /*!< [0] */
3017 uint32_t DPE
: 1; /*!< [1] */
3018 uint32_t RESERVED0
: 26; /*!< [27:2] */
3019 uint32_t VER
: 4; /*!< [31:28] CAU version */
3021 } hw_cau_xor_casr_t
;
3024 * @name Constants and macros for entire CAU_XOR_CASR register
3027 #define HW_CAU_XOR_CASR_ADDR(x) ((x) + 0x980U)
3029 #define HW_CAU_XOR_CASR(x) (*(__O hw_cau_xor_casr_t *) HW_CAU_XOR_CASR_ADDR(x))
3030 #define HW_CAU_XOR_CASR_WR(x, v) (HW_CAU_XOR_CASR(x).U = (v))
3034 * Constants & macros for individual CAU_XOR_CASR bitfields
3038 * @name Register CAU_XOR_CASR, field IC[0] (WO)
3041 * - 0 - No illegal commands issued
3042 * - 1 - Illegal command issued
3045 #define BP_CAU_XOR_CASR_IC (0U) /*!< Bit position for CAU_XOR_CASR_IC. */
3046 #define BM_CAU_XOR_CASR_IC (0x00000001U) /*!< Bit mask for CAU_XOR_CASR_IC. */
3047 #define BS_CAU_XOR_CASR_IC (1U) /*!< Bit field size in bits for CAU_XOR_CASR_IC. */
3049 /*! @brief Format value for bitfield CAU_XOR_CASR_IC. */
3050 #define BF_CAU_XOR_CASR_IC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CASR_IC) & BM_CAU_XOR_CASR_IC)
3054 * @name Register CAU_XOR_CASR, field DPE[1] (WO)
3057 * - 0 - No error detected
3058 * - 1 - DES key parity error detected
3061 #define BP_CAU_XOR_CASR_DPE (1U) /*!< Bit position for CAU_XOR_CASR_DPE. */
3062 #define BM_CAU_XOR_CASR_DPE (0x00000002U) /*!< Bit mask for CAU_XOR_CASR_DPE. */
3063 #define BS_CAU_XOR_CASR_DPE (1U) /*!< Bit field size in bits for CAU_XOR_CASR_DPE. */
3065 /*! @brief Format value for bitfield CAU_XOR_CASR_DPE. */
3066 #define BF_CAU_XOR_CASR_DPE(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CASR_DPE) & BM_CAU_XOR_CASR_DPE)
3070 * @name Register CAU_XOR_CASR, field VER[31:28] (WO)
3073 * - 0001 - Initial CAU version
3074 * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
3075 * value on this device)
3078 #define BP_CAU_XOR_CASR_VER (28U) /*!< Bit position for CAU_XOR_CASR_VER. */
3079 #define BM_CAU_XOR_CASR_VER (0xF0000000U) /*!< Bit mask for CAU_XOR_CASR_VER. */
3080 #define BS_CAU_XOR_CASR_VER (4U) /*!< Bit field size in bits for CAU_XOR_CASR_VER. */
3082 /*! @brief Format value for bitfield CAU_XOR_CASR_VER. */
3083 #define BF_CAU_XOR_CASR_VER(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CASR_VER) & BM_CAU_XOR_CASR_VER)
3086 /*******************************************************************************
3087 * HW_CAU_XOR_CAA - Accumulator register - Exclusive Or command
3088 ******************************************************************************/
3091 * @brief HW_CAU_XOR_CAA - Accumulator register - Exclusive Or command (WO)
3093 * Reset value: 0x00000000U
3095 typedef union _hw_cau_xor_caa
3098 struct _hw_cau_xor_caa_bitfields
3100 uint32_t ACC
: 32; /*!< [31:0] ACC */
3105 * @name Constants and macros for entire CAU_XOR_CAA register
3108 #define HW_CAU_XOR_CAA_ADDR(x) ((x) + 0x984U)
3110 #define HW_CAU_XOR_CAA(x) (*(__O hw_cau_xor_caa_t *) HW_CAU_XOR_CAA_ADDR(x))
3111 #define HW_CAU_XOR_CAA_WR(x, v) (HW_CAU_XOR_CAA(x).U = (v))
3115 * Constants & macros for individual CAU_XOR_CAA bitfields
3119 * @name Register CAU_XOR_CAA, field ACC[31:0] (WO)
3122 #define BP_CAU_XOR_CAA_ACC (0U) /*!< Bit position for CAU_XOR_CAA_ACC. */
3123 #define BM_CAU_XOR_CAA_ACC (0xFFFFFFFFU) /*!< Bit mask for CAU_XOR_CAA_ACC. */
3124 #define BS_CAU_XOR_CAA_ACC (32U) /*!< Bit field size in bits for CAU_XOR_CAA_ACC. */
3126 /*! @brief Format value for bitfield CAU_XOR_CAA_ACC. */
3127 #define BF_CAU_XOR_CAA_ACC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CAA_ACC) & BM_CAU_XOR_CAA_ACC)
3130 /*******************************************************************************
3131 * HW_CAU_XOR_CA0 - General Purpose Register 0 - Exclusive Or command
3132 ******************************************************************************/
3135 * @brief HW_CAU_XOR_CA0 - General Purpose Register 0 - Exclusive Or command (WO)
3137 * Reset value: 0x00000000U
3139 typedef union _hw_cau_xor_ca0
3142 struct _hw_cau_xor_ca0_bitfields
3144 uint32_t CA0
: 32; /*!< [31:0] CA0 */
3149 * @name Constants and macros for entire CAU_XOR_CA0 register
3152 #define HW_CAU_XOR_CA0_ADDR(x) ((x) + 0x988U)
3154 #define HW_CAU_XOR_CA0(x) (*(__O hw_cau_xor_ca0_t *) HW_CAU_XOR_CA0_ADDR(x))
3155 #define HW_CAU_XOR_CA0_WR(x, v) (HW_CAU_XOR_CA0(x).U = (v))
3159 * Constants & macros for individual CAU_XOR_CA0 bitfields
3163 * @name Register CAU_XOR_CA0, field CA0[31:0] (WO)
3166 #define BP_CAU_XOR_CA0_CA0 (0U) /*!< Bit position for CAU_XOR_CA0_CA0. */
3167 #define BM_CAU_XOR_CA0_CA0 (0xFFFFFFFFU) /*!< Bit mask for CAU_XOR_CA0_CA0. */
3168 #define BS_CAU_XOR_CA0_CA0 (32U) /*!< Bit field size in bits for CAU_XOR_CA0_CA0. */
3170 /*! @brief Format value for bitfield CAU_XOR_CA0_CA0. */
3171 #define BF_CAU_XOR_CA0_CA0(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CA0_CA0) & BM_CAU_XOR_CA0_CA0)
3174 /*******************************************************************************
3175 * HW_CAU_XOR_CA1 - General Purpose Register 1 - Exclusive Or command
3176 ******************************************************************************/
3179 * @brief HW_CAU_XOR_CA1 - General Purpose Register 1 - Exclusive Or command (WO)
3181 * Reset value: 0x00000000U
3183 typedef union _hw_cau_xor_ca1
3186 struct _hw_cau_xor_ca1_bitfields
3188 uint32_t CA1
: 32; /*!< [31:0] CA1 */
3193 * @name Constants and macros for entire CAU_XOR_CA1 register
3196 #define HW_CAU_XOR_CA1_ADDR(x) ((x) + 0x98CU)
3198 #define HW_CAU_XOR_CA1(x) (*(__O hw_cau_xor_ca1_t *) HW_CAU_XOR_CA1_ADDR(x))
3199 #define HW_CAU_XOR_CA1_WR(x, v) (HW_CAU_XOR_CA1(x).U = (v))
3203 * Constants & macros for individual CAU_XOR_CA1 bitfields
3207 * @name Register CAU_XOR_CA1, field CA1[31:0] (WO)
3210 #define BP_CAU_XOR_CA1_CA1 (0U) /*!< Bit position for CAU_XOR_CA1_CA1. */
3211 #define BM_CAU_XOR_CA1_CA1 (0xFFFFFFFFU) /*!< Bit mask for CAU_XOR_CA1_CA1. */
3212 #define BS_CAU_XOR_CA1_CA1 (32U) /*!< Bit field size in bits for CAU_XOR_CA1_CA1. */
3214 /*! @brief Format value for bitfield CAU_XOR_CA1_CA1. */
3215 #define BF_CAU_XOR_CA1_CA1(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CA1_CA1) & BM_CAU_XOR_CA1_CA1)
3218 /*******************************************************************************
3219 * HW_CAU_XOR_CA2 - General Purpose Register 2 - Exclusive Or command
3220 ******************************************************************************/
3223 * @brief HW_CAU_XOR_CA2 - General Purpose Register 2 - Exclusive Or command (WO)
3225 * Reset value: 0x00000000U
3227 typedef union _hw_cau_xor_ca2
3230 struct _hw_cau_xor_ca2_bitfields
3232 uint32_t CA2
: 32; /*!< [31:0] CA2 */
3237 * @name Constants and macros for entire CAU_XOR_CA2 register
3240 #define HW_CAU_XOR_CA2_ADDR(x) ((x) + 0x990U)
3242 #define HW_CAU_XOR_CA2(x) (*(__O hw_cau_xor_ca2_t *) HW_CAU_XOR_CA2_ADDR(x))
3243 #define HW_CAU_XOR_CA2_WR(x, v) (HW_CAU_XOR_CA2(x).U = (v))
3247 * Constants & macros for individual CAU_XOR_CA2 bitfields
3251 * @name Register CAU_XOR_CA2, field CA2[31:0] (WO)
3254 #define BP_CAU_XOR_CA2_CA2 (0U) /*!< Bit position for CAU_XOR_CA2_CA2. */
3255 #define BM_CAU_XOR_CA2_CA2 (0xFFFFFFFFU) /*!< Bit mask for CAU_XOR_CA2_CA2. */
3256 #define BS_CAU_XOR_CA2_CA2 (32U) /*!< Bit field size in bits for CAU_XOR_CA2_CA2. */
3258 /*! @brief Format value for bitfield CAU_XOR_CA2_CA2. */
3259 #define BF_CAU_XOR_CA2_CA2(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CA2_CA2) & BM_CAU_XOR_CA2_CA2)
3262 /*******************************************************************************
3263 * HW_CAU_XOR_CA3 - General Purpose Register 3 - Exclusive Or command
3264 ******************************************************************************/
3267 * @brief HW_CAU_XOR_CA3 - General Purpose Register 3 - Exclusive Or command (WO)
3269 * Reset value: 0x00000000U
3271 typedef union _hw_cau_xor_ca3
3274 struct _hw_cau_xor_ca3_bitfields
3276 uint32_t CA3
: 32; /*!< [31:0] CA3 */
3281 * @name Constants and macros for entire CAU_XOR_CA3 register
3284 #define HW_CAU_XOR_CA3_ADDR(x) ((x) + 0x994U)
3286 #define HW_CAU_XOR_CA3(x) (*(__O hw_cau_xor_ca3_t *) HW_CAU_XOR_CA3_ADDR(x))
3287 #define HW_CAU_XOR_CA3_WR(x, v) (HW_CAU_XOR_CA3(x).U = (v))
3291 * Constants & macros for individual CAU_XOR_CA3 bitfields
3295 * @name Register CAU_XOR_CA3, field CA3[31:0] (WO)
3298 #define BP_CAU_XOR_CA3_CA3 (0U) /*!< Bit position for CAU_XOR_CA3_CA3. */
3299 #define BM_CAU_XOR_CA3_CA3 (0xFFFFFFFFU) /*!< Bit mask for CAU_XOR_CA3_CA3. */
3300 #define BS_CAU_XOR_CA3_CA3 (32U) /*!< Bit field size in bits for CAU_XOR_CA3_CA3. */
3302 /*! @brief Format value for bitfield CAU_XOR_CA3_CA3. */
3303 #define BF_CAU_XOR_CA3_CA3(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CA3_CA3) & BM_CAU_XOR_CA3_CA3)
3306 /*******************************************************************************
3307 * HW_CAU_XOR_CA4 - General Purpose Register 4 - Exclusive Or command
3308 ******************************************************************************/
3311 * @brief HW_CAU_XOR_CA4 - General Purpose Register 4 - Exclusive Or command (WO)
3313 * Reset value: 0x00000000U
3315 typedef union _hw_cau_xor_ca4
3318 struct _hw_cau_xor_ca4_bitfields
3320 uint32_t CA4
: 32; /*!< [31:0] CA4 */
3325 * @name Constants and macros for entire CAU_XOR_CA4 register
3328 #define HW_CAU_XOR_CA4_ADDR(x) ((x) + 0x998U)
3330 #define HW_CAU_XOR_CA4(x) (*(__O hw_cau_xor_ca4_t *) HW_CAU_XOR_CA4_ADDR(x))
3331 #define HW_CAU_XOR_CA4_WR(x, v) (HW_CAU_XOR_CA4(x).U = (v))
3335 * Constants & macros for individual CAU_XOR_CA4 bitfields
3339 * @name Register CAU_XOR_CA4, field CA4[31:0] (WO)
3342 #define BP_CAU_XOR_CA4_CA4 (0U) /*!< Bit position for CAU_XOR_CA4_CA4. */
3343 #define BM_CAU_XOR_CA4_CA4 (0xFFFFFFFFU) /*!< Bit mask for CAU_XOR_CA4_CA4. */
3344 #define BS_CAU_XOR_CA4_CA4 (32U) /*!< Bit field size in bits for CAU_XOR_CA4_CA4. */
3346 /*! @brief Format value for bitfield CAU_XOR_CA4_CA4. */
3347 #define BF_CAU_XOR_CA4_CA4(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CA4_CA4) & BM_CAU_XOR_CA4_CA4)
3350 /*******************************************************************************
3351 * HW_CAU_XOR_CA5 - General Purpose Register 5 - Exclusive Or command
3352 ******************************************************************************/
3355 * @brief HW_CAU_XOR_CA5 - General Purpose Register 5 - Exclusive Or command (WO)
3357 * Reset value: 0x00000000U
3359 typedef union _hw_cau_xor_ca5
3362 struct _hw_cau_xor_ca5_bitfields
3364 uint32_t CA5
: 32; /*!< [31:0] CA5 */
3369 * @name Constants and macros for entire CAU_XOR_CA5 register
3372 #define HW_CAU_XOR_CA5_ADDR(x) ((x) + 0x99CU)
3374 #define HW_CAU_XOR_CA5(x) (*(__O hw_cau_xor_ca5_t *) HW_CAU_XOR_CA5_ADDR(x))
3375 #define HW_CAU_XOR_CA5_WR(x, v) (HW_CAU_XOR_CA5(x).U = (v))
3379 * Constants & macros for individual CAU_XOR_CA5 bitfields
3383 * @name Register CAU_XOR_CA5, field CA5[31:0] (WO)
3386 #define BP_CAU_XOR_CA5_CA5 (0U) /*!< Bit position for CAU_XOR_CA5_CA5. */
3387 #define BM_CAU_XOR_CA5_CA5 (0xFFFFFFFFU) /*!< Bit mask for CAU_XOR_CA5_CA5. */
3388 #define BS_CAU_XOR_CA5_CA5 (32U) /*!< Bit field size in bits for CAU_XOR_CA5_CA5. */
3390 /*! @brief Format value for bitfield CAU_XOR_CA5_CA5. */
3391 #define BF_CAU_XOR_CA5_CA5(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CA5_CA5) & BM_CAU_XOR_CA5_CA5)
3394 /*******************************************************************************
3395 * HW_CAU_XOR_CA6 - General Purpose Register 6 - Exclusive Or command
3396 ******************************************************************************/
3399 * @brief HW_CAU_XOR_CA6 - General Purpose Register 6 - Exclusive Or command (WO)
3401 * Reset value: 0x00000000U
3403 typedef union _hw_cau_xor_ca6
3406 struct _hw_cau_xor_ca6_bitfields
3408 uint32_t CA6
: 32; /*!< [31:0] CA6 */
3413 * @name Constants and macros for entire CAU_XOR_CA6 register
3416 #define HW_CAU_XOR_CA6_ADDR(x) ((x) + 0x9A0U)
3418 #define HW_CAU_XOR_CA6(x) (*(__O hw_cau_xor_ca6_t *) HW_CAU_XOR_CA6_ADDR(x))
3419 #define HW_CAU_XOR_CA6_WR(x, v) (HW_CAU_XOR_CA6(x).U = (v))
3423 * Constants & macros for individual CAU_XOR_CA6 bitfields
3427 * @name Register CAU_XOR_CA6, field CA6[31:0] (WO)
3430 #define BP_CAU_XOR_CA6_CA6 (0U) /*!< Bit position for CAU_XOR_CA6_CA6. */
3431 #define BM_CAU_XOR_CA6_CA6 (0xFFFFFFFFU) /*!< Bit mask for CAU_XOR_CA6_CA6. */
3432 #define BS_CAU_XOR_CA6_CA6 (32U) /*!< Bit field size in bits for CAU_XOR_CA6_CA6. */
3434 /*! @brief Format value for bitfield CAU_XOR_CA6_CA6. */
3435 #define BF_CAU_XOR_CA6_CA6(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CA6_CA6) & BM_CAU_XOR_CA6_CA6)
3438 /*******************************************************************************
3439 * HW_CAU_XOR_CA7 - General Purpose Register 7 - Exclusive Or command
3440 ******************************************************************************/
3443 * @brief HW_CAU_XOR_CA7 - General Purpose Register 7 - Exclusive Or command (WO)
3445 * Reset value: 0x00000000U
3447 typedef union _hw_cau_xor_ca7
3450 struct _hw_cau_xor_ca7_bitfields
3452 uint32_t CA7
: 32; /*!< [31:0] CA7 */
3457 * @name Constants and macros for entire CAU_XOR_CA7 register
3460 #define HW_CAU_XOR_CA7_ADDR(x) ((x) + 0x9A4U)
3462 #define HW_CAU_XOR_CA7(x) (*(__O hw_cau_xor_ca7_t *) HW_CAU_XOR_CA7_ADDR(x))
3463 #define HW_CAU_XOR_CA7_WR(x, v) (HW_CAU_XOR_CA7(x).U = (v))
3467 * Constants & macros for individual CAU_XOR_CA7 bitfields
3471 * @name Register CAU_XOR_CA7, field CA7[31:0] (WO)
3474 #define BP_CAU_XOR_CA7_CA7 (0U) /*!< Bit position for CAU_XOR_CA7_CA7. */
3475 #define BM_CAU_XOR_CA7_CA7 (0xFFFFFFFFU) /*!< Bit mask for CAU_XOR_CA7_CA7. */
3476 #define BS_CAU_XOR_CA7_CA7 (32U) /*!< Bit field size in bits for CAU_XOR_CA7_CA7. */
3478 /*! @brief Format value for bitfield CAU_XOR_CA7_CA7. */
3479 #define BF_CAU_XOR_CA7_CA7(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CA7_CA7) & BM_CAU_XOR_CA7_CA7)
3482 /*******************************************************************************
3483 * HW_CAU_XOR_CA8 - General Purpose Register 8 - Exclusive Or command
3484 ******************************************************************************/
3487 * @brief HW_CAU_XOR_CA8 - General Purpose Register 8 - Exclusive Or command (WO)
3489 * Reset value: 0x00000000U
3491 typedef union _hw_cau_xor_ca8
3494 struct _hw_cau_xor_ca8_bitfields
3496 uint32_t CA8
: 32; /*!< [31:0] CA8 */
3501 * @name Constants and macros for entire CAU_XOR_CA8 register
3504 #define HW_CAU_XOR_CA8_ADDR(x) ((x) + 0x9A8U)
3506 #define HW_CAU_XOR_CA8(x) (*(__O hw_cau_xor_ca8_t *) HW_CAU_XOR_CA8_ADDR(x))
3507 #define HW_CAU_XOR_CA8_WR(x, v) (HW_CAU_XOR_CA8(x).U = (v))
3511 * Constants & macros for individual CAU_XOR_CA8 bitfields
3515 * @name Register CAU_XOR_CA8, field CA8[31:0] (WO)
3518 #define BP_CAU_XOR_CA8_CA8 (0U) /*!< Bit position for CAU_XOR_CA8_CA8. */
3519 #define BM_CAU_XOR_CA8_CA8 (0xFFFFFFFFU) /*!< Bit mask for CAU_XOR_CA8_CA8. */
3520 #define BS_CAU_XOR_CA8_CA8 (32U) /*!< Bit field size in bits for CAU_XOR_CA8_CA8. */
3522 /*! @brief Format value for bitfield CAU_XOR_CA8_CA8. */
3523 #define BF_CAU_XOR_CA8_CA8(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CA8_CA8) & BM_CAU_XOR_CA8_CA8)
3526 /*******************************************************************************
3527 * HW_CAU_ROTL_CASR - Status register - Rotate Left command
3528 ******************************************************************************/
3531 * @brief HW_CAU_ROTL_CASR - Status register - Rotate Left command (WO)
3533 * Reset value: 0x20000000U
3535 typedef union _hw_cau_rotl_casr
3538 struct _hw_cau_rotl_casr_bitfields
3540 uint32_t IC
: 1; /*!< [0] */
3541 uint32_t DPE
: 1; /*!< [1] */
3542 uint32_t RESERVED0
: 26; /*!< [27:2] */
3543 uint32_t VER
: 4; /*!< [31:28] CAU version */
3545 } hw_cau_rotl_casr_t
;
3548 * @name Constants and macros for entire CAU_ROTL_CASR register
3551 #define HW_CAU_ROTL_CASR_ADDR(x) ((x) + 0x9C0U)
3553 #define HW_CAU_ROTL_CASR(x) (*(__O hw_cau_rotl_casr_t *) HW_CAU_ROTL_CASR_ADDR(x))
3554 #define HW_CAU_ROTL_CASR_WR(x, v) (HW_CAU_ROTL_CASR(x).U = (v))
3558 * Constants & macros for individual CAU_ROTL_CASR bitfields
3562 * @name Register CAU_ROTL_CASR, field IC[0] (WO)
3565 * - 0 - No illegal commands issued
3566 * - 1 - Illegal command issued
3569 #define BP_CAU_ROTL_CASR_IC (0U) /*!< Bit position for CAU_ROTL_CASR_IC. */
3570 #define BM_CAU_ROTL_CASR_IC (0x00000001U) /*!< Bit mask for CAU_ROTL_CASR_IC. */
3571 #define BS_CAU_ROTL_CASR_IC (1U) /*!< Bit field size in bits for CAU_ROTL_CASR_IC. */
3573 /*! @brief Format value for bitfield CAU_ROTL_CASR_IC. */
3574 #define BF_CAU_ROTL_CASR_IC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CASR_IC) & BM_CAU_ROTL_CASR_IC)
3578 * @name Register CAU_ROTL_CASR, field DPE[1] (WO)
3581 * - 0 - No error detected
3582 * - 1 - DES key parity error detected
3585 #define BP_CAU_ROTL_CASR_DPE (1U) /*!< Bit position for CAU_ROTL_CASR_DPE. */
3586 #define BM_CAU_ROTL_CASR_DPE (0x00000002U) /*!< Bit mask for CAU_ROTL_CASR_DPE. */
3587 #define BS_CAU_ROTL_CASR_DPE (1U) /*!< Bit field size in bits for CAU_ROTL_CASR_DPE. */
3589 /*! @brief Format value for bitfield CAU_ROTL_CASR_DPE. */
3590 #define BF_CAU_ROTL_CASR_DPE(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CASR_DPE) & BM_CAU_ROTL_CASR_DPE)
3594 * @name Register CAU_ROTL_CASR, field VER[31:28] (WO)
3597 * - 0001 - Initial CAU version
3598 * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
3599 * value on this device)
3602 #define BP_CAU_ROTL_CASR_VER (28U) /*!< Bit position for CAU_ROTL_CASR_VER. */
3603 #define BM_CAU_ROTL_CASR_VER (0xF0000000U) /*!< Bit mask for CAU_ROTL_CASR_VER. */
3604 #define BS_CAU_ROTL_CASR_VER (4U) /*!< Bit field size in bits for CAU_ROTL_CASR_VER. */
3606 /*! @brief Format value for bitfield CAU_ROTL_CASR_VER. */
3607 #define BF_CAU_ROTL_CASR_VER(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CASR_VER) & BM_CAU_ROTL_CASR_VER)
3610 /*******************************************************************************
3611 * HW_CAU_ROTL_CAA - Accumulator register - Rotate Left command
3612 ******************************************************************************/
3615 * @brief HW_CAU_ROTL_CAA - Accumulator register - Rotate Left command (WO)
3617 * Reset value: 0x00000000U
3619 typedef union _hw_cau_rotl_caa
3622 struct _hw_cau_rotl_caa_bitfields
3624 uint32_t ACC
: 32; /*!< [31:0] ACC */
3626 } hw_cau_rotl_caa_t
;
3629 * @name Constants and macros for entire CAU_ROTL_CAA register
3632 #define HW_CAU_ROTL_CAA_ADDR(x) ((x) + 0x9C4U)
3634 #define HW_CAU_ROTL_CAA(x) (*(__O hw_cau_rotl_caa_t *) HW_CAU_ROTL_CAA_ADDR(x))
3635 #define HW_CAU_ROTL_CAA_WR(x, v) (HW_CAU_ROTL_CAA(x).U = (v))
3639 * Constants & macros for individual CAU_ROTL_CAA bitfields
3643 * @name Register CAU_ROTL_CAA, field ACC[31:0] (WO)
3646 #define BP_CAU_ROTL_CAA_ACC (0U) /*!< Bit position for CAU_ROTL_CAA_ACC. */
3647 #define BM_CAU_ROTL_CAA_ACC (0xFFFFFFFFU) /*!< Bit mask for CAU_ROTL_CAA_ACC. */
3648 #define BS_CAU_ROTL_CAA_ACC (32U) /*!< Bit field size in bits for CAU_ROTL_CAA_ACC. */
3650 /*! @brief Format value for bitfield CAU_ROTL_CAA_ACC. */
3651 #define BF_CAU_ROTL_CAA_ACC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CAA_ACC) & BM_CAU_ROTL_CAA_ACC)
3654 /*******************************************************************************
3655 * HW_CAU_ROTL_CA0 - General Purpose Register 0 - Rotate Left command
3656 ******************************************************************************/
3659 * @brief HW_CAU_ROTL_CA0 - General Purpose Register 0 - Rotate Left command (WO)
3661 * Reset value: 0x00000000U
3663 typedef union _hw_cau_rotl_ca0
3666 struct _hw_cau_rotl_ca0_bitfields
3668 uint32_t CA0
: 32; /*!< [31:0] CA0 */
3670 } hw_cau_rotl_ca0_t
;
3673 * @name Constants and macros for entire CAU_ROTL_CA0 register
3676 #define HW_CAU_ROTL_CA0_ADDR(x) ((x) + 0x9C8U)
3678 #define HW_CAU_ROTL_CA0(x) (*(__O hw_cau_rotl_ca0_t *) HW_CAU_ROTL_CA0_ADDR(x))
3679 #define HW_CAU_ROTL_CA0_WR(x, v) (HW_CAU_ROTL_CA0(x).U = (v))
3683 * Constants & macros for individual CAU_ROTL_CA0 bitfields
3687 * @name Register CAU_ROTL_CA0, field CA0[31:0] (WO)
3690 #define BP_CAU_ROTL_CA0_CA0 (0U) /*!< Bit position for CAU_ROTL_CA0_CA0. */
3691 #define BM_CAU_ROTL_CA0_CA0 (0xFFFFFFFFU) /*!< Bit mask for CAU_ROTL_CA0_CA0. */
3692 #define BS_CAU_ROTL_CA0_CA0 (32U) /*!< Bit field size in bits for CAU_ROTL_CA0_CA0. */
3694 /*! @brief Format value for bitfield CAU_ROTL_CA0_CA0. */
3695 #define BF_CAU_ROTL_CA0_CA0(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CA0_CA0) & BM_CAU_ROTL_CA0_CA0)
3698 /*******************************************************************************
3699 * HW_CAU_ROTL_CA1 - General Purpose Register 1 - Rotate Left command
3700 ******************************************************************************/
3703 * @brief HW_CAU_ROTL_CA1 - General Purpose Register 1 - Rotate Left command (WO)
3705 * Reset value: 0x00000000U
3707 typedef union _hw_cau_rotl_ca1
3710 struct _hw_cau_rotl_ca1_bitfields
3712 uint32_t CA1
: 32; /*!< [31:0] CA1 */
3714 } hw_cau_rotl_ca1_t
;
3717 * @name Constants and macros for entire CAU_ROTL_CA1 register
3720 #define HW_CAU_ROTL_CA1_ADDR(x) ((x) + 0x9CCU)
3722 #define HW_CAU_ROTL_CA1(x) (*(__O hw_cau_rotl_ca1_t *) HW_CAU_ROTL_CA1_ADDR(x))
3723 #define HW_CAU_ROTL_CA1_WR(x, v) (HW_CAU_ROTL_CA1(x).U = (v))
3727 * Constants & macros for individual CAU_ROTL_CA1 bitfields
3731 * @name Register CAU_ROTL_CA1, field CA1[31:0] (WO)
3734 #define BP_CAU_ROTL_CA1_CA1 (0U) /*!< Bit position for CAU_ROTL_CA1_CA1. */
3735 #define BM_CAU_ROTL_CA1_CA1 (0xFFFFFFFFU) /*!< Bit mask for CAU_ROTL_CA1_CA1. */
3736 #define BS_CAU_ROTL_CA1_CA1 (32U) /*!< Bit field size in bits for CAU_ROTL_CA1_CA1. */
3738 /*! @brief Format value for bitfield CAU_ROTL_CA1_CA1. */
3739 #define BF_CAU_ROTL_CA1_CA1(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CA1_CA1) & BM_CAU_ROTL_CA1_CA1)
3742 /*******************************************************************************
3743 * HW_CAU_ROTL_CA2 - General Purpose Register 2 - Rotate Left command
3744 ******************************************************************************/
3747 * @brief HW_CAU_ROTL_CA2 - General Purpose Register 2 - Rotate Left command (WO)
3749 * Reset value: 0x00000000U
3751 typedef union _hw_cau_rotl_ca2
3754 struct _hw_cau_rotl_ca2_bitfields
3756 uint32_t CA2
: 32; /*!< [31:0] CA2 */
3758 } hw_cau_rotl_ca2_t
;
3761 * @name Constants and macros for entire CAU_ROTL_CA2 register
3764 #define HW_CAU_ROTL_CA2_ADDR(x) ((x) + 0x9D0U)
3766 #define HW_CAU_ROTL_CA2(x) (*(__O hw_cau_rotl_ca2_t *) HW_CAU_ROTL_CA2_ADDR(x))
3767 #define HW_CAU_ROTL_CA2_WR(x, v) (HW_CAU_ROTL_CA2(x).U = (v))
3771 * Constants & macros for individual CAU_ROTL_CA2 bitfields
3775 * @name Register CAU_ROTL_CA2, field CA2[31:0] (WO)
3778 #define BP_CAU_ROTL_CA2_CA2 (0U) /*!< Bit position for CAU_ROTL_CA2_CA2. */
3779 #define BM_CAU_ROTL_CA2_CA2 (0xFFFFFFFFU) /*!< Bit mask for CAU_ROTL_CA2_CA2. */
3780 #define BS_CAU_ROTL_CA2_CA2 (32U) /*!< Bit field size in bits for CAU_ROTL_CA2_CA2. */
3782 /*! @brief Format value for bitfield CAU_ROTL_CA2_CA2. */
3783 #define BF_CAU_ROTL_CA2_CA2(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CA2_CA2) & BM_CAU_ROTL_CA2_CA2)
3786 /*******************************************************************************
3787 * HW_CAU_ROTL_CA3 - General Purpose Register 3 - Rotate Left command
3788 ******************************************************************************/
3791 * @brief HW_CAU_ROTL_CA3 - General Purpose Register 3 - Rotate Left command (WO)
3793 * Reset value: 0x00000000U
3795 typedef union _hw_cau_rotl_ca3
3798 struct _hw_cau_rotl_ca3_bitfields
3800 uint32_t CA3
: 32; /*!< [31:0] CA3 */
3802 } hw_cau_rotl_ca3_t
;
3805 * @name Constants and macros for entire CAU_ROTL_CA3 register
3808 #define HW_CAU_ROTL_CA3_ADDR(x) ((x) + 0x9D4U)
3810 #define HW_CAU_ROTL_CA3(x) (*(__O hw_cau_rotl_ca3_t *) HW_CAU_ROTL_CA3_ADDR(x))
3811 #define HW_CAU_ROTL_CA3_WR(x, v) (HW_CAU_ROTL_CA3(x).U = (v))
3815 * Constants & macros for individual CAU_ROTL_CA3 bitfields
3819 * @name Register CAU_ROTL_CA3, field CA3[31:0] (WO)
3822 #define BP_CAU_ROTL_CA3_CA3 (0U) /*!< Bit position for CAU_ROTL_CA3_CA3. */
3823 #define BM_CAU_ROTL_CA3_CA3 (0xFFFFFFFFU) /*!< Bit mask for CAU_ROTL_CA3_CA3. */
3824 #define BS_CAU_ROTL_CA3_CA3 (32U) /*!< Bit field size in bits for CAU_ROTL_CA3_CA3. */
3826 /*! @brief Format value for bitfield CAU_ROTL_CA3_CA3. */
3827 #define BF_CAU_ROTL_CA3_CA3(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CA3_CA3) & BM_CAU_ROTL_CA3_CA3)
3830 /*******************************************************************************
3831 * HW_CAU_ROTL_CA4 - General Purpose Register 4 - Rotate Left command
3832 ******************************************************************************/
3835 * @brief HW_CAU_ROTL_CA4 - General Purpose Register 4 - Rotate Left command (WO)
3837 * Reset value: 0x00000000U
3839 typedef union _hw_cau_rotl_ca4
3842 struct _hw_cau_rotl_ca4_bitfields
3844 uint32_t CA4
: 32; /*!< [31:0] CA4 */
3846 } hw_cau_rotl_ca4_t
;
3849 * @name Constants and macros for entire CAU_ROTL_CA4 register
3852 #define HW_CAU_ROTL_CA4_ADDR(x) ((x) + 0x9D8U)
3854 #define HW_CAU_ROTL_CA4(x) (*(__O hw_cau_rotl_ca4_t *) HW_CAU_ROTL_CA4_ADDR(x))
3855 #define HW_CAU_ROTL_CA4_WR(x, v) (HW_CAU_ROTL_CA4(x).U = (v))
3859 * Constants & macros for individual CAU_ROTL_CA4 bitfields
3863 * @name Register CAU_ROTL_CA4, field CA4[31:0] (WO)
3866 #define BP_CAU_ROTL_CA4_CA4 (0U) /*!< Bit position for CAU_ROTL_CA4_CA4. */
3867 #define BM_CAU_ROTL_CA4_CA4 (0xFFFFFFFFU) /*!< Bit mask for CAU_ROTL_CA4_CA4. */
3868 #define BS_CAU_ROTL_CA4_CA4 (32U) /*!< Bit field size in bits for CAU_ROTL_CA4_CA4. */
3870 /*! @brief Format value for bitfield CAU_ROTL_CA4_CA4. */
3871 #define BF_CAU_ROTL_CA4_CA4(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CA4_CA4) & BM_CAU_ROTL_CA4_CA4)
3874 /*******************************************************************************
3875 * HW_CAU_ROTL_CA5 - General Purpose Register 5 - Rotate Left command
3876 ******************************************************************************/
3879 * @brief HW_CAU_ROTL_CA5 - General Purpose Register 5 - Rotate Left command (WO)
3881 * Reset value: 0x00000000U
3883 typedef union _hw_cau_rotl_ca5
3886 struct _hw_cau_rotl_ca5_bitfields
3888 uint32_t CA5
: 32; /*!< [31:0] CA5 */
3890 } hw_cau_rotl_ca5_t
;
3893 * @name Constants and macros for entire CAU_ROTL_CA5 register
3896 #define HW_CAU_ROTL_CA5_ADDR(x) ((x) + 0x9DCU)
3898 #define HW_CAU_ROTL_CA5(x) (*(__O hw_cau_rotl_ca5_t *) HW_CAU_ROTL_CA5_ADDR(x))
3899 #define HW_CAU_ROTL_CA5_WR(x, v) (HW_CAU_ROTL_CA5(x).U = (v))
3903 * Constants & macros for individual CAU_ROTL_CA5 bitfields
3907 * @name Register CAU_ROTL_CA5, field CA5[31:0] (WO)
3910 #define BP_CAU_ROTL_CA5_CA5 (0U) /*!< Bit position for CAU_ROTL_CA5_CA5. */
3911 #define BM_CAU_ROTL_CA5_CA5 (0xFFFFFFFFU) /*!< Bit mask for CAU_ROTL_CA5_CA5. */
3912 #define BS_CAU_ROTL_CA5_CA5 (32U) /*!< Bit field size in bits for CAU_ROTL_CA5_CA5. */
3914 /*! @brief Format value for bitfield CAU_ROTL_CA5_CA5. */
3915 #define BF_CAU_ROTL_CA5_CA5(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CA5_CA5) & BM_CAU_ROTL_CA5_CA5)
3918 /*******************************************************************************
3919 * HW_CAU_ROTL_CA6 - General Purpose Register 6 - Rotate Left command
3920 ******************************************************************************/
3923 * @brief HW_CAU_ROTL_CA6 - General Purpose Register 6 - Rotate Left command (WO)
3925 * Reset value: 0x00000000U
3927 typedef union _hw_cau_rotl_ca6
3930 struct _hw_cau_rotl_ca6_bitfields
3932 uint32_t CA6
: 32; /*!< [31:0] CA6 */
3934 } hw_cau_rotl_ca6_t
;
3937 * @name Constants and macros for entire CAU_ROTL_CA6 register
3940 #define HW_CAU_ROTL_CA6_ADDR(x) ((x) + 0x9E0U)
3942 #define HW_CAU_ROTL_CA6(x) (*(__O hw_cau_rotl_ca6_t *) HW_CAU_ROTL_CA6_ADDR(x))
3943 #define HW_CAU_ROTL_CA6_WR(x, v) (HW_CAU_ROTL_CA6(x).U = (v))
3947 * Constants & macros for individual CAU_ROTL_CA6 bitfields
3951 * @name Register CAU_ROTL_CA6, field CA6[31:0] (WO)
3954 #define BP_CAU_ROTL_CA6_CA6 (0U) /*!< Bit position for CAU_ROTL_CA6_CA6. */
3955 #define BM_CAU_ROTL_CA6_CA6 (0xFFFFFFFFU) /*!< Bit mask for CAU_ROTL_CA6_CA6. */
3956 #define BS_CAU_ROTL_CA6_CA6 (32U) /*!< Bit field size in bits for CAU_ROTL_CA6_CA6. */
3958 /*! @brief Format value for bitfield CAU_ROTL_CA6_CA6. */
3959 #define BF_CAU_ROTL_CA6_CA6(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CA6_CA6) & BM_CAU_ROTL_CA6_CA6)
3962 /*******************************************************************************
3963 * HW_CAU_ROTL_CA7 - General Purpose Register 7 - Rotate Left command
3964 ******************************************************************************/
3967 * @brief HW_CAU_ROTL_CA7 - General Purpose Register 7 - Rotate Left command (WO)
3969 * Reset value: 0x00000000U
3971 typedef union _hw_cau_rotl_ca7
3974 struct _hw_cau_rotl_ca7_bitfields
3976 uint32_t CA7
: 32; /*!< [31:0] CA7 */
3978 } hw_cau_rotl_ca7_t
;
3981 * @name Constants and macros for entire CAU_ROTL_CA7 register
3984 #define HW_CAU_ROTL_CA7_ADDR(x) ((x) + 0x9E4U)
3986 #define HW_CAU_ROTL_CA7(x) (*(__O hw_cau_rotl_ca7_t *) HW_CAU_ROTL_CA7_ADDR(x))
3987 #define HW_CAU_ROTL_CA7_WR(x, v) (HW_CAU_ROTL_CA7(x).U = (v))
3991 * Constants & macros for individual CAU_ROTL_CA7 bitfields
3995 * @name Register CAU_ROTL_CA7, field CA7[31:0] (WO)
3998 #define BP_CAU_ROTL_CA7_CA7 (0U) /*!< Bit position for CAU_ROTL_CA7_CA7. */
3999 #define BM_CAU_ROTL_CA7_CA7 (0xFFFFFFFFU) /*!< Bit mask for CAU_ROTL_CA7_CA7. */
4000 #define BS_CAU_ROTL_CA7_CA7 (32U) /*!< Bit field size in bits for CAU_ROTL_CA7_CA7. */
4002 /*! @brief Format value for bitfield CAU_ROTL_CA7_CA7. */
4003 #define BF_CAU_ROTL_CA7_CA7(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CA7_CA7) & BM_CAU_ROTL_CA7_CA7)
4006 /*******************************************************************************
4007 * HW_CAU_ROTL_CA8 - General Purpose Register 8 - Rotate Left command
4008 ******************************************************************************/
4011 * @brief HW_CAU_ROTL_CA8 - General Purpose Register 8 - Rotate Left command (WO)
4013 * Reset value: 0x00000000U
4015 typedef union _hw_cau_rotl_ca8
4018 struct _hw_cau_rotl_ca8_bitfields
4020 uint32_t CA8
: 32; /*!< [31:0] CA8 */
4022 } hw_cau_rotl_ca8_t
;
4025 * @name Constants and macros for entire CAU_ROTL_CA8 register
4028 #define HW_CAU_ROTL_CA8_ADDR(x) ((x) + 0x9E8U)
4030 #define HW_CAU_ROTL_CA8(x) (*(__O hw_cau_rotl_ca8_t *) HW_CAU_ROTL_CA8_ADDR(x))
4031 #define HW_CAU_ROTL_CA8_WR(x, v) (HW_CAU_ROTL_CA8(x).U = (v))
4035 * Constants & macros for individual CAU_ROTL_CA8 bitfields
4039 * @name Register CAU_ROTL_CA8, field CA8[31:0] (WO)
4042 #define BP_CAU_ROTL_CA8_CA8 (0U) /*!< Bit position for CAU_ROTL_CA8_CA8. */
4043 #define BM_CAU_ROTL_CA8_CA8 (0xFFFFFFFFU) /*!< Bit mask for CAU_ROTL_CA8_CA8. */
4044 #define BS_CAU_ROTL_CA8_CA8 (32U) /*!< Bit field size in bits for CAU_ROTL_CA8_CA8. */
4046 /*! @brief Format value for bitfield CAU_ROTL_CA8_CA8. */
4047 #define BF_CAU_ROTL_CA8_CA8(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CA8_CA8) & BM_CAU_ROTL_CA8_CA8)
4050 /*******************************************************************************
4051 * HW_CAU_AESC_CASR - Status register - AES Column Operation command
4052 ******************************************************************************/
4055 * @brief HW_CAU_AESC_CASR - Status register - AES Column Operation command (WO)
4057 * Reset value: 0x20000000U
4059 typedef union _hw_cau_aesc_casr
4062 struct _hw_cau_aesc_casr_bitfields
4064 uint32_t IC
: 1; /*!< [0] */
4065 uint32_t DPE
: 1; /*!< [1] */
4066 uint32_t RESERVED0
: 26; /*!< [27:2] */
4067 uint32_t VER
: 4; /*!< [31:28] CAU version */
4069 } hw_cau_aesc_casr_t
;
4072 * @name Constants and macros for entire CAU_AESC_CASR register
4075 #define HW_CAU_AESC_CASR_ADDR(x) ((x) + 0xB00U)
4077 #define HW_CAU_AESC_CASR(x) (*(__O hw_cau_aesc_casr_t *) HW_CAU_AESC_CASR_ADDR(x))
4078 #define HW_CAU_AESC_CASR_WR(x, v) (HW_CAU_AESC_CASR(x).U = (v))
4082 * Constants & macros for individual CAU_AESC_CASR bitfields
4086 * @name Register CAU_AESC_CASR, field IC[0] (WO)
4089 * - 0 - No illegal commands issued
4090 * - 1 - Illegal command issued
4093 #define BP_CAU_AESC_CASR_IC (0U) /*!< Bit position for CAU_AESC_CASR_IC. */
4094 #define BM_CAU_AESC_CASR_IC (0x00000001U) /*!< Bit mask for CAU_AESC_CASR_IC. */
4095 #define BS_CAU_AESC_CASR_IC (1U) /*!< Bit field size in bits for CAU_AESC_CASR_IC. */
4097 /*! @brief Format value for bitfield CAU_AESC_CASR_IC. */
4098 #define BF_CAU_AESC_CASR_IC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CASR_IC) & BM_CAU_AESC_CASR_IC)
4102 * @name Register CAU_AESC_CASR, field DPE[1] (WO)
4105 * - 0 - No error detected
4106 * - 1 - DES key parity error detected
4109 #define BP_CAU_AESC_CASR_DPE (1U) /*!< Bit position for CAU_AESC_CASR_DPE. */
4110 #define BM_CAU_AESC_CASR_DPE (0x00000002U) /*!< Bit mask for CAU_AESC_CASR_DPE. */
4111 #define BS_CAU_AESC_CASR_DPE (1U) /*!< Bit field size in bits for CAU_AESC_CASR_DPE. */
4113 /*! @brief Format value for bitfield CAU_AESC_CASR_DPE. */
4114 #define BF_CAU_AESC_CASR_DPE(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CASR_DPE) & BM_CAU_AESC_CASR_DPE)
4118 * @name Register CAU_AESC_CASR, field VER[31:28] (WO)
4121 * - 0001 - Initial CAU version
4122 * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
4123 * value on this device)
4126 #define BP_CAU_AESC_CASR_VER (28U) /*!< Bit position for CAU_AESC_CASR_VER. */
4127 #define BM_CAU_AESC_CASR_VER (0xF0000000U) /*!< Bit mask for CAU_AESC_CASR_VER. */
4128 #define BS_CAU_AESC_CASR_VER (4U) /*!< Bit field size in bits for CAU_AESC_CASR_VER. */
4130 /*! @brief Format value for bitfield CAU_AESC_CASR_VER. */
4131 #define BF_CAU_AESC_CASR_VER(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CASR_VER) & BM_CAU_AESC_CASR_VER)
4134 /*******************************************************************************
4135 * HW_CAU_AESC_CAA - Accumulator register - AES Column Operation command
4136 ******************************************************************************/
4139 * @brief HW_CAU_AESC_CAA - Accumulator register - AES Column Operation command (WO)
4141 * Reset value: 0x00000000U
4143 typedef union _hw_cau_aesc_caa
4146 struct _hw_cau_aesc_caa_bitfields
4148 uint32_t ACC
: 32; /*!< [31:0] ACC */
4150 } hw_cau_aesc_caa_t
;
4153 * @name Constants and macros for entire CAU_AESC_CAA register
4156 #define HW_CAU_AESC_CAA_ADDR(x) ((x) + 0xB04U)
4158 #define HW_CAU_AESC_CAA(x) (*(__O hw_cau_aesc_caa_t *) HW_CAU_AESC_CAA_ADDR(x))
4159 #define HW_CAU_AESC_CAA_WR(x, v) (HW_CAU_AESC_CAA(x).U = (v))
4163 * Constants & macros for individual CAU_AESC_CAA bitfields
4167 * @name Register CAU_AESC_CAA, field ACC[31:0] (WO)
4170 #define BP_CAU_AESC_CAA_ACC (0U) /*!< Bit position for CAU_AESC_CAA_ACC. */
4171 #define BM_CAU_AESC_CAA_ACC (0xFFFFFFFFU) /*!< Bit mask for CAU_AESC_CAA_ACC. */
4172 #define BS_CAU_AESC_CAA_ACC (32U) /*!< Bit field size in bits for CAU_AESC_CAA_ACC. */
4174 /*! @brief Format value for bitfield CAU_AESC_CAA_ACC. */
4175 #define BF_CAU_AESC_CAA_ACC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CAA_ACC) & BM_CAU_AESC_CAA_ACC)
4178 /*******************************************************************************
4179 * HW_CAU_AESC_CA0 - General Purpose Register 0 - AES Column Operation command
4180 ******************************************************************************/
4183 * @brief HW_CAU_AESC_CA0 - General Purpose Register 0 - AES Column Operation command (WO)
4185 * Reset value: 0x00000000U
4187 typedef union _hw_cau_aesc_ca0
4190 struct _hw_cau_aesc_ca0_bitfields
4192 uint32_t CA0
: 32; /*!< [31:0] CA0 */
4194 } hw_cau_aesc_ca0_t
;
4197 * @name Constants and macros for entire CAU_AESC_CA0 register
4200 #define HW_CAU_AESC_CA0_ADDR(x) ((x) + 0xB08U)
4202 #define HW_CAU_AESC_CA0(x) (*(__O hw_cau_aesc_ca0_t *) HW_CAU_AESC_CA0_ADDR(x))
4203 #define HW_CAU_AESC_CA0_WR(x, v) (HW_CAU_AESC_CA0(x).U = (v))
4207 * Constants & macros for individual CAU_AESC_CA0 bitfields
4211 * @name Register CAU_AESC_CA0, field CA0[31:0] (WO)
4214 #define BP_CAU_AESC_CA0_CA0 (0U) /*!< Bit position for CAU_AESC_CA0_CA0. */
4215 #define BM_CAU_AESC_CA0_CA0 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESC_CA0_CA0. */
4216 #define BS_CAU_AESC_CA0_CA0 (32U) /*!< Bit field size in bits for CAU_AESC_CA0_CA0. */
4218 /*! @brief Format value for bitfield CAU_AESC_CA0_CA0. */
4219 #define BF_CAU_AESC_CA0_CA0(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CA0_CA0) & BM_CAU_AESC_CA0_CA0)
4222 /*******************************************************************************
4223 * HW_CAU_AESC_CA1 - General Purpose Register 1 - AES Column Operation command
4224 ******************************************************************************/
4227 * @brief HW_CAU_AESC_CA1 - General Purpose Register 1 - AES Column Operation command (WO)
4229 * Reset value: 0x00000000U
4231 typedef union _hw_cau_aesc_ca1
4234 struct _hw_cau_aesc_ca1_bitfields
4236 uint32_t CA1
: 32; /*!< [31:0] CA1 */
4238 } hw_cau_aesc_ca1_t
;
4241 * @name Constants and macros for entire CAU_AESC_CA1 register
4244 #define HW_CAU_AESC_CA1_ADDR(x) ((x) + 0xB0CU)
4246 #define HW_CAU_AESC_CA1(x) (*(__O hw_cau_aesc_ca1_t *) HW_CAU_AESC_CA1_ADDR(x))
4247 #define HW_CAU_AESC_CA1_WR(x, v) (HW_CAU_AESC_CA1(x).U = (v))
4251 * Constants & macros for individual CAU_AESC_CA1 bitfields
4255 * @name Register CAU_AESC_CA1, field CA1[31:0] (WO)
4258 #define BP_CAU_AESC_CA1_CA1 (0U) /*!< Bit position for CAU_AESC_CA1_CA1. */
4259 #define BM_CAU_AESC_CA1_CA1 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESC_CA1_CA1. */
4260 #define BS_CAU_AESC_CA1_CA1 (32U) /*!< Bit field size in bits for CAU_AESC_CA1_CA1. */
4262 /*! @brief Format value for bitfield CAU_AESC_CA1_CA1. */
4263 #define BF_CAU_AESC_CA1_CA1(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CA1_CA1) & BM_CAU_AESC_CA1_CA1)
4266 /*******************************************************************************
4267 * HW_CAU_AESC_CA2 - General Purpose Register 2 - AES Column Operation command
4268 ******************************************************************************/
4271 * @brief HW_CAU_AESC_CA2 - General Purpose Register 2 - AES Column Operation command (WO)
4273 * Reset value: 0x00000000U
4275 typedef union _hw_cau_aesc_ca2
4278 struct _hw_cau_aesc_ca2_bitfields
4280 uint32_t CA2
: 32; /*!< [31:0] CA2 */
4282 } hw_cau_aesc_ca2_t
;
4285 * @name Constants and macros for entire CAU_AESC_CA2 register
4288 #define HW_CAU_AESC_CA2_ADDR(x) ((x) + 0xB10U)
4290 #define HW_CAU_AESC_CA2(x) (*(__O hw_cau_aesc_ca2_t *) HW_CAU_AESC_CA2_ADDR(x))
4291 #define HW_CAU_AESC_CA2_WR(x, v) (HW_CAU_AESC_CA2(x).U = (v))
4295 * Constants & macros for individual CAU_AESC_CA2 bitfields
4299 * @name Register CAU_AESC_CA2, field CA2[31:0] (WO)
4302 #define BP_CAU_AESC_CA2_CA2 (0U) /*!< Bit position for CAU_AESC_CA2_CA2. */
4303 #define BM_CAU_AESC_CA2_CA2 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESC_CA2_CA2. */
4304 #define BS_CAU_AESC_CA2_CA2 (32U) /*!< Bit field size in bits for CAU_AESC_CA2_CA2. */
4306 /*! @brief Format value for bitfield CAU_AESC_CA2_CA2. */
4307 #define BF_CAU_AESC_CA2_CA2(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CA2_CA2) & BM_CAU_AESC_CA2_CA2)
4310 /*******************************************************************************
4311 * HW_CAU_AESC_CA3 - General Purpose Register 3 - AES Column Operation command
4312 ******************************************************************************/
4315 * @brief HW_CAU_AESC_CA3 - General Purpose Register 3 - AES Column Operation command (WO)
4317 * Reset value: 0x00000000U
4319 typedef union _hw_cau_aesc_ca3
4322 struct _hw_cau_aesc_ca3_bitfields
4324 uint32_t CA3
: 32; /*!< [31:0] CA3 */
4326 } hw_cau_aesc_ca3_t
;
4329 * @name Constants and macros for entire CAU_AESC_CA3 register
4332 #define HW_CAU_AESC_CA3_ADDR(x) ((x) + 0xB14U)
4334 #define HW_CAU_AESC_CA3(x) (*(__O hw_cau_aesc_ca3_t *) HW_CAU_AESC_CA3_ADDR(x))
4335 #define HW_CAU_AESC_CA3_WR(x, v) (HW_CAU_AESC_CA3(x).U = (v))
4339 * Constants & macros for individual CAU_AESC_CA3 bitfields
4343 * @name Register CAU_AESC_CA3, field CA3[31:0] (WO)
4346 #define BP_CAU_AESC_CA3_CA3 (0U) /*!< Bit position for CAU_AESC_CA3_CA3. */
4347 #define BM_CAU_AESC_CA3_CA3 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESC_CA3_CA3. */
4348 #define BS_CAU_AESC_CA3_CA3 (32U) /*!< Bit field size in bits for CAU_AESC_CA3_CA3. */
4350 /*! @brief Format value for bitfield CAU_AESC_CA3_CA3. */
4351 #define BF_CAU_AESC_CA3_CA3(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CA3_CA3) & BM_CAU_AESC_CA3_CA3)
4354 /*******************************************************************************
4355 * HW_CAU_AESC_CA4 - General Purpose Register 4 - AES Column Operation command
4356 ******************************************************************************/
4359 * @brief HW_CAU_AESC_CA4 - General Purpose Register 4 - AES Column Operation command (WO)
4361 * Reset value: 0x00000000U
4363 typedef union _hw_cau_aesc_ca4
4366 struct _hw_cau_aesc_ca4_bitfields
4368 uint32_t CA4
: 32; /*!< [31:0] CA4 */
4370 } hw_cau_aesc_ca4_t
;
4373 * @name Constants and macros for entire CAU_AESC_CA4 register
4376 #define HW_CAU_AESC_CA4_ADDR(x) ((x) + 0xB18U)
4378 #define HW_CAU_AESC_CA4(x) (*(__O hw_cau_aesc_ca4_t *) HW_CAU_AESC_CA4_ADDR(x))
4379 #define HW_CAU_AESC_CA4_WR(x, v) (HW_CAU_AESC_CA4(x).U = (v))
4383 * Constants & macros for individual CAU_AESC_CA4 bitfields
4387 * @name Register CAU_AESC_CA4, field CA4[31:0] (WO)
4390 #define BP_CAU_AESC_CA4_CA4 (0U) /*!< Bit position for CAU_AESC_CA4_CA4. */
4391 #define BM_CAU_AESC_CA4_CA4 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESC_CA4_CA4. */
4392 #define BS_CAU_AESC_CA4_CA4 (32U) /*!< Bit field size in bits for CAU_AESC_CA4_CA4. */
4394 /*! @brief Format value for bitfield CAU_AESC_CA4_CA4. */
4395 #define BF_CAU_AESC_CA4_CA4(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CA4_CA4) & BM_CAU_AESC_CA4_CA4)
4398 /*******************************************************************************
4399 * HW_CAU_AESC_CA5 - General Purpose Register 5 - AES Column Operation command
4400 ******************************************************************************/
4403 * @brief HW_CAU_AESC_CA5 - General Purpose Register 5 - AES Column Operation command (WO)
4405 * Reset value: 0x00000000U
4407 typedef union _hw_cau_aesc_ca5
4410 struct _hw_cau_aesc_ca5_bitfields
4412 uint32_t CA5
: 32; /*!< [31:0] CA5 */
4414 } hw_cau_aesc_ca5_t
;
4417 * @name Constants and macros for entire CAU_AESC_CA5 register
4420 #define HW_CAU_AESC_CA5_ADDR(x) ((x) + 0xB1CU)
4422 #define HW_CAU_AESC_CA5(x) (*(__O hw_cau_aesc_ca5_t *) HW_CAU_AESC_CA5_ADDR(x))
4423 #define HW_CAU_AESC_CA5_WR(x, v) (HW_CAU_AESC_CA5(x).U = (v))
4427 * Constants & macros for individual CAU_AESC_CA5 bitfields
4431 * @name Register CAU_AESC_CA5, field CA5[31:0] (WO)
4434 #define BP_CAU_AESC_CA5_CA5 (0U) /*!< Bit position for CAU_AESC_CA5_CA5. */
4435 #define BM_CAU_AESC_CA5_CA5 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESC_CA5_CA5. */
4436 #define BS_CAU_AESC_CA5_CA5 (32U) /*!< Bit field size in bits for CAU_AESC_CA5_CA5. */
4438 /*! @brief Format value for bitfield CAU_AESC_CA5_CA5. */
4439 #define BF_CAU_AESC_CA5_CA5(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CA5_CA5) & BM_CAU_AESC_CA5_CA5)
4442 /*******************************************************************************
4443 * HW_CAU_AESC_CA6 - General Purpose Register 6 - AES Column Operation command
4444 ******************************************************************************/
4447 * @brief HW_CAU_AESC_CA6 - General Purpose Register 6 - AES Column Operation command (WO)
4449 * Reset value: 0x00000000U
4451 typedef union _hw_cau_aesc_ca6
4454 struct _hw_cau_aesc_ca6_bitfields
4456 uint32_t CA6
: 32; /*!< [31:0] CA6 */
4458 } hw_cau_aesc_ca6_t
;
4461 * @name Constants and macros for entire CAU_AESC_CA6 register
4464 #define HW_CAU_AESC_CA6_ADDR(x) ((x) + 0xB20U)
4466 #define HW_CAU_AESC_CA6(x) (*(__O hw_cau_aesc_ca6_t *) HW_CAU_AESC_CA6_ADDR(x))
4467 #define HW_CAU_AESC_CA6_WR(x, v) (HW_CAU_AESC_CA6(x).U = (v))
4471 * Constants & macros for individual CAU_AESC_CA6 bitfields
4475 * @name Register CAU_AESC_CA6, field CA6[31:0] (WO)
4478 #define BP_CAU_AESC_CA6_CA6 (0U) /*!< Bit position for CAU_AESC_CA6_CA6. */
4479 #define BM_CAU_AESC_CA6_CA6 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESC_CA6_CA6. */
4480 #define BS_CAU_AESC_CA6_CA6 (32U) /*!< Bit field size in bits for CAU_AESC_CA6_CA6. */
4482 /*! @brief Format value for bitfield CAU_AESC_CA6_CA6. */
4483 #define BF_CAU_AESC_CA6_CA6(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CA6_CA6) & BM_CAU_AESC_CA6_CA6)
4486 /*******************************************************************************
4487 * HW_CAU_AESC_CA7 - General Purpose Register 7 - AES Column Operation command
4488 ******************************************************************************/
4491 * @brief HW_CAU_AESC_CA7 - General Purpose Register 7 - AES Column Operation command (WO)
4493 * Reset value: 0x00000000U
4495 typedef union _hw_cau_aesc_ca7
4498 struct _hw_cau_aesc_ca7_bitfields
4500 uint32_t CA7
: 32; /*!< [31:0] CA7 */
4502 } hw_cau_aesc_ca7_t
;
4505 * @name Constants and macros for entire CAU_AESC_CA7 register
4508 #define HW_CAU_AESC_CA7_ADDR(x) ((x) + 0xB24U)
4510 #define HW_CAU_AESC_CA7(x) (*(__O hw_cau_aesc_ca7_t *) HW_CAU_AESC_CA7_ADDR(x))
4511 #define HW_CAU_AESC_CA7_WR(x, v) (HW_CAU_AESC_CA7(x).U = (v))
4515 * Constants & macros for individual CAU_AESC_CA7 bitfields
4519 * @name Register CAU_AESC_CA7, field CA7[31:0] (WO)
4522 #define BP_CAU_AESC_CA7_CA7 (0U) /*!< Bit position for CAU_AESC_CA7_CA7. */
4523 #define BM_CAU_AESC_CA7_CA7 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESC_CA7_CA7. */
4524 #define BS_CAU_AESC_CA7_CA7 (32U) /*!< Bit field size in bits for CAU_AESC_CA7_CA7. */
4526 /*! @brief Format value for bitfield CAU_AESC_CA7_CA7. */
4527 #define BF_CAU_AESC_CA7_CA7(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CA7_CA7) & BM_CAU_AESC_CA7_CA7)
4530 /*******************************************************************************
4531 * HW_CAU_AESC_CA8 - General Purpose Register 8 - AES Column Operation command
4532 ******************************************************************************/
4535 * @brief HW_CAU_AESC_CA8 - General Purpose Register 8 - AES Column Operation command (WO)
4537 * Reset value: 0x00000000U
4539 typedef union _hw_cau_aesc_ca8
4542 struct _hw_cau_aesc_ca8_bitfields
4544 uint32_t CA8
: 32; /*!< [31:0] CA8 */
4546 } hw_cau_aesc_ca8_t
;
4549 * @name Constants and macros for entire CAU_AESC_CA8 register
4552 #define HW_CAU_AESC_CA8_ADDR(x) ((x) + 0xB28U)
4554 #define HW_CAU_AESC_CA8(x) (*(__O hw_cau_aesc_ca8_t *) HW_CAU_AESC_CA8_ADDR(x))
4555 #define HW_CAU_AESC_CA8_WR(x, v) (HW_CAU_AESC_CA8(x).U = (v))
4559 * Constants & macros for individual CAU_AESC_CA8 bitfields
4563 * @name Register CAU_AESC_CA8, field CA8[31:0] (WO)
4566 #define BP_CAU_AESC_CA8_CA8 (0U) /*!< Bit position for CAU_AESC_CA8_CA8. */
4567 #define BM_CAU_AESC_CA8_CA8 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESC_CA8_CA8. */
4568 #define BS_CAU_AESC_CA8_CA8 (32U) /*!< Bit field size in bits for CAU_AESC_CA8_CA8. */
4570 /*! @brief Format value for bitfield CAU_AESC_CA8_CA8. */
4571 #define BF_CAU_AESC_CA8_CA8(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CA8_CA8) & BM_CAU_AESC_CA8_CA8)
4574 /*******************************************************************************
4575 * HW_CAU_AESIC_CASR - Status register - AES Inverse Column Operation command
4576 ******************************************************************************/
4579 * @brief HW_CAU_AESIC_CASR - Status register - AES Inverse Column Operation command (WO)
4581 * Reset value: 0x20000000U
4583 typedef union _hw_cau_aesic_casr
4586 struct _hw_cau_aesic_casr_bitfields
4588 uint32_t IC
: 1; /*!< [0] */
4589 uint32_t DPE
: 1; /*!< [1] */
4590 uint32_t RESERVED0
: 26; /*!< [27:2] */
4591 uint32_t VER
: 4; /*!< [31:28] CAU version */
4593 } hw_cau_aesic_casr_t
;
4596 * @name Constants and macros for entire CAU_AESIC_CASR register
4599 #define HW_CAU_AESIC_CASR_ADDR(x) ((x) + 0xB40U)
4601 #define HW_CAU_AESIC_CASR(x) (*(__O hw_cau_aesic_casr_t *) HW_CAU_AESIC_CASR_ADDR(x))
4602 #define HW_CAU_AESIC_CASR_WR(x, v) (HW_CAU_AESIC_CASR(x).U = (v))
4606 * Constants & macros for individual CAU_AESIC_CASR bitfields
4610 * @name Register CAU_AESIC_CASR, field IC[0] (WO)
4613 * - 0 - No illegal commands issued
4614 * - 1 - Illegal command issued
4617 #define BP_CAU_AESIC_CASR_IC (0U) /*!< Bit position for CAU_AESIC_CASR_IC. */
4618 #define BM_CAU_AESIC_CASR_IC (0x00000001U) /*!< Bit mask for CAU_AESIC_CASR_IC. */
4619 #define BS_CAU_AESIC_CASR_IC (1U) /*!< Bit field size in bits for CAU_AESIC_CASR_IC. */
4621 /*! @brief Format value for bitfield CAU_AESIC_CASR_IC. */
4622 #define BF_CAU_AESIC_CASR_IC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CASR_IC) & BM_CAU_AESIC_CASR_IC)
4626 * @name Register CAU_AESIC_CASR, field DPE[1] (WO)
4629 * - 0 - No error detected
4630 * - 1 - DES key parity error detected
4633 #define BP_CAU_AESIC_CASR_DPE (1U) /*!< Bit position for CAU_AESIC_CASR_DPE. */
4634 #define BM_CAU_AESIC_CASR_DPE (0x00000002U) /*!< Bit mask for CAU_AESIC_CASR_DPE. */
4635 #define BS_CAU_AESIC_CASR_DPE (1U) /*!< Bit field size in bits for CAU_AESIC_CASR_DPE. */
4637 /*! @brief Format value for bitfield CAU_AESIC_CASR_DPE. */
4638 #define BF_CAU_AESIC_CASR_DPE(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CASR_DPE) & BM_CAU_AESIC_CASR_DPE)
4642 * @name Register CAU_AESIC_CASR, field VER[31:28] (WO)
4645 * - 0001 - Initial CAU version
4646 * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
4647 * value on this device)
4650 #define BP_CAU_AESIC_CASR_VER (28U) /*!< Bit position for CAU_AESIC_CASR_VER. */
4651 #define BM_CAU_AESIC_CASR_VER (0xF0000000U) /*!< Bit mask for CAU_AESIC_CASR_VER. */
4652 #define BS_CAU_AESIC_CASR_VER (4U) /*!< Bit field size in bits for CAU_AESIC_CASR_VER. */
4654 /*! @brief Format value for bitfield CAU_AESIC_CASR_VER. */
4655 #define BF_CAU_AESIC_CASR_VER(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CASR_VER) & BM_CAU_AESIC_CASR_VER)
4658 /*******************************************************************************
4659 * HW_CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command
4660 ******************************************************************************/
4663 * @brief HW_CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command (WO)
4665 * Reset value: 0x00000000U
4667 typedef union _hw_cau_aesic_caa
4670 struct _hw_cau_aesic_caa_bitfields
4672 uint32_t ACC
: 32; /*!< [31:0] ACC */
4674 } hw_cau_aesic_caa_t
;
4677 * @name Constants and macros for entire CAU_AESIC_CAA register
4680 #define HW_CAU_AESIC_CAA_ADDR(x) ((x) + 0xB44U)
4682 #define HW_CAU_AESIC_CAA(x) (*(__O hw_cau_aesic_caa_t *) HW_CAU_AESIC_CAA_ADDR(x))
4683 #define HW_CAU_AESIC_CAA_WR(x, v) (HW_CAU_AESIC_CAA(x).U = (v))
4687 * Constants & macros for individual CAU_AESIC_CAA bitfields
4691 * @name Register CAU_AESIC_CAA, field ACC[31:0] (WO)
4694 #define BP_CAU_AESIC_CAA_ACC (0U) /*!< Bit position for CAU_AESIC_CAA_ACC. */
4695 #define BM_CAU_AESIC_CAA_ACC (0xFFFFFFFFU) /*!< Bit mask for CAU_AESIC_CAA_ACC. */
4696 #define BS_CAU_AESIC_CAA_ACC (32U) /*!< Bit field size in bits for CAU_AESIC_CAA_ACC. */
4698 /*! @brief Format value for bitfield CAU_AESIC_CAA_ACC. */
4699 #define BF_CAU_AESIC_CAA_ACC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CAA_ACC) & BM_CAU_AESIC_CAA_ACC)
4702 /*******************************************************************************
4703 * HW_CAU_AESIC_CA0 - General Purpose Register 0 - AES Inverse Column Operation command
4704 ******************************************************************************/
4707 * @brief HW_CAU_AESIC_CA0 - General Purpose Register 0 - AES Inverse Column Operation command (WO)
4709 * Reset value: 0x00000000U
4711 typedef union _hw_cau_aesic_ca0
4714 struct _hw_cau_aesic_ca0_bitfields
4716 uint32_t CA0
: 32; /*!< [31:0] CA0 */
4718 } hw_cau_aesic_ca0_t
;
4721 * @name Constants and macros for entire CAU_AESIC_CA0 register
4724 #define HW_CAU_AESIC_CA0_ADDR(x) ((x) + 0xB48U)
4726 #define HW_CAU_AESIC_CA0(x) (*(__O hw_cau_aesic_ca0_t *) HW_CAU_AESIC_CA0_ADDR(x))
4727 #define HW_CAU_AESIC_CA0_WR(x, v) (HW_CAU_AESIC_CA0(x).U = (v))
4731 * Constants & macros for individual CAU_AESIC_CA0 bitfields
4735 * @name Register CAU_AESIC_CA0, field CA0[31:0] (WO)
4738 #define BP_CAU_AESIC_CA0_CA0 (0U) /*!< Bit position for CAU_AESIC_CA0_CA0. */
4739 #define BM_CAU_AESIC_CA0_CA0 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESIC_CA0_CA0. */
4740 #define BS_CAU_AESIC_CA0_CA0 (32U) /*!< Bit field size in bits for CAU_AESIC_CA0_CA0. */
4742 /*! @brief Format value for bitfield CAU_AESIC_CA0_CA0. */
4743 #define BF_CAU_AESIC_CA0_CA0(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CA0_CA0) & BM_CAU_AESIC_CA0_CA0)
4746 /*******************************************************************************
4747 * HW_CAU_AESIC_CA1 - General Purpose Register 1 - AES Inverse Column Operation command
4748 ******************************************************************************/
4751 * @brief HW_CAU_AESIC_CA1 - General Purpose Register 1 - AES Inverse Column Operation command (WO)
4753 * Reset value: 0x00000000U
4755 typedef union _hw_cau_aesic_ca1
4758 struct _hw_cau_aesic_ca1_bitfields
4760 uint32_t CA1
: 32; /*!< [31:0] CA1 */
4762 } hw_cau_aesic_ca1_t
;
4765 * @name Constants and macros for entire CAU_AESIC_CA1 register
4768 #define HW_CAU_AESIC_CA1_ADDR(x) ((x) + 0xB4CU)
4770 #define HW_CAU_AESIC_CA1(x) (*(__O hw_cau_aesic_ca1_t *) HW_CAU_AESIC_CA1_ADDR(x))
4771 #define HW_CAU_AESIC_CA1_WR(x, v) (HW_CAU_AESIC_CA1(x).U = (v))
4775 * Constants & macros for individual CAU_AESIC_CA1 bitfields
4779 * @name Register CAU_AESIC_CA1, field CA1[31:0] (WO)
4782 #define BP_CAU_AESIC_CA1_CA1 (0U) /*!< Bit position for CAU_AESIC_CA1_CA1. */
4783 #define BM_CAU_AESIC_CA1_CA1 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESIC_CA1_CA1. */
4784 #define BS_CAU_AESIC_CA1_CA1 (32U) /*!< Bit field size in bits for CAU_AESIC_CA1_CA1. */
4786 /*! @brief Format value for bitfield CAU_AESIC_CA1_CA1. */
4787 #define BF_CAU_AESIC_CA1_CA1(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CA1_CA1) & BM_CAU_AESIC_CA1_CA1)
4790 /*******************************************************************************
4791 * HW_CAU_AESIC_CA2 - General Purpose Register 2 - AES Inverse Column Operation command
4792 ******************************************************************************/
4795 * @brief HW_CAU_AESIC_CA2 - General Purpose Register 2 - AES Inverse Column Operation command (WO)
4797 * Reset value: 0x00000000U
4799 typedef union _hw_cau_aesic_ca2
4802 struct _hw_cau_aesic_ca2_bitfields
4804 uint32_t CA2
: 32; /*!< [31:0] CA2 */
4806 } hw_cau_aesic_ca2_t
;
4809 * @name Constants and macros for entire CAU_AESIC_CA2 register
4812 #define HW_CAU_AESIC_CA2_ADDR(x) ((x) + 0xB50U)
4814 #define HW_CAU_AESIC_CA2(x) (*(__O hw_cau_aesic_ca2_t *) HW_CAU_AESIC_CA2_ADDR(x))
4815 #define HW_CAU_AESIC_CA2_WR(x, v) (HW_CAU_AESIC_CA2(x).U = (v))
4819 * Constants & macros for individual CAU_AESIC_CA2 bitfields
4823 * @name Register CAU_AESIC_CA2, field CA2[31:0] (WO)
4826 #define BP_CAU_AESIC_CA2_CA2 (0U) /*!< Bit position for CAU_AESIC_CA2_CA2. */
4827 #define BM_CAU_AESIC_CA2_CA2 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESIC_CA2_CA2. */
4828 #define BS_CAU_AESIC_CA2_CA2 (32U) /*!< Bit field size in bits for CAU_AESIC_CA2_CA2. */
4830 /*! @brief Format value for bitfield CAU_AESIC_CA2_CA2. */
4831 #define BF_CAU_AESIC_CA2_CA2(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CA2_CA2) & BM_CAU_AESIC_CA2_CA2)
4834 /*******************************************************************************
4835 * HW_CAU_AESIC_CA3 - General Purpose Register 3 - AES Inverse Column Operation command
4836 ******************************************************************************/
4839 * @brief HW_CAU_AESIC_CA3 - General Purpose Register 3 - AES Inverse Column Operation command (WO)
4841 * Reset value: 0x00000000U
4843 typedef union _hw_cau_aesic_ca3
4846 struct _hw_cau_aesic_ca3_bitfields
4848 uint32_t CA3
: 32; /*!< [31:0] CA3 */
4850 } hw_cau_aesic_ca3_t
;
4853 * @name Constants and macros for entire CAU_AESIC_CA3 register
4856 #define HW_CAU_AESIC_CA3_ADDR(x) ((x) + 0xB54U)
4858 #define HW_CAU_AESIC_CA3(x) (*(__O hw_cau_aesic_ca3_t *) HW_CAU_AESIC_CA3_ADDR(x))
4859 #define HW_CAU_AESIC_CA3_WR(x, v) (HW_CAU_AESIC_CA3(x).U = (v))
4863 * Constants & macros for individual CAU_AESIC_CA3 bitfields
4867 * @name Register CAU_AESIC_CA3, field CA3[31:0] (WO)
4870 #define BP_CAU_AESIC_CA3_CA3 (0U) /*!< Bit position for CAU_AESIC_CA3_CA3. */
4871 #define BM_CAU_AESIC_CA3_CA3 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESIC_CA3_CA3. */
4872 #define BS_CAU_AESIC_CA3_CA3 (32U) /*!< Bit field size in bits for CAU_AESIC_CA3_CA3. */
4874 /*! @brief Format value for bitfield CAU_AESIC_CA3_CA3. */
4875 #define BF_CAU_AESIC_CA3_CA3(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CA3_CA3) & BM_CAU_AESIC_CA3_CA3)
4878 /*******************************************************************************
4879 * HW_CAU_AESIC_CA4 - General Purpose Register 4 - AES Inverse Column Operation command
4880 ******************************************************************************/
4883 * @brief HW_CAU_AESIC_CA4 - General Purpose Register 4 - AES Inverse Column Operation command (WO)
4885 * Reset value: 0x00000000U
4887 typedef union _hw_cau_aesic_ca4
4890 struct _hw_cau_aesic_ca4_bitfields
4892 uint32_t CA4
: 32; /*!< [31:0] CA4 */
4894 } hw_cau_aesic_ca4_t
;
4897 * @name Constants and macros for entire CAU_AESIC_CA4 register
4900 #define HW_CAU_AESIC_CA4_ADDR(x) ((x) + 0xB58U)
4902 #define HW_CAU_AESIC_CA4(x) (*(__O hw_cau_aesic_ca4_t *) HW_CAU_AESIC_CA4_ADDR(x))
4903 #define HW_CAU_AESIC_CA4_WR(x, v) (HW_CAU_AESIC_CA4(x).U = (v))
4907 * Constants & macros for individual CAU_AESIC_CA4 bitfields
4911 * @name Register CAU_AESIC_CA4, field CA4[31:0] (WO)
4914 #define BP_CAU_AESIC_CA4_CA4 (0U) /*!< Bit position for CAU_AESIC_CA4_CA4. */
4915 #define BM_CAU_AESIC_CA4_CA4 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESIC_CA4_CA4. */
4916 #define BS_CAU_AESIC_CA4_CA4 (32U) /*!< Bit field size in bits for CAU_AESIC_CA4_CA4. */
4918 /*! @brief Format value for bitfield CAU_AESIC_CA4_CA4. */
4919 #define BF_CAU_AESIC_CA4_CA4(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CA4_CA4) & BM_CAU_AESIC_CA4_CA4)
4922 /*******************************************************************************
4923 * HW_CAU_AESIC_CA5 - General Purpose Register 5 - AES Inverse Column Operation command
4924 ******************************************************************************/
4927 * @brief HW_CAU_AESIC_CA5 - General Purpose Register 5 - AES Inverse Column Operation command (WO)
4929 * Reset value: 0x00000000U
4931 typedef union _hw_cau_aesic_ca5
4934 struct _hw_cau_aesic_ca5_bitfields
4936 uint32_t CA5
: 32; /*!< [31:0] CA5 */
4938 } hw_cau_aesic_ca5_t
;
4941 * @name Constants and macros for entire CAU_AESIC_CA5 register
4944 #define HW_CAU_AESIC_CA5_ADDR(x) ((x) + 0xB5CU)
4946 #define HW_CAU_AESIC_CA5(x) (*(__O hw_cau_aesic_ca5_t *) HW_CAU_AESIC_CA5_ADDR(x))
4947 #define HW_CAU_AESIC_CA5_WR(x, v) (HW_CAU_AESIC_CA5(x).U = (v))
4951 * Constants & macros for individual CAU_AESIC_CA5 bitfields
4955 * @name Register CAU_AESIC_CA5, field CA5[31:0] (WO)
4958 #define BP_CAU_AESIC_CA5_CA5 (0U) /*!< Bit position for CAU_AESIC_CA5_CA5. */
4959 #define BM_CAU_AESIC_CA5_CA5 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESIC_CA5_CA5. */
4960 #define BS_CAU_AESIC_CA5_CA5 (32U) /*!< Bit field size in bits for CAU_AESIC_CA5_CA5. */
4962 /*! @brief Format value for bitfield CAU_AESIC_CA5_CA5. */
4963 #define BF_CAU_AESIC_CA5_CA5(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CA5_CA5) & BM_CAU_AESIC_CA5_CA5)
4966 /*******************************************************************************
4967 * HW_CAU_AESIC_CA6 - General Purpose Register 6 - AES Inverse Column Operation command
4968 ******************************************************************************/
4971 * @brief HW_CAU_AESIC_CA6 - General Purpose Register 6 - AES Inverse Column Operation command (WO)
4973 * Reset value: 0x00000000U
4975 typedef union _hw_cau_aesic_ca6
4978 struct _hw_cau_aesic_ca6_bitfields
4980 uint32_t CA6
: 32; /*!< [31:0] CA6 */
4982 } hw_cau_aesic_ca6_t
;
4985 * @name Constants and macros for entire CAU_AESIC_CA6 register
4988 #define HW_CAU_AESIC_CA6_ADDR(x) ((x) + 0xB60U)
4990 #define HW_CAU_AESIC_CA6(x) (*(__O hw_cau_aesic_ca6_t *) HW_CAU_AESIC_CA6_ADDR(x))
4991 #define HW_CAU_AESIC_CA6_WR(x, v) (HW_CAU_AESIC_CA6(x).U = (v))
4995 * Constants & macros for individual CAU_AESIC_CA6 bitfields
4999 * @name Register CAU_AESIC_CA6, field CA6[31:0] (WO)
5002 #define BP_CAU_AESIC_CA6_CA6 (0U) /*!< Bit position for CAU_AESIC_CA6_CA6. */
5003 #define BM_CAU_AESIC_CA6_CA6 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESIC_CA6_CA6. */
5004 #define BS_CAU_AESIC_CA6_CA6 (32U) /*!< Bit field size in bits for CAU_AESIC_CA6_CA6. */
5006 /*! @brief Format value for bitfield CAU_AESIC_CA6_CA6. */
5007 #define BF_CAU_AESIC_CA6_CA6(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CA6_CA6) & BM_CAU_AESIC_CA6_CA6)
5010 /*******************************************************************************
5011 * HW_CAU_AESIC_CA7 - General Purpose Register 7 - AES Inverse Column Operation command
5012 ******************************************************************************/
5015 * @brief HW_CAU_AESIC_CA7 - General Purpose Register 7 - AES Inverse Column Operation command (WO)
5017 * Reset value: 0x00000000U
5019 typedef union _hw_cau_aesic_ca7
5022 struct _hw_cau_aesic_ca7_bitfields
5024 uint32_t CA7
: 32; /*!< [31:0] CA7 */
5026 } hw_cau_aesic_ca7_t
;
5029 * @name Constants and macros for entire CAU_AESIC_CA7 register
5032 #define HW_CAU_AESIC_CA7_ADDR(x) ((x) + 0xB64U)
5034 #define HW_CAU_AESIC_CA7(x) (*(__O hw_cau_aesic_ca7_t *) HW_CAU_AESIC_CA7_ADDR(x))
5035 #define HW_CAU_AESIC_CA7_WR(x, v) (HW_CAU_AESIC_CA7(x).U = (v))
5039 * Constants & macros for individual CAU_AESIC_CA7 bitfields
5043 * @name Register CAU_AESIC_CA7, field CA7[31:0] (WO)
5046 #define BP_CAU_AESIC_CA7_CA7 (0U) /*!< Bit position for CAU_AESIC_CA7_CA7. */
5047 #define BM_CAU_AESIC_CA7_CA7 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESIC_CA7_CA7. */
5048 #define BS_CAU_AESIC_CA7_CA7 (32U) /*!< Bit field size in bits for CAU_AESIC_CA7_CA7. */
5050 /*! @brief Format value for bitfield CAU_AESIC_CA7_CA7. */
5051 #define BF_CAU_AESIC_CA7_CA7(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CA7_CA7) & BM_CAU_AESIC_CA7_CA7)
5054 /*******************************************************************************
5055 * HW_CAU_AESIC_CA8 - General Purpose Register 8 - AES Inverse Column Operation command
5056 ******************************************************************************/
5059 * @brief HW_CAU_AESIC_CA8 - General Purpose Register 8 - AES Inverse Column Operation command (WO)
5061 * Reset value: 0x00000000U
5063 typedef union _hw_cau_aesic_ca8
5066 struct _hw_cau_aesic_ca8_bitfields
5068 uint32_t CA8
: 32; /*!< [31:0] CA8 */
5070 } hw_cau_aesic_ca8_t
;
5073 * @name Constants and macros for entire CAU_AESIC_CA8 register
5076 #define HW_CAU_AESIC_CA8_ADDR(x) ((x) + 0xB68U)
5078 #define HW_CAU_AESIC_CA8(x) (*(__O hw_cau_aesic_ca8_t *) HW_CAU_AESIC_CA8_ADDR(x))
5079 #define HW_CAU_AESIC_CA8_WR(x, v) (HW_CAU_AESIC_CA8(x).U = (v))
5083 * Constants & macros for individual CAU_AESIC_CA8 bitfields
5087 * @name Register CAU_AESIC_CA8, field CA8[31:0] (WO)
5090 #define BP_CAU_AESIC_CA8_CA8 (0U) /*!< Bit position for CAU_AESIC_CA8_CA8. */
5091 #define BM_CAU_AESIC_CA8_CA8 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESIC_CA8_CA8. */
5092 #define BS_CAU_AESIC_CA8_CA8 (32U) /*!< Bit field size in bits for CAU_AESIC_CA8_CA8. */
5094 /*! @brief Format value for bitfield CAU_AESIC_CA8_CA8. */
5095 #define BF_CAU_AESIC_CA8_CA8(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CA8_CA8) & BM_CAU_AESIC_CA8_CA8)
5098 /*******************************************************************************
5099 * hw_cau_t - module struct
5100 ******************************************************************************/
5102 * @brief All CAU module registers.
5105 typedef struct _hw_cau
5107 __O hw_cau_direct0_t DIRECT0
; /*!< [0x0] Direct access register 0 */
5108 __O hw_cau_direct1_t DIRECT1
; /*!< [0x4] Direct access register 1 */
5109 __O hw_cau_direct2_t DIRECT2
; /*!< [0x8] Direct access register 2 */
5110 __O hw_cau_direct3_t DIRECT3
; /*!< [0xC] Direct access register 3 */
5111 __O hw_cau_direct4_t DIRECT4
; /*!< [0x10] Direct access register 4 */
5112 __O hw_cau_direct5_t DIRECT5
; /*!< [0x14] Direct access register 5 */
5113 __O hw_cau_direct6_t DIRECT6
; /*!< [0x18] Direct access register 6 */
5114 __O hw_cau_direct7_t DIRECT7
; /*!< [0x1C] Direct access register 7 */
5115 __O hw_cau_direct8_t DIRECT8
; /*!< [0x20] Direct access register 8 */
5116 __O hw_cau_direct9_t DIRECT9
; /*!< [0x24] Direct access register 9 */
5117 __O hw_cau_direct10_t DIRECT10
; /*!< [0x28] Direct access register 10 */
5118 __O hw_cau_direct11_t DIRECT11
; /*!< [0x2C] Direct access register 11 */
5119 __O hw_cau_direct12_t DIRECT12
; /*!< [0x30] Direct access register 12 */
5120 __O hw_cau_direct13_t DIRECT13
; /*!< [0x34] Direct access register 13 */
5121 __O hw_cau_direct14_t DIRECT14
; /*!< [0x38] Direct access register 14 */
5122 __O hw_cau_direct15_t DIRECT15
; /*!< [0x3C] Direct access register 15 */
5123 uint8_t _reserved0
[2048];
5124 __O hw_cau_ldr_casr_t LDR_CASR
; /*!< [0x840] Status register - Load Register command */
5125 __O hw_cau_ldr_caa_t LDR_CAA
; /*!< [0x844] Accumulator register - Load Register command */
5126 __O hw_cau_ldr_ca0_t LDR_CA0
; /*!< [0x848] General Purpose Register 0 - Load Register command */
5127 __O hw_cau_ldr_ca1_t LDR_CA1
; /*!< [0x84C] General Purpose Register 1 - Load Register command */
5128 __O hw_cau_ldr_ca2_t LDR_CA2
; /*!< [0x850] General Purpose Register 2 - Load Register command */
5129 __O hw_cau_ldr_ca3_t LDR_CA3
; /*!< [0x854] General Purpose Register 3 - Load Register command */
5130 __O hw_cau_ldr_ca4_t LDR_CA4
; /*!< [0x858] General Purpose Register 4 - Load Register command */
5131 __O hw_cau_ldr_ca5_t LDR_CA5
; /*!< [0x85C] General Purpose Register 5 - Load Register command */
5132 __O hw_cau_ldr_ca6_t LDR_CA6
; /*!< [0x860] General Purpose Register 6 - Load Register command */
5133 __O hw_cau_ldr_ca7_t LDR_CA7
; /*!< [0x864] General Purpose Register 7 - Load Register command */
5134 __O hw_cau_ldr_ca8_t LDR_CA8
; /*!< [0x868] General Purpose Register 8 - Load Register command */
5135 uint8_t _reserved1
[20];
5136 __I hw_cau_str_casr_t STR_CASR
; /*!< [0x880] Status register - Store Register command */
5137 __I hw_cau_str_caa_t STR_CAA
; /*!< [0x884] Accumulator register - Store Register command */
5138 __I hw_cau_str_ca0_t STR_CA0
; /*!< [0x888] General Purpose Register 0 - Store Register command */
5139 __I hw_cau_str_ca1_t STR_CA1
; /*!< [0x88C] General Purpose Register 1 - Store Register command */
5140 __I hw_cau_str_ca2_t STR_CA2
; /*!< [0x890] General Purpose Register 2 - Store Register command */
5141 __I hw_cau_str_ca3_t STR_CA3
; /*!< [0x894] General Purpose Register 3 - Store Register command */
5142 __I hw_cau_str_ca4_t STR_CA4
; /*!< [0x898] General Purpose Register 4 - Store Register command */
5143 __I hw_cau_str_ca5_t STR_CA5
; /*!< [0x89C] General Purpose Register 5 - Store Register command */
5144 __I hw_cau_str_ca6_t STR_CA6
; /*!< [0x8A0] General Purpose Register 6 - Store Register command */
5145 __I hw_cau_str_ca7_t STR_CA7
; /*!< [0x8A4] General Purpose Register 7 - Store Register command */
5146 __I hw_cau_str_ca8_t STR_CA8
; /*!< [0x8A8] General Purpose Register 8 - Store Register command */
5147 uint8_t _reserved2
[20];
5148 __O hw_cau_adr_casr_t ADR_CASR
; /*!< [0x8C0] Status register - Add Register command */
5149 __O hw_cau_adr_caa_t ADR_CAA
; /*!< [0x8C4] Accumulator register - Add to register command */
5150 __O hw_cau_adr_ca0_t ADR_CA0
; /*!< [0x8C8] General Purpose Register 0 - Add to register command */
5151 __O hw_cau_adr_ca1_t ADR_CA1
; /*!< [0x8CC] General Purpose Register 1 - Add to register command */
5152 __O hw_cau_adr_ca2_t ADR_CA2
; /*!< [0x8D0] General Purpose Register 2 - Add to register command */
5153 __O hw_cau_adr_ca3_t ADR_CA3
; /*!< [0x8D4] General Purpose Register 3 - Add to register command */
5154 __O hw_cau_adr_ca4_t ADR_CA4
; /*!< [0x8D8] General Purpose Register 4 - Add to register command */
5155 __O hw_cau_adr_ca5_t ADR_CA5
; /*!< [0x8DC] General Purpose Register 5 - Add to register command */
5156 __O hw_cau_adr_ca6_t ADR_CA6
; /*!< [0x8E0] General Purpose Register 6 - Add to register command */
5157 __O hw_cau_adr_ca7_t ADR_CA7
; /*!< [0x8E4] General Purpose Register 7 - Add to register command */
5158 __O hw_cau_adr_ca8_t ADR_CA8
; /*!< [0x8E8] General Purpose Register 8 - Add to register command */
5159 uint8_t _reserved3
[20];
5160 __O hw_cau_radr_casr_t RADR_CASR
; /*!< [0x900] Status register - Reverse and Add to Register command */
5161 __O hw_cau_radr_caa_t RADR_CAA
; /*!< [0x904] Accumulator register - Reverse and Add to Register command */
5162 __O hw_cau_radr_ca0_t RADR_CA0
; /*!< [0x908] General Purpose Register 0 - Reverse and Add to Register command */
5163 __O hw_cau_radr_ca1_t RADR_CA1
; /*!< [0x90C] General Purpose Register 1 - Reverse and Add to Register command */
5164 __O hw_cau_radr_ca2_t RADR_CA2
; /*!< [0x910] General Purpose Register 2 - Reverse and Add to Register command */
5165 __O hw_cau_radr_ca3_t RADR_CA3
; /*!< [0x914] General Purpose Register 3 - Reverse and Add to Register command */
5166 __O hw_cau_radr_ca4_t RADR_CA4
; /*!< [0x918] General Purpose Register 4 - Reverse and Add to Register command */
5167 __O hw_cau_radr_ca5_t RADR_CA5
; /*!< [0x91C] General Purpose Register 5 - Reverse and Add to Register command */
5168 __O hw_cau_radr_ca6_t RADR_CA6
; /*!< [0x920] General Purpose Register 6 - Reverse and Add to Register command */
5169 __O hw_cau_radr_ca7_t RADR_CA7
; /*!< [0x924] General Purpose Register 7 - Reverse and Add to Register command */
5170 __O hw_cau_radr_ca8_t RADR_CA8
; /*!< [0x928] General Purpose Register 8 - Reverse and Add to Register command */
5171 uint8_t _reserved4
[84];
5172 __O hw_cau_xor_casr_t XOR_CASR
; /*!< [0x980] Status register - Exclusive Or command */
5173 __O hw_cau_xor_caa_t XOR_CAA
; /*!< [0x984] Accumulator register - Exclusive Or command */
5174 __O hw_cau_xor_ca0_t XOR_CA0
; /*!< [0x988] General Purpose Register 0 - Exclusive Or command */
5175 __O hw_cau_xor_ca1_t XOR_CA1
; /*!< [0x98C] General Purpose Register 1 - Exclusive Or command */
5176 __O hw_cau_xor_ca2_t XOR_CA2
; /*!< [0x990] General Purpose Register 2 - Exclusive Or command */
5177 __O hw_cau_xor_ca3_t XOR_CA3
; /*!< [0x994] General Purpose Register 3 - Exclusive Or command */
5178 __O hw_cau_xor_ca4_t XOR_CA4
; /*!< [0x998] General Purpose Register 4 - Exclusive Or command */
5179 __O hw_cau_xor_ca5_t XOR_CA5
; /*!< [0x99C] General Purpose Register 5 - Exclusive Or command */
5180 __O hw_cau_xor_ca6_t XOR_CA6
; /*!< [0x9A0] General Purpose Register 6 - Exclusive Or command */
5181 __O hw_cau_xor_ca7_t XOR_CA7
; /*!< [0x9A4] General Purpose Register 7 - Exclusive Or command */
5182 __O hw_cau_xor_ca8_t XOR_CA8
; /*!< [0x9A8] General Purpose Register 8 - Exclusive Or command */
5183 uint8_t _reserved5
[20];
5184 __O hw_cau_rotl_casr_t ROTL_CASR
; /*!< [0x9C0] Status register - Rotate Left command */
5185 __O hw_cau_rotl_caa_t ROTL_CAA
; /*!< [0x9C4] Accumulator register - Rotate Left command */
5186 __O hw_cau_rotl_ca0_t ROTL_CA0
; /*!< [0x9C8] General Purpose Register 0 - Rotate Left command */
5187 __O hw_cau_rotl_ca1_t ROTL_CA1
; /*!< [0x9CC] General Purpose Register 1 - Rotate Left command */
5188 __O hw_cau_rotl_ca2_t ROTL_CA2
; /*!< [0x9D0] General Purpose Register 2 - Rotate Left command */
5189 __O hw_cau_rotl_ca3_t ROTL_CA3
; /*!< [0x9D4] General Purpose Register 3 - Rotate Left command */
5190 __O hw_cau_rotl_ca4_t ROTL_CA4
; /*!< [0x9D8] General Purpose Register 4 - Rotate Left command */
5191 __O hw_cau_rotl_ca5_t ROTL_CA5
; /*!< [0x9DC] General Purpose Register 5 - Rotate Left command */
5192 __O hw_cau_rotl_ca6_t ROTL_CA6
; /*!< [0x9E0] General Purpose Register 6 - Rotate Left command */
5193 __O hw_cau_rotl_ca7_t ROTL_CA7
; /*!< [0x9E4] General Purpose Register 7 - Rotate Left command */
5194 __O hw_cau_rotl_ca8_t ROTL_CA8
; /*!< [0x9E8] General Purpose Register 8 - Rotate Left command */
5195 uint8_t _reserved6
[276];
5196 __O hw_cau_aesc_casr_t AESC_CASR
; /*!< [0xB00] Status register - AES Column Operation command */
5197 __O hw_cau_aesc_caa_t AESC_CAA
; /*!< [0xB04] Accumulator register - AES Column Operation command */
5198 __O hw_cau_aesc_ca0_t AESC_CA0
; /*!< [0xB08] General Purpose Register 0 - AES Column Operation command */
5199 __O hw_cau_aesc_ca1_t AESC_CA1
; /*!< [0xB0C] General Purpose Register 1 - AES Column Operation command */
5200 __O hw_cau_aesc_ca2_t AESC_CA2
; /*!< [0xB10] General Purpose Register 2 - AES Column Operation command */
5201 __O hw_cau_aesc_ca3_t AESC_CA3
; /*!< [0xB14] General Purpose Register 3 - AES Column Operation command */
5202 __O hw_cau_aesc_ca4_t AESC_CA4
; /*!< [0xB18] General Purpose Register 4 - AES Column Operation command */
5203 __O hw_cau_aesc_ca5_t AESC_CA5
; /*!< [0xB1C] General Purpose Register 5 - AES Column Operation command */
5204 __O hw_cau_aesc_ca6_t AESC_CA6
; /*!< [0xB20] General Purpose Register 6 - AES Column Operation command */
5205 __O hw_cau_aesc_ca7_t AESC_CA7
; /*!< [0xB24] General Purpose Register 7 - AES Column Operation command */
5206 __O hw_cau_aesc_ca8_t AESC_CA8
; /*!< [0xB28] General Purpose Register 8 - AES Column Operation command */
5207 uint8_t _reserved7
[20];
5208 __O hw_cau_aesic_casr_t AESIC_CASR
; /*!< [0xB40] Status register - AES Inverse Column Operation command */
5209 __O hw_cau_aesic_caa_t AESIC_CAA
; /*!< [0xB44] Accumulator register - AES Inverse Column Operation command */
5210 __O hw_cau_aesic_ca0_t AESIC_CA0
; /*!< [0xB48] General Purpose Register 0 - AES Inverse Column Operation command */
5211 __O hw_cau_aesic_ca1_t AESIC_CA1
; /*!< [0xB4C] General Purpose Register 1 - AES Inverse Column Operation command */
5212 __O hw_cau_aesic_ca2_t AESIC_CA2
; /*!< [0xB50] General Purpose Register 2 - AES Inverse Column Operation command */
5213 __O hw_cau_aesic_ca3_t AESIC_CA3
; /*!< [0xB54] General Purpose Register 3 - AES Inverse Column Operation command */
5214 __O hw_cau_aesic_ca4_t AESIC_CA4
; /*!< [0xB58] General Purpose Register 4 - AES Inverse Column Operation command */
5215 __O hw_cau_aesic_ca5_t AESIC_CA5
; /*!< [0xB5C] General Purpose Register 5 - AES Inverse Column Operation command */
5216 __O hw_cau_aesic_ca6_t AESIC_CA6
; /*!< [0xB60] General Purpose Register 6 - AES Inverse Column Operation command */
5217 __O hw_cau_aesic_ca7_t AESIC_CA7
; /*!< [0xB64] General Purpose Register 7 - AES Inverse Column Operation command */
5218 __O hw_cau_aesic_ca8_t AESIC_CA8
; /*!< [0xB68] General Purpose Register 8 - AES Inverse Column Operation command */
5222 /*! @brief Macro to access all CAU registers. */
5223 /*! @param x CAU module instance base address. */
5224 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
5225 * use the '&' operator, like <code>&HW_CAU(CAU_BASE)</code>. */
5226 #define HW_CAU(x) (*(hw_cau_t *)(x))
5228 #endif /* __HW_CAU_REGISTERS_H__ */