tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_cmp.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
   9 **     Version:             rev. 2.5, 2014-02-10
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-08-12)
  48 **         Initial version.
  49 **     - rev. 2.0 (2013-10-29)
  50 **         Register accessor macros added to the memory map.
  51 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  52 **         Startup file for gcc has been updated according to CMSIS 3.2.
  53 **         System initialization updated.
  54 **         MCG - registers updated.
  55 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-09)
  59 **         DMA - EARS register removed.
  60 **         AIPS0, AIPS1 - MPRA register updated.
  61 **     - rev. 2.3 (2014-01-24)
  62 **         Update according to reference manual rev. 2
  63 **         ENET, MCG, MCM, SIM, USB - registers updated
  64 **     - rev. 2.4 (2014-02-10)
  65 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  66 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  67 **     - rev. 2.5 (2014-02-10)
  68 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  69 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  70 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  71 **
  72 ** ###################################################################
  73 */
  74
  75 /*
  76  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  77  *
  78  * This file was generated automatically and any changes may be lost.
  79  */
  80 #ifndef __HW_CMP_REGISTERS_H__
  81 #define __HW_CMP_REGISTERS_H__
  82
  83 #include "MK64F12.h"
  84 #include "fsl_bitaccess.h"
  85
  86 /*
  87  * MK64F12 CMP
  88  *
  89  * High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
  90  *
  91  * Registers defined in this header file:
  92  * - HW_CMP_CR0 - CMP Control Register 0
  93  * - HW_CMP_CR1 - CMP Control Register 1
  94  * - HW_CMP_FPR - CMP Filter Period Register
  95  * - HW_CMP_SCR - CMP Status and Control Register
  96  * - HW_CMP_DACCR - DAC Control Register
  97  * - HW_CMP_MUXCR - MUX Control Register
  98  *
  99  * - hw_cmp_t - Struct containing all module registers.
 100  */
 101
 102 #define HW_CMP_INSTANCE_COUNT (3U) /*!< Number of instances of the CMP module. */
 103 #define HW_CMP0 (0U) /*!< Instance number for CMP0. */
 104 #define HW_CMP1 (1U) /*!< Instance number for CMP1. */
 105 #define HW_CMP2 (2U) /*!< Instance number for CMP2. */
 106
 107 /*******************************************************************************
 108  * HW_CMP_CR0 - CMP Control Register 0
 109  ******************************************************************************/
 110
 111 /*!
 112  * @brief HW_CMP_CR0 - CMP Control Register 0 (RW)
 113  *
 114  * Reset value: 0x00U
 115  */
 116 typedef union _hw_cmp_cr0
 117 {
 118     uint8_t U;
 119     struct _hw_cmp_cr0_bitfields
 120     {
 121         uint8_t HYSTCTR : 2;           /*!< [1:0] Comparator hard block hysteresis
 122                                         * control */
 123         uint8_t RESERVED0 : 2;         /*!< [3:2]  */
 124         uint8_t FILTER_CNT : 3;        /*!< [6:4] Filter Sample Count */
 125         uint8_t RESERVED1 : 1;         /*!< [7]  */
 126     } B;
 127 } hw_cmp_cr0_t;
 128
 129 /*!
 130  * @name Constants and macros for entire CMP_CR0 register
 131  */
 132 /*@{*/
 133 #define HW_CMP_CR0_ADDR(x)       ((x) + 0x0U)
 134
 135 #define HW_CMP_CR0(x)            (*(__IO hw_cmp_cr0_t *) HW_CMP_CR0_ADDR(x))
 136 #define HW_CMP_CR0_RD(x)         (HW_CMP_CR0(x).U)
 137 #define HW_CMP_CR0_WR(x, v)      (HW_CMP_CR0(x).U = (v))
 138 #define HW_CMP_CR0_SET(x, v)     (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) |  (v)))
 139 #define HW_CMP_CR0_CLR(x, v)     (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) & ~(v)))
 140 #define HW_CMP_CR0_TOG(x, v)     (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) ^  (v)))
 141 /*@}*/
 142
 143 /*
 144  * Constants & macros for individual CMP_CR0 bitfields
 145  */
 146
 147 /*!
 148  * @name Register CMP_CR0, field HYSTCTR[1:0] (RW)
 149  *
 150  * Defines the programmable hysteresis level. The hysteresis values associated
 151  * with each level are device-specific. See the Data Sheet of the device for the
 152  * exact values.
 153  *
 154  * Values:
 155  * - 00 - Level 0
 156  * - 01 - Level 1
 157  * - 10 - Level 2
 158  * - 11 - Level 3
 159  */
 160 /*@{*/
 161 #define BP_CMP_CR0_HYSTCTR   (0U)          /*!< Bit position for CMP_CR0_HYSTCTR. */
 162 #define BM_CMP_CR0_HYSTCTR   (0x03U)       /*!< Bit mask for CMP_CR0_HYSTCTR. */
 163 #define BS_CMP_CR0_HYSTCTR   (2U)          /*!< Bit field size in bits for CMP_CR0_HYSTCTR. */
 164
 165 /*! @brief Read current value of the CMP_CR0_HYSTCTR field. */
 166 #define BR_CMP_CR0_HYSTCTR(x) (HW_CMP_CR0(x).B.HYSTCTR)
 167
 168 /*! @brief Format value for bitfield CMP_CR0_HYSTCTR. */
 169 #define BF_CMP_CR0_HYSTCTR(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR0_HYSTCTR) & BM_CMP_CR0_HYSTCTR)
 170
 171 /*! @brief Set the HYSTCTR field to a new value. */
 172 #define BW_CMP_CR0_HYSTCTR(x, v) (HW_CMP_CR0_WR(x, (HW_CMP_CR0_RD(x) & ~BM_CMP_CR0_HYSTCTR) | BF_CMP_CR0_HYSTCTR(v)))
 173 /*@}*/
 174
 175 /*!
 176  * @name Register CMP_CR0, field FILTER_CNT[6:4] (RW)
 177  *
 178  * Represents the number of consecutive samples that must agree prior to the
 179  * comparator ouput filter accepting a new output state. For information regarding
 180  * filter programming and latency, see the Functional descriptionThe CMP module
 181  * can be used to compare two analog input voltages applied to INP and INM. .
 182  *
 183  * Values:
 184  * - 000 - Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a
 185  *     legal state, and is not recommended. If SE = 0, COUT = COUTA.
 186  * - 001 - One sample must agree. The comparator output is simply sampled.
 187  * - 010 - 2 consecutive samples must agree.
 188  * - 011 - 3 consecutive samples must agree.
 189  * - 100 - 4 consecutive samples must agree.
 190  * - 101 - 5 consecutive samples must agree.
 191  * - 110 - 6 consecutive samples must agree.
 192  * - 111 - 7 consecutive samples must agree.
 193  */
 194 /*@{*/
 195 #define BP_CMP_CR0_FILTER_CNT (4U)         /*!< Bit position for CMP_CR0_FILTER_CNT. */
 196 #define BM_CMP_CR0_FILTER_CNT (0x70U)      /*!< Bit mask for CMP_CR0_FILTER_CNT. */
 197 #define BS_CMP_CR0_FILTER_CNT (3U)         /*!< Bit field size in bits for CMP_CR0_FILTER_CNT. */
 198
 199 /*! @brief Read current value of the CMP_CR0_FILTER_CNT field. */
 200 #define BR_CMP_CR0_FILTER_CNT(x) (HW_CMP_CR0(x).B.FILTER_CNT)
 201
 202 /*! @brief Format value for bitfield CMP_CR0_FILTER_CNT. */
 203 #define BF_CMP_CR0_FILTER_CNT(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR0_FILTER_CNT) & BM_CMP_CR0_FILTER_CNT)
 204
 205 /*! @brief Set the FILTER_CNT field to a new value. */
 206 #define BW_CMP_CR0_FILTER_CNT(x, v) (HW_CMP_CR0_WR(x, (HW_CMP_CR0_RD(x) & ~BM_CMP_CR0_FILTER_CNT) | BF_CMP_CR0_FILTER_CNT(v)))
 207 /*@}*/
 208
 209 /*******************************************************************************
 210  * HW_CMP_CR1 - CMP Control Register 1
 211  ******************************************************************************/
 212
 213 /*!
 214  * @brief HW_CMP_CR1 - CMP Control Register 1 (RW)
 215  *
 216  * Reset value: 0x00U
 217  */
 218 typedef union _hw_cmp_cr1
 219 {
 220     uint8_t U;
 221     struct _hw_cmp_cr1_bitfields
 222     {
 223         uint8_t EN : 1;                /*!< [0] Comparator Module Enable */
 224         uint8_t OPE : 1;               /*!< [1] Comparator Output Pin Enable */
 225         uint8_t COS : 1;               /*!< [2] Comparator Output Select */
 226         uint8_t INV : 1;               /*!< [3] Comparator INVERT */
 227         uint8_t PMODE : 1;             /*!< [4] Power Mode Select */
 228         uint8_t RESERVED0 : 1;         /*!< [5]  */
 229         uint8_t WE : 1;                /*!< [6] Windowing Enable */
 230         uint8_t SE : 1;                /*!< [7] Sample Enable */
 231     } B;
 232 } hw_cmp_cr1_t;
 233
 234 /*!
 235  * @name Constants and macros for entire CMP_CR1 register
 236  */
 237 /*@{*/
 238 #define HW_CMP_CR1_ADDR(x)       ((x) + 0x1U)
 239
 240 #define HW_CMP_CR1(x)            (*(__IO hw_cmp_cr1_t *) HW_CMP_CR1_ADDR(x))
 241 #define HW_CMP_CR1_RD(x)         (HW_CMP_CR1(x).U)
 242 #define HW_CMP_CR1_WR(x, v)      (HW_CMP_CR1(x).U = (v))
 243 #define HW_CMP_CR1_SET(x, v)     (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) |  (v)))
 244 #define HW_CMP_CR1_CLR(x, v)     (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) & ~(v)))
 245 #define HW_CMP_CR1_TOG(x, v)     (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) ^  (v)))
 246 /*@}*/
 247
 248 /*
 249  * Constants & macros for individual CMP_CR1 bitfields
 250  */
 251
 252 /*!
 253  * @name Register CMP_CR1, field EN[0] (RW)
 254  *
 255  * Enables the Analog Comparator module. When the module is not enabled, it
 256  * remains in the off state, and consumes no power. When the user selects the same
 257  * input from analog mux to the positive and negative port, the comparator is
 258  * disabled automatically.
 259  *
 260  * Values:
 261  * - 0 - Analog Comparator is disabled.
 262  * - 1 - Analog Comparator is enabled.
 263  */
 264 /*@{*/
 265 #define BP_CMP_CR1_EN        (0U)          /*!< Bit position for CMP_CR1_EN. */
 266 #define BM_CMP_CR1_EN        (0x01U)       /*!< Bit mask for CMP_CR1_EN. */
 267 #define BS_CMP_CR1_EN        (1U)          /*!< Bit field size in bits for CMP_CR1_EN. */
 268
 269 /*! @brief Read current value of the CMP_CR1_EN field. */
 270 #define BR_CMP_CR1_EN(x)     (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_EN))
 271
 272 /*! @brief Format value for bitfield CMP_CR1_EN. */
 273 #define BF_CMP_CR1_EN(v)     ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_EN) & BM_CMP_CR1_EN)
 274
 275 /*! @brief Set the EN field to a new value. */
 276 #define BW_CMP_CR1_EN(x, v)  (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_EN) = (v))
 277 /*@}*/
 278
 279 /*!
 280  * @name Register CMP_CR1, field OPE[1] (RW)
 281  *
 282  * Values:
 283  * - 0 - CMPO is not available on the associated CMPO output pin. If the
 284  *     comparator does not own the pin, this field has no effect.
 285  * - 1 - CMPO is available on the associated CMPO output pin. The comparator
 286  *     output (CMPO) is driven out on the associated CMPO output pin if the
 287  *     comparator owns the pin. If the comparator does not own the field, this bit has no
 288  *     effect.
 289  */
 290 /*@{*/
 291 #define BP_CMP_CR1_OPE       (1U)          /*!< Bit position for CMP_CR1_OPE. */
 292 #define BM_CMP_CR1_OPE       (0x02U)       /*!< Bit mask for CMP_CR1_OPE. */
 293 #define BS_CMP_CR1_OPE       (1U)          /*!< Bit field size in bits for CMP_CR1_OPE. */
 294
 295 /*! @brief Read current value of the CMP_CR1_OPE field. */
 296 #define BR_CMP_CR1_OPE(x)    (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_OPE))
 297
 298 /*! @brief Format value for bitfield CMP_CR1_OPE. */
 299 #define BF_CMP_CR1_OPE(v)    ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_OPE) & BM_CMP_CR1_OPE)
 300
 301 /*! @brief Set the OPE field to a new value. */
 302 #define BW_CMP_CR1_OPE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_OPE) = (v))
 303 /*@}*/
 304
 305 /*!
 306  * @name Register CMP_CR1, field COS[2] (RW)
 307  *
 308  * Values:
 309  * - 0 - Set the filtered comparator output (CMPO) to equal COUT.
 310  * - 1 - Set the unfiltered comparator output (CMPO) to equal COUTA.
 311  */
 312 /*@{*/
 313 #define BP_CMP_CR1_COS       (2U)          /*!< Bit position for CMP_CR1_COS. */
 314 #define BM_CMP_CR1_COS       (0x04U)       /*!< Bit mask for CMP_CR1_COS. */
 315 #define BS_CMP_CR1_COS       (1U)          /*!< Bit field size in bits for CMP_CR1_COS. */
 316
 317 /*! @brief Read current value of the CMP_CR1_COS field. */
 318 #define BR_CMP_CR1_COS(x)    (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_COS))
 319
 320 /*! @brief Format value for bitfield CMP_CR1_COS. */
 321 #define BF_CMP_CR1_COS(v)    ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_COS) & BM_CMP_CR1_COS)
 322
 323 /*! @brief Set the COS field to a new value. */
 324 #define BW_CMP_CR1_COS(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_COS) = (v))
 325 /*@}*/
 326
 327 /*!
 328  * @name Register CMP_CR1, field INV[3] (RW)
 329  *
 330  * Allows selection of the polarity of the analog comparator function. It is
 331  * also driven to the COUT output, on both the device pin and as SCR[COUT], when
 332  * OPE=0.
 333  *
 334  * Values:
 335  * - 0 - Does not invert the comparator output.
 336  * - 1 - Inverts the comparator output.
 337  */
 338 /*@{*/
 339 #define BP_CMP_CR1_INV       (3U)          /*!< Bit position for CMP_CR1_INV. */
 340 #define BM_CMP_CR1_INV       (0x08U)       /*!< Bit mask for CMP_CR1_INV. */
 341 #define BS_CMP_CR1_INV       (1U)          /*!< Bit field size in bits for CMP_CR1_INV. */
 342
 343 /*! @brief Read current value of the CMP_CR1_INV field. */
 344 #define BR_CMP_CR1_INV(x)    (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_INV))
 345
 346 /*! @brief Format value for bitfield CMP_CR1_INV. */
 347 #define BF_CMP_CR1_INV(v)    ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_INV) & BM_CMP_CR1_INV)
 348
 349 /*! @brief Set the INV field to a new value. */
 350 #define BW_CMP_CR1_INV(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_INV) = (v))
 351 /*@}*/
 352
 353 /*!
 354  * @name Register CMP_CR1, field PMODE[4] (RW)
 355  *
 356  * See the electrical specifications table in the device Data Sheet for details.
 357  *
 358  * Values:
 359  * - 0 - Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower
 360  *     output propagation delay and lower current consumption.
 361  * - 1 - High-Speed (HS) Comparison mode selected. In this mode, CMP has faster
 362  *     output propagation delay and higher current consumption.
 363  */
 364 /*@{*/
 365 #define BP_CMP_CR1_PMODE     (4U)          /*!< Bit position for CMP_CR1_PMODE. */
 366 #define BM_CMP_CR1_PMODE     (0x10U)       /*!< Bit mask for CMP_CR1_PMODE. */
 367 #define BS_CMP_CR1_PMODE     (1U)          /*!< Bit field size in bits for CMP_CR1_PMODE. */
 368
 369 /*! @brief Read current value of the CMP_CR1_PMODE field. */
 370 #define BR_CMP_CR1_PMODE(x)  (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_PMODE))
 371
 372 /*! @brief Format value for bitfield CMP_CR1_PMODE. */
 373 #define BF_CMP_CR1_PMODE(v)  ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_PMODE) & BM_CMP_CR1_PMODE)
 374
 375 /*! @brief Set the PMODE field to a new value. */
 376 #define BW_CMP_CR1_PMODE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_PMODE) = (v))
 377 /*@}*/
 378
 379 /*!
 380  * @name Register CMP_CR1, field WE[6] (RW)
 381  *
 382  * At any given time, either SE or WE can be set. If a write to this register
 383  * attempts to set both, then SE is set and WE is cleared. However, avoid writing
 384  * 1s to both field locations because this "11" case is reserved and may change in
 385  * future implementations.
 386  *
 387  * Values:
 388  * - 0 - Windowing mode is not selected.
 389  * - 1 - Windowing mode is selected.
 390  */
 391 /*@{*/
 392 #define BP_CMP_CR1_WE        (6U)          /*!< Bit position for CMP_CR1_WE. */
 393 #define BM_CMP_CR1_WE        (0x40U)       /*!< Bit mask for CMP_CR1_WE. */
 394 #define BS_CMP_CR1_WE        (1U)          /*!< Bit field size in bits for CMP_CR1_WE. */
 395
 396 /*! @brief Read current value of the CMP_CR1_WE field. */
 397 #define BR_CMP_CR1_WE(x)     (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_WE))
 398
 399 /*! @brief Format value for bitfield CMP_CR1_WE. */
 400 #define BF_CMP_CR1_WE(v)     ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_WE) & BM_CMP_CR1_WE)
 401
 402 /*! @brief Set the WE field to a new value. */
 403 #define BW_CMP_CR1_WE(x, v)  (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_WE) = (v))
 404 /*@}*/
 405
 406 /*!
 407  * @name Register CMP_CR1, field SE[7] (RW)
 408  *
 409  * At any given time, either SE or WE can be set. If a write to this register
 410  * attempts to set both, then SE is set and WE is cleared. However, avoid writing
 411  * 1s to both field locations because this "11" case is reserved and may change in
 412  * future implementations.
 413  *
 414  * Values:
 415  * - 0 - Sampling mode is not selected.
 416  * - 1 - Sampling mode is selected.
 417  */
 418 /*@{*/
 419 #define BP_CMP_CR1_SE        (7U)          /*!< Bit position for CMP_CR1_SE. */
 420 #define BM_CMP_CR1_SE        (0x80U)       /*!< Bit mask for CMP_CR1_SE. */
 421 #define BS_CMP_CR1_SE        (1U)          /*!< Bit field size in bits for CMP_CR1_SE. */
 422
 423 /*! @brief Read current value of the CMP_CR1_SE field. */
 424 #define BR_CMP_CR1_SE(x)     (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_SE))
 425
 426 /*! @brief Format value for bitfield CMP_CR1_SE. */
 427 #define BF_CMP_CR1_SE(v)     ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_SE) & BM_CMP_CR1_SE)
 428
 429 /*! @brief Set the SE field to a new value. */
 430 #define BW_CMP_CR1_SE(x, v)  (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_SE) = (v))
 431 /*@}*/
 432
 433 /*******************************************************************************
 434  * HW_CMP_FPR - CMP Filter Period Register
 435  ******************************************************************************/
 436
 437 /*!
 438  * @brief HW_CMP_FPR - CMP Filter Period Register (RW)
 439  *
 440  * Reset value: 0x00U
 441  */
 442 typedef union _hw_cmp_fpr
 443 {
 444     uint8_t U;
 445     struct _hw_cmp_fpr_bitfields
 446     {
 447         uint8_t FILT_PER : 8;          /*!< [7:0] Filter Sample Period */
 448     } B;
 449 } hw_cmp_fpr_t;
 450
 451 /*!
 452  * @name Constants and macros for entire CMP_FPR register
 453  */
 454 /*@{*/
 455 #define HW_CMP_FPR_ADDR(x)       ((x) + 0x2U)
 456
 457 #define HW_CMP_FPR(x)            (*(__IO hw_cmp_fpr_t *) HW_CMP_FPR_ADDR(x))
 458 #define HW_CMP_FPR_RD(x)         (HW_CMP_FPR(x).U)
 459 #define HW_CMP_FPR_WR(x, v)      (HW_CMP_FPR(x).U = (v))
 460 #define HW_CMP_FPR_SET(x, v)     (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) |  (v)))
 461 #define HW_CMP_FPR_CLR(x, v)     (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) & ~(v)))
 462 #define HW_CMP_FPR_TOG(x, v)     (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) ^  (v)))
 463 /*@}*/
 464
 465 /*
 466  * Constants & macros for individual CMP_FPR bitfields
 467  */
 468
 469 /*!
 470  * @name Register CMP_FPR, field FILT_PER[7:0] (RW)
 471  *
 472  * Specifies the sampling period, in bus clock cycles, of the comparator output
 473  * filter, when CR1[SE]=0. Setting FILT_PER to 0x0 disables the filter. Filter
 474  * programming and latency details appear in the Functional descriptionThe CMP
 475  * module can be used to compare two analog input voltages applied to INP and INM. .
 476  * This field has no effect when CR1[SE]=1. In that case, the external SAMPLE
 477  * signal is used to determine the sampling period.
 478  */
 479 /*@{*/
 480 #define BP_CMP_FPR_FILT_PER  (0U)          /*!< Bit position for CMP_FPR_FILT_PER. */
 481 #define BM_CMP_FPR_FILT_PER  (0xFFU)       /*!< Bit mask for CMP_FPR_FILT_PER. */
 482 #define BS_CMP_FPR_FILT_PER  (8U)          /*!< Bit field size in bits for CMP_FPR_FILT_PER. */
 483
 484 /*! @brief Read current value of the CMP_FPR_FILT_PER field. */
 485 #define BR_CMP_FPR_FILT_PER(x) (HW_CMP_FPR(x).U)
 486
 487 /*! @brief Format value for bitfield CMP_FPR_FILT_PER. */
 488 #define BF_CMP_FPR_FILT_PER(v) ((uint8_t)((uint8_t)(v) << BP_CMP_FPR_FILT_PER) & BM_CMP_FPR_FILT_PER)
 489
 490 /*! @brief Set the FILT_PER field to a new value. */
 491 #define BW_CMP_FPR_FILT_PER(x, v) (HW_CMP_FPR_WR(x, v))
 492 /*@}*/
 493
 494 /*******************************************************************************
 495  * HW_CMP_SCR - CMP Status and Control Register
 496  ******************************************************************************/
 497
 498 /*!
 499  * @brief HW_CMP_SCR - CMP Status and Control Register (RW)
 500  *
 501  * Reset value: 0x00U
 502  */
 503 typedef union _hw_cmp_scr
 504 {
 505     uint8_t U;
 506     struct _hw_cmp_scr_bitfields
 507     {
 508         uint8_t COUT : 1;              /*!< [0] Analog Comparator Output */
 509         uint8_t CFF : 1;               /*!< [1] Analog Comparator Flag Falling */
 510         uint8_t CFR : 1;               /*!< [2] Analog Comparator Flag Rising */
 511         uint8_t IEF : 1;               /*!< [3] Comparator Interrupt Enable Falling */
 512         uint8_t IER : 1;               /*!< [4] Comparator Interrupt Enable Rising */
 513         uint8_t RESERVED0 : 1;         /*!< [5]  */
 514         uint8_t DMAEN : 1;             /*!< [6] DMA Enable Control */
 515         uint8_t RESERVED1 : 1;         /*!< [7]  */
 516     } B;
 517 } hw_cmp_scr_t;
 518
 519 /*!
 520  * @name Constants and macros for entire CMP_SCR register
 521  */
 522 /*@{*/
 523 #define HW_CMP_SCR_ADDR(x)       ((x) + 0x3U)
 524
 525 #define HW_CMP_SCR(x)            (*(__IO hw_cmp_scr_t *) HW_CMP_SCR_ADDR(x))
 526 #define HW_CMP_SCR_RD(x)         (HW_CMP_SCR(x).U)
 527 #define HW_CMP_SCR_WR(x, v)      (HW_CMP_SCR(x).U = (v))
 528 #define HW_CMP_SCR_SET(x, v)     (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) |  (v)))
 529 #define HW_CMP_SCR_CLR(x, v)     (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) & ~(v)))
 530 #define HW_CMP_SCR_TOG(x, v)     (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) ^  (v)))
 531 /*@}*/
 532
 533 /*
 534  * Constants & macros for individual CMP_SCR bitfields
 535  */
 536
 537 /*!
 538  * @name Register CMP_SCR, field COUT[0] (RO)
 539  *
 540  * Returns the current value of the Analog Comparator output, when read. The
 541  * field is reset to 0 and will read as CR1[INV] when the Analog Comparator module
 542  * is disabled, that is, when CR1[EN] = 0. Writes to this field are ignored.
 543  */
 544 /*@{*/
 545 #define BP_CMP_SCR_COUT      (0U)          /*!< Bit position for CMP_SCR_COUT. */
 546 #define BM_CMP_SCR_COUT      (0x01U)       /*!< Bit mask for CMP_SCR_COUT. */
 547 #define BS_CMP_SCR_COUT      (1U)          /*!< Bit field size in bits for CMP_SCR_COUT. */
 548
 549 /*! @brief Read current value of the CMP_SCR_COUT field. */
 550 #define BR_CMP_SCR_COUT(x)   (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_COUT))
 551 /*@}*/
 552
 553 /*!
 554  * @name Register CMP_SCR, field CFF[1] (W1C)
 555  *
 556  * Detects a falling-edge on COUT, when set, during normal operation. CFF is
 557  * cleared by writing 1 to it. During Stop modes, CFF is level sensitive is edge
 558  * sensitive .
 559  *
 560  * Values:
 561  * - 0 - Falling-edge on COUT has not been detected.
 562  * - 1 - Falling-edge on COUT has occurred.
 563  */
 564 /*@{*/
 565 #define BP_CMP_SCR_CFF       (1U)          /*!< Bit position for CMP_SCR_CFF. */
 566 #define BM_CMP_SCR_CFF       (0x02U)       /*!< Bit mask for CMP_SCR_CFF. */
 567 #define BS_CMP_SCR_CFF       (1U)          /*!< Bit field size in bits for CMP_SCR_CFF. */
 568
 569 /*! @brief Read current value of the CMP_SCR_CFF field. */
 570 #define BR_CMP_SCR_CFF(x)    (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFF))
 571
 572 /*! @brief Format value for bitfield CMP_SCR_CFF. */
 573 #define BF_CMP_SCR_CFF(v)    ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_CFF) & BM_CMP_SCR_CFF)
 574
 575 /*! @brief Set the CFF field to a new value. */
 576 #define BW_CMP_SCR_CFF(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFF) = (v))
 577 /*@}*/
 578
 579 /*!
 580  * @name Register CMP_SCR, field CFR[2] (W1C)
 581  *
 582  * Detects a rising-edge on COUT, when set, during normal operation. CFR is
 583  * cleared by writing 1 to it. During Stop modes, CFR is level sensitive is edge
 584  * sensitive .
 585  *
 586  * Values:
 587  * - 0 - Rising-edge on COUT has not been detected.
 588  * - 1 - Rising-edge on COUT has occurred.
 589  */
 590 /*@{*/
 591 #define BP_CMP_SCR_CFR       (2U)          /*!< Bit position for CMP_SCR_CFR. */
 592 #define BM_CMP_SCR_CFR       (0x04U)       /*!< Bit mask for CMP_SCR_CFR. */
 593 #define BS_CMP_SCR_CFR       (1U)          /*!< Bit field size in bits for CMP_SCR_CFR. */
 594
 595 /*! @brief Read current value of the CMP_SCR_CFR field. */
 596 #define BR_CMP_SCR_CFR(x)    (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFR))
 597
 598 /*! @brief Format value for bitfield CMP_SCR_CFR. */
 599 #define BF_CMP_SCR_CFR(v)    ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_CFR) & BM_CMP_SCR_CFR)
 600
 601 /*! @brief Set the CFR field to a new value. */
 602 #define BW_CMP_SCR_CFR(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFR) = (v))
 603 /*@}*/
 604
 605 /*!
 606  * @name Register CMP_SCR, field IEF[3] (RW)
 607  *
 608  * Enables the CFF interrupt from the CMP. When this field is set, an interrupt
 609  * will be asserted when CFF is set.
 610  *
 611  * Values:
 612  * - 0 - Interrupt is disabled.
 613  * - 1 - Interrupt is enabled.
 614  */
 615 /*@{*/
 616 #define BP_CMP_SCR_IEF       (3U)          /*!< Bit position for CMP_SCR_IEF. */
 617 #define BM_CMP_SCR_IEF       (0x08U)       /*!< Bit mask for CMP_SCR_IEF. */
 618 #define BS_CMP_SCR_IEF       (1U)          /*!< Bit field size in bits for CMP_SCR_IEF. */
 619
 620 /*! @brief Read current value of the CMP_SCR_IEF field. */
 621 #define BR_CMP_SCR_IEF(x)    (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IEF))
 622
 623 /*! @brief Format value for bitfield CMP_SCR_IEF. */
 624 #define BF_CMP_SCR_IEF(v)    ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_IEF) & BM_CMP_SCR_IEF)
 625
 626 /*! @brief Set the IEF field to a new value. */
 627 #define BW_CMP_SCR_IEF(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IEF) = (v))
 628 /*@}*/
 629
 630 /*!
 631  * @name Register CMP_SCR, field IER[4] (RW)
 632  *
 633  * Enables the CFR interrupt from the CMP. When this field is set, an interrupt
 634  * will be asserted when CFR is set.
 635  *
 636  * Values:
 637  * - 0 - Interrupt is disabled.
 638  * - 1 - Interrupt is enabled.
 639  */
 640 /*@{*/
 641 #define BP_CMP_SCR_IER       (4U)          /*!< Bit position for CMP_SCR_IER. */
 642 #define BM_CMP_SCR_IER       (0x10U)       /*!< Bit mask for CMP_SCR_IER. */
 643 #define BS_CMP_SCR_IER       (1U)          /*!< Bit field size in bits for CMP_SCR_IER. */
 644
 645 /*! @brief Read current value of the CMP_SCR_IER field. */
 646 #define BR_CMP_SCR_IER(x)    (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IER))
 647
 648 /*! @brief Format value for bitfield CMP_SCR_IER. */
 649 #define BF_CMP_SCR_IER(v)    ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_IER) & BM_CMP_SCR_IER)
 650
 651 /*! @brief Set the IER field to a new value. */
 652 #define BW_CMP_SCR_IER(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IER) = (v))
 653 /*@}*/
 654
 655 /*!
 656  * @name Register CMP_SCR, field DMAEN[6] (RW)
 657  *
 658  * Enables the DMA transfer triggered from the CMP module. When this field is
 659  * set, a DMA request is asserted when CFR or CFF is set.
 660  *
 661  * Values:
 662  * - 0 - DMA is disabled.
 663  * - 1 - DMA is enabled.
 664  */
 665 /*@{*/
 666 #define BP_CMP_SCR_DMAEN     (6U)          /*!< Bit position for CMP_SCR_DMAEN. */
 667 #define BM_CMP_SCR_DMAEN     (0x40U)       /*!< Bit mask for CMP_SCR_DMAEN. */
 668 #define BS_CMP_SCR_DMAEN     (1U)          /*!< Bit field size in bits for CMP_SCR_DMAEN. */
 669
 670 /*! @brief Read current value of the CMP_SCR_DMAEN field. */
 671 #define BR_CMP_SCR_DMAEN(x)  (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_DMAEN))
 672
 673 /*! @brief Format value for bitfield CMP_SCR_DMAEN. */
 674 #define BF_CMP_SCR_DMAEN(v)  ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_DMAEN) & BM_CMP_SCR_DMAEN)
 675
 676 /*! @brief Set the DMAEN field to a new value. */
 677 #define BW_CMP_SCR_DMAEN(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_DMAEN) = (v))
 678 /*@}*/
 679
 680 /*******************************************************************************
 681  * HW_CMP_DACCR - DAC Control Register
 682  ******************************************************************************/
 683
 684 /*!
 685  * @brief HW_CMP_DACCR - DAC Control Register (RW)
 686  *
 687  * Reset value: 0x00U
 688  */
 689 typedef union _hw_cmp_daccr
 690 {
 691     uint8_t U;
 692     struct _hw_cmp_daccr_bitfields
 693     {
 694         uint8_t VOSEL : 6;             /*!< [5:0] DAC Output Voltage Select */
 695         uint8_t VRSEL : 1;             /*!< [6] Supply Voltage Reference Source Select */
 696         uint8_t DACEN : 1;             /*!< [7] DAC Enable */
 697     } B;
 698 } hw_cmp_daccr_t;
 699
 700 /*!
 701  * @name Constants and macros for entire CMP_DACCR register
 702  */
 703 /*@{*/
 704 #define HW_CMP_DACCR_ADDR(x)     ((x) + 0x4U)
 705
 706 #define HW_CMP_DACCR(x)          (*(__IO hw_cmp_daccr_t *) HW_CMP_DACCR_ADDR(x))
 707 #define HW_CMP_DACCR_RD(x)       (HW_CMP_DACCR(x).U)
 708 #define HW_CMP_DACCR_WR(x, v)    (HW_CMP_DACCR(x).U = (v))
 709 #define HW_CMP_DACCR_SET(x, v)   (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) |  (v)))
 710 #define HW_CMP_DACCR_CLR(x, v)   (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) & ~(v)))
 711 #define HW_CMP_DACCR_TOG(x, v)   (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) ^  (v)))
 712 /*@}*/
 713
 714 /*
 715  * Constants & macros for individual CMP_DACCR bitfields
 716  */
 717
 718 /*!
 719  * @name Register CMP_DACCR, field VOSEL[5:0] (RW)
 720  *
 721  * Selects an output voltage from one of 64 distinct levels. DACO = (V in /64) *
 722  * (VOSEL[5:0] + 1) , so the DACO range is from V in /64 to V in .
 723  */
 724 /*@{*/
 725 #define BP_CMP_DACCR_VOSEL   (0U)          /*!< Bit position for CMP_DACCR_VOSEL. */
 726 #define BM_CMP_DACCR_VOSEL   (0x3FU)       /*!< Bit mask for CMP_DACCR_VOSEL. */
 727 #define BS_CMP_DACCR_VOSEL   (6U)          /*!< Bit field size in bits for CMP_DACCR_VOSEL. */
 728
 729 /*! @brief Read current value of the CMP_DACCR_VOSEL field. */
 730 #define BR_CMP_DACCR_VOSEL(x) (HW_CMP_DACCR(x).B.VOSEL)
 731
 732 /*! @brief Format value for bitfield CMP_DACCR_VOSEL. */
 733 #define BF_CMP_DACCR_VOSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_DACCR_VOSEL) & BM_CMP_DACCR_VOSEL)
 734
 735 /*! @brief Set the VOSEL field to a new value. */
 736 #define BW_CMP_DACCR_VOSEL(x, v) (HW_CMP_DACCR_WR(x, (HW_CMP_DACCR_RD(x) & ~BM_CMP_DACCR_VOSEL) | BF_CMP_DACCR_VOSEL(v)))
 737 /*@}*/
 738
 739 /*!
 740  * @name Register CMP_DACCR, field VRSEL[6] (RW)
 741  *
 742  * Values:
 743  * - 0 - V is selected as resistor ladder network supply reference V. in1 in
 744  * - 1 - V is selected as resistor ladder network supply reference V. in2 in
 745  */
 746 /*@{*/
 747 #define BP_CMP_DACCR_VRSEL   (6U)          /*!< Bit position for CMP_DACCR_VRSEL. */
 748 #define BM_CMP_DACCR_VRSEL   (0x40U)       /*!< Bit mask for CMP_DACCR_VRSEL. */
 749 #define BS_CMP_DACCR_VRSEL   (1U)          /*!< Bit field size in bits for CMP_DACCR_VRSEL. */
 750
 751 /*! @brief Read current value of the CMP_DACCR_VRSEL field. */
 752 #define BR_CMP_DACCR_VRSEL(x) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_VRSEL))
 753
 754 /*! @brief Format value for bitfield CMP_DACCR_VRSEL. */
 755 #define BF_CMP_DACCR_VRSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_DACCR_VRSEL) & BM_CMP_DACCR_VRSEL)
 756
 757 /*! @brief Set the VRSEL field to a new value. */
 758 #define BW_CMP_DACCR_VRSEL(x, v) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_VRSEL) = (v))
 759 /*@}*/
 760
 761 /*!
 762  * @name Register CMP_DACCR, field DACEN[7] (RW)
 763  *
 764  * Enables the DAC. When the DAC is disabled, it is powered down to conserve
 765  * power.
 766  *
 767  * Values:
 768  * - 0 - DAC is disabled.
 769  * - 1 - DAC is enabled.
 770  */
 771 /*@{*/
 772 #define BP_CMP_DACCR_DACEN   (7U)          /*!< Bit position for CMP_DACCR_DACEN. */
 773 #define BM_CMP_DACCR_DACEN   (0x80U)       /*!< Bit mask for CMP_DACCR_DACEN. */
 774 #define BS_CMP_DACCR_DACEN   (1U)          /*!< Bit field size in bits for CMP_DACCR_DACEN. */
 775
 776 /*! @brief Read current value of the CMP_DACCR_DACEN field. */
 777 #define BR_CMP_DACCR_DACEN(x) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_DACEN))
 778
 779 /*! @brief Format value for bitfield CMP_DACCR_DACEN. */
 780 #define BF_CMP_DACCR_DACEN(v) ((uint8_t)((uint8_t)(v) << BP_CMP_DACCR_DACEN) & BM_CMP_DACCR_DACEN)
 781
 782 /*! @brief Set the DACEN field to a new value. */
 783 #define BW_CMP_DACCR_DACEN(x, v) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_DACEN) = (v))
 784 /*@}*/
 785
 786 /*******************************************************************************
 787  * HW_CMP_MUXCR - MUX Control Register
 788  ******************************************************************************/
 789
 790 /*!
 791  * @brief HW_CMP_MUXCR - MUX Control Register (RW)
 792  *
 793  * Reset value: 0x00U
 794  */
 795 typedef union _hw_cmp_muxcr
 796 {
 797     uint8_t U;
 798     struct _hw_cmp_muxcr_bitfields
 799     {
 800         uint8_t MSEL : 3;              /*!< [2:0] Minus Input Mux Control */
 801         uint8_t PSEL : 3;              /*!< [5:3] Plus Input Mux Control */
 802         uint8_t RESERVED0 : 1;         /*!< [6]  */
 803         uint8_t PSTM : 1;              /*!< [7] Pass Through Mode Enable */
 804     } B;
 805 } hw_cmp_muxcr_t;
 806
 807 /*!
 808  * @name Constants and macros for entire CMP_MUXCR register
 809  */
 810 /*@{*/
 811 #define HW_CMP_MUXCR_ADDR(x)     ((x) + 0x5U)
 812
 813 #define HW_CMP_MUXCR(x)          (*(__IO hw_cmp_muxcr_t *) HW_CMP_MUXCR_ADDR(x))
 814 #define HW_CMP_MUXCR_RD(x)       (HW_CMP_MUXCR(x).U)
 815 #define HW_CMP_MUXCR_WR(x, v)    (HW_CMP_MUXCR(x).U = (v))
 816 #define HW_CMP_MUXCR_SET(x, v)   (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) |  (v)))
 817 #define HW_CMP_MUXCR_CLR(x, v)   (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) & ~(v)))
 818 #define HW_CMP_MUXCR_TOG(x, v)   (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) ^  (v)))
 819 /*@}*/
 820
 821 /*
 822  * Constants & macros for individual CMP_MUXCR bitfields
 823  */
 824
 825 /*!
 826  * @name Register CMP_MUXCR, field MSEL[2:0] (RW)
 827  *
 828  * Determines which input is selected for the minus input of the comparator. For
 829  * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
 830  * operation selects the same input for both muxes, the comparator automatically
 831  * shuts down to prevent itself from becoming a noise generator.
 832  *
 833  * Values:
 834  * - 000 - IN0
 835  * - 001 - IN1
 836  * - 010 - IN2
 837  * - 011 - IN3
 838  * - 100 - IN4
 839  * - 101 - IN5
 840  * - 110 - IN6
 841  * - 111 - IN7
 842  */
 843 /*@{*/
 844 #define BP_CMP_MUXCR_MSEL    (0U)          /*!< Bit position for CMP_MUXCR_MSEL. */
 845 #define BM_CMP_MUXCR_MSEL    (0x07U)       /*!< Bit mask for CMP_MUXCR_MSEL. */
 846 #define BS_CMP_MUXCR_MSEL    (3U)          /*!< Bit field size in bits for CMP_MUXCR_MSEL. */
 847
 848 /*! @brief Read current value of the CMP_MUXCR_MSEL field. */
 849 #define BR_CMP_MUXCR_MSEL(x) (HW_CMP_MUXCR(x).B.MSEL)
 850
 851 /*! @brief Format value for bitfield CMP_MUXCR_MSEL. */
 852 #define BF_CMP_MUXCR_MSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_MUXCR_MSEL) & BM_CMP_MUXCR_MSEL)
 853
 854 /*! @brief Set the MSEL field to a new value. */
 855 #define BW_CMP_MUXCR_MSEL(x, v) (HW_CMP_MUXCR_WR(x, (HW_CMP_MUXCR_RD(x) & ~BM_CMP_MUXCR_MSEL) | BF_CMP_MUXCR_MSEL(v)))
 856 /*@}*/
 857
 858 /*!
 859  * @name Register CMP_MUXCR, field PSEL[5:3] (RW)
 860  *
 861  * Determines which input is selected for the plus input of the comparator. For
 862  * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
 863  * operation selects the same input for both muxes, the comparator automatically
 864  * shuts down to prevent itself from becoming a noise generator.
 865  *
 866  * Values:
 867  * - 000 - IN0
 868  * - 001 - IN1
 869  * - 010 - IN2
 870  * - 011 - IN3
 871  * - 100 - IN4
 872  * - 101 - IN5
 873  * - 110 - IN6
 874  * - 111 - IN7
 875  */
 876 /*@{*/
 877 #define BP_CMP_MUXCR_PSEL    (3U)          /*!< Bit position for CMP_MUXCR_PSEL. */
 878 #define BM_CMP_MUXCR_PSEL    (0x38U)       /*!< Bit mask for CMP_MUXCR_PSEL. */
 879 #define BS_CMP_MUXCR_PSEL    (3U)          /*!< Bit field size in bits for CMP_MUXCR_PSEL. */
 880
 881 /*! @brief Read current value of the CMP_MUXCR_PSEL field. */
 882 #define BR_CMP_MUXCR_PSEL(x) (HW_CMP_MUXCR(x).B.PSEL)
 883
 884 /*! @brief Format value for bitfield CMP_MUXCR_PSEL. */
 885 #define BF_CMP_MUXCR_PSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_MUXCR_PSEL) & BM_CMP_MUXCR_PSEL)
 886
 887 /*! @brief Set the PSEL field to a new value. */
 888 #define BW_CMP_MUXCR_PSEL(x, v) (HW_CMP_MUXCR_WR(x, (HW_CMP_MUXCR_RD(x) & ~BM_CMP_MUXCR_PSEL) | BF_CMP_MUXCR_PSEL(v)))
 889 /*@}*/
 890
 891 /*!
 892  * @name Register CMP_MUXCR, field PSTM[7] (RW)
 893  *
 894  * This bit is used to enable to MUX pass through mode. Pass through mode is
 895  * always available but for some devices this feature must be always disabled due to
 896  * the lack of package pins.
 897  *
 898  * Values:
 899  * - 0 - Pass Through Mode is disabled.
 900  * - 1 - Pass Through Mode is enabled.
 901  */
 902 /*@{*/
 903 #define BP_CMP_MUXCR_PSTM    (7U)          /*!< Bit position for CMP_MUXCR_PSTM. */
 904 #define BM_CMP_MUXCR_PSTM    (0x80U)       /*!< Bit mask for CMP_MUXCR_PSTM. */
 905 #define BS_CMP_MUXCR_PSTM    (1U)          /*!< Bit field size in bits for CMP_MUXCR_PSTM. */
 906
 907 /*! @brief Read current value of the CMP_MUXCR_PSTM field. */
 908 #define BR_CMP_MUXCR_PSTM(x) (BITBAND_ACCESS8(HW_CMP_MUXCR_ADDR(x), BP_CMP_MUXCR_PSTM))
 909
 910 /*! @brief Format value for bitfield CMP_MUXCR_PSTM. */
 911 #define BF_CMP_MUXCR_PSTM(v) ((uint8_t)((uint8_t)(v) << BP_CMP_MUXCR_PSTM) & BM_CMP_MUXCR_PSTM)
 912
 913 /*! @brief Set the PSTM field to a new value. */
 914 #define BW_CMP_MUXCR_PSTM(x, v) (BITBAND_ACCESS8(HW_CMP_MUXCR_ADDR(x), BP_CMP_MUXCR_PSTM) = (v))
 915 /*@}*/
 916
 917 /*******************************************************************************
 918  * hw_cmp_t - module struct
 919  ******************************************************************************/
 920 /*!
 921  * @brief All CMP module registers.
 922  */
 923 #pragma pack(1)
 924 typedef struct _hw_cmp
 925 {
 926     __IO hw_cmp_cr0_t CR0;                 /*!< [0x0] CMP Control Register 0 */
 927     __IO hw_cmp_cr1_t CR1;                 /*!< [0x1] CMP Control Register 1 */
 928     __IO hw_cmp_fpr_t FPR;                 /*!< [0x2] CMP Filter Period Register */
 929     __IO hw_cmp_scr_t SCR;                 /*!< [0x3] CMP Status and Control Register */
 930     __IO hw_cmp_daccr_t DACCR;             /*!< [0x4] DAC Control Register */
 931     __IO hw_cmp_muxcr_t MUXCR;             /*!< [0x5] MUX Control Register */
 932 } hw_cmp_t;
 933 #pragma pack()
 934
 935 /*! @brief Macro to access all CMP registers. */
 936 /*! @param x CMP module instance base address. */
 937 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
 938  *     use the '&' operator, like <code>&HW_CMP(CMP0_BASE)</code>. */
 939 #define HW_CMP(x)      (*(hw_cmp_t *)(x))
 940
 941 #endif /* __HW_CMP_REGISTERS_H__ */
 942 /* EOF */