tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_crc.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
   9 **     Version:             rev. 2.5, 2014-02-10
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-08-12)
  48 **         Initial version.
  49 **     - rev. 2.0 (2013-10-29)
  50 **         Register accessor macros added to the memory map.
  51 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  52 **         Startup file for gcc has been updated according to CMSIS 3.2.
  53 **         System initialization updated.
  54 **         MCG - registers updated.
  55 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-09)
  59 **         DMA - EARS register removed.
  60 **         AIPS0, AIPS1 - MPRA register updated.
  61 **     - rev. 2.3 (2014-01-24)
  62 **         Update according to reference manual rev. 2
  63 **         ENET, MCG, MCM, SIM, USB - registers updated
  64 **     - rev. 2.4 (2014-02-10)
  65 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  66 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  67 **     - rev. 2.5 (2014-02-10)
  68 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  69 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  70 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  71 **
  72 ** ###################################################################
  73 */
  74
  75 /*
  76  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  77  *
  78  * This file was generated automatically and any changes may be lost.
  79  */
  80 #ifndef __HW_CRC_REGISTERS_H__
  81 #define __HW_CRC_REGISTERS_H__
  82
  83 #include "MK64F12.h"
  84 #include "fsl_bitaccess.h"
  85
  86 /*
  87  * MK64F12 CRC
  88  *
  89  * Cyclic Redundancy Check
  90  *
  91  * Registers defined in this header file:
  92  * - HW_CRC_DATAL - CRC_DATAL register.
  93  * - HW_CRC_DATAH - CRC_DATAH register.
  94  * - HW_CRC_DATALL - CRC_DATALL register.
  95  * - HW_CRC_DATALU - CRC_DATALU register.
  96  * - HW_CRC_DATAHL - CRC_DATAHL register.
  97  * - HW_CRC_DATAHU - CRC_DATAHU register.
  98  * - HW_CRC_DATA - CRC Data register
  99  * - HW_CRC_GPOLY - CRC Polynomial register
 100  * - HW_CRC_GPOLYL - CRC_GPOLYL register.
 101  * - HW_CRC_GPOLYH - CRC_GPOLYH register.
 102  * - HW_CRC_GPOLYLL - CRC_GPOLYLL register.
 103  * - HW_CRC_GPOLYLU - CRC_GPOLYLU register.
 104  * - HW_CRC_GPOLYHL - CRC_GPOLYHL register.
 105  * - HW_CRC_GPOLYHU - CRC_GPOLYHU register.
 106  * - HW_CRC_CTRL - CRC Control register
 107  * - HW_CRC_CTRLHU - CRC_CTRLHU register.
 108  *
 109  * - hw_crc_t - Struct containing all module registers.
 110  */
 111
 112 #define HW_CRC_INSTANCE_COUNT (1U) /*!< Number of instances of the CRC module. */
 113
 114 /*******************************************************************************
 115  * HW_CRC_DATAL - CRC_DATAL register.
 116  ******************************************************************************/
 117
 118 /*!
 119  * @brief HW_CRC_DATAL - CRC_DATAL register. (RW)
 120  *
 121  * Reset value: 0xFFFFU
 122  */
 123 typedef union _hw_crc_datal
 124 {
 125     uint16_t U;
 126     struct _hw_crc_datal_bitfields
 127     {
 128         uint16_t DATAL : 16;           /*!< [15:0] DATAL stores the lower 16 bits of
 129                                         * the 16/32 bit CRC */
 130     } B;
 131 } hw_crc_datal_t;
 132
 133 /*!
 134  * @name Constants and macros for entire CRC_DATAL register
 135  */
 136 /*@{*/
 137 #define HW_CRC_DATAL_ADDR(x)     ((x) + 0x0U)
 138
 139 #define HW_CRC_DATAL(x)          (*(__IO hw_crc_datal_t *) HW_CRC_DATAL_ADDR(x))
 140 #define HW_CRC_DATAL_RD(x)       (HW_CRC_DATAL(x).U)
 141 #define HW_CRC_DATAL_WR(x, v)    (HW_CRC_DATAL(x).U = (v))
 142 #define HW_CRC_DATAL_SET(x, v)   (HW_CRC_DATAL_WR(x, HW_CRC_DATAL_RD(x) |  (v)))
 143 #define HW_CRC_DATAL_CLR(x, v)   (HW_CRC_DATAL_WR(x, HW_CRC_DATAL_RD(x) & ~(v)))
 144 #define HW_CRC_DATAL_TOG(x, v)   (HW_CRC_DATAL_WR(x, HW_CRC_DATAL_RD(x) ^  (v)))
 145 /*@}*/
 146
 147 /*
 148  * Constants & macros for individual CRC_DATAL bitfields
 149  */
 150
 151 /*!
 152  * @name Register CRC_DATAL, field DATAL[15:0] (RW)
 153  */
 154 /*@{*/
 155 #define BP_CRC_DATAL_DATAL   (0U)          /*!< Bit position for CRC_DATAL_DATAL. */
 156 #define BM_CRC_DATAL_DATAL   (0xFFFFU)     /*!< Bit mask for CRC_DATAL_DATAL. */
 157 #define BS_CRC_DATAL_DATAL   (16U)         /*!< Bit field size in bits for CRC_DATAL_DATAL. */
 158
 159 /*! @brief Read current value of the CRC_DATAL_DATAL field. */
 160 #define BR_CRC_DATAL_DATAL(x) (HW_CRC_DATAL(x).U)
 161
 162 /*! @brief Format value for bitfield CRC_DATAL_DATAL. */
 163 #define BF_CRC_DATAL_DATAL(v) ((uint16_t)((uint16_t)(v) << BP_CRC_DATAL_DATAL) & BM_CRC_DATAL_DATAL)
 164
 165 /*! @brief Set the DATAL field to a new value. */
 166 #define BW_CRC_DATAL_DATAL(x, v) (HW_CRC_DATAL_WR(x, v))
 167 /*@}*/
 168 /*******************************************************************************
 169  * HW_CRC_DATAH - CRC_DATAH register.
 170  ******************************************************************************/
 171
 172 /*!
 173  * @brief HW_CRC_DATAH - CRC_DATAH register. (RW)
 174  *
 175  * Reset value: 0xFFFFU
 176  */
 177 typedef union _hw_crc_datah
 178 {
 179     uint16_t U;
 180     struct _hw_crc_datah_bitfields
 181     {
 182         uint16_t DATAH : 16;           /*!< [15:0] DATAH stores the high 16 bits of the
 183                                         * 16/32 bit CRC */
 184     } B;
 185 } hw_crc_datah_t;
 186
 187 /*!
 188  * @name Constants and macros for entire CRC_DATAH register
 189  */
 190 /*@{*/
 191 #define HW_CRC_DATAH_ADDR(x)     ((x) + 0x2U)
 192
 193 #define HW_CRC_DATAH(x)          (*(__IO hw_crc_datah_t *) HW_CRC_DATAH_ADDR(x))
 194 #define HW_CRC_DATAH_RD(x)       (HW_CRC_DATAH(x).U)
 195 #define HW_CRC_DATAH_WR(x, v)    (HW_CRC_DATAH(x).U = (v))
 196 #define HW_CRC_DATAH_SET(x, v)   (HW_CRC_DATAH_WR(x, HW_CRC_DATAH_RD(x) |  (v)))
 197 #define HW_CRC_DATAH_CLR(x, v)   (HW_CRC_DATAH_WR(x, HW_CRC_DATAH_RD(x) & ~(v)))
 198 #define HW_CRC_DATAH_TOG(x, v)   (HW_CRC_DATAH_WR(x, HW_CRC_DATAH_RD(x) ^  (v)))
 199 /*@}*/
 200
 201 /*
 202  * Constants & macros for individual CRC_DATAH bitfields
 203  */
 204
 205 /*!
 206  * @name Register CRC_DATAH, field DATAH[15:0] (RW)
 207  */
 208 /*@{*/
 209 #define BP_CRC_DATAH_DATAH   (0U)          /*!< Bit position for CRC_DATAH_DATAH. */
 210 #define BM_CRC_DATAH_DATAH   (0xFFFFU)     /*!< Bit mask for CRC_DATAH_DATAH. */
 211 #define BS_CRC_DATAH_DATAH   (16U)         /*!< Bit field size in bits for CRC_DATAH_DATAH. */
 212
 213 /*! @brief Read current value of the CRC_DATAH_DATAH field. */
 214 #define BR_CRC_DATAH_DATAH(x) (HW_CRC_DATAH(x).U)
 215
 216 /*! @brief Format value for bitfield CRC_DATAH_DATAH. */
 217 #define BF_CRC_DATAH_DATAH(v) ((uint16_t)((uint16_t)(v) << BP_CRC_DATAH_DATAH) & BM_CRC_DATAH_DATAH)
 218
 219 /*! @brief Set the DATAH field to a new value. */
 220 #define BW_CRC_DATAH_DATAH(x, v) (HW_CRC_DATAH_WR(x, v))
 221 /*@}*/
 222 /*******************************************************************************
 223  * HW_CRC_DATALL - CRC_DATALL register.
 224  ******************************************************************************/
 225
 226 /*!
 227  * @brief HW_CRC_DATALL - CRC_DATALL register. (RW)
 228  *
 229  * Reset value: 0xFFU
 230  */
 231 typedef union _hw_crc_datall
 232 {
 233     uint8_t U;
 234     struct _hw_crc_datall_bitfields
 235     {
 236         uint8_t DATALL : 8;            /*!< [7:0] CRCLL stores the first 8 bits of the
 237                                         * 32 bit DATA */
 238     } B;
 239 } hw_crc_datall_t;
 240
 241 /*!
 242  * @name Constants and macros for entire CRC_DATALL register
 243  */
 244 /*@{*/
 245 #define HW_CRC_DATALL_ADDR(x)    ((x) + 0x0U)
 246
 247 #define HW_CRC_DATALL(x)         (*(__IO hw_crc_datall_t *) HW_CRC_DATALL_ADDR(x))
 248 #define HW_CRC_DATALL_RD(x)      (HW_CRC_DATALL(x).U)
 249 #define HW_CRC_DATALL_WR(x, v)   (HW_CRC_DATALL(x).U = (v))
 250 #define HW_CRC_DATALL_SET(x, v)  (HW_CRC_DATALL_WR(x, HW_CRC_DATALL_RD(x) |  (v)))
 251 #define HW_CRC_DATALL_CLR(x, v)  (HW_CRC_DATALL_WR(x, HW_CRC_DATALL_RD(x) & ~(v)))
 252 #define HW_CRC_DATALL_TOG(x, v)  (HW_CRC_DATALL_WR(x, HW_CRC_DATALL_RD(x) ^  (v)))
 253 /*@}*/
 254
 255 /*
 256  * Constants & macros for individual CRC_DATALL bitfields
 257  */
 258
 259 /*!
 260  * @name Register CRC_DATALL, field DATALL[7:0] (RW)
 261  */
 262 /*@{*/
 263 #define BP_CRC_DATALL_DATALL (0U)          /*!< Bit position for CRC_DATALL_DATALL. */
 264 #define BM_CRC_DATALL_DATALL (0xFFU)       /*!< Bit mask for CRC_DATALL_DATALL. */
 265 #define BS_CRC_DATALL_DATALL (8U)          /*!< Bit field size in bits for CRC_DATALL_DATALL. */
 266
 267 /*! @brief Read current value of the CRC_DATALL_DATALL field. */
 268 #define BR_CRC_DATALL_DATALL(x) (HW_CRC_DATALL(x).U)
 269
 270 /*! @brief Format value for bitfield CRC_DATALL_DATALL. */
 271 #define BF_CRC_DATALL_DATALL(v) ((uint8_t)((uint8_t)(v) << BP_CRC_DATALL_DATALL) & BM_CRC_DATALL_DATALL)
 272
 273 /*! @brief Set the DATALL field to a new value. */
 274 #define BW_CRC_DATALL_DATALL(x, v) (HW_CRC_DATALL_WR(x, v))
 275 /*@}*/
 276 /*******************************************************************************
 277  * HW_CRC_DATALU - CRC_DATALU register.
 278  ******************************************************************************/
 279
 280 /*!
 281  * @brief HW_CRC_DATALU - CRC_DATALU register. (RW)
 282  *
 283  * Reset value: 0xFFU
 284  */
 285 typedef union _hw_crc_datalu
 286 {
 287     uint8_t U;
 288     struct _hw_crc_datalu_bitfields
 289     {
 290         uint8_t DATALU : 8;            /*!< [7:0] DATALL stores the second 8 bits of the
 291                                         * 32 bit CRC */
 292     } B;
 293 } hw_crc_datalu_t;
 294
 295 /*!
 296  * @name Constants and macros for entire CRC_DATALU register
 297  */
 298 /*@{*/
 299 #define HW_CRC_DATALU_ADDR(x)    ((x) + 0x1U)
 300
 301 #define HW_CRC_DATALU(x)         (*(__IO hw_crc_datalu_t *) HW_CRC_DATALU_ADDR(x))
 302 #define HW_CRC_DATALU_RD(x)      (HW_CRC_DATALU(x).U)
 303 #define HW_CRC_DATALU_WR(x, v)   (HW_CRC_DATALU(x).U = (v))
 304 #define HW_CRC_DATALU_SET(x, v)  (HW_CRC_DATALU_WR(x, HW_CRC_DATALU_RD(x) |  (v)))
 305 #define HW_CRC_DATALU_CLR(x, v)  (HW_CRC_DATALU_WR(x, HW_CRC_DATALU_RD(x) & ~(v)))
 306 #define HW_CRC_DATALU_TOG(x, v)  (HW_CRC_DATALU_WR(x, HW_CRC_DATALU_RD(x) ^  (v)))
 307 /*@}*/
 308
 309 /*
 310  * Constants & macros for individual CRC_DATALU bitfields
 311  */
 312
 313 /*!
 314  * @name Register CRC_DATALU, field DATALU[7:0] (RW)
 315  */
 316 /*@{*/
 317 #define BP_CRC_DATALU_DATALU (0U)          /*!< Bit position for CRC_DATALU_DATALU. */
 318 #define BM_CRC_DATALU_DATALU (0xFFU)       /*!< Bit mask for CRC_DATALU_DATALU. */
 319 #define BS_CRC_DATALU_DATALU (8U)          /*!< Bit field size in bits for CRC_DATALU_DATALU. */
 320
 321 /*! @brief Read current value of the CRC_DATALU_DATALU field. */
 322 #define BR_CRC_DATALU_DATALU(x) (HW_CRC_DATALU(x).U)
 323
 324 /*! @brief Format value for bitfield CRC_DATALU_DATALU. */
 325 #define BF_CRC_DATALU_DATALU(v) ((uint8_t)((uint8_t)(v) << BP_CRC_DATALU_DATALU) & BM_CRC_DATALU_DATALU)
 326
 327 /*! @brief Set the DATALU field to a new value. */
 328 #define BW_CRC_DATALU_DATALU(x, v) (HW_CRC_DATALU_WR(x, v))
 329 /*@}*/
 330 /*******************************************************************************
 331  * HW_CRC_DATAHL - CRC_DATAHL register.
 332  ******************************************************************************/
 333
 334 /*!
 335  * @brief HW_CRC_DATAHL - CRC_DATAHL register. (RW)
 336  *
 337  * Reset value: 0xFFU
 338  */
 339 typedef union _hw_crc_datahl
 340 {
 341     uint8_t U;
 342     struct _hw_crc_datahl_bitfields
 343     {
 344         uint8_t DATAHL : 8;            /*!< [7:0] DATAHL stores the third 8 bits of the
 345                                         * 32 bit CRC */
 346     } B;
 347 } hw_crc_datahl_t;
 348
 349 /*!
 350  * @name Constants and macros for entire CRC_DATAHL register
 351  */
 352 /*@{*/
 353 #define HW_CRC_DATAHL_ADDR(x)    ((x) + 0x2U)
 354
 355 #define HW_CRC_DATAHL(x)         (*(__IO hw_crc_datahl_t *) HW_CRC_DATAHL_ADDR(x))
 356 #define HW_CRC_DATAHL_RD(x)      (HW_CRC_DATAHL(x).U)
 357 #define HW_CRC_DATAHL_WR(x, v)   (HW_CRC_DATAHL(x).U = (v))
 358 #define HW_CRC_DATAHL_SET(x, v)  (HW_CRC_DATAHL_WR(x, HW_CRC_DATAHL_RD(x) |  (v)))
 359 #define HW_CRC_DATAHL_CLR(x, v)  (HW_CRC_DATAHL_WR(x, HW_CRC_DATAHL_RD(x) & ~(v)))
 360 #define HW_CRC_DATAHL_TOG(x, v)  (HW_CRC_DATAHL_WR(x, HW_CRC_DATAHL_RD(x) ^  (v)))
 361 /*@}*/
 362
 363 /*
 364  * Constants & macros for individual CRC_DATAHL bitfields
 365  */
 366
 367 /*!
 368  * @name Register CRC_DATAHL, field DATAHL[7:0] (RW)
 369  */
 370 /*@{*/
 371 #define BP_CRC_DATAHL_DATAHL (0U)          /*!< Bit position for CRC_DATAHL_DATAHL. */
 372 #define BM_CRC_DATAHL_DATAHL (0xFFU)       /*!< Bit mask for CRC_DATAHL_DATAHL. */
 373 #define BS_CRC_DATAHL_DATAHL (8U)          /*!< Bit field size in bits for CRC_DATAHL_DATAHL. */
 374
 375 /*! @brief Read current value of the CRC_DATAHL_DATAHL field. */
 376 #define BR_CRC_DATAHL_DATAHL(x) (HW_CRC_DATAHL(x).U)
 377
 378 /*! @brief Format value for bitfield CRC_DATAHL_DATAHL. */
 379 #define BF_CRC_DATAHL_DATAHL(v) ((uint8_t)((uint8_t)(v) << BP_CRC_DATAHL_DATAHL) & BM_CRC_DATAHL_DATAHL)
 380
 381 /*! @brief Set the DATAHL field to a new value. */
 382 #define BW_CRC_DATAHL_DATAHL(x, v) (HW_CRC_DATAHL_WR(x, v))
 383 /*@}*/
 384 /*******************************************************************************
 385  * HW_CRC_DATAHU - CRC_DATAHU register.
 386  ******************************************************************************/
 387
 388 /*!
 389  * @brief HW_CRC_DATAHU - CRC_DATAHU register. (RW)
 390  *
 391  * Reset value: 0xFFU
 392  */
 393 typedef union _hw_crc_datahu
 394 {
 395     uint8_t U;
 396     struct _hw_crc_datahu_bitfields
 397     {
 398         uint8_t DATAHU : 8;            /*!< [7:0] DATAHU stores the fourth 8 bits of the
 399                                         * 32 bit CRC */
 400     } B;
 401 } hw_crc_datahu_t;
 402
 403 /*!
 404  * @name Constants and macros for entire CRC_DATAHU register
 405  */
 406 /*@{*/
 407 #define HW_CRC_DATAHU_ADDR(x)    ((x) + 0x3U)
 408
 409 #define HW_CRC_DATAHU(x)         (*(__IO hw_crc_datahu_t *) HW_CRC_DATAHU_ADDR(x))
 410 #define HW_CRC_DATAHU_RD(x)      (HW_CRC_DATAHU(x).U)
 411 #define HW_CRC_DATAHU_WR(x, v)   (HW_CRC_DATAHU(x).U = (v))
 412 #define HW_CRC_DATAHU_SET(x, v)  (HW_CRC_DATAHU_WR(x, HW_CRC_DATAHU_RD(x) |  (v)))
 413 #define HW_CRC_DATAHU_CLR(x, v)  (HW_CRC_DATAHU_WR(x, HW_CRC_DATAHU_RD(x) & ~(v)))
 414 #define HW_CRC_DATAHU_TOG(x, v)  (HW_CRC_DATAHU_WR(x, HW_CRC_DATAHU_RD(x) ^  (v)))
 415 /*@}*/
 416
 417 /*
 418  * Constants & macros for individual CRC_DATAHU bitfields
 419  */
 420
 421 /*!
 422  * @name Register CRC_DATAHU, field DATAHU[7:0] (RW)
 423  */
 424 /*@{*/
 425 #define BP_CRC_DATAHU_DATAHU (0U)          /*!< Bit position for CRC_DATAHU_DATAHU. */
 426 #define BM_CRC_DATAHU_DATAHU (0xFFU)       /*!< Bit mask for CRC_DATAHU_DATAHU. */
 427 #define BS_CRC_DATAHU_DATAHU (8U)          /*!< Bit field size in bits for CRC_DATAHU_DATAHU. */
 428
 429 /*! @brief Read current value of the CRC_DATAHU_DATAHU field. */
 430 #define BR_CRC_DATAHU_DATAHU(x) (HW_CRC_DATAHU(x).U)
 431
 432 /*! @brief Format value for bitfield CRC_DATAHU_DATAHU. */
 433 #define BF_CRC_DATAHU_DATAHU(v) ((uint8_t)((uint8_t)(v) << BP_CRC_DATAHU_DATAHU) & BM_CRC_DATAHU_DATAHU)
 434
 435 /*! @brief Set the DATAHU field to a new value. */
 436 #define BW_CRC_DATAHU_DATAHU(x, v) (HW_CRC_DATAHU_WR(x, v))
 437 /*@}*/
 438 /*******************************************************************************
 439  * HW_CRC_DATA - CRC Data register
 440  ******************************************************************************/
 441
 442 /*!
 443  * @brief HW_CRC_DATA - CRC Data register (RW)
 444  *
 445  * Reset value: 0xFFFFFFFFU
 446  *
 447  * The CRC Data register contains the value of the seed, data, and checksum.
 448  * When CTRL[WAS] is set, any write to the data register is regarded as the seed
 449  * value. When CTRL[WAS] is cleared, any write to the data register is regarded as
 450  * data for general CRC computation. In 16-bit CRC mode, the HU and HL fields are
 451  * not used for programming the seed value, and reads of these fields return an
 452  * indeterminate value. In 32-bit CRC mode, all fields are used for programming
 453  * the seed value. When programming data values, the values can be written 8 bits,
 454  * 16 bits, or 32 bits at a time, provided all bytes are contiguous; with MSB of
 455  * data value written first. After all data values are written, the CRC result
 456  * can be read from this data register. In 16-bit CRC mode, the CRC result is
 457  * available in the LU and LL fields. In 32-bit CRC mode, all fields contain the
 458  * result. Reads of this register at any time return the intermediate CRC value,
 459  * provided the CRC module is configured.
 460  */
 461 typedef union _hw_crc_data
 462 {
 463     uint32_t U;
 464     struct _hw_crc_data_bitfields
 465     {
 466         uint32_t LL : 8;               /*!< [7:0] CRC Low Lower Byte */
 467         uint32_t LU : 8;               /*!< [15:8] CRC Low Upper Byte */
 468         uint32_t HL : 8;               /*!< [23:16] CRC High Lower Byte */
 469         uint32_t HU : 8;               /*!< [31:24] CRC High Upper Byte */
 470     } B;
 471 } hw_crc_data_t;
 472
 473 /*!
 474  * @name Constants and macros for entire CRC_DATA register
 475  */
 476 /*@{*/
 477 #define HW_CRC_DATA_ADDR(x)      ((x) + 0x0U)
 478
 479 #define HW_CRC_DATA(x)           (*(__IO hw_crc_data_t *) HW_CRC_DATA_ADDR(x))
 480 #define HW_CRC_DATA_RD(x)        (HW_CRC_DATA(x).U)
 481 #define HW_CRC_DATA_WR(x, v)     (HW_CRC_DATA(x).U = (v))
 482 #define HW_CRC_DATA_SET(x, v)    (HW_CRC_DATA_WR(x, HW_CRC_DATA_RD(x) |  (v)))
 483 #define HW_CRC_DATA_CLR(x, v)    (HW_CRC_DATA_WR(x, HW_CRC_DATA_RD(x) & ~(v)))
 484 #define HW_CRC_DATA_TOG(x, v)    (HW_CRC_DATA_WR(x, HW_CRC_DATA_RD(x) ^  (v)))
 485 /*@}*/
 486
 487 /*
 488  * Constants & macros for individual CRC_DATA bitfields
 489  */
 490
 491 /*!
 492  * @name Register CRC_DATA, field LL[7:0] (RW)
 493  *
 494  * When CTRL[WAS] is 1, values written to this field are part of the seed value.
 495  * When CTRL[WAS] is 0, data written to this field is used for CRC checksum
 496  * generation.
 497  */
 498 /*@{*/
 499 #define BP_CRC_DATA_LL       (0U)          /*!< Bit position for CRC_DATA_LL. */
 500 #define BM_CRC_DATA_LL       (0x000000FFU) /*!< Bit mask for CRC_DATA_LL. */
 501 #define BS_CRC_DATA_LL       (8U)          /*!< Bit field size in bits for CRC_DATA_LL. */
 502
 503 /*! @brief Read current value of the CRC_DATA_LL field. */
 504 #define BR_CRC_DATA_LL(x)    (HW_CRC_DATA(x).B.LL)
 505
 506 /*! @brief Format value for bitfield CRC_DATA_LL. */
 507 #define BF_CRC_DATA_LL(v)    ((uint32_t)((uint32_t)(v) << BP_CRC_DATA_LL) & BM_CRC_DATA_LL)
 508
 509 /*! @brief Set the LL field to a new value. */
 510 #define BW_CRC_DATA_LL(x, v) (HW_CRC_DATA_WR(x, (HW_CRC_DATA_RD(x) & ~BM_CRC_DATA_LL) | BF_CRC_DATA_LL(v)))
 511 /*@}*/
 512
 513 /*!
 514  * @name Register CRC_DATA, field LU[15:8] (RW)
 515  *
 516  * When CTRL[WAS] is 1, values written to this field are part of the seed value.
 517  * When CTRL[WAS] is 0, data written to this field is used for CRC checksum
 518  * generation.
 519  */
 520 /*@{*/
 521 #define BP_CRC_DATA_LU       (8U)          /*!< Bit position for CRC_DATA_LU. */
 522 #define BM_CRC_DATA_LU       (0x0000FF00U) /*!< Bit mask for CRC_DATA_LU. */
 523 #define BS_CRC_DATA_LU       (8U)          /*!< Bit field size in bits for CRC_DATA_LU. */
 524
 525 /*! @brief Read current value of the CRC_DATA_LU field. */
 526 #define BR_CRC_DATA_LU(x)    (HW_CRC_DATA(x).B.LU)
 527
 528 /*! @brief Format value for bitfield CRC_DATA_LU. */
 529 #define BF_CRC_DATA_LU(v)    ((uint32_t)((uint32_t)(v) << BP_CRC_DATA_LU) & BM_CRC_DATA_LU)
 530
 531 /*! @brief Set the LU field to a new value. */
 532 #define BW_CRC_DATA_LU(x, v) (HW_CRC_DATA_WR(x, (HW_CRC_DATA_RD(x) & ~BM_CRC_DATA_LU) | BF_CRC_DATA_LU(v)))
 533 /*@}*/
 534
 535 /*!
 536  * @name Register CRC_DATA, field HL[23:16] (RW)
 537  *
 538  * In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming
 539  * a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this
 540  * field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data
 541  * written to this field is used for CRC checksum generation in both 16-bit and
 542  * 32-bit CRC modes.
 543  */
 544 /*@{*/
 545 #define BP_CRC_DATA_HL       (16U)         /*!< Bit position for CRC_DATA_HL. */
 546 #define BM_CRC_DATA_HL       (0x00FF0000U) /*!< Bit mask for CRC_DATA_HL. */
 547 #define BS_CRC_DATA_HL       (8U)          /*!< Bit field size in bits for CRC_DATA_HL. */
 548
 549 /*! @brief Read current value of the CRC_DATA_HL field. */
 550 #define BR_CRC_DATA_HL(x)    (HW_CRC_DATA(x).B.HL)
 551
 552 /*! @brief Format value for bitfield CRC_DATA_HL. */
 553 #define BF_CRC_DATA_HL(v)    ((uint32_t)((uint32_t)(v) << BP_CRC_DATA_HL) & BM_CRC_DATA_HL)
 554
 555 /*! @brief Set the HL field to a new value. */
 556 #define BW_CRC_DATA_HL(x, v) (HW_CRC_DATA_WR(x, (HW_CRC_DATA_RD(x) & ~BM_CRC_DATA_HL) | BF_CRC_DATA_HL(v)))
 557 /*@}*/
 558
 559 /*!
 560  * @name Register CRC_DATA, field HU[31:24] (RW)
 561  *
 562  * In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming
 563  * a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this
 564  * field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data
 565  * written to this field is used for CRC checksum generation in both 16-bit and
 566  * 32-bit CRC modes.
 567  */
 568 /*@{*/
 569 #define BP_CRC_DATA_HU       (24U)         /*!< Bit position for CRC_DATA_HU. */
 570 #define BM_CRC_DATA_HU       (0xFF000000U) /*!< Bit mask for CRC_DATA_HU. */
 571 #define BS_CRC_DATA_HU       (8U)          /*!< Bit field size in bits for CRC_DATA_HU. */
 572
 573 /*! @brief Read current value of the CRC_DATA_HU field. */
 574 #define BR_CRC_DATA_HU(x)    (HW_CRC_DATA(x).B.HU)
 575
 576 /*! @brief Format value for bitfield CRC_DATA_HU. */
 577 #define BF_CRC_DATA_HU(v)    ((uint32_t)((uint32_t)(v) << BP_CRC_DATA_HU) & BM_CRC_DATA_HU)
 578
 579 /*! @brief Set the HU field to a new value. */
 580 #define BW_CRC_DATA_HU(x, v) (HW_CRC_DATA_WR(x, (HW_CRC_DATA_RD(x) & ~BM_CRC_DATA_HU) | BF_CRC_DATA_HU(v)))
 581 /*@}*/
 582
 583 /*******************************************************************************
 584  * HW_CRC_GPOLY - CRC Polynomial register
 585  ******************************************************************************/
 586
 587 /*!
 588  * @brief HW_CRC_GPOLY - CRC Polynomial register (RW)
 589  *
 590  * Reset value: 0x00001021U
 591  *
 592  * This register contains the value of the polynomial for the CRC calculation.
 593  * The HIGH field contains the upper 16 bits of the CRC polynomial, which are used
 594  * only in 32-bit CRC mode. Writes to the HIGH field are ignored in 16-bit CRC
 595  * mode. The LOW field contains the lower 16 bits of the CRC polynomial, which are
 596  * used in both 16- and 32-bit CRC modes.
 597  */
 598 typedef union _hw_crc_gpoly
 599 {
 600     uint32_t U;
 601     struct _hw_crc_gpoly_bitfields
 602     {
 603         uint32_t LOW : 16;             /*!< [15:0] Low Polynominal Half-word */
 604         uint32_t HIGH : 16;            /*!< [31:16] High Polynominal Half-word */
 605     } B;
 606 } hw_crc_gpoly_t;
 607
 608 /*!
 609  * @name Constants and macros for entire CRC_GPOLY register
 610  */
 611 /*@{*/
 612 #define HW_CRC_GPOLY_ADDR(x)     ((x) + 0x4U)
 613
 614 #define HW_CRC_GPOLY(x)          (*(__IO hw_crc_gpoly_t *) HW_CRC_GPOLY_ADDR(x))
 615 #define HW_CRC_GPOLY_RD(x)       (HW_CRC_GPOLY(x).U)
 616 #define HW_CRC_GPOLY_WR(x, v)    (HW_CRC_GPOLY(x).U = (v))
 617 #define HW_CRC_GPOLY_SET(x, v)   (HW_CRC_GPOLY_WR(x, HW_CRC_GPOLY_RD(x) |  (v)))
 618 #define HW_CRC_GPOLY_CLR(x, v)   (HW_CRC_GPOLY_WR(x, HW_CRC_GPOLY_RD(x) & ~(v)))
 619 #define HW_CRC_GPOLY_TOG(x, v)   (HW_CRC_GPOLY_WR(x, HW_CRC_GPOLY_RD(x) ^  (v)))
 620 /*@}*/
 621
 622 /*
 623  * Constants & macros for individual CRC_GPOLY bitfields
 624  */
 625
 626 /*!
 627  * @name Register CRC_GPOLY, field LOW[15:0] (RW)
 628  *
 629  * Writable and readable in both 32-bit and 16-bit CRC modes.
 630  */
 631 /*@{*/
 632 #define BP_CRC_GPOLY_LOW     (0U)          /*!< Bit position for CRC_GPOLY_LOW. */
 633 #define BM_CRC_GPOLY_LOW     (0x0000FFFFU) /*!< Bit mask for CRC_GPOLY_LOW. */
 634 #define BS_CRC_GPOLY_LOW     (16U)         /*!< Bit field size in bits for CRC_GPOLY_LOW. */
 635
 636 /*! @brief Read current value of the CRC_GPOLY_LOW field. */
 637 #define BR_CRC_GPOLY_LOW(x)  (HW_CRC_GPOLY(x).B.LOW)
 638
 639 /*! @brief Format value for bitfield CRC_GPOLY_LOW. */
 640 #define BF_CRC_GPOLY_LOW(v)  ((uint32_t)((uint32_t)(v) << BP_CRC_GPOLY_LOW) & BM_CRC_GPOLY_LOW)
 641
 642 /*! @brief Set the LOW field to a new value. */
 643 #define BW_CRC_GPOLY_LOW(x, v) (HW_CRC_GPOLY_WR(x, (HW_CRC_GPOLY_RD(x) & ~BM_CRC_GPOLY_LOW) | BF_CRC_GPOLY_LOW(v)))
 644 /*@}*/
 645
 646 /*!
 647  * @name Register CRC_GPOLY, field HIGH[31:16] (RW)
 648  *
 649  * Writable and readable in 32-bit CRC mode (CTRL[TCRC] is 1). This field is not
 650  * writable in 16-bit CRC mode (CTRL[TCRC] is 0).
 651  */
 652 /*@{*/
 653 #define BP_CRC_GPOLY_HIGH    (16U)         /*!< Bit position for CRC_GPOLY_HIGH. */
 654 #define BM_CRC_GPOLY_HIGH    (0xFFFF0000U) /*!< Bit mask for CRC_GPOLY_HIGH. */
 655 #define BS_CRC_GPOLY_HIGH    (16U)         /*!< Bit field size in bits for CRC_GPOLY_HIGH. */
 656
 657 /*! @brief Read current value of the CRC_GPOLY_HIGH field. */
 658 #define BR_CRC_GPOLY_HIGH(x) (HW_CRC_GPOLY(x).B.HIGH)
 659
 660 /*! @brief Format value for bitfield CRC_GPOLY_HIGH. */
 661 #define BF_CRC_GPOLY_HIGH(v) ((uint32_t)((uint32_t)(v) << BP_CRC_GPOLY_HIGH) & BM_CRC_GPOLY_HIGH)
 662
 663 /*! @brief Set the HIGH field to a new value. */
 664 #define BW_CRC_GPOLY_HIGH(x, v) (HW_CRC_GPOLY_WR(x, (HW_CRC_GPOLY_RD(x) & ~BM_CRC_GPOLY_HIGH) | BF_CRC_GPOLY_HIGH(v)))
 665 /*@}*/
 666 /*******************************************************************************
 667  * HW_CRC_GPOLYL - CRC_GPOLYL register.
 668  ******************************************************************************/
 669
 670 /*!
 671  * @brief HW_CRC_GPOLYL - CRC_GPOLYL register. (RW)
 672  *
 673  * Reset value: 0xFFFFU
 674  */
 675 typedef union _hw_crc_gpolyl
 676 {
 677     uint16_t U;
 678     struct _hw_crc_gpolyl_bitfields
 679     {
 680         uint16_t GPOLYL : 16;          /*!< [15:0] POLYL stores the lower 16 bits of
 681                                         * the 16/32 bit CRC polynomial value */
 682     } B;
 683 } hw_crc_gpolyl_t;
 684
 685 /*!
 686  * @name Constants and macros for entire CRC_GPOLYL register
 687  */
 688 /*@{*/
 689 #define HW_CRC_GPOLYL_ADDR(x)    ((x) + 0x4U)
 690
 691 #define HW_CRC_GPOLYL(x)         (*(__IO hw_crc_gpolyl_t *) HW_CRC_GPOLYL_ADDR(x))
 692 #define HW_CRC_GPOLYL_RD(x)      (HW_CRC_GPOLYL(x).U)
 693 #define HW_CRC_GPOLYL_WR(x, v)   (HW_CRC_GPOLYL(x).U = (v))
 694 #define HW_CRC_GPOLYL_SET(x, v)  (HW_CRC_GPOLYL_WR(x, HW_CRC_GPOLYL_RD(x) |  (v)))
 695 #define HW_CRC_GPOLYL_CLR(x, v)  (HW_CRC_GPOLYL_WR(x, HW_CRC_GPOLYL_RD(x) & ~(v)))
 696 #define HW_CRC_GPOLYL_TOG(x, v)  (HW_CRC_GPOLYL_WR(x, HW_CRC_GPOLYL_RD(x) ^  (v)))
 697 /*@}*/
 698
 699 /*
 700  * Constants & macros for individual CRC_GPOLYL bitfields
 701  */
 702
 703 /*!
 704  * @name Register CRC_GPOLYL, field GPOLYL[15:0] (RW)
 705  */
 706 /*@{*/
 707 #define BP_CRC_GPOLYL_GPOLYL (0U)          /*!< Bit position for CRC_GPOLYL_GPOLYL. */
 708 #define BM_CRC_GPOLYL_GPOLYL (0xFFFFU)     /*!< Bit mask for CRC_GPOLYL_GPOLYL. */
 709 #define BS_CRC_GPOLYL_GPOLYL (16U)         /*!< Bit field size in bits for CRC_GPOLYL_GPOLYL. */
 710
 711 /*! @brief Read current value of the CRC_GPOLYL_GPOLYL field. */
 712 #define BR_CRC_GPOLYL_GPOLYL(x) (HW_CRC_GPOLYL(x).U)
 713
 714 /*! @brief Format value for bitfield CRC_GPOLYL_GPOLYL. */
 715 #define BF_CRC_GPOLYL_GPOLYL(v) ((uint16_t)((uint16_t)(v) << BP_CRC_GPOLYL_GPOLYL) & BM_CRC_GPOLYL_GPOLYL)
 716
 717 /*! @brief Set the GPOLYL field to a new value. */
 718 #define BW_CRC_GPOLYL_GPOLYL(x, v) (HW_CRC_GPOLYL_WR(x, v))
 719 /*@}*/
 720 /*******************************************************************************
 721  * HW_CRC_GPOLYH - CRC_GPOLYH register.
 722  ******************************************************************************/
 723
 724 /*!
 725  * @brief HW_CRC_GPOLYH - CRC_GPOLYH register. (RW)
 726  *
 727  * Reset value: 0xFFFFU
 728  */
 729 typedef union _hw_crc_gpolyh
 730 {
 731     uint16_t U;
 732     struct _hw_crc_gpolyh_bitfields
 733     {
 734         uint16_t GPOLYH : 16;          /*!< [15:0] POLYH stores the high 16 bits of
 735                                         * the 16/32 bit CRC polynomial value */
 736     } B;
 737 } hw_crc_gpolyh_t;
 738
 739 /*!
 740  * @name Constants and macros for entire CRC_GPOLYH register
 741  */
 742 /*@{*/
 743 #define HW_CRC_GPOLYH_ADDR(x)    ((x) + 0x6U)
 744
 745 #define HW_CRC_GPOLYH(x)         (*(__IO hw_crc_gpolyh_t *) HW_CRC_GPOLYH_ADDR(x))
 746 #define HW_CRC_GPOLYH_RD(x)      (HW_CRC_GPOLYH(x).U)
 747 #define HW_CRC_GPOLYH_WR(x, v)   (HW_CRC_GPOLYH(x).U = (v))
 748 #define HW_CRC_GPOLYH_SET(x, v)  (HW_CRC_GPOLYH_WR(x, HW_CRC_GPOLYH_RD(x) |  (v)))
 749 #define HW_CRC_GPOLYH_CLR(x, v)  (HW_CRC_GPOLYH_WR(x, HW_CRC_GPOLYH_RD(x) & ~(v)))
 750 #define HW_CRC_GPOLYH_TOG(x, v)  (HW_CRC_GPOLYH_WR(x, HW_CRC_GPOLYH_RD(x) ^  (v)))
 751 /*@}*/
 752
 753 /*
 754  * Constants & macros for individual CRC_GPOLYH bitfields
 755  */
 756
 757 /*!
 758  * @name Register CRC_GPOLYH, field GPOLYH[15:0] (RW)
 759  */
 760 /*@{*/
 761 #define BP_CRC_GPOLYH_GPOLYH (0U)          /*!< Bit position for CRC_GPOLYH_GPOLYH. */
 762 #define BM_CRC_GPOLYH_GPOLYH (0xFFFFU)     /*!< Bit mask for CRC_GPOLYH_GPOLYH. */
 763 #define BS_CRC_GPOLYH_GPOLYH (16U)         /*!< Bit field size in bits for CRC_GPOLYH_GPOLYH. */
 764
 765 /*! @brief Read current value of the CRC_GPOLYH_GPOLYH field. */
 766 #define BR_CRC_GPOLYH_GPOLYH(x) (HW_CRC_GPOLYH(x).U)
 767
 768 /*! @brief Format value for bitfield CRC_GPOLYH_GPOLYH. */
 769 #define BF_CRC_GPOLYH_GPOLYH(v) ((uint16_t)((uint16_t)(v) << BP_CRC_GPOLYH_GPOLYH) & BM_CRC_GPOLYH_GPOLYH)
 770
 771 /*! @brief Set the GPOLYH field to a new value. */
 772 #define BW_CRC_GPOLYH_GPOLYH(x, v) (HW_CRC_GPOLYH_WR(x, v))
 773 /*@}*/
 774 /*******************************************************************************
 775  * HW_CRC_GPOLYLL - CRC_GPOLYLL register.
 776  ******************************************************************************/
 777
 778 /*!
 779  * @brief HW_CRC_GPOLYLL - CRC_GPOLYLL register. (RW)
 780  *
 781  * Reset value: 0xFFU
 782  */
 783 typedef union _hw_crc_gpolyll
 784 {
 785     uint8_t U;
 786     struct _hw_crc_gpolyll_bitfields
 787     {
 788         uint8_t GPOLYLL : 8;           /*!< [7:0] POLYLL stores the first 8 bits of the
 789                                         * 32 bit CRC */
 790     } B;
 791 } hw_crc_gpolyll_t;
 792
 793 /*!
 794  * @name Constants and macros for entire CRC_GPOLYLL register
 795  */
 796 /*@{*/
 797 #define HW_CRC_GPOLYLL_ADDR(x)   ((x) + 0x4U)
 798
 799 #define HW_CRC_GPOLYLL(x)        (*(__IO hw_crc_gpolyll_t *) HW_CRC_GPOLYLL_ADDR(x))
 800 #define HW_CRC_GPOLYLL_RD(x)     (HW_CRC_GPOLYLL(x).U)
 801 #define HW_CRC_GPOLYLL_WR(x, v)  (HW_CRC_GPOLYLL(x).U = (v))
 802 #define HW_CRC_GPOLYLL_SET(x, v) (HW_CRC_GPOLYLL_WR(x, HW_CRC_GPOLYLL_RD(x) |  (v)))
 803 #define HW_CRC_GPOLYLL_CLR(x, v) (HW_CRC_GPOLYLL_WR(x, HW_CRC_GPOLYLL_RD(x) & ~(v)))
 804 #define HW_CRC_GPOLYLL_TOG(x, v) (HW_CRC_GPOLYLL_WR(x, HW_CRC_GPOLYLL_RD(x) ^  (v)))
 805 /*@}*/
 806
 807 /*
 808  * Constants & macros for individual CRC_GPOLYLL bitfields
 809  */
 810
 811 /*!
 812  * @name Register CRC_GPOLYLL, field GPOLYLL[7:0] (RW)
 813  */
 814 /*@{*/
 815 #define BP_CRC_GPOLYLL_GPOLYLL (0U)        /*!< Bit position for CRC_GPOLYLL_GPOLYLL. */
 816 #define BM_CRC_GPOLYLL_GPOLYLL (0xFFU)     /*!< Bit mask for CRC_GPOLYLL_GPOLYLL. */
 817 #define BS_CRC_GPOLYLL_GPOLYLL (8U)        /*!< Bit field size in bits for CRC_GPOLYLL_GPOLYLL. */
 818
 819 /*! @brief Read current value of the CRC_GPOLYLL_GPOLYLL field. */
 820 #define BR_CRC_GPOLYLL_GPOLYLL(x) (HW_CRC_GPOLYLL(x).U)
 821
 822 /*! @brief Format value for bitfield CRC_GPOLYLL_GPOLYLL. */
 823 #define BF_CRC_GPOLYLL_GPOLYLL(v) ((uint8_t)((uint8_t)(v) << BP_CRC_GPOLYLL_GPOLYLL) & BM_CRC_GPOLYLL_GPOLYLL)
 824
 825 /*! @brief Set the GPOLYLL field to a new value. */
 826 #define BW_CRC_GPOLYLL_GPOLYLL(x, v) (HW_CRC_GPOLYLL_WR(x, v))
 827 /*@}*/
 828 /*******************************************************************************
 829  * HW_CRC_GPOLYLU - CRC_GPOLYLU register.
 830  ******************************************************************************/
 831
 832 /*!
 833  * @brief HW_CRC_GPOLYLU - CRC_GPOLYLU register. (RW)
 834  *
 835  * Reset value: 0xFFU
 836  */
 837 typedef union _hw_crc_gpolylu
 838 {
 839     uint8_t U;
 840     struct _hw_crc_gpolylu_bitfields
 841     {
 842         uint8_t GPOLYLU : 8;           /*!< [7:0] POLYLL stores the second 8 bits of
 843                                         * the 32 bit CRC */
 844     } B;
 845 } hw_crc_gpolylu_t;
 846
 847 /*!
 848  * @name Constants and macros for entire CRC_GPOLYLU register
 849  */
 850 /*@{*/
 851 #define HW_CRC_GPOLYLU_ADDR(x)   ((x) + 0x5U)
 852
 853 #define HW_CRC_GPOLYLU(x)        (*(__IO hw_crc_gpolylu_t *) HW_CRC_GPOLYLU_ADDR(x))
 854 #define HW_CRC_GPOLYLU_RD(x)     (HW_CRC_GPOLYLU(x).U)
 855 #define HW_CRC_GPOLYLU_WR(x, v)  (HW_CRC_GPOLYLU(x).U = (v))
 856 #define HW_CRC_GPOLYLU_SET(x, v) (HW_CRC_GPOLYLU_WR(x, HW_CRC_GPOLYLU_RD(x) |  (v)))
 857 #define HW_CRC_GPOLYLU_CLR(x, v) (HW_CRC_GPOLYLU_WR(x, HW_CRC_GPOLYLU_RD(x) & ~(v)))
 858 #define HW_CRC_GPOLYLU_TOG(x, v) (HW_CRC_GPOLYLU_WR(x, HW_CRC_GPOLYLU_RD(x) ^  (v)))
 859 /*@}*/
 860
 861 /*
 862  * Constants & macros for individual CRC_GPOLYLU bitfields
 863  */
 864
 865 /*!
 866  * @name Register CRC_GPOLYLU, field GPOLYLU[7:0] (RW)
 867  */
 868 /*@{*/
 869 #define BP_CRC_GPOLYLU_GPOLYLU (0U)        /*!< Bit position for CRC_GPOLYLU_GPOLYLU. */
 870 #define BM_CRC_GPOLYLU_GPOLYLU (0xFFU)     /*!< Bit mask for CRC_GPOLYLU_GPOLYLU. */
 871 #define BS_CRC_GPOLYLU_GPOLYLU (8U)        /*!< Bit field size in bits for CRC_GPOLYLU_GPOLYLU. */
 872
 873 /*! @brief Read current value of the CRC_GPOLYLU_GPOLYLU field. */
 874 #define BR_CRC_GPOLYLU_GPOLYLU(x) (HW_CRC_GPOLYLU(x).U)
 875
 876 /*! @brief Format value for bitfield CRC_GPOLYLU_GPOLYLU. */
 877 #define BF_CRC_GPOLYLU_GPOLYLU(v) ((uint8_t)((uint8_t)(v) << BP_CRC_GPOLYLU_GPOLYLU) & BM_CRC_GPOLYLU_GPOLYLU)
 878
 879 /*! @brief Set the GPOLYLU field to a new value. */
 880 #define BW_CRC_GPOLYLU_GPOLYLU(x, v) (HW_CRC_GPOLYLU_WR(x, v))
 881 /*@}*/
 882 /*******************************************************************************
 883  * HW_CRC_GPOLYHL - CRC_GPOLYHL register.
 884  ******************************************************************************/
 885
 886 /*!
 887  * @brief HW_CRC_GPOLYHL - CRC_GPOLYHL register. (RW)
 888  *
 889  * Reset value: 0xFFU
 890  */
 891 typedef union _hw_crc_gpolyhl
 892 {
 893     uint8_t U;
 894     struct _hw_crc_gpolyhl_bitfields
 895     {
 896         uint8_t GPOLYHL : 8;           /*!< [7:0] POLYHL stores the third 8 bits of the
 897                                         * 32 bit CRC */
 898     } B;
 899 } hw_crc_gpolyhl_t;
 900
 901 /*!
 902  * @name Constants and macros for entire CRC_GPOLYHL register
 903  */
 904 /*@{*/
 905 #define HW_CRC_GPOLYHL_ADDR(x)   ((x) + 0x6U)
 906
 907 #define HW_CRC_GPOLYHL(x)        (*(__IO hw_crc_gpolyhl_t *) HW_CRC_GPOLYHL_ADDR(x))
 908 #define HW_CRC_GPOLYHL_RD(x)     (HW_CRC_GPOLYHL(x).U)
 909 #define HW_CRC_GPOLYHL_WR(x, v)  (HW_CRC_GPOLYHL(x).U = (v))
 910 #define HW_CRC_GPOLYHL_SET(x, v) (HW_CRC_GPOLYHL_WR(x, HW_CRC_GPOLYHL_RD(x) |  (v)))
 911 #define HW_CRC_GPOLYHL_CLR(x, v) (HW_CRC_GPOLYHL_WR(x, HW_CRC_GPOLYHL_RD(x) & ~(v)))
 912 #define HW_CRC_GPOLYHL_TOG(x, v) (HW_CRC_GPOLYHL_WR(x, HW_CRC_GPOLYHL_RD(x) ^  (v)))
 913 /*@}*/
 914
 915 /*
 916  * Constants & macros for individual CRC_GPOLYHL bitfields
 917  */
 918
 919 /*!
 920  * @name Register CRC_GPOLYHL, field GPOLYHL[7:0] (RW)
 921  */
 922 /*@{*/
 923 #define BP_CRC_GPOLYHL_GPOLYHL (0U)        /*!< Bit position for CRC_GPOLYHL_GPOLYHL. */
 924 #define BM_CRC_GPOLYHL_GPOLYHL (0xFFU)     /*!< Bit mask for CRC_GPOLYHL_GPOLYHL. */
 925 #define BS_CRC_GPOLYHL_GPOLYHL (8U)        /*!< Bit field size in bits for CRC_GPOLYHL_GPOLYHL. */
 926
 927 /*! @brief Read current value of the CRC_GPOLYHL_GPOLYHL field. */
 928 #define BR_CRC_GPOLYHL_GPOLYHL(x) (HW_CRC_GPOLYHL(x).U)
 929
 930 /*! @brief Format value for bitfield CRC_GPOLYHL_GPOLYHL. */
 931 #define BF_CRC_GPOLYHL_GPOLYHL(v) ((uint8_t)((uint8_t)(v) << BP_CRC_GPOLYHL_GPOLYHL) & BM_CRC_GPOLYHL_GPOLYHL)
 932
 933 /*! @brief Set the GPOLYHL field to a new value. */
 934 #define BW_CRC_GPOLYHL_GPOLYHL(x, v) (HW_CRC_GPOLYHL_WR(x, v))
 935 /*@}*/
 936 /*******************************************************************************
 937  * HW_CRC_GPOLYHU - CRC_GPOLYHU register.
 938  ******************************************************************************/
 939
 940 /*!
 941  * @brief HW_CRC_GPOLYHU - CRC_GPOLYHU register. (RW)
 942  *
 943  * Reset value: 0xFFU
 944  */
 945 typedef union _hw_crc_gpolyhu
 946 {
 947     uint8_t U;
 948     struct _hw_crc_gpolyhu_bitfields
 949     {
 950         uint8_t GPOLYHU : 8;           /*!< [7:0] POLYHU stores the fourth 8 bits of
 951                                         * the 32 bit CRC */
 952     } B;
 953 } hw_crc_gpolyhu_t;
 954
 955 /*!
 956  * @name Constants and macros for entire CRC_GPOLYHU register
 957  */
 958 /*@{*/
 959 #define HW_CRC_GPOLYHU_ADDR(x)   ((x) + 0x7U)
 960
 961 #define HW_CRC_GPOLYHU(x)        (*(__IO hw_crc_gpolyhu_t *) HW_CRC_GPOLYHU_ADDR(x))
 962 #define HW_CRC_GPOLYHU_RD(x)     (HW_CRC_GPOLYHU(x).U)
 963 #define HW_CRC_GPOLYHU_WR(x, v)  (HW_CRC_GPOLYHU(x).U = (v))
 964 #define HW_CRC_GPOLYHU_SET(x, v) (HW_CRC_GPOLYHU_WR(x, HW_CRC_GPOLYHU_RD(x) |  (v)))
 965 #define HW_CRC_GPOLYHU_CLR(x, v) (HW_CRC_GPOLYHU_WR(x, HW_CRC_GPOLYHU_RD(x) & ~(v)))
 966 #define HW_CRC_GPOLYHU_TOG(x, v) (HW_CRC_GPOLYHU_WR(x, HW_CRC_GPOLYHU_RD(x) ^  (v)))
 967 /*@}*/
 968
 969 /*
 970  * Constants & macros for individual CRC_GPOLYHU bitfields
 971  */
 972
 973 /*!
 974  * @name Register CRC_GPOLYHU, field GPOLYHU[7:0] (RW)
 975  */
 976 /*@{*/
 977 #define BP_CRC_GPOLYHU_GPOLYHU (0U)        /*!< Bit position for CRC_GPOLYHU_GPOLYHU. */
 978 #define BM_CRC_GPOLYHU_GPOLYHU (0xFFU)     /*!< Bit mask for CRC_GPOLYHU_GPOLYHU. */
 979 #define BS_CRC_GPOLYHU_GPOLYHU (8U)        /*!< Bit field size in bits for CRC_GPOLYHU_GPOLYHU. */
 980
 981 /*! @brief Read current value of the CRC_GPOLYHU_GPOLYHU field. */
 982 #define BR_CRC_GPOLYHU_GPOLYHU(x) (HW_CRC_GPOLYHU(x).U)
 983
 984 /*! @brief Format value for bitfield CRC_GPOLYHU_GPOLYHU. */
 985 #define BF_CRC_GPOLYHU_GPOLYHU(v) ((uint8_t)((uint8_t)(v) << BP_CRC_GPOLYHU_GPOLYHU) & BM_CRC_GPOLYHU_GPOLYHU)
 986
 987 /*! @brief Set the GPOLYHU field to a new value. */
 988 #define BW_CRC_GPOLYHU_GPOLYHU(x, v) (HW_CRC_GPOLYHU_WR(x, v))
 989 /*@}*/
 990
 991 /*******************************************************************************
 992  * HW_CRC_CTRL - CRC Control register
 993  ******************************************************************************/
 994
 995 /*!
 996  * @brief HW_CRC_CTRL - CRC Control register (RW)
 997  *
 998  * Reset value: 0x00000000U
 999  *
1000  * This register controls the configuration and working of the CRC module.
1001  * Appropriate bits must be set before starting a new CRC calculation. A new CRC
1002  * calculation is initialized by asserting CTRL[WAS] and then writing the seed into
1003  * the CRC data register.
1004  */
1005 typedef union _hw_crc_ctrl
1006 {
1007     uint32_t U;
1008     struct _hw_crc_ctrl_bitfields
1009     {
1010         uint32_t RESERVED0 : 24;       /*!< [23:0]  */
1011         uint32_t TCRC : 1;             /*!< [24]  */
1012         uint32_t WAS : 1;              /*!< [25] Write CRC Data Register As Seed */
1013         uint32_t FXOR : 1;             /*!< [26] Complement Read Of CRC Data Register */
1014         uint32_t RESERVED1 : 1;        /*!< [27]  */
1015         uint32_t TOTR : 2;             /*!< [29:28] Type Of Transpose For Read */
1016         uint32_t TOT : 2;              /*!< [31:30] Type Of Transpose For Writes */
1017     } B;
1018 } hw_crc_ctrl_t;
1019
1020 /*!
1021  * @name Constants and macros for entire CRC_CTRL register
1022  */
1023 /*@{*/
1024 #define HW_CRC_CTRL_ADDR(x)      ((x) + 0x8U)
1025
1026 #define HW_CRC_CTRL(x)           (*(__IO hw_crc_ctrl_t *) HW_CRC_CTRL_ADDR(x))
1027 #define HW_CRC_CTRL_RD(x)        (HW_CRC_CTRL(x).U)
1028 #define HW_CRC_CTRL_WR(x, v)     (HW_CRC_CTRL(x).U = (v))
1029 #define HW_CRC_CTRL_SET(x, v)    (HW_CRC_CTRL_WR(x, HW_CRC_CTRL_RD(x) |  (v)))
1030 #define HW_CRC_CTRL_CLR(x, v)    (HW_CRC_CTRL_WR(x, HW_CRC_CTRL_RD(x) & ~(v)))
1031 #define HW_CRC_CTRL_TOG(x, v)    (HW_CRC_CTRL_WR(x, HW_CRC_CTRL_RD(x) ^  (v)))
1032 /*@}*/
1033
1034 /*
1035  * Constants & macros for individual CRC_CTRL bitfields
1036  */
1037
1038 /*!
1039  * @name Register CRC_CTRL, field TCRC[24] (RW)
1040  *
1041  * Width of CRC protocol.
1042  *
1043  * Values:
1044  * - 0 - 16-bit CRC protocol.
1045  * - 1 - 32-bit CRC protocol.
1046  */
1047 /*@{*/
1048 #define BP_CRC_CTRL_TCRC     (24U)         /*!< Bit position for CRC_CTRL_TCRC. */
1049 #define BM_CRC_CTRL_TCRC     (0x01000000U) /*!< Bit mask for CRC_CTRL_TCRC. */
1050 #define BS_CRC_CTRL_TCRC     (1U)          /*!< Bit field size in bits for CRC_CTRL_TCRC. */
1051
1052 /*! @brief Read current value of the CRC_CTRL_TCRC field. */
1053 #define BR_CRC_CTRL_TCRC(x)  (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_TCRC))
1054
1055 /*! @brief Format value for bitfield CRC_CTRL_TCRC. */
1056 #define BF_CRC_CTRL_TCRC(v)  ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_TCRC) & BM_CRC_CTRL_TCRC)
1057
1058 /*! @brief Set the TCRC field to a new value. */
1059 #define BW_CRC_CTRL_TCRC(x, v) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_TCRC) = (v))
1060 /*@}*/
1061
1062 /*!
1063  * @name Register CRC_CTRL, field WAS[25] (RW)
1064  *
1065  * When asserted, a value written to the CRC data register is considered a seed
1066  * value. When deasserted, a value written to the CRC data register is taken as
1067  * data for CRC computation.
1068  *
1069  * Values:
1070  * - 0 - Writes to the CRC data register are data values.
1071  * - 1 - Writes to the CRC data register are seed values.
1072  */
1073 /*@{*/
1074 #define BP_CRC_CTRL_WAS      (25U)         /*!< Bit position for CRC_CTRL_WAS. */
1075 #define BM_CRC_CTRL_WAS      (0x02000000U) /*!< Bit mask for CRC_CTRL_WAS. */
1076 #define BS_CRC_CTRL_WAS      (1U)          /*!< Bit field size in bits for CRC_CTRL_WAS. */
1077
1078 /*! @brief Read current value of the CRC_CTRL_WAS field. */
1079 #define BR_CRC_CTRL_WAS(x)   (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_WAS))
1080
1081 /*! @brief Format value for bitfield CRC_CTRL_WAS. */
1082 #define BF_CRC_CTRL_WAS(v)   ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_WAS) & BM_CRC_CTRL_WAS)
1083
1084 /*! @brief Set the WAS field to a new value. */
1085 #define BW_CRC_CTRL_WAS(x, v) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_WAS) = (v))
1086 /*@}*/
1087
1088 /*!
1089  * @name Register CRC_CTRL, field FXOR[26] (RW)
1090  *
1091  * Some CRC protocols require the final checksum to be XORed with 0xFFFFFFFF or
1092  * 0xFFFF. Asserting this bit enables on the fly complementing of read data.
1093  *
1094  * Values:
1095  * - 0 - No XOR on reading.
1096  * - 1 - Invert or complement the read value of the CRC Data register.
1097  */
1098 /*@{*/
1099 #define BP_CRC_CTRL_FXOR     (26U)         /*!< Bit position for CRC_CTRL_FXOR. */
1100 #define BM_CRC_CTRL_FXOR     (0x04000000U) /*!< Bit mask for CRC_CTRL_FXOR. */
1101 #define BS_CRC_CTRL_FXOR     (1U)          /*!< Bit field size in bits for CRC_CTRL_FXOR. */
1102
1103 /*! @brief Read current value of the CRC_CTRL_FXOR field. */
1104 #define BR_CRC_CTRL_FXOR(x)  (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_FXOR))
1105
1106 /*! @brief Format value for bitfield CRC_CTRL_FXOR. */
1107 #define BF_CRC_CTRL_FXOR(v)  ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_FXOR) & BM_CRC_CTRL_FXOR)
1108
1109 /*! @brief Set the FXOR field to a new value. */
1110 #define BW_CRC_CTRL_FXOR(x, v) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_FXOR) = (v))
1111 /*@}*/
1112
1113 /*!
1114  * @name Register CRC_CTRL, field TOTR[29:28] (RW)
1115  *
1116  * Identifies the transpose configuration of the value read from the CRC Data
1117  * register. See the description of the transpose feature for the available
1118  * transpose options.
1119  *
1120  * Values:
1121  * - 00 - No transposition.
1122  * - 01 - Bits in bytes are transposed; bytes are not transposed.
1123  * - 10 - Both bits in bytes and bytes are transposed.
1124  * - 11 - Only bytes are transposed; no bits in a byte are transposed.
1125  */
1126 /*@{*/
1127 #define BP_CRC_CTRL_TOTR     (28U)         /*!< Bit position for CRC_CTRL_TOTR. */
1128 #define BM_CRC_CTRL_TOTR     (0x30000000U) /*!< Bit mask for CRC_CTRL_TOTR. */
1129 #define BS_CRC_CTRL_TOTR     (2U)          /*!< Bit field size in bits for CRC_CTRL_TOTR. */
1130
1131 /*! @brief Read current value of the CRC_CTRL_TOTR field. */
1132 #define BR_CRC_CTRL_TOTR(x)  (HW_CRC_CTRL(x).B.TOTR)
1133
1134 /*! @brief Format value for bitfield CRC_CTRL_TOTR. */
1135 #define BF_CRC_CTRL_TOTR(v)  ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_TOTR) & BM_CRC_CTRL_TOTR)
1136
1137 /*! @brief Set the TOTR field to a new value. */
1138 #define BW_CRC_CTRL_TOTR(x, v) (HW_CRC_CTRL_WR(x, (HW_CRC_CTRL_RD(x) & ~BM_CRC_CTRL_TOTR) | BF_CRC_CTRL_TOTR(v)))
1139 /*@}*/
1140
1141 /*!
1142  * @name Register CRC_CTRL, field TOT[31:30] (RW)
1143  *
1144  * Defines the transpose configuration of the data written to the CRC data
1145  * register. See the description of the transpose feature for the available transpose
1146  * options.
1147  *
1148  * Values:
1149  * - 00 - No transposition.
1150  * - 01 - Bits in bytes are transposed; bytes are not transposed.
1151  * - 10 - Both bits in bytes and bytes are transposed.
1152  * - 11 - Only bytes are transposed; no bits in a byte are transposed.
1153  */
1154 /*@{*/
1155 #define BP_CRC_CTRL_TOT      (30U)         /*!< Bit position for CRC_CTRL_TOT. */
1156 #define BM_CRC_CTRL_TOT      (0xC0000000U) /*!< Bit mask for CRC_CTRL_TOT. */
1157 #define BS_CRC_CTRL_TOT      (2U)          /*!< Bit field size in bits for CRC_CTRL_TOT. */
1158
1159 /*! @brief Read current value of the CRC_CTRL_TOT field. */
1160 #define BR_CRC_CTRL_TOT(x)   (HW_CRC_CTRL(x).B.TOT)
1161
1162 /*! @brief Format value for bitfield CRC_CTRL_TOT. */
1163 #define BF_CRC_CTRL_TOT(v)   ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_TOT) & BM_CRC_CTRL_TOT)
1164
1165 /*! @brief Set the TOT field to a new value. */
1166 #define BW_CRC_CTRL_TOT(x, v) (HW_CRC_CTRL_WR(x, (HW_CRC_CTRL_RD(x) & ~BM_CRC_CTRL_TOT) | BF_CRC_CTRL_TOT(v)))
1167 /*@}*/
1168 /*******************************************************************************
1169  * HW_CRC_CTRLHU - CRC_CTRLHU register.
1170  ******************************************************************************/
1171
1172 /*!
1173  * @brief HW_CRC_CTRLHU - CRC_CTRLHU register. (RW)
1174  *
1175  * Reset value: 0x00U
1176  */
1177 typedef union _hw_crc_ctrlhu
1178 {
1179     uint8_t U;
1180     struct _hw_crc_ctrlhu_bitfields
1181     {
1182         uint8_t TCRC : 1;              /*!< [0]  */
1183         uint8_t WAS : 1;               /*!< [1]  */
1184         uint8_t FXOR : 1;              /*!< [2]  */
1185         uint8_t RESERVED0 : 1;         /*!< [3]  */
1186         uint8_t TOTR : 2;              /*!< [5:4]  */
1187         uint8_t TOT : 2;               /*!< [7:6]  */
1188     } B;
1189 } hw_crc_ctrlhu_t;
1190
1191 /*!
1192  * @name Constants and macros for entire CRC_CTRLHU register
1193  */
1194 /*@{*/
1195 #define HW_CRC_CTRLHU_ADDR(x)    ((x) + 0xBU)
1196
1197 #define HW_CRC_CTRLHU(x)         (*(__IO hw_crc_ctrlhu_t *) HW_CRC_CTRLHU_ADDR(x))
1198 #define HW_CRC_CTRLHU_RD(x)      (HW_CRC_CTRLHU(x).U)
1199 #define HW_CRC_CTRLHU_WR(x, v)   (HW_CRC_CTRLHU(x).U = (v))
1200 #define HW_CRC_CTRLHU_SET(x, v)  (HW_CRC_CTRLHU_WR(x, HW_CRC_CTRLHU_RD(x) |  (v)))
1201 #define HW_CRC_CTRLHU_CLR(x, v)  (HW_CRC_CTRLHU_WR(x, HW_CRC_CTRLHU_RD(x) & ~(v)))
1202 #define HW_CRC_CTRLHU_TOG(x, v)  (HW_CRC_CTRLHU_WR(x, HW_CRC_CTRLHU_RD(x) ^  (v)))
1203 /*@}*/
1204
1205 /*
1206  * Constants & macros for individual CRC_CTRLHU bitfields
1207  */
1208
1209 /*!
1210  * @name Register CRC_CTRLHU, field TCRC[0] (RW)
1211  *
1212  * Values:
1213  * - 0 - 16-bit CRC protocol.
1214  * - 1 - 32-bit CRC protocol.
1215  */
1216 /*@{*/
1217 #define BP_CRC_CTRLHU_TCRC   (0U)          /*!< Bit position for CRC_CTRLHU_TCRC. */
1218 #define BM_CRC_CTRLHU_TCRC   (0x01U)       /*!< Bit mask for CRC_CTRLHU_TCRC. */
1219 #define BS_CRC_CTRLHU_TCRC   (1U)          /*!< Bit field size in bits for CRC_CTRLHU_TCRC. */
1220
1221 /*! @brief Read current value of the CRC_CTRLHU_TCRC field. */
1222 #define BR_CRC_CTRLHU_TCRC(x) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_TCRC))
1223
1224 /*! @brief Format value for bitfield CRC_CTRLHU_TCRC. */
1225 #define BF_CRC_CTRLHU_TCRC(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_TCRC) & BM_CRC_CTRLHU_TCRC)
1226
1227 /*! @brief Set the TCRC field to a new value. */
1228 #define BW_CRC_CTRLHU_TCRC(x, v) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_TCRC) = (v))
1229 /*@}*/
1230
1231 /*!
1232  * @name Register CRC_CTRLHU, field WAS[1] (RW)
1233  *
1234  * Values:
1235  * - 0 - Writes to CRC data register are data values.
1236  * - 1 - Writes to CRC data reguster are seed values.
1237  */
1238 /*@{*/
1239 #define BP_CRC_CTRLHU_WAS    (1U)          /*!< Bit position for CRC_CTRLHU_WAS. */
1240 #define BM_CRC_CTRLHU_WAS    (0x02U)       /*!< Bit mask for CRC_CTRLHU_WAS. */
1241 #define BS_CRC_CTRLHU_WAS    (1U)          /*!< Bit field size in bits for CRC_CTRLHU_WAS. */
1242
1243 /*! @brief Read current value of the CRC_CTRLHU_WAS field. */
1244 #define BR_CRC_CTRLHU_WAS(x) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_WAS))
1245
1246 /*! @brief Format value for bitfield CRC_CTRLHU_WAS. */
1247 #define BF_CRC_CTRLHU_WAS(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_WAS) & BM_CRC_CTRLHU_WAS)
1248
1249 /*! @brief Set the WAS field to a new value. */
1250 #define BW_CRC_CTRLHU_WAS(x, v) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_WAS) = (v))
1251 /*@}*/
1252
1253 /*!
1254  * @name Register CRC_CTRLHU, field FXOR[2] (RW)
1255  *
1256  * Values:
1257  * - 0 - No XOR on reading.
1258  * - 1 - Invert or complement the read value of CRC data register.
1259  */
1260 /*@{*/
1261 #define BP_CRC_CTRLHU_FXOR   (2U)          /*!< Bit position for CRC_CTRLHU_FXOR. */
1262 #define BM_CRC_CTRLHU_FXOR   (0x04U)       /*!< Bit mask for CRC_CTRLHU_FXOR. */
1263 #define BS_CRC_CTRLHU_FXOR   (1U)          /*!< Bit field size in bits for CRC_CTRLHU_FXOR. */
1264
1265 /*! @brief Read current value of the CRC_CTRLHU_FXOR field. */
1266 #define BR_CRC_CTRLHU_FXOR(x) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_FXOR))
1267
1268 /*! @brief Format value for bitfield CRC_CTRLHU_FXOR. */
1269 #define BF_CRC_CTRLHU_FXOR(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_FXOR) & BM_CRC_CTRLHU_FXOR)
1270
1271 /*! @brief Set the FXOR field to a new value. */
1272 #define BW_CRC_CTRLHU_FXOR(x, v) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_FXOR) = (v))
1273 /*@}*/
1274
1275 /*!
1276  * @name Register CRC_CTRLHU, field TOTR[5:4] (RW)
1277  *
1278  * Values:
1279  * - 00 - No Transposition.
1280  * - 01 - Bits in bytes are transposed, bytes are not transposed.
1281  * - 10 - Both bits in bytes and bytes are transposed.
1282  * - 11 - Only bytes are transposed; no bits in a byte are transposed.
1283  */
1284 /*@{*/
1285 #define BP_CRC_CTRLHU_TOTR   (4U)          /*!< Bit position for CRC_CTRLHU_TOTR. */
1286 #define BM_CRC_CTRLHU_TOTR   (0x30U)       /*!< Bit mask for CRC_CTRLHU_TOTR. */
1287 #define BS_CRC_CTRLHU_TOTR   (2U)          /*!< Bit field size in bits for CRC_CTRLHU_TOTR. */
1288
1289 /*! @brief Read current value of the CRC_CTRLHU_TOTR field. */
1290 #define BR_CRC_CTRLHU_TOTR(x) (HW_CRC_CTRLHU(x).B.TOTR)
1291
1292 /*! @brief Format value for bitfield CRC_CTRLHU_TOTR. */
1293 #define BF_CRC_CTRLHU_TOTR(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_TOTR) & BM_CRC_CTRLHU_TOTR)
1294
1295 /*! @brief Set the TOTR field to a new value. */
1296 #define BW_CRC_CTRLHU_TOTR(x, v) (HW_CRC_CTRLHU_WR(x, (HW_CRC_CTRLHU_RD(x) & ~BM_CRC_CTRLHU_TOTR) | BF_CRC_CTRLHU_TOTR(v)))
1297 /*@}*/
1298
1299 /*!
1300  * @name Register CRC_CTRLHU, field TOT[7:6] (RW)
1301  *
1302  * Values:
1303  * - 00 - No Transposition.
1304  * - 01 - Bits in bytes are transposed, bytes are not transposed.
1305  * - 10 - Both bits in bytes and bytes are transposed.
1306  * - 11 - Only bytes are transposed; no bits in a byte are transposed.
1307  */
1308 /*@{*/
1309 #define BP_CRC_CTRLHU_TOT    (6U)          /*!< Bit position for CRC_CTRLHU_TOT. */
1310 #define BM_CRC_CTRLHU_TOT    (0xC0U)       /*!< Bit mask for CRC_CTRLHU_TOT. */
1311 #define BS_CRC_CTRLHU_TOT    (2U)          /*!< Bit field size in bits for CRC_CTRLHU_TOT. */
1312
1313 /*! @brief Read current value of the CRC_CTRLHU_TOT field. */
1314 #define BR_CRC_CTRLHU_TOT(x) (HW_CRC_CTRLHU(x).B.TOT)
1315
1316 /*! @brief Format value for bitfield CRC_CTRLHU_TOT. */
1317 #define BF_CRC_CTRLHU_TOT(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_TOT) & BM_CRC_CTRLHU_TOT)
1318
1319 /*! @brief Set the TOT field to a new value. */
1320 #define BW_CRC_CTRLHU_TOT(x, v) (HW_CRC_CTRLHU_WR(x, (HW_CRC_CTRLHU_RD(x) & ~BM_CRC_CTRLHU_TOT) | BF_CRC_CTRLHU_TOT(v)))
1321 /*@}*/
1322
1323 /*
1324 ** Start of section using anonymous unions
1325 */
1326
1327 #if defined(__ARMCC_VERSION)
1328   #pragma push
1329   #pragma anon_unions
1330 #elif defined(__CWCC__)
1331   #pragma push
1332   #pragma cpp_extensions on
1333 #elif defined(__GNUC__)
1334   /* anonymous unions are enabled by default */
1335 #elif defined(__IAR_SYSTEMS_ICC__)
1336   #pragma language=extended
1337 #else
1338   #error Not supported compiler type
1339 #endif
1340
1341 /*******************************************************************************
1342  * hw_crc_t - module struct
1343  ******************************************************************************/
1344 /*!
1345  * @brief All CRC module registers.
1346  */
1347 #pragma pack(1)
1348 typedef struct _hw_crc
1349 {
1350     union {
1351         struct {
1352             __IO hw_crc_datal_t DATAL;     /*!< [0x0] CRC_DATAL register. */
1353             __IO hw_crc_datah_t DATAH;     /*!< [0x2] CRC_DATAH register. */
1354         } ACCESS16BIT;
1355         struct {
1356             __IO hw_crc_datall_t DATALL;   /*!< [0x0] CRC_DATALL register. */
1357             __IO hw_crc_datalu_t DATALU;   /*!< [0x1] CRC_DATALU register. */
1358             __IO hw_crc_datahl_t DATAHL;   /*!< [0x2] CRC_DATAHL register. */
1359             __IO hw_crc_datahu_t DATAHU;   /*!< [0x3] CRC_DATAHU register. */
1360         } ACCESS8BIT;
1361         __IO hw_crc_data_t DATA;           /*!< [0x0] CRC Data register */
1362     };
1363     union {
1364         __IO hw_crc_gpoly_t GPOLY;         /*!< [0x4] CRC Polynomial register */
1365         struct {
1366             __IO hw_crc_gpolyl_t GPOLYL;   /*!< [0x4] CRC_GPOLYL register. */
1367             __IO hw_crc_gpolyh_t GPOLYH;   /*!< [0x6] CRC_GPOLYH register. */
1368         } GPOLY_ACCESS16BIT;
1369         struct {
1370             __IO hw_crc_gpolyll_t GPOLYLL; /*!< [0x4] CRC_GPOLYLL register. */
1371             __IO hw_crc_gpolylu_t GPOLYLU; /*!< [0x5] CRC_GPOLYLU register. */
1372             __IO hw_crc_gpolyhl_t GPOLYHL; /*!< [0x6] CRC_GPOLYHL register. */
1373             __IO hw_crc_gpolyhu_t GPOLYHU; /*!< [0x7] CRC_GPOLYHU register. */
1374         } GPOLY_ACCESS8BIT;
1375     };
1376     union {
1377         __IO hw_crc_ctrl_t CTRL;           /*!< [0x8] CRC Control register */
1378         struct {
1379             uint8_t _reserved0[3];
1380             __IO hw_crc_ctrlhu_t CTRLHU;   /*!< [0xB] CRC_CTRLHU register. */
1381         } CTRL_ACCESS8BIT;
1382     };
1383 } hw_crc_t;
1384 #pragma pack()
1385
1386 /*! @brief Macro to access all CRC registers. */
1387 /*! @param x CRC module instance base address. */
1388 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
1389  *     use the '&' operator, like <code>&HW_CRC(CRC_BASE)</code>. */
1390 #define HW_CRC(x)      (*(hw_crc_t *)(x))
1391
1392 /*
1393 ** End of section using anonymous unions
1394 */
1395
1396 #if defined(__ARMCC_VERSION)
1397   #pragma pop
1398 #elif defined(__CWCC__)
1399   #pragma pop
1400 #elif defined(__GNUC__)
1401   /* leave anonymous unions enabled */
1402 #elif defined(__IAR_SYSTEMS_ICC__)
1403   #pragma language=default
1404 #else
1405   #error Not supported compiler type
1406 #endif
1407
1408 #endif /* __HW_CRC_REGISTERS_H__ */
1409 /* EOF */