tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_dac.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
   9 **     Version:             rev. 2.5, 2014-02-10
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-08-12)
  48 **         Initial version.
  49 **     - rev. 2.0 (2013-10-29)
  50 **         Register accessor macros added to the memory map.
  51 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  52 **         Startup file for gcc has been updated according to CMSIS 3.2.
  53 **         System initialization updated.
  54 **         MCG - registers updated.
  55 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-09)
  59 **         DMA - EARS register removed.
  60 **         AIPS0, AIPS1 - MPRA register updated.
  61 **     - rev. 2.3 (2014-01-24)
  62 **         Update according to reference manual rev. 2
  63 **         ENET, MCG, MCM, SIM, USB - registers updated
  64 **     - rev. 2.4 (2014-02-10)
  65 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  66 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  67 **     - rev. 2.5 (2014-02-10)
  68 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  69 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  70 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  71 **
  72 ** ###################################################################
  73 */
  74
  75 /*
  76  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  77  *
  78  * This file was generated automatically and any changes may be lost.
  79  */
  80 #ifndef __HW_DAC_REGISTERS_H__
  81 #define __HW_DAC_REGISTERS_H__
  82
  83 #include "MK64F12.h"
  84 #include "fsl_bitaccess.h"
  85
  86 /*
  87  * MK64F12 DAC
  88  *
  89  * 12-Bit Digital-to-Analog Converter
  90  *
  91  * Registers defined in this header file:
  92  * - HW_DAC_DATnL - DAC Data Low Register
  93  * - HW_DAC_DATnH - DAC Data High Register
  94  * - HW_DAC_SR - DAC Status Register
  95  * - HW_DAC_C0 - DAC Control Register
  96  * - HW_DAC_C1 - DAC Control Register 1
  97  * - HW_DAC_C2 - DAC Control Register 2
  98  *
  99  * - hw_dac_t - Struct containing all module registers.
 100  */
 101
 102 #define HW_DAC_INSTANCE_COUNT (2U) /*!< Number of instances of the DAC module. */
 103 #define HW_DAC0 (0U) /*!< Instance number for DAC0. */
 104 #define HW_DAC1 (1U) /*!< Instance number for DAC1. */
 105
 106 /*******************************************************************************
 107  * HW_DAC_DATnL - DAC Data Low Register
 108  ******************************************************************************/
 109
 110 /*!
 111  * @brief HW_DAC_DATnL - DAC Data Low Register (RW)
 112  *
 113  * Reset value: 0x00U
 114  */
 115 typedef union _hw_dac_datnl
 116 {
 117     uint8_t U;
 118     struct _hw_dac_datnl_bitfields
 119     {
 120         uint8_t DATA0 : 8;             /*!< [7:0]  */
 121     } B;
 122 } hw_dac_datnl_t;
 123
 124 /*!
 125  * @name Constants and macros for entire DAC_DATnL register
 126  */
 127 /*@{*/
 128 #define HW_DAC_DATnL_COUNT (16U)
 129
 130 #define HW_DAC_DATnL_ADDR(x, n)  ((x) + 0x0U + (0x2U * (n)))
 131
 132 #define HW_DAC_DATnL(x, n)       (*(__IO hw_dac_datnl_t *) HW_DAC_DATnL_ADDR(x, n))
 133 #define HW_DAC_DATnL_RD(x, n)    (HW_DAC_DATnL(x, n).U)
 134 #define HW_DAC_DATnL_WR(x, n, v) (HW_DAC_DATnL(x, n).U = (v))
 135 #define HW_DAC_DATnL_SET(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) |  (v)))
 136 #define HW_DAC_DATnL_CLR(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) & ~(v)))
 137 #define HW_DAC_DATnL_TOG(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) ^  (v)))
 138 /*@}*/
 139
 140 /*
 141  * Constants & macros for individual DAC_DATnL bitfields
 142  */
 143
 144 /*!
 145  * @name Register DAC_DATnL, field DATA0[7:0] (RW)
 146  *
 147  * When the DAC buffer is not enabled, DATA[11:0] controls the output voltage
 148  * based on the following formula: V out = V in * (1 + DACDAT0[11:0])/4096 When the
 149  * DAC buffer is enabled, DATA is mapped to the 16-word buffer.
 150  */
 151 /*@{*/
 152 #define BP_DAC_DATnL_DATA0   (0U)          /*!< Bit position for DAC_DATnL_DATA0. */
 153 #define BM_DAC_DATnL_DATA0   (0xFFU)       /*!< Bit mask for DAC_DATnL_DATA0. */
 154 #define BS_DAC_DATnL_DATA0   (8U)          /*!< Bit field size in bits for DAC_DATnL_DATA0. */
 155
 156 /*! @brief Read current value of the DAC_DATnL_DATA0 field. */
 157 #define BR_DAC_DATnL_DATA0(x, n) (HW_DAC_DATnL(x, n).U)
 158
 159 /*! @brief Format value for bitfield DAC_DATnL_DATA0. */
 160 #define BF_DAC_DATnL_DATA0(v) ((uint8_t)((uint8_t)(v) << BP_DAC_DATnL_DATA0) & BM_DAC_DATnL_DATA0)
 161
 162 /*! @brief Set the DATA0 field to a new value. */
 163 #define BW_DAC_DATnL_DATA0(x, n, v) (HW_DAC_DATnL_WR(x, n, v))
 164 /*@}*/
 165 /*******************************************************************************
 166  * HW_DAC_DATnH - DAC Data High Register
 167  ******************************************************************************/
 168
 169 /*!
 170  * @brief HW_DAC_DATnH - DAC Data High Register (RW)
 171  *
 172  * Reset value: 0x00U
 173  */
 174 typedef union _hw_dac_datnh
 175 {
 176     uint8_t U;
 177     struct _hw_dac_datnh_bitfields
 178     {
 179         uint8_t DATA1 : 4;             /*!< [3:0]  */
 180         uint8_t RESERVED0 : 4;         /*!< [7:4]  */
 181     } B;
 182 } hw_dac_datnh_t;
 183
 184 /*!
 185  * @name Constants and macros for entire DAC_DATnH register
 186  */
 187 /*@{*/
 188 #define HW_DAC_DATnH_COUNT (16U)
 189
 190 #define HW_DAC_DATnH_ADDR(x, n)  ((x) + 0x1U + (0x2U * (n)))
 191
 192 #define HW_DAC_DATnH(x, n)       (*(__IO hw_dac_datnh_t *) HW_DAC_DATnH_ADDR(x, n))
 193 #define HW_DAC_DATnH_RD(x, n)    (HW_DAC_DATnH(x, n).U)
 194 #define HW_DAC_DATnH_WR(x, n, v) (HW_DAC_DATnH(x, n).U = (v))
 195 #define HW_DAC_DATnH_SET(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) |  (v)))
 196 #define HW_DAC_DATnH_CLR(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) & ~(v)))
 197 #define HW_DAC_DATnH_TOG(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) ^  (v)))
 198 /*@}*/
 199
 200 /*
 201  * Constants & macros for individual DAC_DATnH bitfields
 202  */
 203
 204 /*!
 205  * @name Register DAC_DATnH, field DATA1[3:0] (RW)
 206  *
 207  * When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage
 208  * based on the following formula. V out = V in * (1 + DACDAT0[11:0])/4096 When the
 209  * DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer.
 210  */
 211 /*@{*/
 212 #define BP_DAC_DATnH_DATA1   (0U)          /*!< Bit position for DAC_DATnH_DATA1. */
 213 #define BM_DAC_DATnH_DATA1   (0x0FU)       /*!< Bit mask for DAC_DATnH_DATA1. */
 214 #define BS_DAC_DATnH_DATA1   (4U)          /*!< Bit field size in bits for DAC_DATnH_DATA1. */
 215
 216 /*! @brief Read current value of the DAC_DATnH_DATA1 field. */
 217 #define BR_DAC_DATnH_DATA1(x, n) (HW_DAC_DATnH(x, n).B.DATA1)
 218
 219 /*! @brief Format value for bitfield DAC_DATnH_DATA1. */
 220 #define BF_DAC_DATnH_DATA1(v) ((uint8_t)((uint8_t)(v) << BP_DAC_DATnH_DATA1) & BM_DAC_DATnH_DATA1)
 221
 222 /*! @brief Set the DATA1 field to a new value. */
 223 #define BW_DAC_DATnH_DATA1(x, n, v) (HW_DAC_DATnH_WR(x, n, (HW_DAC_DATnH_RD(x, n) & ~BM_DAC_DATnH_DATA1) | BF_DAC_DATnH_DATA1(v)))
 224 /*@}*/
 225
 226 /*******************************************************************************
 227  * HW_DAC_SR - DAC Status Register
 228  ******************************************************************************/
 229
 230 /*!
 231  * @brief HW_DAC_SR - DAC Status Register (RW)
 232  *
 233  * Reset value: 0x02U
 234  *
 235  * If DMA is enabled, the flags can be cleared automatically by DMA when the DMA
 236  * request is done. Writing 0 to a field clears it whereas writing 1 has no
 237  * effect. After reset, DACBFRPTF is set and can be cleared by software, if needed.
 238  * The flags are set only when the data buffer status is changed. Do not use
 239  * 32/16-bit accesses to this register.
 240  */
 241 typedef union _hw_dac_sr
 242 {
 243     uint8_t U;
 244     struct _hw_dac_sr_bitfields
 245     {
 246         uint8_t DACBFRPBF : 1;         /*!< [0] DAC Buffer Read Pointer Bottom
 247                                         * Position Flag */
 248         uint8_t DACBFRPTF : 1;         /*!< [1] DAC Buffer Read Pointer Top Position
 249                                         * Flag */
 250         uint8_t DACBFWMF : 1;          /*!< [2] DAC Buffer Watermark Flag */
 251         uint8_t RESERVED0 : 5;         /*!< [7:3]  */
 252     } B;
 253 } hw_dac_sr_t;
 254
 255 /*!
 256  * @name Constants and macros for entire DAC_SR register
 257  */
 258 /*@{*/
 259 #define HW_DAC_SR_ADDR(x)        ((x) + 0x20U)
 260
 261 #define HW_DAC_SR(x)             (*(__IO hw_dac_sr_t *) HW_DAC_SR_ADDR(x))
 262 #define HW_DAC_SR_RD(x)          (HW_DAC_SR(x).U)
 263 #define HW_DAC_SR_WR(x, v)       (HW_DAC_SR(x).U = (v))
 264 #define HW_DAC_SR_SET(x, v)      (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) |  (v)))
 265 #define HW_DAC_SR_CLR(x, v)      (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) & ~(v)))
 266 #define HW_DAC_SR_TOG(x, v)      (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) ^  (v)))
 267 /*@}*/
 268
 269 /*
 270  * Constants & macros for individual DAC_SR bitfields
 271  */
 272
 273 /*!
 274  * @name Register DAC_SR, field DACBFRPBF[0] (RW)
 275  *
 276  * Values:
 277  * - 0 - The DAC buffer read pointer is not equal to C2[DACBFUP].
 278  * - 1 - The DAC buffer read pointer is equal to C2[DACBFUP].
 279  */
 280 /*@{*/
 281 #define BP_DAC_SR_DACBFRPBF  (0U)          /*!< Bit position for DAC_SR_DACBFRPBF. */
 282 #define BM_DAC_SR_DACBFRPBF  (0x01U)       /*!< Bit mask for DAC_SR_DACBFRPBF. */
 283 #define BS_DAC_SR_DACBFRPBF  (1U)          /*!< Bit field size in bits for DAC_SR_DACBFRPBF. */
 284
 285 /*! @brief Read current value of the DAC_SR_DACBFRPBF field. */
 286 #define BR_DAC_SR_DACBFRPBF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPBF))
 287
 288 /*! @brief Format value for bitfield DAC_SR_DACBFRPBF. */
 289 #define BF_DAC_SR_DACBFRPBF(v) ((uint8_t)((uint8_t)(v) << BP_DAC_SR_DACBFRPBF) & BM_DAC_SR_DACBFRPBF)
 290
 291 /*! @brief Set the DACBFRPBF field to a new value. */
 292 #define BW_DAC_SR_DACBFRPBF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPBF) = (v))
 293 /*@}*/
 294
 295 /*!
 296  * @name Register DAC_SR, field DACBFRPTF[1] (RW)
 297  *
 298  * Values:
 299  * - 0 - The DAC buffer read pointer is not zero.
 300  * - 1 - The DAC buffer read pointer is zero.
 301  */
 302 /*@{*/
 303 #define BP_DAC_SR_DACBFRPTF  (1U)          /*!< Bit position for DAC_SR_DACBFRPTF. */
 304 #define BM_DAC_SR_DACBFRPTF  (0x02U)       /*!< Bit mask for DAC_SR_DACBFRPTF. */
 305 #define BS_DAC_SR_DACBFRPTF  (1U)          /*!< Bit field size in bits for DAC_SR_DACBFRPTF. */
 306
 307 /*! @brief Read current value of the DAC_SR_DACBFRPTF field. */
 308 #define BR_DAC_SR_DACBFRPTF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPTF))
 309
 310 /*! @brief Format value for bitfield DAC_SR_DACBFRPTF. */
 311 #define BF_DAC_SR_DACBFRPTF(v) ((uint8_t)((uint8_t)(v) << BP_DAC_SR_DACBFRPTF) & BM_DAC_SR_DACBFRPTF)
 312
 313 /*! @brief Set the DACBFRPTF field to a new value. */
 314 #define BW_DAC_SR_DACBFRPTF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPTF) = (v))
 315 /*@}*/
 316
 317 /*!
 318  * @name Register DAC_SR, field DACBFWMF[2] (RW)
 319  *
 320  * Values:
 321  * - 0 - The DAC buffer read pointer has not reached the watermark level.
 322  * - 1 - The DAC buffer read pointer has reached the watermark level.
 323  */
 324 /*@{*/
 325 #define BP_DAC_SR_DACBFWMF   (2U)          /*!< Bit position for DAC_SR_DACBFWMF. */
 326 #define BM_DAC_SR_DACBFWMF   (0x04U)       /*!< Bit mask for DAC_SR_DACBFWMF. */
 327 #define BS_DAC_SR_DACBFWMF   (1U)          /*!< Bit field size in bits for DAC_SR_DACBFWMF. */
 328
 329 /*! @brief Read current value of the DAC_SR_DACBFWMF field. */
 330 #define BR_DAC_SR_DACBFWMF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFWMF))
 331
 332 /*! @brief Format value for bitfield DAC_SR_DACBFWMF. */
 333 #define BF_DAC_SR_DACBFWMF(v) ((uint8_t)((uint8_t)(v) << BP_DAC_SR_DACBFWMF) & BM_DAC_SR_DACBFWMF)
 334
 335 /*! @brief Set the DACBFWMF field to a new value. */
 336 #define BW_DAC_SR_DACBFWMF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFWMF) = (v))
 337 /*@}*/
 338
 339 /*******************************************************************************
 340  * HW_DAC_C0 - DAC Control Register
 341  ******************************************************************************/
 342
 343 /*!
 344  * @brief HW_DAC_C0 - DAC Control Register (RW)
 345  *
 346  * Reset value: 0x00U
 347  *
 348  * Do not use 32- or 16-bit accesses to this register.
 349  */
 350 typedef union _hw_dac_c0
 351 {
 352     uint8_t U;
 353     struct _hw_dac_c0_bitfields
 354     {
 355         uint8_t DACBBIEN : 1;          /*!< [0] DAC Buffer Read Pointer Bottom Flag
 356                                         * Interrupt Enable */
 357         uint8_t DACBTIEN : 1;          /*!< [1] DAC Buffer Read Pointer Top Flag
 358                                         * Interrupt Enable */
 359         uint8_t DACBWIEN : 1;          /*!< [2] DAC Buffer Watermark Interrupt Enable
 360                                         * */
 361         uint8_t LPEN : 1;              /*!< [3] DAC Low Power Control */
 362         uint8_t DACSWTRG : 1;          /*!< [4] DAC Software Trigger */
 363         uint8_t DACTRGSEL : 1;         /*!< [5] DAC Trigger Select */
 364         uint8_t DACRFS : 1;            /*!< [6] DAC Reference Select */
 365         uint8_t DACEN : 1;             /*!< [7] DAC Enable */
 366     } B;
 367 } hw_dac_c0_t;
 368
 369 /*!
 370  * @name Constants and macros for entire DAC_C0 register
 371  */
 372 /*@{*/
 373 #define HW_DAC_C0_ADDR(x)        ((x) + 0x21U)
 374
 375 #define HW_DAC_C0(x)             (*(__IO hw_dac_c0_t *) HW_DAC_C0_ADDR(x))
 376 #define HW_DAC_C0_RD(x)          (HW_DAC_C0(x).U)
 377 #define HW_DAC_C0_WR(x, v)       (HW_DAC_C0(x).U = (v))
 378 #define HW_DAC_C0_SET(x, v)      (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) |  (v)))
 379 #define HW_DAC_C0_CLR(x, v)      (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) & ~(v)))
 380 #define HW_DAC_C0_TOG(x, v)      (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) ^  (v)))
 381 /*@}*/
 382
 383 /*
 384  * Constants & macros for individual DAC_C0 bitfields
 385  */
 386
 387 /*!
 388  * @name Register DAC_C0, field DACBBIEN[0] (RW)
 389  *
 390  * Values:
 391  * - 0 - The DAC buffer read pointer bottom flag interrupt is disabled.
 392  * - 1 - The DAC buffer read pointer bottom flag interrupt is enabled.
 393  */
 394 /*@{*/
 395 #define BP_DAC_C0_DACBBIEN   (0U)          /*!< Bit position for DAC_C0_DACBBIEN. */
 396 #define BM_DAC_C0_DACBBIEN   (0x01U)       /*!< Bit mask for DAC_C0_DACBBIEN. */
 397 #define BS_DAC_C0_DACBBIEN   (1U)          /*!< Bit field size in bits for DAC_C0_DACBBIEN. */
 398
 399 /*! @brief Read current value of the DAC_C0_DACBBIEN field. */
 400 #define BR_DAC_C0_DACBBIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBBIEN))
 401
 402 /*! @brief Format value for bitfield DAC_C0_DACBBIEN. */
 403 #define BF_DAC_C0_DACBBIEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACBBIEN) & BM_DAC_C0_DACBBIEN)
 404
 405 /*! @brief Set the DACBBIEN field to a new value. */
 406 #define BW_DAC_C0_DACBBIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBBIEN) = (v))
 407 /*@}*/
 408
 409 /*!
 410  * @name Register DAC_C0, field DACBTIEN[1] (RW)
 411  *
 412  * Values:
 413  * - 0 - The DAC buffer read pointer top flag interrupt is disabled.
 414  * - 1 - The DAC buffer read pointer top flag interrupt is enabled.
 415  */
 416 /*@{*/
 417 #define BP_DAC_C0_DACBTIEN   (1U)          /*!< Bit position for DAC_C0_DACBTIEN. */
 418 #define BM_DAC_C0_DACBTIEN   (0x02U)       /*!< Bit mask for DAC_C0_DACBTIEN. */
 419 #define BS_DAC_C0_DACBTIEN   (1U)          /*!< Bit field size in bits for DAC_C0_DACBTIEN. */
 420
 421 /*! @brief Read current value of the DAC_C0_DACBTIEN field. */
 422 #define BR_DAC_C0_DACBTIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBTIEN))
 423
 424 /*! @brief Format value for bitfield DAC_C0_DACBTIEN. */
 425 #define BF_DAC_C0_DACBTIEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACBTIEN) & BM_DAC_C0_DACBTIEN)
 426
 427 /*! @brief Set the DACBTIEN field to a new value. */
 428 #define BW_DAC_C0_DACBTIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBTIEN) = (v))
 429 /*@}*/
 430
 431 /*!
 432  * @name Register DAC_C0, field DACBWIEN[2] (RW)
 433  *
 434  * Values:
 435  * - 0 - The DAC buffer watermark interrupt is disabled.
 436  * - 1 - The DAC buffer watermark interrupt is enabled.
 437  */
 438 /*@{*/
 439 #define BP_DAC_C0_DACBWIEN   (2U)          /*!< Bit position for DAC_C0_DACBWIEN. */
 440 #define BM_DAC_C0_DACBWIEN   (0x04U)       /*!< Bit mask for DAC_C0_DACBWIEN. */
 441 #define BS_DAC_C0_DACBWIEN   (1U)          /*!< Bit field size in bits for DAC_C0_DACBWIEN. */
 442
 443 /*! @brief Read current value of the DAC_C0_DACBWIEN field. */
 444 #define BR_DAC_C0_DACBWIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBWIEN))
 445
 446 /*! @brief Format value for bitfield DAC_C0_DACBWIEN. */
 447 #define BF_DAC_C0_DACBWIEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACBWIEN) & BM_DAC_C0_DACBWIEN)
 448
 449 /*! @brief Set the DACBWIEN field to a new value. */
 450 #define BW_DAC_C0_DACBWIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBWIEN) = (v))
 451 /*@}*/
 452
 453 /*!
 454  * @name Register DAC_C0, field LPEN[3] (RW)
 455  *
 456  * See the 12-bit DAC electrical characteristics of the device data sheet for
 457  * details on the impact of the modes below.
 458  *
 459  * Values:
 460  * - 0 - High-Power mode
 461  * - 1 - Low-Power mode
 462  */
 463 /*@{*/
 464 #define BP_DAC_C0_LPEN       (3U)          /*!< Bit position for DAC_C0_LPEN. */
 465 #define BM_DAC_C0_LPEN       (0x08U)       /*!< Bit mask for DAC_C0_LPEN. */
 466 #define BS_DAC_C0_LPEN       (1U)          /*!< Bit field size in bits for DAC_C0_LPEN. */
 467
 468 /*! @brief Read current value of the DAC_C0_LPEN field. */
 469 #define BR_DAC_C0_LPEN(x)    (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_LPEN))
 470
 471 /*! @brief Format value for bitfield DAC_C0_LPEN. */
 472 #define BF_DAC_C0_LPEN(v)    ((uint8_t)((uint8_t)(v) << BP_DAC_C0_LPEN) & BM_DAC_C0_LPEN)
 473
 474 /*! @brief Set the LPEN field to a new value. */
 475 #define BW_DAC_C0_LPEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_LPEN) = (v))
 476 /*@}*/
 477
 478 /*!
 479  * @name Register DAC_C0, field DACSWTRG[4] (WORZ)
 480  *
 481  * Active high. This is a write-only field, which always reads 0. If DAC
 482  * software trigger is selected and buffer is enabled, writing 1 to this field will
 483  * advance the buffer read pointer once.
 484  *
 485  * Values:
 486  * - 0 - The DAC soft trigger is not valid.
 487  * - 1 - The DAC soft trigger is valid.
 488  */
 489 /*@{*/
 490 #define BP_DAC_C0_DACSWTRG   (4U)          /*!< Bit position for DAC_C0_DACSWTRG. */
 491 #define BM_DAC_C0_DACSWTRG   (0x10U)       /*!< Bit mask for DAC_C0_DACSWTRG. */
 492 #define BS_DAC_C0_DACSWTRG   (1U)          /*!< Bit field size in bits for DAC_C0_DACSWTRG. */
 493
 494 /*! @brief Format value for bitfield DAC_C0_DACSWTRG. */
 495 #define BF_DAC_C0_DACSWTRG(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACSWTRG) & BM_DAC_C0_DACSWTRG)
 496
 497 /*! @brief Set the DACSWTRG field to a new value. */
 498 #define BW_DAC_C0_DACSWTRG(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACSWTRG) = (v))
 499 /*@}*/
 500
 501 /*!
 502  * @name Register DAC_C0, field DACTRGSEL[5] (RW)
 503  *
 504  * Values:
 505  * - 0 - The DAC hardware trigger is selected.
 506  * - 1 - The DAC software trigger is selected.
 507  */
 508 /*@{*/
 509 #define BP_DAC_C0_DACTRGSEL  (5U)          /*!< Bit position for DAC_C0_DACTRGSEL. */
 510 #define BM_DAC_C0_DACTRGSEL  (0x20U)       /*!< Bit mask for DAC_C0_DACTRGSEL. */
 511 #define BS_DAC_C0_DACTRGSEL  (1U)          /*!< Bit field size in bits for DAC_C0_DACTRGSEL. */
 512
 513 /*! @brief Read current value of the DAC_C0_DACTRGSEL field. */
 514 #define BR_DAC_C0_DACTRGSEL(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACTRGSEL))
 515
 516 /*! @brief Format value for bitfield DAC_C0_DACTRGSEL. */
 517 #define BF_DAC_C0_DACTRGSEL(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACTRGSEL) & BM_DAC_C0_DACTRGSEL)
 518
 519 /*! @brief Set the DACTRGSEL field to a new value. */
 520 #define BW_DAC_C0_DACTRGSEL(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACTRGSEL) = (v))
 521 /*@}*/
 522
 523 /*!
 524  * @name Register DAC_C0, field DACRFS[6] (RW)
 525  *
 526  * Values:
 527  * - 0 - The DAC selects DACREF_1 as the reference voltage.
 528  * - 1 - The DAC selects DACREF_2 as the reference voltage.
 529  */
 530 /*@{*/
 531 #define BP_DAC_C0_DACRFS     (6U)          /*!< Bit position for DAC_C0_DACRFS. */
 532 #define BM_DAC_C0_DACRFS     (0x40U)       /*!< Bit mask for DAC_C0_DACRFS. */
 533 #define BS_DAC_C0_DACRFS     (1U)          /*!< Bit field size in bits for DAC_C0_DACRFS. */
 534
 535 /*! @brief Read current value of the DAC_C0_DACRFS field. */
 536 #define BR_DAC_C0_DACRFS(x)  (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACRFS))
 537
 538 /*! @brief Format value for bitfield DAC_C0_DACRFS. */
 539 #define BF_DAC_C0_DACRFS(v)  ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACRFS) & BM_DAC_C0_DACRFS)
 540
 541 /*! @brief Set the DACRFS field to a new value. */
 542 #define BW_DAC_C0_DACRFS(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACRFS) = (v))
 543 /*@}*/
 544
 545 /*!
 546  * @name Register DAC_C0, field DACEN[7] (RW)
 547  *
 548  * Starts the Programmable Reference Generator operation.
 549  *
 550  * Values:
 551  * - 0 - The DAC system is disabled.
 552  * - 1 - The DAC system is enabled.
 553  */
 554 /*@{*/
 555 #define BP_DAC_C0_DACEN      (7U)          /*!< Bit position for DAC_C0_DACEN. */
 556 #define BM_DAC_C0_DACEN      (0x80U)       /*!< Bit mask for DAC_C0_DACEN. */
 557 #define BS_DAC_C0_DACEN      (1U)          /*!< Bit field size in bits for DAC_C0_DACEN. */
 558
 559 /*! @brief Read current value of the DAC_C0_DACEN field. */
 560 #define BR_DAC_C0_DACEN(x)   (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACEN))
 561
 562 /*! @brief Format value for bitfield DAC_C0_DACEN. */
 563 #define BF_DAC_C0_DACEN(v)   ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACEN) & BM_DAC_C0_DACEN)
 564
 565 /*! @brief Set the DACEN field to a new value. */
 566 #define BW_DAC_C0_DACEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACEN) = (v))
 567 /*@}*/
 568
 569 /*******************************************************************************
 570  * HW_DAC_C1 - DAC Control Register 1
 571  ******************************************************************************/
 572
 573 /*!
 574  * @brief HW_DAC_C1 - DAC Control Register 1 (RW)
 575  *
 576  * Reset value: 0x00U
 577  *
 578  * Do not use 32- or 16-bit accesses to this register.
 579  */
 580 typedef union _hw_dac_c1
 581 {
 582     uint8_t U;
 583     struct _hw_dac_c1_bitfields
 584     {
 585         uint8_t DACBFEN : 1;           /*!< [0] DAC Buffer Enable */
 586         uint8_t DACBFMD : 2;           /*!< [2:1] DAC Buffer Work Mode Select */
 587         uint8_t DACBFWM : 2;           /*!< [4:3] DAC Buffer Watermark Select */
 588         uint8_t RESERVED0 : 2;         /*!< [6:5]  */
 589         uint8_t DMAEN : 1;             /*!< [7] DMA Enable Select */
 590     } B;
 591 } hw_dac_c1_t;
 592
 593 /*!
 594  * @name Constants and macros for entire DAC_C1 register
 595  */
 596 /*@{*/
 597 #define HW_DAC_C1_ADDR(x)        ((x) + 0x22U)
 598
 599 #define HW_DAC_C1(x)             (*(__IO hw_dac_c1_t *) HW_DAC_C1_ADDR(x))
 600 #define HW_DAC_C1_RD(x)          (HW_DAC_C1(x).U)
 601 #define HW_DAC_C1_WR(x, v)       (HW_DAC_C1(x).U = (v))
 602 #define HW_DAC_C1_SET(x, v)      (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) |  (v)))
 603 #define HW_DAC_C1_CLR(x, v)      (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) & ~(v)))
 604 #define HW_DAC_C1_TOG(x, v)      (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) ^  (v)))
 605 /*@}*/
 606
 607 /*
 608  * Constants & macros for individual DAC_C1 bitfields
 609  */
 610
 611 /*!
 612  * @name Register DAC_C1, field DACBFEN[0] (RW)
 613  *
 614  * Values:
 615  * - 0 - Buffer read pointer is disabled. The converted data is always the first
 616  *     word of the buffer.
 617  * - 1 - Buffer read pointer is enabled. The converted data is the word that the
 618  *     read pointer points to. It means converted data can be from any word of
 619  *     the buffer.
 620  */
 621 /*@{*/
 622 #define BP_DAC_C1_DACBFEN    (0U)          /*!< Bit position for DAC_C1_DACBFEN. */
 623 #define BM_DAC_C1_DACBFEN    (0x01U)       /*!< Bit mask for DAC_C1_DACBFEN. */
 624 #define BS_DAC_C1_DACBFEN    (1U)          /*!< Bit field size in bits for DAC_C1_DACBFEN. */
 625
 626 /*! @brief Read current value of the DAC_C1_DACBFEN field. */
 627 #define BR_DAC_C1_DACBFEN(x) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DACBFEN))
 628
 629 /*! @brief Format value for bitfield DAC_C1_DACBFEN. */
 630 #define BF_DAC_C1_DACBFEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DACBFEN) & BM_DAC_C1_DACBFEN)
 631
 632 /*! @brief Set the DACBFEN field to a new value. */
 633 #define BW_DAC_C1_DACBFEN(x, v) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DACBFEN) = (v))
 634 /*@}*/
 635
 636 /*!
 637  * @name Register DAC_C1, field DACBFMD[2:1] (RW)
 638  *
 639  * Values:
 640  * - 00 - Normal mode
 641  * - 01 - Swing mode
 642  * - 10 - One-Time Scan mode
 643  * - 11 - Reserved
 644  */
 645 /*@{*/
 646 #define BP_DAC_C1_DACBFMD    (1U)          /*!< Bit position for DAC_C1_DACBFMD. */
 647 #define BM_DAC_C1_DACBFMD    (0x06U)       /*!< Bit mask for DAC_C1_DACBFMD. */
 648 #define BS_DAC_C1_DACBFMD    (2U)          /*!< Bit field size in bits for DAC_C1_DACBFMD. */
 649
 650 /*! @brief Read current value of the DAC_C1_DACBFMD field. */
 651 #define BR_DAC_C1_DACBFMD(x) (HW_DAC_C1(x).B.DACBFMD)
 652
 653 /*! @brief Format value for bitfield DAC_C1_DACBFMD. */
 654 #define BF_DAC_C1_DACBFMD(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DACBFMD) & BM_DAC_C1_DACBFMD)
 655
 656 /*! @brief Set the DACBFMD field to a new value. */
 657 #define BW_DAC_C1_DACBFMD(x, v) (HW_DAC_C1_WR(x, (HW_DAC_C1_RD(x) & ~BM_DAC_C1_DACBFMD) | BF_DAC_C1_DACBFMD(v)))
 658 /*@}*/
 659
 660 /*!
 661  * @name Register DAC_C1, field DACBFWM[4:3] (RW)
 662  *
 663  * Controls when SR[DACBFWMF] is set. When the DAC buffer read pointer reaches
 664  * the word defined by this field, which is 1-4 words away from the upper limit
 665  * (DACBUP), SR[DACBFWMF] will be set. This allows user configuration of the
 666  * watermark interrupt.
 667  *
 668  * Values:
 669  * - 00 - 1 word
 670  * - 01 - 2 words
 671  * - 10 - 3 words
 672  * - 11 - 4 words
 673  */
 674 /*@{*/
 675 #define BP_DAC_C1_DACBFWM    (3U)          /*!< Bit position for DAC_C1_DACBFWM. */
 676 #define BM_DAC_C1_DACBFWM    (0x18U)       /*!< Bit mask for DAC_C1_DACBFWM. */
 677 #define BS_DAC_C1_DACBFWM    (2U)          /*!< Bit field size in bits for DAC_C1_DACBFWM. */
 678
 679 /*! @brief Read current value of the DAC_C1_DACBFWM field. */
 680 #define BR_DAC_C1_DACBFWM(x) (HW_DAC_C1(x).B.DACBFWM)
 681
 682 /*! @brief Format value for bitfield DAC_C1_DACBFWM. */
 683 #define BF_DAC_C1_DACBFWM(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DACBFWM) & BM_DAC_C1_DACBFWM)
 684
 685 /*! @brief Set the DACBFWM field to a new value. */
 686 #define BW_DAC_C1_DACBFWM(x, v) (HW_DAC_C1_WR(x, (HW_DAC_C1_RD(x) & ~BM_DAC_C1_DACBFWM) | BF_DAC_C1_DACBFWM(v)))
 687 /*@}*/
 688
 689 /*!
 690  * @name Register DAC_C1, field DMAEN[7] (RW)
 691  *
 692  * Values:
 693  * - 0 - DMA is disabled.
 694  * - 1 - DMA is enabled. When DMA is enabled, the DMA request will be generated
 695  *     by original interrupts. The interrupts will not be presented on this
 696  *     module at the same time.
 697  */
 698 /*@{*/
 699 #define BP_DAC_C1_DMAEN      (7U)          /*!< Bit position for DAC_C1_DMAEN. */
 700 #define BM_DAC_C1_DMAEN      (0x80U)       /*!< Bit mask for DAC_C1_DMAEN. */
 701 #define BS_DAC_C1_DMAEN      (1U)          /*!< Bit field size in bits for DAC_C1_DMAEN. */
 702
 703 /*! @brief Read current value of the DAC_C1_DMAEN field. */
 704 #define BR_DAC_C1_DMAEN(x)   (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DMAEN))
 705
 706 /*! @brief Format value for bitfield DAC_C1_DMAEN. */
 707 #define BF_DAC_C1_DMAEN(v)   ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DMAEN) & BM_DAC_C1_DMAEN)
 708
 709 /*! @brief Set the DMAEN field to a new value. */
 710 #define BW_DAC_C1_DMAEN(x, v) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DMAEN) = (v))
 711 /*@}*/
 712
 713 /*******************************************************************************
 714  * HW_DAC_C2 - DAC Control Register 2
 715  ******************************************************************************/
 716
 717 /*!
 718  * @brief HW_DAC_C2 - DAC Control Register 2 (RW)
 719  *
 720  * Reset value: 0x0FU
 721  */
 722 typedef union _hw_dac_c2
 723 {
 724     uint8_t U;
 725     struct _hw_dac_c2_bitfields
 726     {
 727         uint8_t DACBFUP : 4;           /*!< [3:0] DAC Buffer Upper Limit */
 728         uint8_t DACBFRP : 4;           /*!< [7:4] DAC Buffer Read Pointer */
 729     } B;
 730 } hw_dac_c2_t;
 731
 732 /*!
 733  * @name Constants and macros for entire DAC_C2 register
 734  */
 735 /*@{*/
 736 #define HW_DAC_C2_ADDR(x)        ((x) + 0x23U)
 737
 738 #define HW_DAC_C2(x)             (*(__IO hw_dac_c2_t *) HW_DAC_C2_ADDR(x))
 739 #define HW_DAC_C2_RD(x)          (HW_DAC_C2(x).U)
 740 #define HW_DAC_C2_WR(x, v)       (HW_DAC_C2(x).U = (v))
 741 #define HW_DAC_C2_SET(x, v)      (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) |  (v)))
 742 #define HW_DAC_C2_CLR(x, v)      (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) & ~(v)))
 743 #define HW_DAC_C2_TOG(x, v)      (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) ^  (v)))
 744 /*@}*/
 745
 746 /*
 747  * Constants & macros for individual DAC_C2 bitfields
 748  */
 749
 750 /*!
 751  * @name Register DAC_C2, field DACBFUP[3:0] (RW)
 752  *
 753  * Selects the upper limit of the DAC buffer. The buffer read pointer cannot
 754  * exceed it.
 755  */
 756 /*@{*/
 757 #define BP_DAC_C2_DACBFUP    (0U)          /*!< Bit position for DAC_C2_DACBFUP. */
 758 #define BM_DAC_C2_DACBFUP    (0x0FU)       /*!< Bit mask for DAC_C2_DACBFUP. */
 759 #define BS_DAC_C2_DACBFUP    (4U)          /*!< Bit field size in bits for DAC_C2_DACBFUP. */
 760
 761 /*! @brief Read current value of the DAC_C2_DACBFUP field. */
 762 #define BR_DAC_C2_DACBFUP(x) (HW_DAC_C2(x).B.DACBFUP)
 763
 764 /*! @brief Format value for bitfield DAC_C2_DACBFUP. */
 765 #define BF_DAC_C2_DACBFUP(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C2_DACBFUP) & BM_DAC_C2_DACBFUP)
 766
 767 /*! @brief Set the DACBFUP field to a new value. */
 768 #define BW_DAC_C2_DACBFUP(x, v) (HW_DAC_C2_WR(x, (HW_DAC_C2_RD(x) & ~BM_DAC_C2_DACBFUP) | BF_DAC_C2_DACBFUP(v)))
 769 /*@}*/
 770
 771 /*!
 772  * @name Register DAC_C2, field DACBFRP[7:4] (RW)
 773  *
 774  * Keeps the current value of the buffer read pointer.
 775  */
 776 /*@{*/
 777 #define BP_DAC_C2_DACBFRP    (4U)          /*!< Bit position for DAC_C2_DACBFRP. */
 778 #define BM_DAC_C2_DACBFRP    (0xF0U)       /*!< Bit mask for DAC_C2_DACBFRP. */
 779 #define BS_DAC_C2_DACBFRP    (4U)          /*!< Bit field size in bits for DAC_C2_DACBFRP. */
 780
 781 /*! @brief Read current value of the DAC_C2_DACBFRP field. */
 782 #define BR_DAC_C2_DACBFRP(x) (HW_DAC_C2(x).B.DACBFRP)
 783
 784 /*! @brief Format value for bitfield DAC_C2_DACBFRP. */
 785 #define BF_DAC_C2_DACBFRP(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C2_DACBFRP) & BM_DAC_C2_DACBFRP)
 786
 787 /*! @brief Set the DACBFRP field to a new value. */
 788 #define BW_DAC_C2_DACBFRP(x, v) (HW_DAC_C2_WR(x, (HW_DAC_C2_RD(x) & ~BM_DAC_C2_DACBFRP) | BF_DAC_C2_DACBFRP(v)))
 789 /*@}*/
 790
 791 /*******************************************************************************
 792  * hw_dac_t - module struct
 793  ******************************************************************************/
 794 /*!
 795  * @brief All DAC module registers.
 796  */
 797 #pragma pack(1)
 798 typedef struct _hw_dac
 799 {
 800     struct {
 801         __IO hw_dac_datnl_t DATnL;         /*!< [0x0] DAC Data Low Register */
 802         __IO hw_dac_datnh_t DATnH;         /*!< [0x1] DAC Data High Register */
 803     } DAT[16];
 804     __IO hw_dac_sr_t SR;                   /*!< [0x20] DAC Status Register */
 805     __IO hw_dac_c0_t C0;                   /*!< [0x21] DAC Control Register */
 806     __IO hw_dac_c1_t C1;                   /*!< [0x22] DAC Control Register 1 */
 807     __IO hw_dac_c2_t C2;                   /*!< [0x23] DAC Control Register 2 */
 808 } hw_dac_t;
 809 #pragma pack()
 810
 811 /*! @brief Macro to access all DAC registers. */
 812 /*! @param x DAC module instance base address. */
 813 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
 814  *     use the '&' operator, like <code>&HW_DAC(DAC0_BASE)</code>. */
 815 #define HW_DAC(x)      (*(hw_dac_t *)(x))
 816
 817 #endif /* __HW_DAC_REGISTERS_H__ */
 818 /* EOF */