2 ** ###################################################################
3 ** Compilers: Keil ARM C/C++ Compiler
4 ** Freescale C/C++ for Embedded ARM
6 ** IAR ANSI C/C++ Compiler for ARM
8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
9 ** Version: rev. 2.5, 2014-02-10
13 ** Extension to the CMSIS register access layer header.
15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
16 ** All rights reserved.
18 ** Redistribution and use in source and binary forms, with or without modification,
19 ** are permitted provided that the following conditions are met:
21 ** o Redistributions of source code must retain the above copyright notice, this list
22 ** of conditions and the following disclaimer.
24 ** o Redistributions in binary form must reproduce the above copyright notice, this
25 ** list of conditions and the following disclaimer in the documentation and/or
26 ** other materials provided with the distribution.
28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
29 ** contributors may be used to endorse or promote products derived from this
30 ** software without specific prior written permission.
32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ** http: www.freescale.com
44 ** mail: support@freescale.com
47 ** - rev. 1.0 (2013-08-12)
49 ** - rev. 2.0 (2013-10-29)
50 ** Register accessor macros added to the memory map.
51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
52 ** Startup file for gcc has been updated according to CMSIS 3.2.
53 ** System initialization updated.
54 ** MCG - registers updated.
55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
56 ** - rev. 2.1 (2013-10-30)
57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
58 ** - rev. 2.2 (2013-12-09)
59 ** DMA - EARS register removed.
60 ** AIPS0, AIPS1 - MPRA register updated.
61 ** - rev. 2.3 (2014-01-24)
62 ** Update according to reference manual rev. 2
63 ** ENET, MCG, MCM, SIM, USB - registers updated
64 ** - rev. 2.4 (2014-02-10)
65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
67 ** - rev. 2.5 (2014-02-10)
68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
72 ** ###################################################################
76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
78 * This file was generated automatically and any changes may be lost.
80 #ifndef __HW_DMA_REGISTERS_H__
81 #define __HW_DMA_REGISTERS_H__
84 #include "fsl_bitaccess.h"
89 * Enhanced direct memory access controller
91 * Registers defined in this header file:
92 * - HW_DMA_CR - Control Register
93 * - HW_DMA_ES - Error Status Register
94 * - HW_DMA_ERQ - Enable Request Register
95 * - HW_DMA_EEI - Enable Error Interrupt Register
96 * - HW_DMA_CEEI - Clear Enable Error Interrupt Register
97 * - HW_DMA_SEEI - Set Enable Error Interrupt Register
98 * - HW_DMA_CERQ - Clear Enable Request Register
99 * - HW_DMA_SERQ - Set Enable Request Register
100 * - HW_DMA_CDNE - Clear DONE Status Bit Register
101 * - HW_DMA_SSRT - Set START Bit Register
102 * - HW_DMA_CERR - Clear Error Register
103 * - HW_DMA_CINT - Clear Interrupt Request Register
104 * - HW_DMA_INT - Interrupt Request Register
105 * - HW_DMA_ERR - Error Register
106 * - HW_DMA_HRS - Hardware Request Status Register
107 * - HW_DMA_DCHPRIn - Channel n Priority Register
108 * - HW_DMA_TCDn_SADDR - TCD Source Address
109 * - HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset
110 * - HW_DMA_TCDn_ATTR - TCD Transfer Attributes
111 * - HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)
112 * - HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
113 * - HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
114 * - HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment
115 * - HW_DMA_TCDn_DADDR - TCD Destination Address
116 * - HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset
117 * - HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
118 * - HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
119 * - HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address
120 * - HW_DMA_TCDn_CSR - TCD Control and Status
121 * - HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
122 * - HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
124 * - hw_dma_t - Struct containing all module registers.
127 #define HW_DMA_INSTANCE_COUNT (1U) /*!< Number of instances of the DMA module. */
129 /*******************************************************************************
130 * HW_DMA_CR - Control Register
131 ******************************************************************************/
134 * @brief HW_DMA_CR - Control Register (RW)
136 * Reset value: 0x00000000U
138 * The CR defines the basic operating configuration of the DMA. Arbitration can
139 * be configured to use either a fixed-priority or a round-robin scheme. For
140 * fixed-priority arbitration, the highest priority channel requesting service is
141 * selected to execute. The channel priority registers assign the priorities; see
142 * the DCHPRIn registers. For round-robin arbitration, the channel priorities are
143 * ignored and channels are cycled through (from high to low channel number)
144 * without regard to priority. For correct operation, writes to the CR register must
145 * be performed only when the DMA channels are inactive; that is, when
146 * TCDn_CSR[ACTIVE] bits are cleared. Minor loop offsets are address offset values added to
147 * the final source address (TCDn_SADDR) or destination address (TCDn_DADDR) upon
148 * minor loop completion. When minor loop offsets are enabled, the minor loop
149 * offset (MLOFF) is added to the final source address (TCDn_SADDR), to the final
150 * destination address (TCDn_DADDR), or to both prior to the addresses being
151 * written back into the TCD. If the major loop is complete, the minor loop offset is
152 * ignored and the major loop address offsets (TCDn_SLAST and TCDn_DLAST_SGA) are
153 * used to compute the next TCDn_SADDR and TCDn_DADDR values. When minor loop
154 * mapping is enabled (EMLM is 1), TCDn word2 is redefined. A portion of TCDn word2
155 * is used to specify multiple fields: a source enable bit (SMLOE) to specify
156 * the minor loop offset should be applied to the source address (TCDn_SADDR) upon
157 * minor loop completion, a destination enable bit (DMLOE) to specify the minor
158 * loop offset should be applied to the destination address (TCDn_DADDR) upon
159 * minor loop completion, and the sign extended minor loop offset value (MLOFF). The
160 * same offset value (MLOFF) is used for both source and destination minor loop
161 * offsets. When either minor loop offset is enabled (SMLOE set or DMLOE set), the
162 * NBYTES field is reduced to 10 bits. When both minor loop offsets are disabled
163 * (SMLOE cleared and DMLOE cleared), the NBYTES field is a 30-bit vector. When
164 * minor loop mapping is disabled (EMLM is 0), all 32 bits of TCDn word2 are
165 * assigned to the NBYTES field.
167 typedef union _hw_dma_cr
170 struct _hw_dma_cr_bitfields
172 uint32_t RESERVED0
: 1; /*!< [0] Reserved. */
173 uint32_t EDBG
: 1; /*!< [1] Enable Debug */
174 uint32_t ERCA
: 1; /*!< [2] Enable Round Robin Channel Arbitration */
175 uint32_t RESERVED1
: 1; /*!< [3] Reserved. */
176 uint32_t HOE
: 1; /*!< [4] Halt On Error */
177 uint32_t HALT
: 1; /*!< [5] Halt DMA Operations */
178 uint32_t CLM
: 1; /*!< [6] Continuous Link Mode */
179 uint32_t EMLM
: 1; /*!< [7] Enable Minor Loop Mapping */
180 uint32_t RESERVED2
: 8; /*!< [15:8] */
181 uint32_t ECX
: 1; /*!< [16] Error Cancel Transfer */
182 uint32_t CX
: 1; /*!< [17] Cancel Transfer */
183 uint32_t RESERVED3
: 14; /*!< [31:18] */
188 * @name Constants and macros for entire DMA_CR register
191 #define HW_DMA_CR_ADDR(x) ((x) + 0x0U)
193 #define HW_DMA_CR(x) (*(__IO hw_dma_cr_t *) HW_DMA_CR_ADDR(x))
194 #define HW_DMA_CR_RD(x) (HW_DMA_CR(x).U)
195 #define HW_DMA_CR_WR(x, v) (HW_DMA_CR(x).U = (v))
196 #define HW_DMA_CR_SET(x, v) (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) | (v)))
197 #define HW_DMA_CR_CLR(x, v) (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) & ~(v)))
198 #define HW_DMA_CR_TOG(x, v) (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) ^ (v)))
202 * Constants & macros for individual DMA_CR bitfields
206 * @name Register DMA_CR, field EDBG[1] (RW)
209 * - 0 - When in debug mode, the DMA continues to operate.
210 * - 1 - When in debug mode, the DMA stalls the start of a new channel.
211 * Executing channels are allowed to complete. Channel execution resumes when the
212 * system exits debug mode or the EDBG bit is cleared.
215 #define BP_DMA_CR_EDBG (1U) /*!< Bit position for DMA_CR_EDBG. */
216 #define BM_DMA_CR_EDBG (0x00000002U) /*!< Bit mask for DMA_CR_EDBG. */
217 #define BS_DMA_CR_EDBG (1U) /*!< Bit field size in bits for DMA_CR_EDBG. */
219 /*! @brief Read current value of the DMA_CR_EDBG field. */
220 #define BR_DMA_CR_EDBG(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EDBG))
222 /*! @brief Format value for bitfield DMA_CR_EDBG. */
223 #define BF_DMA_CR_EDBG(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_EDBG) & BM_DMA_CR_EDBG)
225 /*! @brief Set the EDBG field to a new value. */
226 #define BW_DMA_CR_EDBG(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EDBG) = (v))
230 * @name Register DMA_CR, field ERCA[2] (RW)
233 * - 0 - Fixed priority arbitration is used for channel selection .
234 * - 1 - Round robin arbitration is used for channel selection .
237 #define BP_DMA_CR_ERCA (2U) /*!< Bit position for DMA_CR_ERCA. */
238 #define BM_DMA_CR_ERCA (0x00000004U) /*!< Bit mask for DMA_CR_ERCA. */
239 #define BS_DMA_CR_ERCA (1U) /*!< Bit field size in bits for DMA_CR_ERCA. */
241 /*! @brief Read current value of the DMA_CR_ERCA field. */
242 #define BR_DMA_CR_ERCA(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ERCA))
244 /*! @brief Format value for bitfield DMA_CR_ERCA. */
245 #define BF_DMA_CR_ERCA(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_ERCA) & BM_DMA_CR_ERCA)
247 /*! @brief Set the ERCA field to a new value. */
248 #define BW_DMA_CR_ERCA(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ERCA) = (v))
252 * @name Register DMA_CR, field HOE[4] (RW)
255 * - 0 - Normal operation
256 * - 1 - Any error causes the HALT bit to set. Subsequently, all service
257 * requests are ignored until the HALT bit is cleared.
260 #define BP_DMA_CR_HOE (4U) /*!< Bit position for DMA_CR_HOE. */
261 #define BM_DMA_CR_HOE (0x00000010U) /*!< Bit mask for DMA_CR_HOE. */
262 #define BS_DMA_CR_HOE (1U) /*!< Bit field size in bits for DMA_CR_HOE. */
264 /*! @brief Read current value of the DMA_CR_HOE field. */
265 #define BR_DMA_CR_HOE(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HOE))
267 /*! @brief Format value for bitfield DMA_CR_HOE. */
268 #define BF_DMA_CR_HOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_HOE) & BM_DMA_CR_HOE)
270 /*! @brief Set the HOE field to a new value. */
271 #define BW_DMA_CR_HOE(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HOE) = (v))
275 * @name Register DMA_CR, field HALT[5] (RW)
278 * - 0 - Normal operation
279 * - 1 - Stall the start of any new channels. Executing channels are allowed to
280 * complete. Channel execution resumes when this bit is cleared.
283 #define BP_DMA_CR_HALT (5U) /*!< Bit position for DMA_CR_HALT. */
284 #define BM_DMA_CR_HALT (0x00000020U) /*!< Bit mask for DMA_CR_HALT. */
285 #define BS_DMA_CR_HALT (1U) /*!< Bit field size in bits for DMA_CR_HALT. */
287 /*! @brief Read current value of the DMA_CR_HALT field. */
288 #define BR_DMA_CR_HALT(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HALT))
290 /*! @brief Format value for bitfield DMA_CR_HALT. */
291 #define BF_DMA_CR_HALT(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_HALT) & BM_DMA_CR_HALT)
293 /*! @brief Set the HALT field to a new value. */
294 #define BW_DMA_CR_HALT(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HALT) = (v))
298 * @name Register DMA_CR, field CLM[6] (RW)
301 * - 0 - A minor loop channel link made to itself goes through channel
302 * arbitration before being activated again.
303 * - 1 - A minor loop channel link made to itself does not go through channel
304 * arbitration before being activated again. Upon minor loop completion, the
305 * channel activates again if that channel has a minor loop channel link
306 * enabled and the link channel is itself. This effectively applies the minor loop
307 * offsets and restarts the next minor loop.
310 #define BP_DMA_CR_CLM (6U) /*!< Bit position for DMA_CR_CLM. */
311 #define BM_DMA_CR_CLM (0x00000040U) /*!< Bit mask for DMA_CR_CLM. */
312 #define BS_DMA_CR_CLM (1U) /*!< Bit field size in bits for DMA_CR_CLM. */
314 /*! @brief Read current value of the DMA_CR_CLM field. */
315 #define BR_DMA_CR_CLM(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CLM))
317 /*! @brief Format value for bitfield DMA_CR_CLM. */
318 #define BF_DMA_CR_CLM(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_CLM) & BM_DMA_CR_CLM)
320 /*! @brief Set the CLM field to a new value. */
321 #define BW_DMA_CR_CLM(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CLM) = (v))
325 * @name Register DMA_CR, field EMLM[7] (RW)
328 * - 0 - Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
329 * - 1 - Enabled. TCDn.word2 is redefined to include individual enable fields,
330 * an offset field, and the NBYTES field. The individual enable fields allow
331 * the minor loop offset to be applied to the source address, the destination
332 * address, or both. The NBYTES field is reduced when either offset is
336 #define BP_DMA_CR_EMLM (7U) /*!< Bit position for DMA_CR_EMLM. */
337 #define BM_DMA_CR_EMLM (0x00000080U) /*!< Bit mask for DMA_CR_EMLM. */
338 #define BS_DMA_CR_EMLM (1U) /*!< Bit field size in bits for DMA_CR_EMLM. */
340 /*! @brief Read current value of the DMA_CR_EMLM field. */
341 #define BR_DMA_CR_EMLM(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EMLM))
343 /*! @brief Format value for bitfield DMA_CR_EMLM. */
344 #define BF_DMA_CR_EMLM(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_EMLM) & BM_DMA_CR_EMLM)
346 /*! @brief Set the EMLM field to a new value. */
347 #define BW_DMA_CR_EMLM(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EMLM) = (v))
351 * @name Register DMA_CR, field ECX[16] (RW)
354 * - 0 - Normal operation
355 * - 1 - Cancel the remaining data transfer in the same fashion as the CX bit.
356 * Stop the executing channel and force the minor loop to finish. The cancel
357 * takes effect after the last write of the current read/write sequence. The
358 * ECX bit clears itself after the cancel is honored. In addition to
359 * cancelling the transfer, ECX treats the cancel as an error condition, thus updating
360 * the Error Status register (DMAx_ES) and generating an optional error
364 #define BP_DMA_CR_ECX (16U) /*!< Bit position for DMA_CR_ECX. */
365 #define BM_DMA_CR_ECX (0x00010000U) /*!< Bit mask for DMA_CR_ECX. */
366 #define BS_DMA_CR_ECX (1U) /*!< Bit field size in bits for DMA_CR_ECX. */
368 /*! @brief Read current value of the DMA_CR_ECX field. */
369 #define BR_DMA_CR_ECX(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ECX))
371 /*! @brief Format value for bitfield DMA_CR_ECX. */
372 #define BF_DMA_CR_ECX(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_ECX) & BM_DMA_CR_ECX)
374 /*! @brief Set the ECX field to a new value. */
375 #define BW_DMA_CR_ECX(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ECX) = (v))
379 * @name Register DMA_CR, field CX[17] (RW)
382 * - 0 - Normal operation
383 * - 1 - Cancel the remaining data transfer. Stop the executing channel and
384 * force the minor loop to finish. The cancel takes effect after the last write
385 * of the current read/write sequence. The CX bit clears itself after the
386 * cancel has been honored. This cancel retires the channel normally as if the
387 * minor loop was completed.
390 #define BP_DMA_CR_CX (17U) /*!< Bit position for DMA_CR_CX. */
391 #define BM_DMA_CR_CX (0x00020000U) /*!< Bit mask for DMA_CR_CX. */
392 #define BS_DMA_CR_CX (1U) /*!< Bit field size in bits for DMA_CR_CX. */
394 /*! @brief Read current value of the DMA_CR_CX field. */
395 #define BR_DMA_CR_CX(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CX))
397 /*! @brief Format value for bitfield DMA_CR_CX. */
398 #define BF_DMA_CR_CX(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_CX) & BM_DMA_CR_CX)
400 /*! @brief Set the CX field to a new value. */
401 #define BW_DMA_CR_CX(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CX) = (v))
404 /*******************************************************************************
405 * HW_DMA_ES - Error Status Register
406 ******************************************************************************/
409 * @brief HW_DMA_ES - Error Status Register (RO)
411 * Reset value: 0x00000000U
413 * The ES provides information concerning the last recorded channel error.
414 * Channel errors can be caused by: A configuration error, that is: An illegal setting
415 * in the transfer-control descriptor, or An illegal priority register setting
416 * in fixed-arbitration An error termination to a bus master read or write cycle
417 * See the Error Reporting and Handling section for more details.
419 typedef union _hw_dma_es
422 struct _hw_dma_es_bitfields
424 uint32_t DBE
: 1; /*!< [0] Destination Bus Error */
425 uint32_t SBE
: 1; /*!< [1] Source Bus Error */
426 uint32_t SGE
: 1; /*!< [2] Scatter/Gather Configuration Error */
427 uint32_t NCE
: 1; /*!< [3] NBYTES/CITER Configuration Error */
428 uint32_t DOE
: 1; /*!< [4] Destination Offset Error */
429 uint32_t DAE
: 1; /*!< [5] Destination Address Error */
430 uint32_t SOE
: 1; /*!< [6] Source Offset Error */
431 uint32_t SAE
: 1; /*!< [7] Source Address Error */
432 uint32_t ERRCHN
: 4; /*!< [11:8] Error Channel Number or Canceled
434 uint32_t RESERVED0
: 2; /*!< [13:12] */
435 uint32_t CPE
: 1; /*!< [14] Channel Priority Error */
436 uint32_t RESERVED1
: 1; /*!< [15] */
437 uint32_t ECX
: 1; /*!< [16] Transfer Canceled */
438 uint32_t RESERVED2
: 14; /*!< [30:17] */
439 uint32_t VLD
: 1; /*!< [31] */
444 * @name Constants and macros for entire DMA_ES register
447 #define HW_DMA_ES_ADDR(x) ((x) + 0x4U)
449 #define HW_DMA_ES(x) (*(__I hw_dma_es_t *) HW_DMA_ES_ADDR(x))
450 #define HW_DMA_ES_RD(x) (HW_DMA_ES(x).U)
454 * Constants & macros for individual DMA_ES bitfields
458 * @name Register DMA_ES, field DBE[0] (RO)
461 * - 0 - No destination bus error
462 * - 1 - The last recorded error was a bus error on a destination write
465 #define BP_DMA_ES_DBE (0U) /*!< Bit position for DMA_ES_DBE. */
466 #define BM_DMA_ES_DBE (0x00000001U) /*!< Bit mask for DMA_ES_DBE. */
467 #define BS_DMA_ES_DBE (1U) /*!< Bit field size in bits for DMA_ES_DBE. */
469 /*! @brief Read current value of the DMA_ES_DBE field. */
470 #define BR_DMA_ES_DBE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DBE))
474 * @name Register DMA_ES, field SBE[1] (RO)
477 * - 0 - No source bus error
478 * - 1 - The last recorded error was a bus error on a source read
481 #define BP_DMA_ES_SBE (1U) /*!< Bit position for DMA_ES_SBE. */
482 #define BM_DMA_ES_SBE (0x00000002U) /*!< Bit mask for DMA_ES_SBE. */
483 #define BS_DMA_ES_SBE (1U) /*!< Bit field size in bits for DMA_ES_SBE. */
485 /*! @brief Read current value of the DMA_ES_SBE field. */
486 #define BR_DMA_ES_SBE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SBE))
490 * @name Register DMA_ES, field SGE[2] (RO)
493 * - 0 - No scatter/gather configuration error
494 * - 1 - The last recorded error was a configuration error detected in the
495 * TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather
496 * operation after major loop completion if TCDn_CSR[ESG] is enabled.
497 * TCDn_DLASTSGA is not on a 32 byte boundary.
500 #define BP_DMA_ES_SGE (2U) /*!< Bit position for DMA_ES_SGE. */
501 #define BM_DMA_ES_SGE (0x00000004U) /*!< Bit mask for DMA_ES_SGE. */
502 #define BS_DMA_ES_SGE (1U) /*!< Bit field size in bits for DMA_ES_SGE. */
504 /*! @brief Read current value of the DMA_ES_SGE field. */
505 #define BR_DMA_ES_SGE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SGE))
509 * @name Register DMA_ES, field NCE[3] (RO)
512 * - 0 - No NBYTES/CITER configuration error
513 * - 1 - The last recorded error was a configuration error detected in the
514 * TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of
515 * TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or
516 * TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
519 #define BP_DMA_ES_NCE (3U) /*!< Bit position for DMA_ES_NCE. */
520 #define BM_DMA_ES_NCE (0x00000008U) /*!< Bit mask for DMA_ES_NCE. */
521 #define BS_DMA_ES_NCE (1U) /*!< Bit field size in bits for DMA_ES_NCE. */
523 /*! @brief Read current value of the DMA_ES_NCE field. */
524 #define BR_DMA_ES_NCE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_NCE))
528 * @name Register DMA_ES, field DOE[4] (RO)
531 * - 0 - No destination offset configuration error
532 * - 1 - The last recorded error was a configuration error detected in the
533 * TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
536 #define BP_DMA_ES_DOE (4U) /*!< Bit position for DMA_ES_DOE. */
537 #define BM_DMA_ES_DOE (0x00000010U) /*!< Bit mask for DMA_ES_DOE. */
538 #define BS_DMA_ES_DOE (1U) /*!< Bit field size in bits for DMA_ES_DOE. */
540 /*! @brief Read current value of the DMA_ES_DOE field. */
541 #define BR_DMA_ES_DOE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DOE))
545 * @name Register DMA_ES, field DAE[5] (RO)
548 * - 0 - No destination address configuration error
549 * - 1 - The last recorded error was a configuration error detected in the
550 * TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
553 #define BP_DMA_ES_DAE (5U) /*!< Bit position for DMA_ES_DAE. */
554 #define BM_DMA_ES_DAE (0x00000020U) /*!< Bit mask for DMA_ES_DAE. */
555 #define BS_DMA_ES_DAE (1U) /*!< Bit field size in bits for DMA_ES_DAE. */
557 /*! @brief Read current value of the DMA_ES_DAE field. */
558 #define BR_DMA_ES_DAE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DAE))
562 * @name Register DMA_ES, field SOE[6] (RO)
565 * - 0 - No source offset configuration error
566 * - 1 - The last recorded error was a configuration error detected in the
567 * TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
570 #define BP_DMA_ES_SOE (6U) /*!< Bit position for DMA_ES_SOE. */
571 #define BM_DMA_ES_SOE (0x00000040U) /*!< Bit mask for DMA_ES_SOE. */
572 #define BS_DMA_ES_SOE (1U) /*!< Bit field size in bits for DMA_ES_SOE. */
574 /*! @brief Read current value of the DMA_ES_SOE field. */
575 #define BR_DMA_ES_SOE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SOE))
579 * @name Register DMA_ES, field SAE[7] (RO)
582 * - 0 - No source address configuration error.
583 * - 1 - The last recorded error was a configuration error detected in the
584 * TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
587 #define BP_DMA_ES_SAE (7U) /*!< Bit position for DMA_ES_SAE. */
588 #define BM_DMA_ES_SAE (0x00000080U) /*!< Bit mask for DMA_ES_SAE. */
589 #define BS_DMA_ES_SAE (1U) /*!< Bit field size in bits for DMA_ES_SAE. */
591 /*! @brief Read current value of the DMA_ES_SAE field. */
592 #define BR_DMA_ES_SAE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SAE))
596 * @name Register DMA_ES, field ERRCHN[11:8] (RO)
598 * The channel number of the last recorded error (excluding CPE errors) or last
599 * recorded error canceled transfer.
602 #define BP_DMA_ES_ERRCHN (8U) /*!< Bit position for DMA_ES_ERRCHN. */
603 #define BM_DMA_ES_ERRCHN (0x00000F00U) /*!< Bit mask for DMA_ES_ERRCHN. */
604 #define BS_DMA_ES_ERRCHN (4U) /*!< Bit field size in bits for DMA_ES_ERRCHN. */
606 /*! @brief Read current value of the DMA_ES_ERRCHN field. */
607 #define BR_DMA_ES_ERRCHN(x) (HW_DMA_ES(x).B.ERRCHN)
611 * @name Register DMA_ES, field CPE[14] (RO)
614 * - 0 - No channel priority error
615 * - 1 - The last recorded error was a configuration error in the channel
616 * priorities . Channel priorities are not unique.
619 #define BP_DMA_ES_CPE (14U) /*!< Bit position for DMA_ES_CPE. */
620 #define BM_DMA_ES_CPE (0x00004000U) /*!< Bit mask for DMA_ES_CPE. */
621 #define BS_DMA_ES_CPE (1U) /*!< Bit field size in bits for DMA_ES_CPE. */
623 /*! @brief Read current value of the DMA_ES_CPE field. */
624 #define BR_DMA_ES_CPE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_CPE))
628 * @name Register DMA_ES, field ECX[16] (RO)
631 * - 0 - No canceled transfers
632 * - 1 - The last recorded entry was a canceled transfer by the error cancel
636 #define BP_DMA_ES_ECX (16U) /*!< Bit position for DMA_ES_ECX. */
637 #define BM_DMA_ES_ECX (0x00010000U) /*!< Bit mask for DMA_ES_ECX. */
638 #define BS_DMA_ES_ECX (1U) /*!< Bit field size in bits for DMA_ES_ECX. */
640 /*! @brief Read current value of the DMA_ES_ECX field. */
641 #define BR_DMA_ES_ECX(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_ECX))
645 * @name Register DMA_ES, field VLD[31] (RO)
647 * Logical OR of all ERR status bits
650 * - 0 - No ERR bits are set
651 * - 1 - At least one ERR bit is set indicating a valid error exists that has
655 #define BP_DMA_ES_VLD (31U) /*!< Bit position for DMA_ES_VLD. */
656 #define BM_DMA_ES_VLD (0x80000000U) /*!< Bit mask for DMA_ES_VLD. */
657 #define BS_DMA_ES_VLD (1U) /*!< Bit field size in bits for DMA_ES_VLD. */
659 /*! @brief Read current value of the DMA_ES_VLD field. */
660 #define BR_DMA_ES_VLD(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_VLD))
663 /*******************************************************************************
664 * HW_DMA_ERQ - Enable Request Register
665 ******************************************************************************/
668 * @brief HW_DMA_ERQ - Enable Request Register (RW)
670 * Reset value: 0x00000000U
672 * The ERQ register provides a bit map for the 16 implemented channels to enable
673 * the request signal for each channel. The state of any given channel enable is
674 * directly affected by writes to this register; it is also affected by writes
675 * to the SERQ and CERQ. The {S,C}ERQ registers are provided so the request enable
676 * for a single channel can easily be modified without needing to perform a
677 * read-modify-write sequence to the ERQ. DMA request input signals and this enable
678 * request flag must be asserted before a channel's hardware service request is
679 * accepted. The state of the DMA enable request flag does not affect a channel
680 * service request made explicitly through software or a linked channel request.
682 typedef union _hw_dma_erq
685 struct _hw_dma_erq_bitfields
687 uint32_t ERQ0
: 1; /*!< [0] Enable DMA Request 0 */
688 uint32_t ERQ1
: 1; /*!< [1] Enable DMA Request 1 */
689 uint32_t ERQ2
: 1; /*!< [2] Enable DMA Request 2 */
690 uint32_t ERQ3
: 1; /*!< [3] Enable DMA Request 3 */
691 uint32_t ERQ4
: 1; /*!< [4] Enable DMA Request 4 */
692 uint32_t ERQ5
: 1; /*!< [5] Enable DMA Request 5 */
693 uint32_t ERQ6
: 1; /*!< [6] Enable DMA Request 6 */
694 uint32_t ERQ7
: 1; /*!< [7] Enable DMA Request 7 */
695 uint32_t ERQ8
: 1; /*!< [8] Enable DMA Request 8 */
696 uint32_t ERQ9
: 1; /*!< [9] Enable DMA Request 9 */
697 uint32_t ERQ10
: 1; /*!< [10] Enable DMA Request 10 */
698 uint32_t ERQ11
: 1; /*!< [11] Enable DMA Request 11 */
699 uint32_t ERQ12
: 1; /*!< [12] Enable DMA Request 12 */
700 uint32_t ERQ13
: 1; /*!< [13] Enable DMA Request 13 */
701 uint32_t ERQ14
: 1; /*!< [14] Enable DMA Request 14 */
702 uint32_t ERQ15
: 1; /*!< [15] Enable DMA Request 15 */
703 uint32_t RESERVED0
: 16; /*!< [31:16] */
708 * @name Constants and macros for entire DMA_ERQ register
711 #define HW_DMA_ERQ_ADDR(x) ((x) + 0xCU)
713 #define HW_DMA_ERQ(x) (*(__IO hw_dma_erq_t *) HW_DMA_ERQ_ADDR(x))
714 #define HW_DMA_ERQ_RD(x) (HW_DMA_ERQ(x).U)
715 #define HW_DMA_ERQ_WR(x, v) (HW_DMA_ERQ(x).U = (v))
716 #define HW_DMA_ERQ_SET(x, v) (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) | (v)))
717 #define HW_DMA_ERQ_CLR(x, v) (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) & ~(v)))
718 #define HW_DMA_ERQ_TOG(x, v) (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) ^ (v)))
722 * Constants & macros for individual DMA_ERQ bitfields
726 * @name Register DMA_ERQ, field ERQ0[0] (RW)
729 * - 0 - The DMA request signal for the corresponding channel is disabled
730 * - 1 - The DMA request signal for the corresponding channel is enabled
733 #define BP_DMA_ERQ_ERQ0 (0U) /*!< Bit position for DMA_ERQ_ERQ0. */
734 #define BM_DMA_ERQ_ERQ0 (0x00000001U) /*!< Bit mask for DMA_ERQ_ERQ0. */
735 #define BS_DMA_ERQ_ERQ0 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ0. */
737 /*! @brief Read current value of the DMA_ERQ_ERQ0 field. */
738 #define BR_DMA_ERQ_ERQ0(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ0))
740 /*! @brief Format value for bitfield DMA_ERQ_ERQ0. */
741 #define BF_DMA_ERQ_ERQ0(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ0) & BM_DMA_ERQ_ERQ0)
743 /*! @brief Set the ERQ0 field to a new value. */
744 #define BW_DMA_ERQ_ERQ0(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ0) = (v))
748 * @name Register DMA_ERQ, field ERQ1[1] (RW)
751 * - 0 - The DMA request signal for the corresponding channel is disabled
752 * - 1 - The DMA request signal for the corresponding channel is enabled
755 #define BP_DMA_ERQ_ERQ1 (1U) /*!< Bit position for DMA_ERQ_ERQ1. */
756 #define BM_DMA_ERQ_ERQ1 (0x00000002U) /*!< Bit mask for DMA_ERQ_ERQ1. */
757 #define BS_DMA_ERQ_ERQ1 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ1. */
759 /*! @brief Read current value of the DMA_ERQ_ERQ1 field. */
760 #define BR_DMA_ERQ_ERQ1(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ1))
762 /*! @brief Format value for bitfield DMA_ERQ_ERQ1. */
763 #define BF_DMA_ERQ_ERQ1(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ1) & BM_DMA_ERQ_ERQ1)
765 /*! @brief Set the ERQ1 field to a new value. */
766 #define BW_DMA_ERQ_ERQ1(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ1) = (v))
770 * @name Register DMA_ERQ, field ERQ2[2] (RW)
773 * - 0 - The DMA request signal for the corresponding channel is disabled
774 * - 1 - The DMA request signal for the corresponding channel is enabled
777 #define BP_DMA_ERQ_ERQ2 (2U) /*!< Bit position for DMA_ERQ_ERQ2. */
778 #define BM_DMA_ERQ_ERQ2 (0x00000004U) /*!< Bit mask for DMA_ERQ_ERQ2. */
779 #define BS_DMA_ERQ_ERQ2 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ2. */
781 /*! @brief Read current value of the DMA_ERQ_ERQ2 field. */
782 #define BR_DMA_ERQ_ERQ2(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ2))
784 /*! @brief Format value for bitfield DMA_ERQ_ERQ2. */
785 #define BF_DMA_ERQ_ERQ2(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ2) & BM_DMA_ERQ_ERQ2)
787 /*! @brief Set the ERQ2 field to a new value. */
788 #define BW_DMA_ERQ_ERQ2(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ2) = (v))
792 * @name Register DMA_ERQ, field ERQ3[3] (RW)
795 * - 0 - The DMA request signal for the corresponding channel is disabled
796 * - 1 - The DMA request signal for the corresponding channel is enabled
799 #define BP_DMA_ERQ_ERQ3 (3U) /*!< Bit position for DMA_ERQ_ERQ3. */
800 #define BM_DMA_ERQ_ERQ3 (0x00000008U) /*!< Bit mask for DMA_ERQ_ERQ3. */
801 #define BS_DMA_ERQ_ERQ3 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ3. */
803 /*! @brief Read current value of the DMA_ERQ_ERQ3 field. */
804 #define BR_DMA_ERQ_ERQ3(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ3))
806 /*! @brief Format value for bitfield DMA_ERQ_ERQ3. */
807 #define BF_DMA_ERQ_ERQ3(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ3) & BM_DMA_ERQ_ERQ3)
809 /*! @brief Set the ERQ3 field to a new value. */
810 #define BW_DMA_ERQ_ERQ3(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ3) = (v))
814 * @name Register DMA_ERQ, field ERQ4[4] (RW)
817 * - 0 - The DMA request signal for the corresponding channel is disabled
818 * - 1 - The DMA request signal for the corresponding channel is enabled
821 #define BP_DMA_ERQ_ERQ4 (4U) /*!< Bit position for DMA_ERQ_ERQ4. */
822 #define BM_DMA_ERQ_ERQ4 (0x00000010U) /*!< Bit mask for DMA_ERQ_ERQ4. */
823 #define BS_DMA_ERQ_ERQ4 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ4. */
825 /*! @brief Read current value of the DMA_ERQ_ERQ4 field. */
826 #define BR_DMA_ERQ_ERQ4(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ4))
828 /*! @brief Format value for bitfield DMA_ERQ_ERQ4. */
829 #define BF_DMA_ERQ_ERQ4(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ4) & BM_DMA_ERQ_ERQ4)
831 /*! @brief Set the ERQ4 field to a new value. */
832 #define BW_DMA_ERQ_ERQ4(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ4) = (v))
836 * @name Register DMA_ERQ, field ERQ5[5] (RW)
839 * - 0 - The DMA request signal for the corresponding channel is disabled
840 * - 1 - The DMA request signal for the corresponding channel is enabled
843 #define BP_DMA_ERQ_ERQ5 (5U) /*!< Bit position for DMA_ERQ_ERQ5. */
844 #define BM_DMA_ERQ_ERQ5 (0x00000020U) /*!< Bit mask for DMA_ERQ_ERQ5. */
845 #define BS_DMA_ERQ_ERQ5 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ5. */
847 /*! @brief Read current value of the DMA_ERQ_ERQ5 field. */
848 #define BR_DMA_ERQ_ERQ5(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ5))
850 /*! @brief Format value for bitfield DMA_ERQ_ERQ5. */
851 #define BF_DMA_ERQ_ERQ5(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ5) & BM_DMA_ERQ_ERQ5)
853 /*! @brief Set the ERQ5 field to a new value. */
854 #define BW_DMA_ERQ_ERQ5(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ5) = (v))
858 * @name Register DMA_ERQ, field ERQ6[6] (RW)
861 * - 0 - The DMA request signal for the corresponding channel is disabled
862 * - 1 - The DMA request signal for the corresponding channel is enabled
865 #define BP_DMA_ERQ_ERQ6 (6U) /*!< Bit position for DMA_ERQ_ERQ6. */
866 #define BM_DMA_ERQ_ERQ6 (0x00000040U) /*!< Bit mask for DMA_ERQ_ERQ6. */
867 #define BS_DMA_ERQ_ERQ6 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ6. */
869 /*! @brief Read current value of the DMA_ERQ_ERQ6 field. */
870 #define BR_DMA_ERQ_ERQ6(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ6))
872 /*! @brief Format value for bitfield DMA_ERQ_ERQ6. */
873 #define BF_DMA_ERQ_ERQ6(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ6) & BM_DMA_ERQ_ERQ6)
875 /*! @brief Set the ERQ6 field to a new value. */
876 #define BW_DMA_ERQ_ERQ6(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ6) = (v))
880 * @name Register DMA_ERQ, field ERQ7[7] (RW)
883 * - 0 - The DMA request signal for the corresponding channel is disabled
884 * - 1 - The DMA request signal for the corresponding channel is enabled
887 #define BP_DMA_ERQ_ERQ7 (7U) /*!< Bit position for DMA_ERQ_ERQ7. */
888 #define BM_DMA_ERQ_ERQ7 (0x00000080U) /*!< Bit mask for DMA_ERQ_ERQ7. */
889 #define BS_DMA_ERQ_ERQ7 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ7. */
891 /*! @brief Read current value of the DMA_ERQ_ERQ7 field. */
892 #define BR_DMA_ERQ_ERQ7(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ7))
894 /*! @brief Format value for bitfield DMA_ERQ_ERQ7. */
895 #define BF_DMA_ERQ_ERQ7(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ7) & BM_DMA_ERQ_ERQ7)
897 /*! @brief Set the ERQ7 field to a new value. */
898 #define BW_DMA_ERQ_ERQ7(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ7) = (v))
902 * @name Register DMA_ERQ, field ERQ8[8] (RW)
905 * - 0 - The DMA request signal for the corresponding channel is disabled
906 * - 1 - The DMA request signal for the corresponding channel is enabled
909 #define BP_DMA_ERQ_ERQ8 (8U) /*!< Bit position for DMA_ERQ_ERQ8. */
910 #define BM_DMA_ERQ_ERQ8 (0x00000100U) /*!< Bit mask for DMA_ERQ_ERQ8. */
911 #define BS_DMA_ERQ_ERQ8 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ8. */
913 /*! @brief Read current value of the DMA_ERQ_ERQ8 field. */
914 #define BR_DMA_ERQ_ERQ8(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ8))
916 /*! @brief Format value for bitfield DMA_ERQ_ERQ8. */
917 #define BF_DMA_ERQ_ERQ8(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ8) & BM_DMA_ERQ_ERQ8)
919 /*! @brief Set the ERQ8 field to a new value. */
920 #define BW_DMA_ERQ_ERQ8(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ8) = (v))
924 * @name Register DMA_ERQ, field ERQ9[9] (RW)
927 * - 0 - The DMA request signal for the corresponding channel is disabled
928 * - 1 - The DMA request signal for the corresponding channel is enabled
931 #define BP_DMA_ERQ_ERQ9 (9U) /*!< Bit position for DMA_ERQ_ERQ9. */
932 #define BM_DMA_ERQ_ERQ9 (0x00000200U) /*!< Bit mask for DMA_ERQ_ERQ9. */
933 #define BS_DMA_ERQ_ERQ9 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ9. */
935 /*! @brief Read current value of the DMA_ERQ_ERQ9 field. */
936 #define BR_DMA_ERQ_ERQ9(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ9))
938 /*! @brief Format value for bitfield DMA_ERQ_ERQ9. */
939 #define BF_DMA_ERQ_ERQ9(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ9) & BM_DMA_ERQ_ERQ9)
941 /*! @brief Set the ERQ9 field to a new value. */
942 #define BW_DMA_ERQ_ERQ9(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ9) = (v))
946 * @name Register DMA_ERQ, field ERQ10[10] (RW)
949 * - 0 - The DMA request signal for the corresponding channel is disabled
950 * - 1 - The DMA request signal for the corresponding channel is enabled
953 #define BP_DMA_ERQ_ERQ10 (10U) /*!< Bit position for DMA_ERQ_ERQ10. */
954 #define BM_DMA_ERQ_ERQ10 (0x00000400U) /*!< Bit mask for DMA_ERQ_ERQ10. */
955 #define BS_DMA_ERQ_ERQ10 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ10. */
957 /*! @brief Read current value of the DMA_ERQ_ERQ10 field. */
958 #define BR_DMA_ERQ_ERQ10(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ10))
960 /*! @brief Format value for bitfield DMA_ERQ_ERQ10. */
961 #define BF_DMA_ERQ_ERQ10(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ10) & BM_DMA_ERQ_ERQ10)
963 /*! @brief Set the ERQ10 field to a new value. */
964 #define BW_DMA_ERQ_ERQ10(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ10) = (v))
968 * @name Register DMA_ERQ, field ERQ11[11] (RW)
971 * - 0 - The DMA request signal for the corresponding channel is disabled
972 * - 1 - The DMA request signal for the corresponding channel is enabled
975 #define BP_DMA_ERQ_ERQ11 (11U) /*!< Bit position for DMA_ERQ_ERQ11. */
976 #define BM_DMA_ERQ_ERQ11 (0x00000800U) /*!< Bit mask for DMA_ERQ_ERQ11. */
977 #define BS_DMA_ERQ_ERQ11 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ11. */
979 /*! @brief Read current value of the DMA_ERQ_ERQ11 field. */
980 #define BR_DMA_ERQ_ERQ11(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ11))
982 /*! @brief Format value for bitfield DMA_ERQ_ERQ11. */
983 #define BF_DMA_ERQ_ERQ11(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ11) & BM_DMA_ERQ_ERQ11)
985 /*! @brief Set the ERQ11 field to a new value. */
986 #define BW_DMA_ERQ_ERQ11(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ11) = (v))
990 * @name Register DMA_ERQ, field ERQ12[12] (RW)
993 * - 0 - The DMA request signal for the corresponding channel is disabled
994 * - 1 - The DMA request signal for the corresponding channel is enabled
997 #define BP_DMA_ERQ_ERQ12 (12U) /*!< Bit position for DMA_ERQ_ERQ12. */
998 #define BM_DMA_ERQ_ERQ12 (0x00001000U) /*!< Bit mask for DMA_ERQ_ERQ12. */
999 #define BS_DMA_ERQ_ERQ12 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ12. */
1001 /*! @brief Read current value of the DMA_ERQ_ERQ12 field. */
1002 #define BR_DMA_ERQ_ERQ12(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ12))
1004 /*! @brief Format value for bitfield DMA_ERQ_ERQ12. */
1005 #define BF_DMA_ERQ_ERQ12(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ12) & BM_DMA_ERQ_ERQ12)
1007 /*! @brief Set the ERQ12 field to a new value. */
1008 #define BW_DMA_ERQ_ERQ12(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ12) = (v))
1012 * @name Register DMA_ERQ, field ERQ13[13] (RW)
1015 * - 0 - The DMA request signal for the corresponding channel is disabled
1016 * - 1 - The DMA request signal for the corresponding channel is enabled
1019 #define BP_DMA_ERQ_ERQ13 (13U) /*!< Bit position for DMA_ERQ_ERQ13. */
1020 #define BM_DMA_ERQ_ERQ13 (0x00002000U) /*!< Bit mask for DMA_ERQ_ERQ13. */
1021 #define BS_DMA_ERQ_ERQ13 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ13. */
1023 /*! @brief Read current value of the DMA_ERQ_ERQ13 field. */
1024 #define BR_DMA_ERQ_ERQ13(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ13))
1026 /*! @brief Format value for bitfield DMA_ERQ_ERQ13. */
1027 #define BF_DMA_ERQ_ERQ13(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ13) & BM_DMA_ERQ_ERQ13)
1029 /*! @brief Set the ERQ13 field to a new value. */
1030 #define BW_DMA_ERQ_ERQ13(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ13) = (v))
1034 * @name Register DMA_ERQ, field ERQ14[14] (RW)
1037 * - 0 - The DMA request signal for the corresponding channel is disabled
1038 * - 1 - The DMA request signal for the corresponding channel is enabled
1041 #define BP_DMA_ERQ_ERQ14 (14U) /*!< Bit position for DMA_ERQ_ERQ14. */
1042 #define BM_DMA_ERQ_ERQ14 (0x00004000U) /*!< Bit mask for DMA_ERQ_ERQ14. */
1043 #define BS_DMA_ERQ_ERQ14 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ14. */
1045 /*! @brief Read current value of the DMA_ERQ_ERQ14 field. */
1046 #define BR_DMA_ERQ_ERQ14(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ14))
1048 /*! @brief Format value for bitfield DMA_ERQ_ERQ14. */
1049 #define BF_DMA_ERQ_ERQ14(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ14) & BM_DMA_ERQ_ERQ14)
1051 /*! @brief Set the ERQ14 field to a new value. */
1052 #define BW_DMA_ERQ_ERQ14(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ14) = (v))
1056 * @name Register DMA_ERQ, field ERQ15[15] (RW)
1059 * - 0 - The DMA request signal for the corresponding channel is disabled
1060 * - 1 - The DMA request signal for the corresponding channel is enabled
1063 #define BP_DMA_ERQ_ERQ15 (15U) /*!< Bit position for DMA_ERQ_ERQ15. */
1064 #define BM_DMA_ERQ_ERQ15 (0x00008000U) /*!< Bit mask for DMA_ERQ_ERQ15. */
1065 #define BS_DMA_ERQ_ERQ15 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ15. */
1067 /*! @brief Read current value of the DMA_ERQ_ERQ15 field. */
1068 #define BR_DMA_ERQ_ERQ15(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ15))
1070 /*! @brief Format value for bitfield DMA_ERQ_ERQ15. */
1071 #define BF_DMA_ERQ_ERQ15(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ15) & BM_DMA_ERQ_ERQ15)
1073 /*! @brief Set the ERQ15 field to a new value. */
1074 #define BW_DMA_ERQ_ERQ15(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ15) = (v))
1077 /*******************************************************************************
1078 * HW_DMA_EEI - Enable Error Interrupt Register
1079 ******************************************************************************/
1082 * @brief HW_DMA_EEI - Enable Error Interrupt Register (RW)
1084 * Reset value: 0x00000000U
1086 * The EEI register provides a bit map for the 16 channels to enable the error
1087 * interrupt signal for each channel. The state of any given channel's error
1088 * interrupt enable is directly affected by writes to this register; it is also
1089 * affected by writes to the SEEI and CEEI. The {S,C}EEI are provided so the error
1090 * interrupt enable for a single channel can easily be modified without the need to
1091 * perform a read-modify-write sequence to the EEI register. The DMA error
1092 * indicator and the error interrupt enable flag must be asserted before an error
1093 * interrupt request for a given channel is asserted to the interrupt controller.
1095 typedef union _hw_dma_eei
1098 struct _hw_dma_eei_bitfields
1100 uint32_t EEI0
: 1; /*!< [0] Enable Error Interrupt 0 */
1101 uint32_t EEI1
: 1; /*!< [1] Enable Error Interrupt 1 */
1102 uint32_t EEI2
: 1; /*!< [2] Enable Error Interrupt 2 */
1103 uint32_t EEI3
: 1; /*!< [3] Enable Error Interrupt 3 */
1104 uint32_t EEI4
: 1; /*!< [4] Enable Error Interrupt 4 */
1105 uint32_t EEI5
: 1; /*!< [5] Enable Error Interrupt 5 */
1106 uint32_t EEI6
: 1; /*!< [6] Enable Error Interrupt 6 */
1107 uint32_t EEI7
: 1; /*!< [7] Enable Error Interrupt 7 */
1108 uint32_t EEI8
: 1; /*!< [8] Enable Error Interrupt 8 */
1109 uint32_t EEI9
: 1; /*!< [9] Enable Error Interrupt 9 */
1110 uint32_t EEI10
: 1; /*!< [10] Enable Error Interrupt 10 */
1111 uint32_t EEI11
: 1; /*!< [11] Enable Error Interrupt 11 */
1112 uint32_t EEI12
: 1; /*!< [12] Enable Error Interrupt 12 */
1113 uint32_t EEI13
: 1; /*!< [13] Enable Error Interrupt 13 */
1114 uint32_t EEI14
: 1; /*!< [14] Enable Error Interrupt 14 */
1115 uint32_t EEI15
: 1; /*!< [15] Enable Error Interrupt 15 */
1116 uint32_t RESERVED0
: 16; /*!< [31:16] */
1121 * @name Constants and macros for entire DMA_EEI register
1124 #define HW_DMA_EEI_ADDR(x) ((x) + 0x14U)
1126 #define HW_DMA_EEI(x) (*(__IO hw_dma_eei_t *) HW_DMA_EEI_ADDR(x))
1127 #define HW_DMA_EEI_RD(x) (HW_DMA_EEI(x).U)
1128 #define HW_DMA_EEI_WR(x, v) (HW_DMA_EEI(x).U = (v))
1129 #define HW_DMA_EEI_SET(x, v) (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) | (v)))
1130 #define HW_DMA_EEI_CLR(x, v) (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) & ~(v)))
1131 #define HW_DMA_EEI_TOG(x, v) (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) ^ (v)))
1135 * Constants & macros for individual DMA_EEI bitfields
1139 * @name Register DMA_EEI, field EEI0[0] (RW)
1142 * - 0 - The error signal for corresponding channel does not generate an error
1144 * - 1 - The assertion of the error signal for corresponding channel generates
1145 * an error interrupt request
1148 #define BP_DMA_EEI_EEI0 (0U) /*!< Bit position for DMA_EEI_EEI0. */
1149 #define BM_DMA_EEI_EEI0 (0x00000001U) /*!< Bit mask for DMA_EEI_EEI0. */
1150 #define BS_DMA_EEI_EEI0 (1U) /*!< Bit field size in bits for DMA_EEI_EEI0. */
1152 /*! @brief Read current value of the DMA_EEI_EEI0 field. */
1153 #define BR_DMA_EEI_EEI0(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI0))
1155 /*! @brief Format value for bitfield DMA_EEI_EEI0. */
1156 #define BF_DMA_EEI_EEI0(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI0) & BM_DMA_EEI_EEI0)
1158 /*! @brief Set the EEI0 field to a new value. */
1159 #define BW_DMA_EEI_EEI0(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI0) = (v))
1163 * @name Register DMA_EEI, field EEI1[1] (RW)
1166 * - 0 - The error signal for corresponding channel does not generate an error
1168 * - 1 - The assertion of the error signal for corresponding channel generates
1169 * an error interrupt request
1172 #define BP_DMA_EEI_EEI1 (1U) /*!< Bit position for DMA_EEI_EEI1. */
1173 #define BM_DMA_EEI_EEI1 (0x00000002U) /*!< Bit mask for DMA_EEI_EEI1. */
1174 #define BS_DMA_EEI_EEI1 (1U) /*!< Bit field size in bits for DMA_EEI_EEI1. */
1176 /*! @brief Read current value of the DMA_EEI_EEI1 field. */
1177 #define BR_DMA_EEI_EEI1(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI1))
1179 /*! @brief Format value for bitfield DMA_EEI_EEI1. */
1180 #define BF_DMA_EEI_EEI1(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI1) & BM_DMA_EEI_EEI1)
1182 /*! @brief Set the EEI1 field to a new value. */
1183 #define BW_DMA_EEI_EEI1(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI1) = (v))
1187 * @name Register DMA_EEI, field EEI2[2] (RW)
1190 * - 0 - The error signal for corresponding channel does not generate an error
1192 * - 1 - The assertion of the error signal for corresponding channel generates
1193 * an error interrupt request
1196 #define BP_DMA_EEI_EEI2 (2U) /*!< Bit position for DMA_EEI_EEI2. */
1197 #define BM_DMA_EEI_EEI2 (0x00000004U) /*!< Bit mask for DMA_EEI_EEI2. */
1198 #define BS_DMA_EEI_EEI2 (1U) /*!< Bit field size in bits for DMA_EEI_EEI2. */
1200 /*! @brief Read current value of the DMA_EEI_EEI2 field. */
1201 #define BR_DMA_EEI_EEI2(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI2))
1203 /*! @brief Format value for bitfield DMA_EEI_EEI2. */
1204 #define BF_DMA_EEI_EEI2(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI2) & BM_DMA_EEI_EEI2)
1206 /*! @brief Set the EEI2 field to a new value. */
1207 #define BW_DMA_EEI_EEI2(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI2) = (v))
1211 * @name Register DMA_EEI, field EEI3[3] (RW)
1214 * - 0 - The error signal for corresponding channel does not generate an error
1216 * - 1 - The assertion of the error signal for corresponding channel generates
1217 * an error interrupt request
1220 #define BP_DMA_EEI_EEI3 (3U) /*!< Bit position for DMA_EEI_EEI3. */
1221 #define BM_DMA_EEI_EEI3 (0x00000008U) /*!< Bit mask for DMA_EEI_EEI3. */
1222 #define BS_DMA_EEI_EEI3 (1U) /*!< Bit field size in bits for DMA_EEI_EEI3. */
1224 /*! @brief Read current value of the DMA_EEI_EEI3 field. */
1225 #define BR_DMA_EEI_EEI3(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI3))
1227 /*! @brief Format value for bitfield DMA_EEI_EEI3. */
1228 #define BF_DMA_EEI_EEI3(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI3) & BM_DMA_EEI_EEI3)
1230 /*! @brief Set the EEI3 field to a new value. */
1231 #define BW_DMA_EEI_EEI3(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI3) = (v))
1235 * @name Register DMA_EEI, field EEI4[4] (RW)
1238 * - 0 - The error signal for corresponding channel does not generate an error
1240 * - 1 - The assertion of the error signal for corresponding channel generates
1241 * an error interrupt request
1244 #define BP_DMA_EEI_EEI4 (4U) /*!< Bit position for DMA_EEI_EEI4. */
1245 #define BM_DMA_EEI_EEI4 (0x00000010U) /*!< Bit mask for DMA_EEI_EEI4. */
1246 #define BS_DMA_EEI_EEI4 (1U) /*!< Bit field size in bits for DMA_EEI_EEI4. */
1248 /*! @brief Read current value of the DMA_EEI_EEI4 field. */
1249 #define BR_DMA_EEI_EEI4(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI4))
1251 /*! @brief Format value for bitfield DMA_EEI_EEI4. */
1252 #define BF_DMA_EEI_EEI4(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI4) & BM_DMA_EEI_EEI4)
1254 /*! @brief Set the EEI4 field to a new value. */
1255 #define BW_DMA_EEI_EEI4(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI4) = (v))
1259 * @name Register DMA_EEI, field EEI5[5] (RW)
1262 * - 0 - The error signal for corresponding channel does not generate an error
1264 * - 1 - The assertion of the error signal for corresponding channel generates
1265 * an error interrupt request
1268 #define BP_DMA_EEI_EEI5 (5U) /*!< Bit position for DMA_EEI_EEI5. */
1269 #define BM_DMA_EEI_EEI5 (0x00000020U) /*!< Bit mask for DMA_EEI_EEI5. */
1270 #define BS_DMA_EEI_EEI5 (1U) /*!< Bit field size in bits for DMA_EEI_EEI5. */
1272 /*! @brief Read current value of the DMA_EEI_EEI5 field. */
1273 #define BR_DMA_EEI_EEI5(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI5))
1275 /*! @brief Format value for bitfield DMA_EEI_EEI5. */
1276 #define BF_DMA_EEI_EEI5(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI5) & BM_DMA_EEI_EEI5)
1278 /*! @brief Set the EEI5 field to a new value. */
1279 #define BW_DMA_EEI_EEI5(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI5) = (v))
1283 * @name Register DMA_EEI, field EEI6[6] (RW)
1286 * - 0 - The error signal for corresponding channel does not generate an error
1288 * - 1 - The assertion of the error signal for corresponding channel generates
1289 * an error interrupt request
1292 #define BP_DMA_EEI_EEI6 (6U) /*!< Bit position for DMA_EEI_EEI6. */
1293 #define BM_DMA_EEI_EEI6 (0x00000040U) /*!< Bit mask for DMA_EEI_EEI6. */
1294 #define BS_DMA_EEI_EEI6 (1U) /*!< Bit field size in bits for DMA_EEI_EEI6. */
1296 /*! @brief Read current value of the DMA_EEI_EEI6 field. */
1297 #define BR_DMA_EEI_EEI6(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI6))
1299 /*! @brief Format value for bitfield DMA_EEI_EEI6. */
1300 #define BF_DMA_EEI_EEI6(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI6) & BM_DMA_EEI_EEI6)
1302 /*! @brief Set the EEI6 field to a new value. */
1303 #define BW_DMA_EEI_EEI6(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI6) = (v))
1307 * @name Register DMA_EEI, field EEI7[7] (RW)
1310 * - 0 - The error signal for corresponding channel does not generate an error
1312 * - 1 - The assertion of the error signal for corresponding channel generates
1313 * an error interrupt request
1316 #define BP_DMA_EEI_EEI7 (7U) /*!< Bit position for DMA_EEI_EEI7. */
1317 #define BM_DMA_EEI_EEI7 (0x00000080U) /*!< Bit mask for DMA_EEI_EEI7. */
1318 #define BS_DMA_EEI_EEI7 (1U) /*!< Bit field size in bits for DMA_EEI_EEI7. */
1320 /*! @brief Read current value of the DMA_EEI_EEI7 field. */
1321 #define BR_DMA_EEI_EEI7(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI7))
1323 /*! @brief Format value for bitfield DMA_EEI_EEI7. */
1324 #define BF_DMA_EEI_EEI7(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI7) & BM_DMA_EEI_EEI7)
1326 /*! @brief Set the EEI7 field to a new value. */
1327 #define BW_DMA_EEI_EEI7(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI7) = (v))
1331 * @name Register DMA_EEI, field EEI8[8] (RW)
1334 * - 0 - The error signal for corresponding channel does not generate an error
1336 * - 1 - The assertion of the error signal for corresponding channel generates
1337 * an error interrupt request
1340 #define BP_DMA_EEI_EEI8 (8U) /*!< Bit position for DMA_EEI_EEI8. */
1341 #define BM_DMA_EEI_EEI8 (0x00000100U) /*!< Bit mask for DMA_EEI_EEI8. */
1342 #define BS_DMA_EEI_EEI8 (1U) /*!< Bit field size in bits for DMA_EEI_EEI8. */
1344 /*! @brief Read current value of the DMA_EEI_EEI8 field. */
1345 #define BR_DMA_EEI_EEI8(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI8))
1347 /*! @brief Format value for bitfield DMA_EEI_EEI8. */
1348 #define BF_DMA_EEI_EEI8(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI8) & BM_DMA_EEI_EEI8)
1350 /*! @brief Set the EEI8 field to a new value. */
1351 #define BW_DMA_EEI_EEI8(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI8) = (v))
1355 * @name Register DMA_EEI, field EEI9[9] (RW)
1358 * - 0 - The error signal for corresponding channel does not generate an error
1360 * - 1 - The assertion of the error signal for corresponding channel generates
1361 * an error interrupt request
1364 #define BP_DMA_EEI_EEI9 (9U) /*!< Bit position for DMA_EEI_EEI9. */
1365 #define BM_DMA_EEI_EEI9 (0x00000200U) /*!< Bit mask for DMA_EEI_EEI9. */
1366 #define BS_DMA_EEI_EEI9 (1U) /*!< Bit field size in bits for DMA_EEI_EEI9. */
1368 /*! @brief Read current value of the DMA_EEI_EEI9 field. */
1369 #define BR_DMA_EEI_EEI9(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI9))
1371 /*! @brief Format value for bitfield DMA_EEI_EEI9. */
1372 #define BF_DMA_EEI_EEI9(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI9) & BM_DMA_EEI_EEI9)
1374 /*! @brief Set the EEI9 field to a new value. */
1375 #define BW_DMA_EEI_EEI9(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI9) = (v))
1379 * @name Register DMA_EEI, field EEI10[10] (RW)
1382 * - 0 - The error signal for corresponding channel does not generate an error
1384 * - 1 - The assertion of the error signal for corresponding channel generates
1385 * an error interrupt request
1388 #define BP_DMA_EEI_EEI10 (10U) /*!< Bit position for DMA_EEI_EEI10. */
1389 #define BM_DMA_EEI_EEI10 (0x00000400U) /*!< Bit mask for DMA_EEI_EEI10. */
1390 #define BS_DMA_EEI_EEI10 (1U) /*!< Bit field size in bits for DMA_EEI_EEI10. */
1392 /*! @brief Read current value of the DMA_EEI_EEI10 field. */
1393 #define BR_DMA_EEI_EEI10(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI10))
1395 /*! @brief Format value for bitfield DMA_EEI_EEI10. */
1396 #define BF_DMA_EEI_EEI10(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI10) & BM_DMA_EEI_EEI10)
1398 /*! @brief Set the EEI10 field to a new value. */
1399 #define BW_DMA_EEI_EEI10(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI10) = (v))
1403 * @name Register DMA_EEI, field EEI11[11] (RW)
1406 * - 0 - The error signal for corresponding channel does not generate an error
1408 * - 1 - The assertion of the error signal for corresponding channel generates
1409 * an error interrupt request
1412 #define BP_DMA_EEI_EEI11 (11U) /*!< Bit position for DMA_EEI_EEI11. */
1413 #define BM_DMA_EEI_EEI11 (0x00000800U) /*!< Bit mask for DMA_EEI_EEI11. */
1414 #define BS_DMA_EEI_EEI11 (1U) /*!< Bit field size in bits for DMA_EEI_EEI11. */
1416 /*! @brief Read current value of the DMA_EEI_EEI11 field. */
1417 #define BR_DMA_EEI_EEI11(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI11))
1419 /*! @brief Format value for bitfield DMA_EEI_EEI11. */
1420 #define BF_DMA_EEI_EEI11(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI11) & BM_DMA_EEI_EEI11)
1422 /*! @brief Set the EEI11 field to a new value. */
1423 #define BW_DMA_EEI_EEI11(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI11) = (v))
1427 * @name Register DMA_EEI, field EEI12[12] (RW)
1430 * - 0 - The error signal for corresponding channel does not generate an error
1432 * - 1 - The assertion of the error signal for corresponding channel generates
1433 * an error interrupt request
1436 #define BP_DMA_EEI_EEI12 (12U) /*!< Bit position for DMA_EEI_EEI12. */
1437 #define BM_DMA_EEI_EEI12 (0x00001000U) /*!< Bit mask for DMA_EEI_EEI12. */
1438 #define BS_DMA_EEI_EEI12 (1U) /*!< Bit field size in bits for DMA_EEI_EEI12. */
1440 /*! @brief Read current value of the DMA_EEI_EEI12 field. */
1441 #define BR_DMA_EEI_EEI12(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI12))
1443 /*! @brief Format value for bitfield DMA_EEI_EEI12. */
1444 #define BF_DMA_EEI_EEI12(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI12) & BM_DMA_EEI_EEI12)
1446 /*! @brief Set the EEI12 field to a new value. */
1447 #define BW_DMA_EEI_EEI12(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI12) = (v))
1451 * @name Register DMA_EEI, field EEI13[13] (RW)
1454 * - 0 - The error signal for corresponding channel does not generate an error
1456 * - 1 - The assertion of the error signal for corresponding channel generates
1457 * an error interrupt request
1460 #define BP_DMA_EEI_EEI13 (13U) /*!< Bit position for DMA_EEI_EEI13. */
1461 #define BM_DMA_EEI_EEI13 (0x00002000U) /*!< Bit mask for DMA_EEI_EEI13. */
1462 #define BS_DMA_EEI_EEI13 (1U) /*!< Bit field size in bits for DMA_EEI_EEI13. */
1464 /*! @brief Read current value of the DMA_EEI_EEI13 field. */
1465 #define BR_DMA_EEI_EEI13(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI13))
1467 /*! @brief Format value for bitfield DMA_EEI_EEI13. */
1468 #define BF_DMA_EEI_EEI13(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI13) & BM_DMA_EEI_EEI13)
1470 /*! @brief Set the EEI13 field to a new value. */
1471 #define BW_DMA_EEI_EEI13(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI13) = (v))
1475 * @name Register DMA_EEI, field EEI14[14] (RW)
1478 * - 0 - The error signal for corresponding channel does not generate an error
1480 * - 1 - The assertion of the error signal for corresponding channel generates
1481 * an error interrupt request
1484 #define BP_DMA_EEI_EEI14 (14U) /*!< Bit position for DMA_EEI_EEI14. */
1485 #define BM_DMA_EEI_EEI14 (0x00004000U) /*!< Bit mask for DMA_EEI_EEI14. */
1486 #define BS_DMA_EEI_EEI14 (1U) /*!< Bit field size in bits for DMA_EEI_EEI14. */
1488 /*! @brief Read current value of the DMA_EEI_EEI14 field. */
1489 #define BR_DMA_EEI_EEI14(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI14))
1491 /*! @brief Format value for bitfield DMA_EEI_EEI14. */
1492 #define BF_DMA_EEI_EEI14(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI14) & BM_DMA_EEI_EEI14)
1494 /*! @brief Set the EEI14 field to a new value. */
1495 #define BW_DMA_EEI_EEI14(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI14) = (v))
1499 * @name Register DMA_EEI, field EEI15[15] (RW)
1502 * - 0 - The error signal for corresponding channel does not generate an error
1504 * - 1 - The assertion of the error signal for corresponding channel generates
1505 * an error interrupt request
1508 #define BP_DMA_EEI_EEI15 (15U) /*!< Bit position for DMA_EEI_EEI15. */
1509 #define BM_DMA_EEI_EEI15 (0x00008000U) /*!< Bit mask for DMA_EEI_EEI15. */
1510 #define BS_DMA_EEI_EEI15 (1U) /*!< Bit field size in bits for DMA_EEI_EEI15. */
1512 /*! @brief Read current value of the DMA_EEI_EEI15 field. */
1513 #define BR_DMA_EEI_EEI15(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI15))
1515 /*! @brief Format value for bitfield DMA_EEI_EEI15. */
1516 #define BF_DMA_EEI_EEI15(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI15) & BM_DMA_EEI_EEI15)
1518 /*! @brief Set the EEI15 field to a new value. */
1519 #define BW_DMA_EEI_EEI15(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI15) = (v))
1522 /*******************************************************************************
1523 * HW_DMA_CEEI - Clear Enable Error Interrupt Register
1524 ******************************************************************************/
1527 * @brief HW_DMA_CEEI - Clear Enable Error Interrupt Register (WO)
1529 * Reset value: 0x00U
1531 * The CEEI provides a simple memory-mapped mechanism to clear a given bit in
1532 * the EEI to disable the error interrupt for a given channel. The data value on a
1533 * register write causes the corresponding bit in the EEI to be cleared. Setting
1534 * the CAEE bit provides a global clear function, forcing the EEI contents to be
1535 * cleared, disabling all DMA request inputs. If the NOP bit is set, the command
1536 * is ignored. This allows you to write multiple-byte registers as a 32-bit word.
1537 * Reads of this register return all zeroes.
1539 typedef union _hw_dma_ceei
1542 struct _hw_dma_ceei_bitfields
1544 uint8_t CEEI
: 4; /*!< [3:0] Clear Enable Error Interrupt */
1545 uint8_t RESERVED0
: 2; /*!< [5:4] */
1546 uint8_t CAEE
: 1; /*!< [6] Clear All Enable Error Interrupts */
1547 uint8_t NOP
: 1; /*!< [7] No Op enable */
1552 * @name Constants and macros for entire DMA_CEEI register
1555 #define HW_DMA_CEEI_ADDR(x) ((x) + 0x18U)
1557 #define HW_DMA_CEEI(x) (*(__O hw_dma_ceei_t *) HW_DMA_CEEI_ADDR(x))
1558 #define HW_DMA_CEEI_RD(x) (HW_DMA_CEEI(x).U)
1559 #define HW_DMA_CEEI_WR(x, v) (HW_DMA_CEEI(x).U = (v))
1563 * Constants & macros for individual DMA_CEEI bitfields
1567 * @name Register DMA_CEEI, field CEEI[3:0] (WORZ)
1569 * Clears the corresponding bit in EEI
1572 #define BP_DMA_CEEI_CEEI (0U) /*!< Bit position for DMA_CEEI_CEEI. */
1573 #define BM_DMA_CEEI_CEEI (0x0FU) /*!< Bit mask for DMA_CEEI_CEEI. */
1574 #define BS_DMA_CEEI_CEEI (4U) /*!< Bit field size in bits for DMA_CEEI_CEEI. */
1576 /*! @brief Format value for bitfield DMA_CEEI_CEEI. */
1577 #define BF_DMA_CEEI_CEEI(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CEEI_CEEI) & BM_DMA_CEEI_CEEI)
1579 /*! @brief Set the CEEI field to a new value. */
1580 #define BW_DMA_CEEI_CEEI(x, v) (HW_DMA_CEEI_WR(x, (HW_DMA_CEEI_RD(x) & ~BM_DMA_CEEI_CEEI) | BF_DMA_CEEI_CEEI(v)))
1584 * @name Register DMA_CEEI, field CAEE[6] (WORZ)
1587 * - 0 - Clear only the EEI bit specified in the CEEI field
1588 * - 1 - Clear all bits in EEI
1591 #define BP_DMA_CEEI_CAEE (6U) /*!< Bit position for DMA_CEEI_CAEE. */
1592 #define BM_DMA_CEEI_CAEE (0x40U) /*!< Bit mask for DMA_CEEI_CAEE. */
1593 #define BS_DMA_CEEI_CAEE (1U) /*!< Bit field size in bits for DMA_CEEI_CAEE. */
1595 /*! @brief Format value for bitfield DMA_CEEI_CAEE. */
1596 #define BF_DMA_CEEI_CAEE(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CEEI_CAEE) & BM_DMA_CEEI_CAEE)
1598 /*! @brief Set the CAEE field to a new value. */
1599 #define BW_DMA_CEEI_CAEE(x, v) (BITBAND_ACCESS8(HW_DMA_CEEI_ADDR(x), BP_DMA_CEEI_CAEE) = (v))
1603 * @name Register DMA_CEEI, field NOP[7] (WORZ)
1606 * - 0 - Normal operation
1607 * - 1 - No operation, ignore the other bits in this register
1610 #define BP_DMA_CEEI_NOP (7U) /*!< Bit position for DMA_CEEI_NOP. */
1611 #define BM_DMA_CEEI_NOP (0x80U) /*!< Bit mask for DMA_CEEI_NOP. */
1612 #define BS_DMA_CEEI_NOP (1U) /*!< Bit field size in bits for DMA_CEEI_NOP. */
1614 /*! @brief Format value for bitfield DMA_CEEI_NOP. */
1615 #define BF_DMA_CEEI_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CEEI_NOP) & BM_DMA_CEEI_NOP)
1617 /*! @brief Set the NOP field to a new value. */
1618 #define BW_DMA_CEEI_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CEEI_ADDR(x), BP_DMA_CEEI_NOP) = (v))
1621 /*******************************************************************************
1622 * HW_DMA_SEEI - Set Enable Error Interrupt Register
1623 ******************************************************************************/
1626 * @brief HW_DMA_SEEI - Set Enable Error Interrupt Register (WO)
1628 * Reset value: 0x00U
1630 * The SEEI provides a simple memory-mapped mechanism to set a given bit in the
1631 * EEI to enable the error interrupt for a given channel. The data value on a
1632 * register write causes the corresponding bit in the EEI to be set. Setting the
1633 * SAEE bit provides a global set function, forcing the entire EEI contents to be
1634 * set. If the NOP bit is set, the command is ignored. This allows you to write
1635 * multiple-byte registers as a 32-bit word. Reads of this register return all
1638 typedef union _hw_dma_seei
1641 struct _hw_dma_seei_bitfields
1643 uint8_t SEEI
: 4; /*!< [3:0] Set Enable Error Interrupt */
1644 uint8_t RESERVED0
: 2; /*!< [5:4] */
1645 uint8_t SAEE
: 1; /*!< [6] Sets All Enable Error Interrupts */
1646 uint8_t NOP
: 1; /*!< [7] No Op enable */
1651 * @name Constants and macros for entire DMA_SEEI register
1654 #define HW_DMA_SEEI_ADDR(x) ((x) + 0x19U)
1656 #define HW_DMA_SEEI(x) (*(__O hw_dma_seei_t *) HW_DMA_SEEI_ADDR(x))
1657 #define HW_DMA_SEEI_RD(x) (HW_DMA_SEEI(x).U)
1658 #define HW_DMA_SEEI_WR(x, v) (HW_DMA_SEEI(x).U = (v))
1662 * Constants & macros for individual DMA_SEEI bitfields
1666 * @name Register DMA_SEEI, field SEEI[3:0] (WORZ)
1668 * Sets the corresponding bit in EEI
1671 #define BP_DMA_SEEI_SEEI (0U) /*!< Bit position for DMA_SEEI_SEEI. */
1672 #define BM_DMA_SEEI_SEEI (0x0FU) /*!< Bit mask for DMA_SEEI_SEEI. */
1673 #define BS_DMA_SEEI_SEEI (4U) /*!< Bit field size in bits for DMA_SEEI_SEEI. */
1675 /*! @brief Format value for bitfield DMA_SEEI_SEEI. */
1676 #define BF_DMA_SEEI_SEEI(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SEEI_SEEI) & BM_DMA_SEEI_SEEI)
1678 /*! @brief Set the SEEI field to a new value. */
1679 #define BW_DMA_SEEI_SEEI(x, v) (HW_DMA_SEEI_WR(x, (HW_DMA_SEEI_RD(x) & ~BM_DMA_SEEI_SEEI) | BF_DMA_SEEI_SEEI(v)))
1683 * @name Register DMA_SEEI, field SAEE[6] (WORZ)
1686 * - 0 - Set only the EEI bit specified in the SEEI field.
1687 * - 1 - Sets all bits in EEI
1690 #define BP_DMA_SEEI_SAEE (6U) /*!< Bit position for DMA_SEEI_SAEE. */
1691 #define BM_DMA_SEEI_SAEE (0x40U) /*!< Bit mask for DMA_SEEI_SAEE. */
1692 #define BS_DMA_SEEI_SAEE (1U) /*!< Bit field size in bits for DMA_SEEI_SAEE. */
1694 /*! @brief Format value for bitfield DMA_SEEI_SAEE. */
1695 #define BF_DMA_SEEI_SAEE(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SEEI_SAEE) & BM_DMA_SEEI_SAEE)
1697 /*! @brief Set the SAEE field to a new value. */
1698 #define BW_DMA_SEEI_SAEE(x, v) (BITBAND_ACCESS8(HW_DMA_SEEI_ADDR(x), BP_DMA_SEEI_SAEE) = (v))
1702 * @name Register DMA_SEEI, field NOP[7] (WORZ)
1705 * - 0 - Normal operation
1706 * - 1 - No operation, ignore the other bits in this register
1709 #define BP_DMA_SEEI_NOP (7U) /*!< Bit position for DMA_SEEI_NOP. */
1710 #define BM_DMA_SEEI_NOP (0x80U) /*!< Bit mask for DMA_SEEI_NOP. */
1711 #define BS_DMA_SEEI_NOP (1U) /*!< Bit field size in bits for DMA_SEEI_NOP. */
1713 /*! @brief Format value for bitfield DMA_SEEI_NOP. */
1714 #define BF_DMA_SEEI_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SEEI_NOP) & BM_DMA_SEEI_NOP)
1716 /*! @brief Set the NOP field to a new value. */
1717 #define BW_DMA_SEEI_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_SEEI_ADDR(x), BP_DMA_SEEI_NOP) = (v))
1720 /*******************************************************************************
1721 * HW_DMA_CERQ - Clear Enable Request Register
1722 ******************************************************************************/
1725 * @brief HW_DMA_CERQ - Clear Enable Request Register (WO)
1727 * Reset value: 0x00U
1729 * The CERQ provides a simple memory-mapped mechanism to clear a given bit in
1730 * the ERQ to disable the DMA request for a given channel. The data value on a
1731 * register write causes the corresponding bit in the ERQ to be cleared. Setting the
1732 * CAER bit provides a global clear function, forcing the entire contents of the
1733 * ERQ to be cleared, disabling all DMA request inputs. If NOP is set, the
1734 * command is ignored. This allows you to write multiple-byte registers as a 32-bit
1735 * word. Reads of this register return all zeroes.
1737 typedef union _hw_dma_cerq
1740 struct _hw_dma_cerq_bitfields
1742 uint8_t CERQ
: 4; /*!< [3:0] Clear Enable Request */
1743 uint8_t RESERVED0
: 2; /*!< [5:4] */
1744 uint8_t CAER
: 1; /*!< [6] Clear All Enable Requests */
1745 uint8_t NOP
: 1; /*!< [7] No Op enable */
1750 * @name Constants and macros for entire DMA_CERQ register
1753 #define HW_DMA_CERQ_ADDR(x) ((x) + 0x1AU)
1755 #define HW_DMA_CERQ(x) (*(__O hw_dma_cerq_t *) HW_DMA_CERQ_ADDR(x))
1756 #define HW_DMA_CERQ_RD(x) (HW_DMA_CERQ(x).U)
1757 #define HW_DMA_CERQ_WR(x, v) (HW_DMA_CERQ(x).U = (v))
1761 * Constants & macros for individual DMA_CERQ bitfields
1765 * @name Register DMA_CERQ, field CERQ[3:0] (WORZ)
1767 * Clears the corresponding bit in ERQ
1770 #define BP_DMA_CERQ_CERQ (0U) /*!< Bit position for DMA_CERQ_CERQ. */
1771 #define BM_DMA_CERQ_CERQ (0x0FU) /*!< Bit mask for DMA_CERQ_CERQ. */
1772 #define BS_DMA_CERQ_CERQ (4U) /*!< Bit field size in bits for DMA_CERQ_CERQ. */
1774 /*! @brief Format value for bitfield DMA_CERQ_CERQ. */
1775 #define BF_DMA_CERQ_CERQ(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERQ_CERQ) & BM_DMA_CERQ_CERQ)
1777 /*! @brief Set the CERQ field to a new value. */
1778 #define BW_DMA_CERQ_CERQ(x, v) (HW_DMA_CERQ_WR(x, (HW_DMA_CERQ_RD(x) & ~BM_DMA_CERQ_CERQ) | BF_DMA_CERQ_CERQ(v)))
1782 * @name Register DMA_CERQ, field CAER[6] (WORZ)
1785 * - 0 - Clear only the ERQ bit specified in the CERQ field
1786 * - 1 - Clear all bits in ERQ
1789 #define BP_DMA_CERQ_CAER (6U) /*!< Bit position for DMA_CERQ_CAER. */
1790 #define BM_DMA_CERQ_CAER (0x40U) /*!< Bit mask for DMA_CERQ_CAER. */
1791 #define BS_DMA_CERQ_CAER (1U) /*!< Bit field size in bits for DMA_CERQ_CAER. */
1793 /*! @brief Format value for bitfield DMA_CERQ_CAER. */
1794 #define BF_DMA_CERQ_CAER(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERQ_CAER) & BM_DMA_CERQ_CAER)
1796 /*! @brief Set the CAER field to a new value. */
1797 #define BW_DMA_CERQ_CAER(x, v) (BITBAND_ACCESS8(HW_DMA_CERQ_ADDR(x), BP_DMA_CERQ_CAER) = (v))
1801 * @name Register DMA_CERQ, field NOP[7] (WORZ)
1804 * - 0 - Normal operation
1805 * - 1 - No operation, ignore the other bits in this register
1808 #define BP_DMA_CERQ_NOP (7U) /*!< Bit position for DMA_CERQ_NOP. */
1809 #define BM_DMA_CERQ_NOP (0x80U) /*!< Bit mask for DMA_CERQ_NOP. */
1810 #define BS_DMA_CERQ_NOP (1U) /*!< Bit field size in bits for DMA_CERQ_NOP. */
1812 /*! @brief Format value for bitfield DMA_CERQ_NOP. */
1813 #define BF_DMA_CERQ_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERQ_NOP) & BM_DMA_CERQ_NOP)
1815 /*! @brief Set the NOP field to a new value. */
1816 #define BW_DMA_CERQ_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CERQ_ADDR(x), BP_DMA_CERQ_NOP) = (v))
1819 /*******************************************************************************
1820 * HW_DMA_SERQ - Set Enable Request Register
1821 ******************************************************************************/
1824 * @brief HW_DMA_SERQ - Set Enable Request Register (WO)
1826 * Reset value: 0x00U
1828 * The SERQ provides a simple memory-mapped mechanism to set a given bit in the
1829 * ERQ to enable the DMA request for a given channel. The data value on a
1830 * register write causes the corresponding bit in the ERQ to be set. Setting the SAER
1831 * bit provides a global set function, forcing the entire contents of ERQ to be
1832 * set. If the NOP bit is set, the command is ignored. This allows you to write
1833 * multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
1835 typedef union _hw_dma_serq
1838 struct _hw_dma_serq_bitfields
1840 uint8_t SERQ
: 4; /*!< [3:0] Set enable request */
1841 uint8_t RESERVED0
: 2; /*!< [5:4] */
1842 uint8_t SAER
: 1; /*!< [6] Set All Enable Requests */
1843 uint8_t NOP
: 1; /*!< [7] No Op enable */
1848 * @name Constants and macros for entire DMA_SERQ register
1851 #define HW_DMA_SERQ_ADDR(x) ((x) + 0x1BU)
1853 #define HW_DMA_SERQ(x) (*(__O hw_dma_serq_t *) HW_DMA_SERQ_ADDR(x))
1854 #define HW_DMA_SERQ_RD(x) (HW_DMA_SERQ(x).U)
1855 #define HW_DMA_SERQ_WR(x, v) (HW_DMA_SERQ(x).U = (v))
1859 * Constants & macros for individual DMA_SERQ bitfields
1863 * @name Register DMA_SERQ, field SERQ[3:0] (WORZ)
1865 * Sets the corresponding bit in ERQ
1868 #define BP_DMA_SERQ_SERQ (0U) /*!< Bit position for DMA_SERQ_SERQ. */
1869 #define BM_DMA_SERQ_SERQ (0x0FU) /*!< Bit mask for DMA_SERQ_SERQ. */
1870 #define BS_DMA_SERQ_SERQ (4U) /*!< Bit field size in bits for DMA_SERQ_SERQ. */
1872 /*! @brief Format value for bitfield DMA_SERQ_SERQ. */
1873 #define BF_DMA_SERQ_SERQ(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SERQ_SERQ) & BM_DMA_SERQ_SERQ)
1875 /*! @brief Set the SERQ field to a new value. */
1876 #define BW_DMA_SERQ_SERQ(x, v) (HW_DMA_SERQ_WR(x, (HW_DMA_SERQ_RD(x) & ~BM_DMA_SERQ_SERQ) | BF_DMA_SERQ_SERQ(v)))
1880 * @name Register DMA_SERQ, field SAER[6] (WORZ)
1883 * - 0 - Set only the ERQ bit specified in the SERQ field
1884 * - 1 - Set all bits in ERQ
1887 #define BP_DMA_SERQ_SAER (6U) /*!< Bit position for DMA_SERQ_SAER. */
1888 #define BM_DMA_SERQ_SAER (0x40U) /*!< Bit mask for DMA_SERQ_SAER. */
1889 #define BS_DMA_SERQ_SAER (1U) /*!< Bit field size in bits for DMA_SERQ_SAER. */
1891 /*! @brief Format value for bitfield DMA_SERQ_SAER. */
1892 #define BF_DMA_SERQ_SAER(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SERQ_SAER) & BM_DMA_SERQ_SAER)
1894 /*! @brief Set the SAER field to a new value. */
1895 #define BW_DMA_SERQ_SAER(x, v) (BITBAND_ACCESS8(HW_DMA_SERQ_ADDR(x), BP_DMA_SERQ_SAER) = (v))
1899 * @name Register DMA_SERQ, field NOP[7] (WORZ)
1902 * - 0 - Normal operation
1903 * - 1 - No operation, ignore the other bits in this register
1906 #define BP_DMA_SERQ_NOP (7U) /*!< Bit position for DMA_SERQ_NOP. */
1907 #define BM_DMA_SERQ_NOP (0x80U) /*!< Bit mask for DMA_SERQ_NOP. */
1908 #define BS_DMA_SERQ_NOP (1U) /*!< Bit field size in bits for DMA_SERQ_NOP. */
1910 /*! @brief Format value for bitfield DMA_SERQ_NOP. */
1911 #define BF_DMA_SERQ_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SERQ_NOP) & BM_DMA_SERQ_NOP)
1913 /*! @brief Set the NOP field to a new value. */
1914 #define BW_DMA_SERQ_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_SERQ_ADDR(x), BP_DMA_SERQ_NOP) = (v))
1917 /*******************************************************************************
1918 * HW_DMA_CDNE - Clear DONE Status Bit Register
1919 ******************************************************************************/
1922 * @brief HW_DMA_CDNE - Clear DONE Status Bit Register (WO)
1924 * Reset value: 0x00U
1926 * The CDNE provides a simple memory-mapped mechanism to clear the DONE bit in
1927 * the TCD of the given channel. The data value on a register write causes the
1928 * DONE bit in the corresponding transfer control descriptor to be cleared. Setting
1929 * the CADN bit provides a global clear function, forcing all DONE bits to be
1930 * cleared. If the NOP bit is set, the command is ignored. This allows you to write
1931 * multiple-byte registers as a 32-bit word. Reads of this register return all
1934 typedef union _hw_dma_cdne
1937 struct _hw_dma_cdne_bitfields
1939 uint8_t CDNE
: 4; /*!< [3:0] Clear DONE Bit */
1940 uint8_t RESERVED0
: 2; /*!< [5:4] */
1941 uint8_t CADN
: 1; /*!< [6] Clears All DONE Bits */
1942 uint8_t NOP
: 1; /*!< [7] No Op enable */
1947 * @name Constants and macros for entire DMA_CDNE register
1950 #define HW_DMA_CDNE_ADDR(x) ((x) + 0x1CU)
1952 #define HW_DMA_CDNE(x) (*(__O hw_dma_cdne_t *) HW_DMA_CDNE_ADDR(x))
1953 #define HW_DMA_CDNE_RD(x) (HW_DMA_CDNE(x).U)
1954 #define HW_DMA_CDNE_WR(x, v) (HW_DMA_CDNE(x).U = (v))
1958 * Constants & macros for individual DMA_CDNE bitfields
1962 * @name Register DMA_CDNE, field CDNE[3:0] (WORZ)
1964 * Clears the corresponding bit in TCDn_CSR[DONE]
1967 #define BP_DMA_CDNE_CDNE (0U) /*!< Bit position for DMA_CDNE_CDNE. */
1968 #define BM_DMA_CDNE_CDNE (0x0FU) /*!< Bit mask for DMA_CDNE_CDNE. */
1969 #define BS_DMA_CDNE_CDNE (4U) /*!< Bit field size in bits for DMA_CDNE_CDNE. */
1971 /*! @brief Format value for bitfield DMA_CDNE_CDNE. */
1972 #define BF_DMA_CDNE_CDNE(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CDNE_CDNE) & BM_DMA_CDNE_CDNE)
1974 /*! @brief Set the CDNE field to a new value. */
1975 #define BW_DMA_CDNE_CDNE(x, v) (HW_DMA_CDNE_WR(x, (HW_DMA_CDNE_RD(x) & ~BM_DMA_CDNE_CDNE) | BF_DMA_CDNE_CDNE(v)))
1979 * @name Register DMA_CDNE, field CADN[6] (WORZ)
1982 * - 0 - Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
1983 * - 1 - Clears all bits in TCDn_CSR[DONE]
1986 #define BP_DMA_CDNE_CADN (6U) /*!< Bit position for DMA_CDNE_CADN. */
1987 #define BM_DMA_CDNE_CADN (0x40U) /*!< Bit mask for DMA_CDNE_CADN. */
1988 #define BS_DMA_CDNE_CADN (1U) /*!< Bit field size in bits for DMA_CDNE_CADN. */
1990 /*! @brief Format value for bitfield DMA_CDNE_CADN. */
1991 #define BF_DMA_CDNE_CADN(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CDNE_CADN) & BM_DMA_CDNE_CADN)
1993 /*! @brief Set the CADN field to a new value. */
1994 #define BW_DMA_CDNE_CADN(x, v) (BITBAND_ACCESS8(HW_DMA_CDNE_ADDR(x), BP_DMA_CDNE_CADN) = (v))
1998 * @name Register DMA_CDNE, field NOP[7] (WORZ)
2001 * - 0 - Normal operation
2002 * - 1 - No operation, ignore the other bits in this register
2005 #define BP_DMA_CDNE_NOP (7U) /*!< Bit position for DMA_CDNE_NOP. */
2006 #define BM_DMA_CDNE_NOP (0x80U) /*!< Bit mask for DMA_CDNE_NOP. */
2007 #define BS_DMA_CDNE_NOP (1U) /*!< Bit field size in bits for DMA_CDNE_NOP. */
2009 /*! @brief Format value for bitfield DMA_CDNE_NOP. */
2010 #define BF_DMA_CDNE_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CDNE_NOP) & BM_DMA_CDNE_NOP)
2012 /*! @brief Set the NOP field to a new value. */
2013 #define BW_DMA_CDNE_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CDNE_ADDR(x), BP_DMA_CDNE_NOP) = (v))
2016 /*******************************************************************************
2017 * HW_DMA_SSRT - Set START Bit Register
2018 ******************************************************************************/
2021 * @brief HW_DMA_SSRT - Set START Bit Register (WO)
2023 * Reset value: 0x00U
2025 * The SSRT provides a simple memory-mapped mechanism to set the START bit in
2026 * the TCD of the given channel. The data value on a register write causes the
2027 * START bit in the corresponding transfer control descriptor to be set. Setting the
2028 * SAST bit provides a global set function, forcing all START bits to be set. If
2029 * the NOP bit is set, the command is ignored. This allows you to write
2030 * multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
2032 typedef union _hw_dma_ssrt
2035 struct _hw_dma_ssrt_bitfields
2037 uint8_t SSRT
: 4; /*!< [3:0] Set START Bit */
2038 uint8_t RESERVED0
: 2; /*!< [5:4] */
2039 uint8_t SAST
: 1; /*!< [6] Set All START Bits (activates all
2041 uint8_t NOP
: 1; /*!< [7] No Op enable */
2046 * @name Constants and macros for entire DMA_SSRT register
2049 #define HW_DMA_SSRT_ADDR(x) ((x) + 0x1DU)
2051 #define HW_DMA_SSRT(x) (*(__O hw_dma_ssrt_t *) HW_DMA_SSRT_ADDR(x))
2052 #define HW_DMA_SSRT_RD(x) (HW_DMA_SSRT(x).U)
2053 #define HW_DMA_SSRT_WR(x, v) (HW_DMA_SSRT(x).U = (v))
2057 * Constants & macros for individual DMA_SSRT bitfields
2061 * @name Register DMA_SSRT, field SSRT[3:0] (WORZ)
2063 * Sets the corresponding bit in TCDn_CSR[START]
2066 #define BP_DMA_SSRT_SSRT (0U) /*!< Bit position for DMA_SSRT_SSRT. */
2067 #define BM_DMA_SSRT_SSRT (0x0FU) /*!< Bit mask for DMA_SSRT_SSRT. */
2068 #define BS_DMA_SSRT_SSRT (4U) /*!< Bit field size in bits for DMA_SSRT_SSRT. */
2070 /*! @brief Format value for bitfield DMA_SSRT_SSRT. */
2071 #define BF_DMA_SSRT_SSRT(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SSRT_SSRT) & BM_DMA_SSRT_SSRT)
2073 /*! @brief Set the SSRT field to a new value. */
2074 #define BW_DMA_SSRT_SSRT(x, v) (HW_DMA_SSRT_WR(x, (HW_DMA_SSRT_RD(x) & ~BM_DMA_SSRT_SSRT) | BF_DMA_SSRT_SSRT(v)))
2078 * @name Register DMA_SSRT, field SAST[6] (WORZ)
2081 * - 0 - Set only the TCDn_CSR[START] bit specified in the SSRT field
2082 * - 1 - Set all bits in TCDn_CSR[START]
2085 #define BP_DMA_SSRT_SAST (6U) /*!< Bit position for DMA_SSRT_SAST. */
2086 #define BM_DMA_SSRT_SAST (0x40U) /*!< Bit mask for DMA_SSRT_SAST. */
2087 #define BS_DMA_SSRT_SAST (1U) /*!< Bit field size in bits for DMA_SSRT_SAST. */
2089 /*! @brief Format value for bitfield DMA_SSRT_SAST. */
2090 #define BF_DMA_SSRT_SAST(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SSRT_SAST) & BM_DMA_SSRT_SAST)
2092 /*! @brief Set the SAST field to a new value. */
2093 #define BW_DMA_SSRT_SAST(x, v) (BITBAND_ACCESS8(HW_DMA_SSRT_ADDR(x), BP_DMA_SSRT_SAST) = (v))
2097 * @name Register DMA_SSRT, field NOP[7] (WORZ)
2100 * - 0 - Normal operation
2101 * - 1 - No operation, ignore the other bits in this register
2104 #define BP_DMA_SSRT_NOP (7U) /*!< Bit position for DMA_SSRT_NOP. */
2105 #define BM_DMA_SSRT_NOP (0x80U) /*!< Bit mask for DMA_SSRT_NOP. */
2106 #define BS_DMA_SSRT_NOP (1U) /*!< Bit field size in bits for DMA_SSRT_NOP. */
2108 /*! @brief Format value for bitfield DMA_SSRT_NOP. */
2109 #define BF_DMA_SSRT_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SSRT_NOP) & BM_DMA_SSRT_NOP)
2111 /*! @brief Set the NOP field to a new value. */
2112 #define BW_DMA_SSRT_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_SSRT_ADDR(x), BP_DMA_SSRT_NOP) = (v))
2115 /*******************************************************************************
2116 * HW_DMA_CERR - Clear Error Register
2117 ******************************************************************************/
2120 * @brief HW_DMA_CERR - Clear Error Register (WO)
2122 * Reset value: 0x00U
2124 * The CERR provides a simple memory-mapped mechanism to clear a given bit in
2125 * the ERR to disable the error condition flag for a given channel. The given value
2126 * on a register write causes the corresponding bit in the ERR to be cleared.
2127 * Setting the CAEI bit provides a global clear function, forcing the ERR contents
2128 * to be cleared, clearing all channel error indicators. If the NOP bit is set,
2129 * the command is ignored. This allows you to write multiple-byte registers as a
2130 * 32-bit word. Reads of this register return all zeroes.
2132 typedef union _hw_dma_cerr
2135 struct _hw_dma_cerr_bitfields
2137 uint8_t CERR
: 4; /*!< [3:0] Clear Error Indicator */
2138 uint8_t RESERVED0
: 2; /*!< [5:4] */
2139 uint8_t CAEI
: 1; /*!< [6] Clear All Error Indicators */
2140 uint8_t NOP
: 1; /*!< [7] No Op enable */
2145 * @name Constants and macros for entire DMA_CERR register
2148 #define HW_DMA_CERR_ADDR(x) ((x) + 0x1EU)
2150 #define HW_DMA_CERR(x) (*(__O hw_dma_cerr_t *) HW_DMA_CERR_ADDR(x))
2151 #define HW_DMA_CERR_RD(x) (HW_DMA_CERR(x).U)
2152 #define HW_DMA_CERR_WR(x, v) (HW_DMA_CERR(x).U = (v))
2156 * Constants & macros for individual DMA_CERR bitfields
2160 * @name Register DMA_CERR, field CERR[3:0] (WORZ)
2162 * Clears the corresponding bit in ERR
2165 #define BP_DMA_CERR_CERR (0U) /*!< Bit position for DMA_CERR_CERR. */
2166 #define BM_DMA_CERR_CERR (0x0FU) /*!< Bit mask for DMA_CERR_CERR. */
2167 #define BS_DMA_CERR_CERR (4U) /*!< Bit field size in bits for DMA_CERR_CERR. */
2169 /*! @brief Format value for bitfield DMA_CERR_CERR. */
2170 #define BF_DMA_CERR_CERR(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERR_CERR) & BM_DMA_CERR_CERR)
2172 /*! @brief Set the CERR field to a new value. */
2173 #define BW_DMA_CERR_CERR(x, v) (HW_DMA_CERR_WR(x, (HW_DMA_CERR_RD(x) & ~BM_DMA_CERR_CERR) | BF_DMA_CERR_CERR(v)))
2177 * @name Register DMA_CERR, field CAEI[6] (WORZ)
2180 * - 0 - Clear only the ERR bit specified in the CERR field
2181 * - 1 - Clear all bits in ERR
2184 #define BP_DMA_CERR_CAEI (6U) /*!< Bit position for DMA_CERR_CAEI. */
2185 #define BM_DMA_CERR_CAEI (0x40U) /*!< Bit mask for DMA_CERR_CAEI. */
2186 #define BS_DMA_CERR_CAEI (1U) /*!< Bit field size in bits for DMA_CERR_CAEI. */
2188 /*! @brief Format value for bitfield DMA_CERR_CAEI. */
2189 #define BF_DMA_CERR_CAEI(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERR_CAEI) & BM_DMA_CERR_CAEI)
2191 /*! @brief Set the CAEI field to a new value. */
2192 #define BW_DMA_CERR_CAEI(x, v) (BITBAND_ACCESS8(HW_DMA_CERR_ADDR(x), BP_DMA_CERR_CAEI) = (v))
2196 * @name Register DMA_CERR, field NOP[7] (WORZ)
2199 * - 0 - Normal operation
2200 * - 1 - No operation, ignore the other bits in this register
2203 #define BP_DMA_CERR_NOP (7U) /*!< Bit position for DMA_CERR_NOP. */
2204 #define BM_DMA_CERR_NOP (0x80U) /*!< Bit mask for DMA_CERR_NOP. */
2205 #define BS_DMA_CERR_NOP (1U) /*!< Bit field size in bits for DMA_CERR_NOP. */
2207 /*! @brief Format value for bitfield DMA_CERR_NOP. */
2208 #define BF_DMA_CERR_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERR_NOP) & BM_DMA_CERR_NOP)
2210 /*! @brief Set the NOP field to a new value. */
2211 #define BW_DMA_CERR_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CERR_ADDR(x), BP_DMA_CERR_NOP) = (v))
2214 /*******************************************************************************
2215 * HW_DMA_CINT - Clear Interrupt Request Register
2216 ******************************************************************************/
2219 * @brief HW_DMA_CINT - Clear Interrupt Request Register (WO)
2221 * Reset value: 0x00U
2223 * The CINT provides a simple, memory-mapped mechanism to clear a given bit in
2224 * the INT to disable the interrupt request for a given channel. The given value
2225 * on a register write causes the corresponding bit in the INT to be cleared.
2226 * Setting the CAIR bit provides a global clear function, forcing the entire contents
2227 * of the INT to be cleared, disabling all DMA interrupt requests. If the NOP
2228 * bit is set, the command is ignored. This allows you to write multiple-byte
2229 * registers as a 32-bit word. Reads of this register return all zeroes.
2231 typedef union _hw_dma_cint
2234 struct _hw_dma_cint_bitfields
2236 uint8_t CINT
: 4; /*!< [3:0] Clear Interrupt Request */
2237 uint8_t RESERVED0
: 2; /*!< [5:4] */
2238 uint8_t CAIR
: 1; /*!< [6] Clear All Interrupt Requests */
2239 uint8_t NOP
: 1; /*!< [7] No Op enable */
2244 * @name Constants and macros for entire DMA_CINT register
2247 #define HW_DMA_CINT_ADDR(x) ((x) + 0x1FU)
2249 #define HW_DMA_CINT(x) (*(__O hw_dma_cint_t *) HW_DMA_CINT_ADDR(x))
2250 #define HW_DMA_CINT_RD(x) (HW_DMA_CINT(x).U)
2251 #define HW_DMA_CINT_WR(x, v) (HW_DMA_CINT(x).U = (v))
2255 * Constants & macros for individual DMA_CINT bitfields
2259 * @name Register DMA_CINT, field CINT[3:0] (WORZ)
2261 * Clears the corresponding bit in INT
2264 #define BP_DMA_CINT_CINT (0U) /*!< Bit position for DMA_CINT_CINT. */
2265 #define BM_DMA_CINT_CINT (0x0FU) /*!< Bit mask for DMA_CINT_CINT. */
2266 #define BS_DMA_CINT_CINT (4U) /*!< Bit field size in bits for DMA_CINT_CINT. */
2268 /*! @brief Format value for bitfield DMA_CINT_CINT. */
2269 #define BF_DMA_CINT_CINT(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CINT_CINT) & BM_DMA_CINT_CINT)
2271 /*! @brief Set the CINT field to a new value. */
2272 #define BW_DMA_CINT_CINT(x, v) (HW_DMA_CINT_WR(x, (HW_DMA_CINT_RD(x) & ~BM_DMA_CINT_CINT) | BF_DMA_CINT_CINT(v)))
2276 * @name Register DMA_CINT, field CAIR[6] (WORZ)
2279 * - 0 - Clear only the INT bit specified in the CINT field
2280 * - 1 - Clear all bits in INT
2283 #define BP_DMA_CINT_CAIR (6U) /*!< Bit position for DMA_CINT_CAIR. */
2284 #define BM_DMA_CINT_CAIR (0x40U) /*!< Bit mask for DMA_CINT_CAIR. */
2285 #define BS_DMA_CINT_CAIR (1U) /*!< Bit field size in bits for DMA_CINT_CAIR. */
2287 /*! @brief Format value for bitfield DMA_CINT_CAIR. */
2288 #define BF_DMA_CINT_CAIR(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CINT_CAIR) & BM_DMA_CINT_CAIR)
2290 /*! @brief Set the CAIR field to a new value. */
2291 #define BW_DMA_CINT_CAIR(x, v) (BITBAND_ACCESS8(HW_DMA_CINT_ADDR(x), BP_DMA_CINT_CAIR) = (v))
2295 * @name Register DMA_CINT, field NOP[7] (WORZ)
2298 * - 0 - Normal operation
2299 * - 1 - No operation, ignore the other bits in this register
2302 #define BP_DMA_CINT_NOP (7U) /*!< Bit position for DMA_CINT_NOP. */
2303 #define BM_DMA_CINT_NOP (0x80U) /*!< Bit mask for DMA_CINT_NOP. */
2304 #define BS_DMA_CINT_NOP (1U) /*!< Bit field size in bits for DMA_CINT_NOP. */
2306 /*! @brief Format value for bitfield DMA_CINT_NOP. */
2307 #define BF_DMA_CINT_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CINT_NOP) & BM_DMA_CINT_NOP)
2309 /*! @brief Set the NOP field to a new value. */
2310 #define BW_DMA_CINT_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CINT_ADDR(x), BP_DMA_CINT_NOP) = (v))
2313 /*******************************************************************************
2314 * HW_DMA_INT - Interrupt Request Register
2315 ******************************************************************************/
2318 * @brief HW_DMA_INT - Interrupt Request Register (RW)
2320 * Reset value: 0x00000000U
2322 * The INT register provides a bit map for the 16 channels signaling the
2323 * presence of an interrupt request for each channel. Depending on the appropriate bit
2324 * setting in the transfer-control descriptors, the eDMA engine generates an
2325 * interrupt on data transfer completion. The outputs of this register are directly
2326 * routed to the interrupt controller (INTC). During the interrupt-service routine
2327 * associated with any given channel, it is the software's responsibility to
2328 * clear the appropriate bit, negating the interrupt request. Typically, a write to
2329 * the CINT register in the interrupt service routine is used for this purpose.
2330 * The state of any given channel's interrupt request is directly affected by
2331 * writes to this register; it is also affected by writes to the CINT register. On
2332 * writes to INT, a 1 in any bit position clears the corresponding channel's
2333 * interrupt request. A zero in any bit position has no affect on the corresponding
2334 * channel's current interrupt status. The CINT register is provided so the interrupt
2335 * request for a single channel can easily be cleared without the need to
2336 * perform a read-modify-write sequence to the INT register.
2338 typedef union _hw_dma_int
2341 struct _hw_dma_int_bitfields
2343 uint32_t INT0
: 1; /*!< [0] Interrupt Request 0 */
2344 uint32_t INT1
: 1; /*!< [1] Interrupt Request 1 */
2345 uint32_t INT2
: 1; /*!< [2] Interrupt Request 2 */
2346 uint32_t INT3
: 1; /*!< [3] Interrupt Request 3 */
2347 uint32_t INT4
: 1; /*!< [4] Interrupt Request 4 */
2348 uint32_t INT5
: 1; /*!< [5] Interrupt Request 5 */
2349 uint32_t INT6
: 1; /*!< [6] Interrupt Request 6 */
2350 uint32_t INT7
: 1; /*!< [7] Interrupt Request 7 */
2351 uint32_t INT8
: 1; /*!< [8] Interrupt Request 8 */
2352 uint32_t INT9
: 1; /*!< [9] Interrupt Request 9 */
2353 uint32_t INT10
: 1; /*!< [10] Interrupt Request 10 */
2354 uint32_t INT11
: 1; /*!< [11] Interrupt Request 11 */
2355 uint32_t INT12
: 1; /*!< [12] Interrupt Request 12 */
2356 uint32_t INT13
: 1; /*!< [13] Interrupt Request 13 */
2357 uint32_t INT14
: 1; /*!< [14] Interrupt Request 14 */
2358 uint32_t INT15
: 1; /*!< [15] Interrupt Request 15 */
2359 uint32_t RESERVED0
: 16; /*!< [31:16] */
2364 * @name Constants and macros for entire DMA_INT register
2367 #define HW_DMA_INT_ADDR(x) ((x) + 0x24U)
2369 #define HW_DMA_INT(x) (*(__IO hw_dma_int_t *) HW_DMA_INT_ADDR(x))
2370 #define HW_DMA_INT_RD(x) (HW_DMA_INT(x).U)
2371 #define HW_DMA_INT_WR(x, v) (HW_DMA_INT(x).U = (v))
2372 #define HW_DMA_INT_SET(x, v) (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) | (v)))
2373 #define HW_DMA_INT_CLR(x, v) (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) & ~(v)))
2374 #define HW_DMA_INT_TOG(x, v) (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) ^ (v)))
2378 * Constants & macros for individual DMA_INT bitfields
2382 * @name Register DMA_INT, field INT0[0] (W1C)
2385 * - 0 - The interrupt request for corresponding channel is cleared
2386 * - 1 - The interrupt request for corresponding channel is active
2389 #define BP_DMA_INT_INT0 (0U) /*!< Bit position for DMA_INT_INT0. */
2390 #define BM_DMA_INT_INT0 (0x00000001U) /*!< Bit mask for DMA_INT_INT0. */
2391 #define BS_DMA_INT_INT0 (1U) /*!< Bit field size in bits for DMA_INT_INT0. */
2393 /*! @brief Read current value of the DMA_INT_INT0 field. */
2394 #define BR_DMA_INT_INT0(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT0))
2396 /*! @brief Format value for bitfield DMA_INT_INT0. */
2397 #define BF_DMA_INT_INT0(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT0) & BM_DMA_INT_INT0)
2399 /*! @brief Set the INT0 field to a new value. */
2400 #define BW_DMA_INT_INT0(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT0) = (v))
2404 * @name Register DMA_INT, field INT1[1] (W1C)
2407 * - 0 - The interrupt request for corresponding channel is cleared
2408 * - 1 - The interrupt request for corresponding channel is active
2411 #define BP_DMA_INT_INT1 (1U) /*!< Bit position for DMA_INT_INT1. */
2412 #define BM_DMA_INT_INT1 (0x00000002U) /*!< Bit mask for DMA_INT_INT1. */
2413 #define BS_DMA_INT_INT1 (1U) /*!< Bit field size in bits for DMA_INT_INT1. */
2415 /*! @brief Read current value of the DMA_INT_INT1 field. */
2416 #define BR_DMA_INT_INT1(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT1))
2418 /*! @brief Format value for bitfield DMA_INT_INT1. */
2419 #define BF_DMA_INT_INT1(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT1) & BM_DMA_INT_INT1)
2421 /*! @brief Set the INT1 field to a new value. */
2422 #define BW_DMA_INT_INT1(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT1) = (v))
2426 * @name Register DMA_INT, field INT2[2] (W1C)
2429 * - 0 - The interrupt request for corresponding channel is cleared
2430 * - 1 - The interrupt request for corresponding channel is active
2433 #define BP_DMA_INT_INT2 (2U) /*!< Bit position for DMA_INT_INT2. */
2434 #define BM_DMA_INT_INT2 (0x00000004U) /*!< Bit mask for DMA_INT_INT2. */
2435 #define BS_DMA_INT_INT2 (1U) /*!< Bit field size in bits for DMA_INT_INT2. */
2437 /*! @brief Read current value of the DMA_INT_INT2 field. */
2438 #define BR_DMA_INT_INT2(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT2))
2440 /*! @brief Format value for bitfield DMA_INT_INT2. */
2441 #define BF_DMA_INT_INT2(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT2) & BM_DMA_INT_INT2)
2443 /*! @brief Set the INT2 field to a new value. */
2444 #define BW_DMA_INT_INT2(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT2) = (v))
2448 * @name Register DMA_INT, field INT3[3] (W1C)
2451 * - 0 - The interrupt request for corresponding channel is cleared
2452 * - 1 - The interrupt request for corresponding channel is active
2455 #define BP_DMA_INT_INT3 (3U) /*!< Bit position for DMA_INT_INT3. */
2456 #define BM_DMA_INT_INT3 (0x00000008U) /*!< Bit mask for DMA_INT_INT3. */
2457 #define BS_DMA_INT_INT3 (1U) /*!< Bit field size in bits for DMA_INT_INT3. */
2459 /*! @brief Read current value of the DMA_INT_INT3 field. */
2460 #define BR_DMA_INT_INT3(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT3))
2462 /*! @brief Format value for bitfield DMA_INT_INT3. */
2463 #define BF_DMA_INT_INT3(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT3) & BM_DMA_INT_INT3)
2465 /*! @brief Set the INT3 field to a new value. */
2466 #define BW_DMA_INT_INT3(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT3) = (v))
2470 * @name Register DMA_INT, field INT4[4] (W1C)
2473 * - 0 - The interrupt request for corresponding channel is cleared
2474 * - 1 - The interrupt request for corresponding channel is active
2477 #define BP_DMA_INT_INT4 (4U) /*!< Bit position for DMA_INT_INT4. */
2478 #define BM_DMA_INT_INT4 (0x00000010U) /*!< Bit mask for DMA_INT_INT4. */
2479 #define BS_DMA_INT_INT4 (1U) /*!< Bit field size in bits for DMA_INT_INT4. */
2481 /*! @brief Read current value of the DMA_INT_INT4 field. */
2482 #define BR_DMA_INT_INT4(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT4))
2484 /*! @brief Format value for bitfield DMA_INT_INT4. */
2485 #define BF_DMA_INT_INT4(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT4) & BM_DMA_INT_INT4)
2487 /*! @brief Set the INT4 field to a new value. */
2488 #define BW_DMA_INT_INT4(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT4) = (v))
2492 * @name Register DMA_INT, field INT5[5] (W1C)
2495 * - 0 - The interrupt request for corresponding channel is cleared
2496 * - 1 - The interrupt request for corresponding channel is active
2499 #define BP_DMA_INT_INT5 (5U) /*!< Bit position for DMA_INT_INT5. */
2500 #define BM_DMA_INT_INT5 (0x00000020U) /*!< Bit mask for DMA_INT_INT5. */
2501 #define BS_DMA_INT_INT5 (1U) /*!< Bit field size in bits for DMA_INT_INT5. */
2503 /*! @brief Read current value of the DMA_INT_INT5 field. */
2504 #define BR_DMA_INT_INT5(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT5))
2506 /*! @brief Format value for bitfield DMA_INT_INT5. */
2507 #define BF_DMA_INT_INT5(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT5) & BM_DMA_INT_INT5)
2509 /*! @brief Set the INT5 field to a new value. */
2510 #define BW_DMA_INT_INT5(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT5) = (v))
2514 * @name Register DMA_INT, field INT6[6] (W1C)
2517 * - 0 - The interrupt request for corresponding channel is cleared
2518 * - 1 - The interrupt request for corresponding channel is active
2521 #define BP_DMA_INT_INT6 (6U) /*!< Bit position for DMA_INT_INT6. */
2522 #define BM_DMA_INT_INT6 (0x00000040U) /*!< Bit mask for DMA_INT_INT6. */
2523 #define BS_DMA_INT_INT6 (1U) /*!< Bit field size in bits for DMA_INT_INT6. */
2525 /*! @brief Read current value of the DMA_INT_INT6 field. */
2526 #define BR_DMA_INT_INT6(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT6))
2528 /*! @brief Format value for bitfield DMA_INT_INT6. */
2529 #define BF_DMA_INT_INT6(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT6) & BM_DMA_INT_INT6)
2531 /*! @brief Set the INT6 field to a new value. */
2532 #define BW_DMA_INT_INT6(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT6) = (v))
2536 * @name Register DMA_INT, field INT7[7] (W1C)
2539 * - 0 - The interrupt request for corresponding channel is cleared
2540 * - 1 - The interrupt request for corresponding channel is active
2543 #define BP_DMA_INT_INT7 (7U) /*!< Bit position for DMA_INT_INT7. */
2544 #define BM_DMA_INT_INT7 (0x00000080U) /*!< Bit mask for DMA_INT_INT7. */
2545 #define BS_DMA_INT_INT7 (1U) /*!< Bit field size in bits for DMA_INT_INT7. */
2547 /*! @brief Read current value of the DMA_INT_INT7 field. */
2548 #define BR_DMA_INT_INT7(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT7))
2550 /*! @brief Format value for bitfield DMA_INT_INT7. */
2551 #define BF_DMA_INT_INT7(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT7) & BM_DMA_INT_INT7)
2553 /*! @brief Set the INT7 field to a new value. */
2554 #define BW_DMA_INT_INT7(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT7) = (v))
2558 * @name Register DMA_INT, field INT8[8] (W1C)
2561 * - 0 - The interrupt request for corresponding channel is cleared
2562 * - 1 - The interrupt request for corresponding channel is active
2565 #define BP_DMA_INT_INT8 (8U) /*!< Bit position for DMA_INT_INT8. */
2566 #define BM_DMA_INT_INT8 (0x00000100U) /*!< Bit mask for DMA_INT_INT8. */
2567 #define BS_DMA_INT_INT8 (1U) /*!< Bit field size in bits for DMA_INT_INT8. */
2569 /*! @brief Read current value of the DMA_INT_INT8 field. */
2570 #define BR_DMA_INT_INT8(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT8))
2572 /*! @brief Format value for bitfield DMA_INT_INT8. */
2573 #define BF_DMA_INT_INT8(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT8) & BM_DMA_INT_INT8)
2575 /*! @brief Set the INT8 field to a new value. */
2576 #define BW_DMA_INT_INT8(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT8) = (v))
2580 * @name Register DMA_INT, field INT9[9] (W1C)
2583 * - 0 - The interrupt request for corresponding channel is cleared
2584 * - 1 - The interrupt request for corresponding channel is active
2587 #define BP_DMA_INT_INT9 (9U) /*!< Bit position for DMA_INT_INT9. */
2588 #define BM_DMA_INT_INT9 (0x00000200U) /*!< Bit mask for DMA_INT_INT9. */
2589 #define BS_DMA_INT_INT9 (1U) /*!< Bit field size in bits for DMA_INT_INT9. */
2591 /*! @brief Read current value of the DMA_INT_INT9 field. */
2592 #define BR_DMA_INT_INT9(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT9))
2594 /*! @brief Format value for bitfield DMA_INT_INT9. */
2595 #define BF_DMA_INT_INT9(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT9) & BM_DMA_INT_INT9)
2597 /*! @brief Set the INT9 field to a new value. */
2598 #define BW_DMA_INT_INT9(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT9) = (v))
2602 * @name Register DMA_INT, field INT10[10] (W1C)
2605 * - 0 - The interrupt request for corresponding channel is cleared
2606 * - 1 - The interrupt request for corresponding channel is active
2609 #define BP_DMA_INT_INT10 (10U) /*!< Bit position for DMA_INT_INT10. */
2610 #define BM_DMA_INT_INT10 (0x00000400U) /*!< Bit mask for DMA_INT_INT10. */
2611 #define BS_DMA_INT_INT10 (1U) /*!< Bit field size in bits for DMA_INT_INT10. */
2613 /*! @brief Read current value of the DMA_INT_INT10 field. */
2614 #define BR_DMA_INT_INT10(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT10))
2616 /*! @brief Format value for bitfield DMA_INT_INT10. */
2617 #define BF_DMA_INT_INT10(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT10) & BM_DMA_INT_INT10)
2619 /*! @brief Set the INT10 field to a new value. */
2620 #define BW_DMA_INT_INT10(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT10) = (v))
2624 * @name Register DMA_INT, field INT11[11] (W1C)
2627 * - 0 - The interrupt request for corresponding channel is cleared
2628 * - 1 - The interrupt request for corresponding channel is active
2631 #define BP_DMA_INT_INT11 (11U) /*!< Bit position for DMA_INT_INT11. */
2632 #define BM_DMA_INT_INT11 (0x00000800U) /*!< Bit mask for DMA_INT_INT11. */
2633 #define BS_DMA_INT_INT11 (1U) /*!< Bit field size in bits for DMA_INT_INT11. */
2635 /*! @brief Read current value of the DMA_INT_INT11 field. */
2636 #define BR_DMA_INT_INT11(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT11))
2638 /*! @brief Format value for bitfield DMA_INT_INT11. */
2639 #define BF_DMA_INT_INT11(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT11) & BM_DMA_INT_INT11)
2641 /*! @brief Set the INT11 field to a new value. */
2642 #define BW_DMA_INT_INT11(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT11) = (v))
2646 * @name Register DMA_INT, field INT12[12] (W1C)
2649 * - 0 - The interrupt request for corresponding channel is cleared
2650 * - 1 - The interrupt request for corresponding channel is active
2653 #define BP_DMA_INT_INT12 (12U) /*!< Bit position for DMA_INT_INT12. */
2654 #define BM_DMA_INT_INT12 (0x00001000U) /*!< Bit mask for DMA_INT_INT12. */
2655 #define BS_DMA_INT_INT12 (1U) /*!< Bit field size in bits for DMA_INT_INT12. */
2657 /*! @brief Read current value of the DMA_INT_INT12 field. */
2658 #define BR_DMA_INT_INT12(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT12))
2660 /*! @brief Format value for bitfield DMA_INT_INT12. */
2661 #define BF_DMA_INT_INT12(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT12) & BM_DMA_INT_INT12)
2663 /*! @brief Set the INT12 field to a new value. */
2664 #define BW_DMA_INT_INT12(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT12) = (v))
2668 * @name Register DMA_INT, field INT13[13] (W1C)
2671 * - 0 - The interrupt request for corresponding channel is cleared
2672 * - 1 - The interrupt request for corresponding channel is active
2675 #define BP_DMA_INT_INT13 (13U) /*!< Bit position for DMA_INT_INT13. */
2676 #define BM_DMA_INT_INT13 (0x00002000U) /*!< Bit mask for DMA_INT_INT13. */
2677 #define BS_DMA_INT_INT13 (1U) /*!< Bit field size in bits for DMA_INT_INT13. */
2679 /*! @brief Read current value of the DMA_INT_INT13 field. */
2680 #define BR_DMA_INT_INT13(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT13))
2682 /*! @brief Format value for bitfield DMA_INT_INT13. */
2683 #define BF_DMA_INT_INT13(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT13) & BM_DMA_INT_INT13)
2685 /*! @brief Set the INT13 field to a new value. */
2686 #define BW_DMA_INT_INT13(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT13) = (v))
2690 * @name Register DMA_INT, field INT14[14] (W1C)
2693 * - 0 - The interrupt request for corresponding channel is cleared
2694 * - 1 - The interrupt request for corresponding channel is active
2697 #define BP_DMA_INT_INT14 (14U) /*!< Bit position for DMA_INT_INT14. */
2698 #define BM_DMA_INT_INT14 (0x00004000U) /*!< Bit mask for DMA_INT_INT14. */
2699 #define BS_DMA_INT_INT14 (1U) /*!< Bit field size in bits for DMA_INT_INT14. */
2701 /*! @brief Read current value of the DMA_INT_INT14 field. */
2702 #define BR_DMA_INT_INT14(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT14))
2704 /*! @brief Format value for bitfield DMA_INT_INT14. */
2705 #define BF_DMA_INT_INT14(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT14) & BM_DMA_INT_INT14)
2707 /*! @brief Set the INT14 field to a new value. */
2708 #define BW_DMA_INT_INT14(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT14) = (v))
2712 * @name Register DMA_INT, field INT15[15] (W1C)
2715 * - 0 - The interrupt request for corresponding channel is cleared
2716 * - 1 - The interrupt request for corresponding channel is active
2719 #define BP_DMA_INT_INT15 (15U) /*!< Bit position for DMA_INT_INT15. */
2720 #define BM_DMA_INT_INT15 (0x00008000U) /*!< Bit mask for DMA_INT_INT15. */
2721 #define BS_DMA_INT_INT15 (1U) /*!< Bit field size in bits for DMA_INT_INT15. */
2723 /*! @brief Read current value of the DMA_INT_INT15 field. */
2724 #define BR_DMA_INT_INT15(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT15))
2726 /*! @brief Format value for bitfield DMA_INT_INT15. */
2727 #define BF_DMA_INT_INT15(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT15) & BM_DMA_INT_INT15)
2729 /*! @brief Set the INT15 field to a new value. */
2730 #define BW_DMA_INT_INT15(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT15) = (v))
2733 /*******************************************************************************
2734 * HW_DMA_ERR - Error Register
2735 ******************************************************************************/
2738 * @brief HW_DMA_ERR - Error Register (RW)
2740 * Reset value: 0x00000000U
2742 * The ERR provides a bit map for the 16 channels, signaling the presence of an
2743 * error for each channel. The eDMA engine signals the occurrence of an error
2744 * condition by setting the appropriate bit in this register. The outputs of this
2745 * register are enabled by the contents of the EEI, and then routed to the
2746 * interrupt controller. During the execution of the interrupt-service routine associated
2747 * with any DMA errors, it is software's responsibility to clear the appropriate
2748 * bit, negating the error-interrupt request. Typically, a write to the CERR in
2749 * the interrupt-service routine is used for this purpose. The normal DMA channel
2750 * completion indicators (setting the transfer control descriptor DONE flag and
2751 * the possible assertion of an interrupt request) are not affected when an error
2752 * is detected. The contents of this register can also be polled because a
2753 * non-zero value indicates the presence of a channel error regardless of the state of
2754 * the EEI. The state of any given channel's error indicators is affected by
2755 * writes to this register; it is also affected by writes to the CERR. On writes to
2756 * the ERR, a one in any bit position clears the corresponding channel's error
2757 * status. A zero in any bit position has no affect on the corresponding channel's
2758 * current error status. The CERR is provided so the error indicator for a single
2759 * channel can easily be cleared.
2761 typedef union _hw_dma_err
2764 struct _hw_dma_err_bitfields
2766 uint32_t ERR0
: 1; /*!< [0] Error In Channel 0 */
2767 uint32_t ERR1
: 1; /*!< [1] Error In Channel 1 */
2768 uint32_t ERR2
: 1; /*!< [2] Error In Channel 2 */
2769 uint32_t ERR3
: 1; /*!< [3] Error In Channel 3 */
2770 uint32_t ERR4
: 1; /*!< [4] Error In Channel 4 */
2771 uint32_t ERR5
: 1; /*!< [5] Error In Channel 5 */
2772 uint32_t ERR6
: 1; /*!< [6] Error In Channel 6 */
2773 uint32_t ERR7
: 1; /*!< [7] Error In Channel 7 */
2774 uint32_t ERR8
: 1; /*!< [8] Error In Channel 8 */
2775 uint32_t ERR9
: 1; /*!< [9] Error In Channel 9 */
2776 uint32_t ERR10
: 1; /*!< [10] Error In Channel 10 */
2777 uint32_t ERR11
: 1; /*!< [11] Error In Channel 11 */
2778 uint32_t ERR12
: 1; /*!< [12] Error In Channel 12 */
2779 uint32_t ERR13
: 1; /*!< [13] Error In Channel 13 */
2780 uint32_t ERR14
: 1; /*!< [14] Error In Channel 14 */
2781 uint32_t ERR15
: 1; /*!< [15] Error In Channel 15 */
2782 uint32_t RESERVED0
: 16; /*!< [31:16] */
2787 * @name Constants and macros for entire DMA_ERR register
2790 #define HW_DMA_ERR_ADDR(x) ((x) + 0x2CU)
2792 #define HW_DMA_ERR(x) (*(__IO hw_dma_err_t *) HW_DMA_ERR_ADDR(x))
2793 #define HW_DMA_ERR_RD(x) (HW_DMA_ERR(x).U)
2794 #define HW_DMA_ERR_WR(x, v) (HW_DMA_ERR(x).U = (v))
2795 #define HW_DMA_ERR_SET(x, v) (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) | (v)))
2796 #define HW_DMA_ERR_CLR(x, v) (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) & ~(v)))
2797 #define HW_DMA_ERR_TOG(x, v) (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) ^ (v)))
2801 * Constants & macros for individual DMA_ERR bitfields
2805 * @name Register DMA_ERR, field ERR0[0] (W1C)
2808 * - 0 - An error in the corresponding channel has not occurred
2809 * - 1 - An error in the corresponding channel has occurred
2812 #define BP_DMA_ERR_ERR0 (0U) /*!< Bit position for DMA_ERR_ERR0. */
2813 #define BM_DMA_ERR_ERR0 (0x00000001U) /*!< Bit mask for DMA_ERR_ERR0. */
2814 #define BS_DMA_ERR_ERR0 (1U) /*!< Bit field size in bits for DMA_ERR_ERR0. */
2816 /*! @brief Read current value of the DMA_ERR_ERR0 field. */
2817 #define BR_DMA_ERR_ERR0(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR0))
2819 /*! @brief Format value for bitfield DMA_ERR_ERR0. */
2820 #define BF_DMA_ERR_ERR0(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR0) & BM_DMA_ERR_ERR0)
2822 /*! @brief Set the ERR0 field to a new value. */
2823 #define BW_DMA_ERR_ERR0(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR0) = (v))
2827 * @name Register DMA_ERR, field ERR1[1] (W1C)
2830 * - 0 - An error in the corresponding channel has not occurred
2831 * - 1 - An error in the corresponding channel has occurred
2834 #define BP_DMA_ERR_ERR1 (1U) /*!< Bit position for DMA_ERR_ERR1. */
2835 #define BM_DMA_ERR_ERR1 (0x00000002U) /*!< Bit mask for DMA_ERR_ERR1. */
2836 #define BS_DMA_ERR_ERR1 (1U) /*!< Bit field size in bits for DMA_ERR_ERR1. */
2838 /*! @brief Read current value of the DMA_ERR_ERR1 field. */
2839 #define BR_DMA_ERR_ERR1(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR1))
2841 /*! @brief Format value for bitfield DMA_ERR_ERR1. */
2842 #define BF_DMA_ERR_ERR1(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR1) & BM_DMA_ERR_ERR1)
2844 /*! @brief Set the ERR1 field to a new value. */
2845 #define BW_DMA_ERR_ERR1(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR1) = (v))
2849 * @name Register DMA_ERR, field ERR2[2] (W1C)
2852 * - 0 - An error in the corresponding channel has not occurred
2853 * - 1 - An error in the corresponding channel has occurred
2856 #define BP_DMA_ERR_ERR2 (2U) /*!< Bit position for DMA_ERR_ERR2. */
2857 #define BM_DMA_ERR_ERR2 (0x00000004U) /*!< Bit mask for DMA_ERR_ERR2. */
2858 #define BS_DMA_ERR_ERR2 (1U) /*!< Bit field size in bits for DMA_ERR_ERR2. */
2860 /*! @brief Read current value of the DMA_ERR_ERR2 field. */
2861 #define BR_DMA_ERR_ERR2(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR2))
2863 /*! @brief Format value for bitfield DMA_ERR_ERR2. */
2864 #define BF_DMA_ERR_ERR2(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR2) & BM_DMA_ERR_ERR2)
2866 /*! @brief Set the ERR2 field to a new value. */
2867 #define BW_DMA_ERR_ERR2(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR2) = (v))
2871 * @name Register DMA_ERR, field ERR3[3] (W1C)
2874 * - 0 - An error in the corresponding channel has not occurred
2875 * - 1 - An error in the corresponding channel has occurred
2878 #define BP_DMA_ERR_ERR3 (3U) /*!< Bit position for DMA_ERR_ERR3. */
2879 #define BM_DMA_ERR_ERR3 (0x00000008U) /*!< Bit mask for DMA_ERR_ERR3. */
2880 #define BS_DMA_ERR_ERR3 (1U) /*!< Bit field size in bits for DMA_ERR_ERR3. */
2882 /*! @brief Read current value of the DMA_ERR_ERR3 field. */
2883 #define BR_DMA_ERR_ERR3(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR3))
2885 /*! @brief Format value for bitfield DMA_ERR_ERR3. */
2886 #define BF_DMA_ERR_ERR3(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR3) & BM_DMA_ERR_ERR3)
2888 /*! @brief Set the ERR3 field to a new value. */
2889 #define BW_DMA_ERR_ERR3(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR3) = (v))
2893 * @name Register DMA_ERR, field ERR4[4] (W1C)
2896 * - 0 - An error in the corresponding channel has not occurred
2897 * - 1 - An error in the corresponding channel has occurred
2900 #define BP_DMA_ERR_ERR4 (4U) /*!< Bit position for DMA_ERR_ERR4. */
2901 #define BM_DMA_ERR_ERR4 (0x00000010U) /*!< Bit mask for DMA_ERR_ERR4. */
2902 #define BS_DMA_ERR_ERR4 (1U) /*!< Bit field size in bits for DMA_ERR_ERR4. */
2904 /*! @brief Read current value of the DMA_ERR_ERR4 field. */
2905 #define BR_DMA_ERR_ERR4(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR4))
2907 /*! @brief Format value for bitfield DMA_ERR_ERR4. */
2908 #define BF_DMA_ERR_ERR4(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR4) & BM_DMA_ERR_ERR4)
2910 /*! @brief Set the ERR4 field to a new value. */
2911 #define BW_DMA_ERR_ERR4(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR4) = (v))
2915 * @name Register DMA_ERR, field ERR5[5] (W1C)
2918 * - 0 - An error in the corresponding channel has not occurred
2919 * - 1 - An error in the corresponding channel has occurred
2922 #define BP_DMA_ERR_ERR5 (5U) /*!< Bit position for DMA_ERR_ERR5. */
2923 #define BM_DMA_ERR_ERR5 (0x00000020U) /*!< Bit mask for DMA_ERR_ERR5. */
2924 #define BS_DMA_ERR_ERR5 (1U) /*!< Bit field size in bits for DMA_ERR_ERR5. */
2926 /*! @brief Read current value of the DMA_ERR_ERR5 field. */
2927 #define BR_DMA_ERR_ERR5(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR5))
2929 /*! @brief Format value for bitfield DMA_ERR_ERR5. */
2930 #define BF_DMA_ERR_ERR5(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR5) & BM_DMA_ERR_ERR5)
2932 /*! @brief Set the ERR5 field to a new value. */
2933 #define BW_DMA_ERR_ERR5(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR5) = (v))
2937 * @name Register DMA_ERR, field ERR6[6] (W1C)
2940 * - 0 - An error in the corresponding channel has not occurred
2941 * - 1 - An error in the corresponding channel has occurred
2944 #define BP_DMA_ERR_ERR6 (6U) /*!< Bit position for DMA_ERR_ERR6. */
2945 #define BM_DMA_ERR_ERR6 (0x00000040U) /*!< Bit mask for DMA_ERR_ERR6. */
2946 #define BS_DMA_ERR_ERR6 (1U) /*!< Bit field size in bits for DMA_ERR_ERR6. */
2948 /*! @brief Read current value of the DMA_ERR_ERR6 field. */
2949 #define BR_DMA_ERR_ERR6(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR6))
2951 /*! @brief Format value for bitfield DMA_ERR_ERR6. */
2952 #define BF_DMA_ERR_ERR6(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR6) & BM_DMA_ERR_ERR6)
2954 /*! @brief Set the ERR6 field to a new value. */
2955 #define BW_DMA_ERR_ERR6(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR6) = (v))
2959 * @name Register DMA_ERR, field ERR7[7] (W1C)
2962 * - 0 - An error in the corresponding channel has not occurred
2963 * - 1 - An error in the corresponding channel has occurred
2966 #define BP_DMA_ERR_ERR7 (7U) /*!< Bit position for DMA_ERR_ERR7. */
2967 #define BM_DMA_ERR_ERR7 (0x00000080U) /*!< Bit mask for DMA_ERR_ERR7. */
2968 #define BS_DMA_ERR_ERR7 (1U) /*!< Bit field size in bits for DMA_ERR_ERR7. */
2970 /*! @brief Read current value of the DMA_ERR_ERR7 field. */
2971 #define BR_DMA_ERR_ERR7(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR7))
2973 /*! @brief Format value for bitfield DMA_ERR_ERR7. */
2974 #define BF_DMA_ERR_ERR7(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR7) & BM_DMA_ERR_ERR7)
2976 /*! @brief Set the ERR7 field to a new value. */
2977 #define BW_DMA_ERR_ERR7(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR7) = (v))
2981 * @name Register DMA_ERR, field ERR8[8] (W1C)
2984 * - 0 - An error in the corresponding channel has not occurred
2985 * - 1 - An error in the corresponding channel has occurred
2988 #define BP_DMA_ERR_ERR8 (8U) /*!< Bit position for DMA_ERR_ERR8. */
2989 #define BM_DMA_ERR_ERR8 (0x00000100U) /*!< Bit mask for DMA_ERR_ERR8. */
2990 #define BS_DMA_ERR_ERR8 (1U) /*!< Bit field size in bits for DMA_ERR_ERR8. */
2992 /*! @brief Read current value of the DMA_ERR_ERR8 field. */
2993 #define BR_DMA_ERR_ERR8(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR8))
2995 /*! @brief Format value for bitfield DMA_ERR_ERR8. */
2996 #define BF_DMA_ERR_ERR8(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR8) & BM_DMA_ERR_ERR8)
2998 /*! @brief Set the ERR8 field to a new value. */
2999 #define BW_DMA_ERR_ERR8(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR8) = (v))
3003 * @name Register DMA_ERR, field ERR9[9] (W1C)
3006 * - 0 - An error in the corresponding channel has not occurred
3007 * - 1 - An error in the corresponding channel has occurred
3010 #define BP_DMA_ERR_ERR9 (9U) /*!< Bit position for DMA_ERR_ERR9. */
3011 #define BM_DMA_ERR_ERR9 (0x00000200U) /*!< Bit mask for DMA_ERR_ERR9. */
3012 #define BS_DMA_ERR_ERR9 (1U) /*!< Bit field size in bits for DMA_ERR_ERR9. */
3014 /*! @brief Read current value of the DMA_ERR_ERR9 field. */
3015 #define BR_DMA_ERR_ERR9(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR9))
3017 /*! @brief Format value for bitfield DMA_ERR_ERR9. */
3018 #define BF_DMA_ERR_ERR9(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR9) & BM_DMA_ERR_ERR9)
3020 /*! @brief Set the ERR9 field to a new value. */
3021 #define BW_DMA_ERR_ERR9(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR9) = (v))
3025 * @name Register DMA_ERR, field ERR10[10] (W1C)
3028 * - 0 - An error in the corresponding channel has not occurred
3029 * - 1 - An error in the corresponding channel has occurred
3032 #define BP_DMA_ERR_ERR10 (10U) /*!< Bit position for DMA_ERR_ERR10. */
3033 #define BM_DMA_ERR_ERR10 (0x00000400U) /*!< Bit mask for DMA_ERR_ERR10. */
3034 #define BS_DMA_ERR_ERR10 (1U) /*!< Bit field size in bits for DMA_ERR_ERR10. */
3036 /*! @brief Read current value of the DMA_ERR_ERR10 field. */
3037 #define BR_DMA_ERR_ERR10(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR10))
3039 /*! @brief Format value for bitfield DMA_ERR_ERR10. */
3040 #define BF_DMA_ERR_ERR10(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR10) & BM_DMA_ERR_ERR10)
3042 /*! @brief Set the ERR10 field to a new value. */
3043 #define BW_DMA_ERR_ERR10(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR10) = (v))
3047 * @name Register DMA_ERR, field ERR11[11] (W1C)
3050 * - 0 - An error in the corresponding channel has not occurred
3051 * - 1 - An error in the corresponding channel has occurred
3054 #define BP_DMA_ERR_ERR11 (11U) /*!< Bit position for DMA_ERR_ERR11. */
3055 #define BM_DMA_ERR_ERR11 (0x00000800U) /*!< Bit mask for DMA_ERR_ERR11. */
3056 #define BS_DMA_ERR_ERR11 (1U) /*!< Bit field size in bits for DMA_ERR_ERR11. */
3058 /*! @brief Read current value of the DMA_ERR_ERR11 field. */
3059 #define BR_DMA_ERR_ERR11(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR11))
3061 /*! @brief Format value for bitfield DMA_ERR_ERR11. */
3062 #define BF_DMA_ERR_ERR11(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR11) & BM_DMA_ERR_ERR11)
3064 /*! @brief Set the ERR11 field to a new value. */
3065 #define BW_DMA_ERR_ERR11(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR11) = (v))
3069 * @name Register DMA_ERR, field ERR12[12] (W1C)
3072 * - 0 - An error in the corresponding channel has not occurred
3073 * - 1 - An error in the corresponding channel has occurred
3076 #define BP_DMA_ERR_ERR12 (12U) /*!< Bit position for DMA_ERR_ERR12. */
3077 #define BM_DMA_ERR_ERR12 (0x00001000U) /*!< Bit mask for DMA_ERR_ERR12. */
3078 #define BS_DMA_ERR_ERR12 (1U) /*!< Bit field size in bits for DMA_ERR_ERR12. */
3080 /*! @brief Read current value of the DMA_ERR_ERR12 field. */
3081 #define BR_DMA_ERR_ERR12(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR12))
3083 /*! @brief Format value for bitfield DMA_ERR_ERR12. */
3084 #define BF_DMA_ERR_ERR12(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR12) & BM_DMA_ERR_ERR12)
3086 /*! @brief Set the ERR12 field to a new value. */
3087 #define BW_DMA_ERR_ERR12(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR12) = (v))
3091 * @name Register DMA_ERR, field ERR13[13] (W1C)
3094 * - 0 - An error in the corresponding channel has not occurred
3095 * - 1 - An error in the corresponding channel has occurred
3098 #define BP_DMA_ERR_ERR13 (13U) /*!< Bit position for DMA_ERR_ERR13. */
3099 #define BM_DMA_ERR_ERR13 (0x00002000U) /*!< Bit mask for DMA_ERR_ERR13. */
3100 #define BS_DMA_ERR_ERR13 (1U) /*!< Bit field size in bits for DMA_ERR_ERR13. */
3102 /*! @brief Read current value of the DMA_ERR_ERR13 field. */
3103 #define BR_DMA_ERR_ERR13(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR13))
3105 /*! @brief Format value for bitfield DMA_ERR_ERR13. */
3106 #define BF_DMA_ERR_ERR13(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR13) & BM_DMA_ERR_ERR13)
3108 /*! @brief Set the ERR13 field to a new value. */
3109 #define BW_DMA_ERR_ERR13(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR13) = (v))
3113 * @name Register DMA_ERR, field ERR14[14] (W1C)
3116 * - 0 - An error in the corresponding channel has not occurred
3117 * - 1 - An error in the corresponding channel has occurred
3120 #define BP_DMA_ERR_ERR14 (14U) /*!< Bit position for DMA_ERR_ERR14. */
3121 #define BM_DMA_ERR_ERR14 (0x00004000U) /*!< Bit mask for DMA_ERR_ERR14. */
3122 #define BS_DMA_ERR_ERR14 (1U) /*!< Bit field size in bits for DMA_ERR_ERR14. */
3124 /*! @brief Read current value of the DMA_ERR_ERR14 field. */
3125 #define BR_DMA_ERR_ERR14(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR14))
3127 /*! @brief Format value for bitfield DMA_ERR_ERR14. */
3128 #define BF_DMA_ERR_ERR14(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR14) & BM_DMA_ERR_ERR14)
3130 /*! @brief Set the ERR14 field to a new value. */
3131 #define BW_DMA_ERR_ERR14(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR14) = (v))
3135 * @name Register DMA_ERR, field ERR15[15] (W1C)
3138 * - 0 - An error in the corresponding channel has not occurred
3139 * - 1 - An error in the corresponding channel has occurred
3142 #define BP_DMA_ERR_ERR15 (15U) /*!< Bit position for DMA_ERR_ERR15. */
3143 #define BM_DMA_ERR_ERR15 (0x00008000U) /*!< Bit mask for DMA_ERR_ERR15. */
3144 #define BS_DMA_ERR_ERR15 (1U) /*!< Bit field size in bits for DMA_ERR_ERR15. */
3146 /*! @brief Read current value of the DMA_ERR_ERR15 field. */
3147 #define BR_DMA_ERR_ERR15(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR15))
3149 /*! @brief Format value for bitfield DMA_ERR_ERR15. */
3150 #define BF_DMA_ERR_ERR15(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR15) & BM_DMA_ERR_ERR15)
3152 /*! @brief Set the ERR15 field to a new value. */
3153 #define BW_DMA_ERR_ERR15(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR15) = (v))
3156 /*******************************************************************************
3157 * HW_DMA_HRS - Hardware Request Status Register
3158 ******************************************************************************/
3161 * @brief HW_DMA_HRS - Hardware Request Status Register (RO)
3163 * Reset value: 0x00000000U
3165 * The HRS register provides a bit map for the DMA channels, signaling the
3166 * presence of a hardware request for each channel. The hardware request status bits
3167 * reflect the current state of the register and qualified (via the ERQ fields)
3168 * DMA request signals as seen by the DMA's arbitration logic. This view into the
3169 * hardware request signals may be used for debug purposes. These bits reflect the
3170 * state of the request as seen by the arbitration logic. Therefore, this status
3171 * is affected by the ERQ bits.
3173 typedef union _hw_dma_hrs
3176 struct _hw_dma_hrs_bitfields
3178 uint32_t HRS0
: 1; /*!< [0] Hardware Request Status Channel 0 */
3179 uint32_t HRS1
: 1; /*!< [1] Hardware Request Status Channel 1 */
3180 uint32_t HRS2
: 1; /*!< [2] Hardware Request Status Channel 2 */
3181 uint32_t HRS3
: 1; /*!< [3] Hardware Request Status Channel 3 */
3182 uint32_t HRS4
: 1; /*!< [4] Hardware Request Status Channel 4 */
3183 uint32_t HRS5
: 1; /*!< [5] Hardware Request Status Channel 5 */
3184 uint32_t HRS6
: 1; /*!< [6] Hardware Request Status Channel 6 */
3185 uint32_t HRS7
: 1; /*!< [7] Hardware Request Status Channel 7 */
3186 uint32_t HRS8
: 1; /*!< [8] Hardware Request Status Channel 8 */
3187 uint32_t HRS9
: 1; /*!< [9] Hardware Request Status Channel 9 */
3188 uint32_t HRS10
: 1; /*!< [10] Hardware Request Status Channel 10 */
3189 uint32_t HRS11
: 1; /*!< [11] Hardware Request Status Channel 11 */
3190 uint32_t HRS12
: 1; /*!< [12] Hardware Request Status Channel 12 */
3191 uint32_t HRS13
: 1; /*!< [13] Hardware Request Status Channel 13 */
3192 uint32_t HRS14
: 1; /*!< [14] Hardware Request Status Channel 14 */
3193 uint32_t HRS15
: 1; /*!< [15] Hardware Request Status Channel 15 */
3194 uint32_t RESERVED0
: 16; /*!< [31:16] Reserved */
3199 * @name Constants and macros for entire DMA_HRS register
3202 #define HW_DMA_HRS_ADDR(x) ((x) + 0x34U)
3204 #define HW_DMA_HRS(x) (*(__I hw_dma_hrs_t *) HW_DMA_HRS_ADDR(x))
3205 #define HW_DMA_HRS_RD(x) (HW_DMA_HRS(x).U)
3209 * Constants & macros for individual DMA_HRS bitfields
3213 * @name Register DMA_HRS, field HRS0[0] (RO)
3215 * The HRS bit for its respective channel remains asserted for the period when a
3216 * Hardware Request is Present on the Channel. After the Request is completed
3217 * and Channel is free , the HRS bit is automatically cleared by hardware.
3220 * - 0 - A hardware service request for channel 0 is not present
3221 * - 1 - A hardware service request for channel 0 is present
3224 #define BP_DMA_HRS_HRS0 (0U) /*!< Bit position for DMA_HRS_HRS0. */
3225 #define BM_DMA_HRS_HRS0 (0x00000001U) /*!< Bit mask for DMA_HRS_HRS0. */
3226 #define BS_DMA_HRS_HRS0 (1U) /*!< Bit field size in bits for DMA_HRS_HRS0. */
3228 /*! @brief Read current value of the DMA_HRS_HRS0 field. */
3229 #define BR_DMA_HRS_HRS0(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS0))
3233 * @name Register DMA_HRS, field HRS1[1] (RO)
3235 * The HRS bit for its respective channel remains asserted for the period when a
3236 * Hardware Request is Present on the Channel. After the Request is completed
3237 * and Channel is free , the HRS bit is automatically cleared by hardware.
3240 * - 0 - A hardware service request for channel 1 is not present
3241 * - 1 - A hardware service request for channel 1 is present
3244 #define BP_DMA_HRS_HRS1 (1U) /*!< Bit position for DMA_HRS_HRS1. */
3245 #define BM_DMA_HRS_HRS1 (0x00000002U) /*!< Bit mask for DMA_HRS_HRS1. */
3246 #define BS_DMA_HRS_HRS1 (1U) /*!< Bit field size in bits for DMA_HRS_HRS1. */
3248 /*! @brief Read current value of the DMA_HRS_HRS1 field. */
3249 #define BR_DMA_HRS_HRS1(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS1))
3253 * @name Register DMA_HRS, field HRS2[2] (RO)
3255 * The HRS bit for its respective channel remains asserted for the period when a
3256 * Hardware Request is Present on the Channel. After the Request is completed
3257 * and Channel is free , the HRS bit is automatically cleared by hardware.
3260 * - 0 - A hardware service request for channel 2 is not present
3261 * - 1 - A hardware service request for channel 2 is present
3264 #define BP_DMA_HRS_HRS2 (2U) /*!< Bit position for DMA_HRS_HRS2. */
3265 #define BM_DMA_HRS_HRS2 (0x00000004U) /*!< Bit mask for DMA_HRS_HRS2. */
3266 #define BS_DMA_HRS_HRS2 (1U) /*!< Bit field size in bits for DMA_HRS_HRS2. */
3268 /*! @brief Read current value of the DMA_HRS_HRS2 field. */
3269 #define BR_DMA_HRS_HRS2(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS2))
3273 * @name Register DMA_HRS, field HRS3[3] (RO)
3275 * The HRS bit for its respective channel remains asserted for the period when a
3276 * Hardware Request is Present on the Channel. After the Request is completed
3277 * and Channel is free , the HRS bit is automatically cleared by hardware.
3280 * - 0 - A hardware service request for channel 3 is not present
3281 * - 1 - A hardware service request for channel 3 is present
3284 #define BP_DMA_HRS_HRS3 (3U) /*!< Bit position for DMA_HRS_HRS3. */
3285 #define BM_DMA_HRS_HRS3 (0x00000008U) /*!< Bit mask for DMA_HRS_HRS3. */
3286 #define BS_DMA_HRS_HRS3 (1U) /*!< Bit field size in bits for DMA_HRS_HRS3. */
3288 /*! @brief Read current value of the DMA_HRS_HRS3 field. */
3289 #define BR_DMA_HRS_HRS3(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS3))
3293 * @name Register DMA_HRS, field HRS4[4] (RO)
3295 * The HRS bit for its respective channel remains asserted for the period when a
3296 * Hardware Request is Present on the Channel. After the Request is completed
3297 * and Channel is free , the HRS bit is automatically cleared by hardware.
3300 * - 0 - A hardware service request for channel 4 is not present
3301 * - 1 - A hardware service request for channel 4 is present
3304 #define BP_DMA_HRS_HRS4 (4U) /*!< Bit position for DMA_HRS_HRS4. */
3305 #define BM_DMA_HRS_HRS4 (0x00000010U) /*!< Bit mask for DMA_HRS_HRS4. */
3306 #define BS_DMA_HRS_HRS4 (1U) /*!< Bit field size in bits for DMA_HRS_HRS4. */
3308 /*! @brief Read current value of the DMA_HRS_HRS4 field. */
3309 #define BR_DMA_HRS_HRS4(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS4))
3313 * @name Register DMA_HRS, field HRS5[5] (RO)
3315 * The HRS bit for its respective channel remains asserted for the period when a
3316 * Hardware Request is Present on the Channel. After the Request is completed
3317 * and Channel is free , the HRS bit is automatically cleared by hardware.
3320 * - 0 - A hardware service request for channel 5 is not present
3321 * - 1 - A hardware service request for channel 5 is present
3324 #define BP_DMA_HRS_HRS5 (5U) /*!< Bit position for DMA_HRS_HRS5. */
3325 #define BM_DMA_HRS_HRS5 (0x00000020U) /*!< Bit mask for DMA_HRS_HRS5. */
3326 #define BS_DMA_HRS_HRS5 (1U) /*!< Bit field size in bits for DMA_HRS_HRS5. */
3328 /*! @brief Read current value of the DMA_HRS_HRS5 field. */
3329 #define BR_DMA_HRS_HRS5(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS5))
3333 * @name Register DMA_HRS, field HRS6[6] (RO)
3335 * The HRS bit for its respective channel remains asserted for the period when a
3336 * Hardware Request is Present on the Channel. After the Request is completed
3337 * and Channel is free , the HRS bit is automatically cleared by hardware.
3340 * - 0 - A hardware service request for channel 6 is not present
3341 * - 1 - A hardware service request for channel 6 is present
3344 #define BP_DMA_HRS_HRS6 (6U) /*!< Bit position for DMA_HRS_HRS6. */
3345 #define BM_DMA_HRS_HRS6 (0x00000040U) /*!< Bit mask for DMA_HRS_HRS6. */
3346 #define BS_DMA_HRS_HRS6 (1U) /*!< Bit field size in bits for DMA_HRS_HRS6. */
3348 /*! @brief Read current value of the DMA_HRS_HRS6 field. */
3349 #define BR_DMA_HRS_HRS6(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS6))
3353 * @name Register DMA_HRS, field HRS7[7] (RO)
3355 * The HRS bit for its respective channel remains asserted for the period when a
3356 * Hardware Request is Present on the Channel. After the Request is completed
3357 * and Channel is free , the HRS bit is automatically cleared by hardware.
3360 * - 0 - A hardware service request for channel 7 is not present
3361 * - 1 - A hardware service request for channel 7 is present
3364 #define BP_DMA_HRS_HRS7 (7U) /*!< Bit position for DMA_HRS_HRS7. */
3365 #define BM_DMA_HRS_HRS7 (0x00000080U) /*!< Bit mask for DMA_HRS_HRS7. */
3366 #define BS_DMA_HRS_HRS7 (1U) /*!< Bit field size in bits for DMA_HRS_HRS7. */
3368 /*! @brief Read current value of the DMA_HRS_HRS7 field. */
3369 #define BR_DMA_HRS_HRS7(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS7))
3373 * @name Register DMA_HRS, field HRS8[8] (RO)
3375 * The HRS bit for its respective channel remains asserted for the period when a
3376 * Hardware Request is Present on the Channel. After the Request is completed
3377 * and Channel is free , the HRS bit is automatically cleared by hardware.
3380 * - 0 - A hardware service request for channel 8 is not present
3381 * - 1 - A hardware service request for channel 8 is present
3384 #define BP_DMA_HRS_HRS8 (8U) /*!< Bit position for DMA_HRS_HRS8. */
3385 #define BM_DMA_HRS_HRS8 (0x00000100U) /*!< Bit mask for DMA_HRS_HRS8. */
3386 #define BS_DMA_HRS_HRS8 (1U) /*!< Bit field size in bits for DMA_HRS_HRS8. */
3388 /*! @brief Read current value of the DMA_HRS_HRS8 field. */
3389 #define BR_DMA_HRS_HRS8(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS8))
3393 * @name Register DMA_HRS, field HRS9[9] (RO)
3395 * The HRS bit for its respective channel remains asserted for the period when a
3396 * Hardware Request is Present on the Channel. After the Request is completed
3397 * and Channel is free , the HRS bit is automatically cleared by hardware.
3400 * - 0 - A hardware service request for channel 9 is not present
3401 * - 1 - A hardware service request for channel 9 is present
3404 #define BP_DMA_HRS_HRS9 (9U) /*!< Bit position for DMA_HRS_HRS9. */
3405 #define BM_DMA_HRS_HRS9 (0x00000200U) /*!< Bit mask for DMA_HRS_HRS9. */
3406 #define BS_DMA_HRS_HRS9 (1U) /*!< Bit field size in bits for DMA_HRS_HRS9. */
3408 /*! @brief Read current value of the DMA_HRS_HRS9 field. */
3409 #define BR_DMA_HRS_HRS9(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS9))
3413 * @name Register DMA_HRS, field HRS10[10] (RO)
3415 * The HRS bit for its respective channel remains asserted for the period when a
3416 * Hardware Request is Present on the Channel. After the Request is completed
3417 * and Channel is free , the HRS bit is automatically cleared by hardware.
3420 * - 0 - A hardware service request for channel 10 is not present
3421 * - 1 - A hardware service request for channel 10 is present
3424 #define BP_DMA_HRS_HRS10 (10U) /*!< Bit position for DMA_HRS_HRS10. */
3425 #define BM_DMA_HRS_HRS10 (0x00000400U) /*!< Bit mask for DMA_HRS_HRS10. */
3426 #define BS_DMA_HRS_HRS10 (1U) /*!< Bit field size in bits for DMA_HRS_HRS10. */
3428 /*! @brief Read current value of the DMA_HRS_HRS10 field. */
3429 #define BR_DMA_HRS_HRS10(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS10))
3433 * @name Register DMA_HRS, field HRS11[11] (RO)
3435 * The HRS bit for its respective channel remains asserted for the period when a
3436 * Hardware Request is Present on the Channel. After the Request is completed
3437 * and Channel is free , the HRS bit is automatically cleared by hardware.
3440 * - 0 - A hardware service request for channel 11 is not present
3441 * - 1 - A hardware service request for channel 11 is present
3444 #define BP_DMA_HRS_HRS11 (11U) /*!< Bit position for DMA_HRS_HRS11. */
3445 #define BM_DMA_HRS_HRS11 (0x00000800U) /*!< Bit mask for DMA_HRS_HRS11. */
3446 #define BS_DMA_HRS_HRS11 (1U) /*!< Bit field size in bits for DMA_HRS_HRS11. */
3448 /*! @brief Read current value of the DMA_HRS_HRS11 field. */
3449 #define BR_DMA_HRS_HRS11(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS11))
3453 * @name Register DMA_HRS, field HRS12[12] (RO)
3455 * The HRS bit for its respective channel remains asserted for the period when a
3456 * Hardware Request is Present on the Channel. After the Request is completed
3457 * and Channel is free , the HRS bit is automatically cleared by hardware.
3460 * - 0 - A hardware service request for channel 12 is not present
3461 * - 1 - A hardware service request for channel 12 is present
3464 #define BP_DMA_HRS_HRS12 (12U) /*!< Bit position for DMA_HRS_HRS12. */
3465 #define BM_DMA_HRS_HRS12 (0x00001000U) /*!< Bit mask for DMA_HRS_HRS12. */
3466 #define BS_DMA_HRS_HRS12 (1U) /*!< Bit field size in bits for DMA_HRS_HRS12. */
3468 /*! @brief Read current value of the DMA_HRS_HRS12 field. */
3469 #define BR_DMA_HRS_HRS12(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS12))
3473 * @name Register DMA_HRS, field HRS13[13] (RO)
3475 * The HRS bit for its respective channel remains asserted for the period when a
3476 * Hardware Request is Present on the Channel. After the Request is completed
3477 * and Channel is free , the HRS bit is automatically cleared by hardware.
3480 * - 0 - A hardware service request for channel 13 is not present
3481 * - 1 - A hardware service request for channel 13 is present
3484 #define BP_DMA_HRS_HRS13 (13U) /*!< Bit position for DMA_HRS_HRS13. */
3485 #define BM_DMA_HRS_HRS13 (0x00002000U) /*!< Bit mask for DMA_HRS_HRS13. */
3486 #define BS_DMA_HRS_HRS13 (1U) /*!< Bit field size in bits for DMA_HRS_HRS13. */
3488 /*! @brief Read current value of the DMA_HRS_HRS13 field. */
3489 #define BR_DMA_HRS_HRS13(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS13))
3493 * @name Register DMA_HRS, field HRS14[14] (RO)
3495 * The HRS bit for its respective channel remains asserted for the period when a
3496 * Hardware Request is Present on the Channel. After the Request is completed
3497 * and Channel is free , the HRS bit is automatically cleared by hardware.
3500 * - 0 - A hardware service request for channel 14 is not present
3501 * - 1 - A hardware service request for channel 14 is present
3504 #define BP_DMA_HRS_HRS14 (14U) /*!< Bit position for DMA_HRS_HRS14. */
3505 #define BM_DMA_HRS_HRS14 (0x00004000U) /*!< Bit mask for DMA_HRS_HRS14. */
3506 #define BS_DMA_HRS_HRS14 (1U) /*!< Bit field size in bits for DMA_HRS_HRS14. */
3508 /*! @brief Read current value of the DMA_HRS_HRS14 field. */
3509 #define BR_DMA_HRS_HRS14(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS14))
3513 * @name Register DMA_HRS, field HRS15[15] (RO)
3515 * The HRS bit for its respective channel remains asserted for the period when a
3516 * Hardware Request is Present on the Channel. After the Request is completed
3517 * and Channel is free , the HRS bit is automatically cleared by hardware.
3520 * - 0 - A hardware service request for channel 15 is not present
3521 * - 1 - A hardware service request for channel 15 is present
3524 #define BP_DMA_HRS_HRS15 (15U) /*!< Bit position for DMA_HRS_HRS15. */
3525 #define BM_DMA_HRS_HRS15 (0x00008000U) /*!< Bit mask for DMA_HRS_HRS15. */
3526 #define BS_DMA_HRS_HRS15 (1U) /*!< Bit field size in bits for DMA_HRS_HRS15. */
3528 /*! @brief Read current value of the DMA_HRS_HRS15 field. */
3529 #define BR_DMA_HRS_HRS15(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS15))
3532 /*******************************************************************************
3533 * HW_DMA_DCHPRIn - Channel n Priority Register
3534 ******************************************************************************/
3537 * @brief HW_DMA_DCHPRIn - Channel n Priority Register (RW)
3539 * Reset value: 0x00U
3541 * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
3542 * contents of these registers define the unique priorities associated with each
3543 * channel . The channel priorities are evaluated by numeric value; for example, 0 is
3544 * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
3545 * program the channel priorities with unique values; otherwise, a configuration
3546 * error is reported. The range of the priority value is limited to the values of 0
3549 typedef union _hw_dma_dchprin
3552 struct _hw_dma_dchprin_bitfields
3554 uint8_t CHPRI
: 4; /*!< [3:0] Channel n Arbitration Priority */
3555 uint8_t RESERVED0
: 2; /*!< [5:4] */
3556 uint8_t DPA
: 1; /*!< [6] Disable Preempt Ability */
3557 uint8_t ECP
: 1; /*!< [7] Enable Channel Preemption */
3562 * @name Constants and macros for entire DMA_DCHPRIn register
3565 #define HW_DMA_DCHPRIn_COUNT (16U)
3567 #define HW_DMA_DCHPRIn_ADDR(x, n) ((x) + 0x100U + (0x1U * (n)))
3569 /* DMA channel index to DMA channel priority register array index conversion macro */
3570 #define HW_DMA_DCHPRIn_CHANNEL(n) (((n) & ~0x03U) | (3 - ((n) & 0x03U)))
3572 #define HW_DMA_DCHPRIn(x, n) (*(__IO hw_dma_dchprin_t *) HW_DMA_DCHPRIn_ADDR(x, n))
3573 #define HW_DMA_DCHPRIn_RD(x, n) (HW_DMA_DCHPRIn(x, n).U)
3574 #define HW_DMA_DCHPRIn_WR(x, n, v) (HW_DMA_DCHPRIn(x, n).U = (v))
3575 #define HW_DMA_DCHPRIn_SET(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) | (v)))
3576 #define HW_DMA_DCHPRIn_CLR(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) & ~(v)))
3577 #define HW_DMA_DCHPRIn_TOG(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) ^ (v)))
3581 * Constants & macros for individual DMA_DCHPRIn bitfields
3585 * @name Register DMA_DCHPRIn, field CHPRI[3:0] (RW)
3587 * Channel priority when fixed-priority arbitration is enabled Reset value for
3588 * the channel priority fields, CHPRI, is equal to the corresponding channel
3589 * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
3592 #define BP_DMA_DCHPRIn_CHPRI (0U) /*!< Bit position for DMA_DCHPRIn_CHPRI. */
3593 #define BM_DMA_DCHPRIn_CHPRI (0x0FU) /*!< Bit mask for DMA_DCHPRIn_CHPRI. */
3594 #define BS_DMA_DCHPRIn_CHPRI (4U) /*!< Bit field size in bits for DMA_DCHPRIn_CHPRI. */
3596 /*! @brief Read current value of the DMA_DCHPRIn_CHPRI field. */
3597 #define BR_DMA_DCHPRIn_CHPRI(x, n) (HW_DMA_DCHPRIn(x, n).B.CHPRI)
3599 /*! @brief Format value for bitfield DMA_DCHPRIn_CHPRI. */
3600 #define BF_DMA_DCHPRIn_CHPRI(v) ((uint8_t)((uint8_t)(v) << BP_DMA_DCHPRIn_CHPRI) & BM_DMA_DCHPRIn_CHPRI)
3602 /*! @brief Set the CHPRI field to a new value. */
3603 #define BW_DMA_DCHPRIn_CHPRI(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, (HW_DMA_DCHPRIn_RD(x, n) & ~BM_DMA_DCHPRIn_CHPRI) | BF_DMA_DCHPRIn_CHPRI(v)))
3607 * @name Register DMA_DCHPRIn, field DPA[6] (RW)
3610 * - 0 - Channel n can suspend a lower priority channel
3611 * - 1 - Channel n cannot suspend any channel, regardless of channel priority
3614 #define BP_DMA_DCHPRIn_DPA (6U) /*!< Bit position for DMA_DCHPRIn_DPA. */
3615 #define BM_DMA_DCHPRIn_DPA (0x40U) /*!< Bit mask for DMA_DCHPRIn_DPA. */
3616 #define BS_DMA_DCHPRIn_DPA (1U) /*!< Bit field size in bits for DMA_DCHPRIn_DPA. */
3618 /*! @brief Read current value of the DMA_DCHPRIn_DPA field. */
3619 #define BR_DMA_DCHPRIn_DPA(x, n) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_DPA))
3621 /*! @brief Format value for bitfield DMA_DCHPRIn_DPA. */
3622 #define BF_DMA_DCHPRIn_DPA(v) ((uint8_t)((uint8_t)(v) << BP_DMA_DCHPRIn_DPA) & BM_DMA_DCHPRIn_DPA)
3624 /*! @brief Set the DPA field to a new value. */
3625 #define BW_DMA_DCHPRIn_DPA(x, n, v) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_DPA) = (v))
3629 * @name Register DMA_DCHPRIn, field ECP[7] (RW)
3632 * - 0 - Channel n cannot be suspended by a higher priority channel's service
3634 * - 1 - Channel n can be temporarily suspended by the service request of a
3635 * higher priority channel
3638 #define BP_DMA_DCHPRIn_ECP (7U) /*!< Bit position for DMA_DCHPRIn_ECP. */
3639 #define BM_DMA_DCHPRIn_ECP (0x80U) /*!< Bit mask for DMA_DCHPRIn_ECP. */
3640 #define BS_DMA_DCHPRIn_ECP (1U) /*!< Bit field size in bits for DMA_DCHPRIn_ECP. */
3642 /*! @brief Read current value of the DMA_DCHPRIn_ECP field. */
3643 #define BR_DMA_DCHPRIn_ECP(x, n) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_ECP))
3645 /*! @brief Format value for bitfield DMA_DCHPRIn_ECP. */
3646 #define BF_DMA_DCHPRIn_ECP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_DCHPRIn_ECP) & BM_DMA_DCHPRIn_ECP)
3648 /*! @brief Set the ECP field to a new value. */
3649 #define BW_DMA_DCHPRIn_ECP(x, n, v) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_ECP) = (v))
3652 /*******************************************************************************
3653 * HW_DMA_TCDn_SADDR - TCD Source Address
3654 ******************************************************************************/
3657 * @brief HW_DMA_TCDn_SADDR - TCD Source Address (RW)
3659 * Reset value: 0x00000000U
3661 typedef union _hw_dma_tcdn_saddr
3664 struct _hw_dma_tcdn_saddr_bitfields
3666 uint32_t SADDR
: 32; /*!< [31:0] Source Address */
3668 } hw_dma_tcdn_saddr_t
;
3671 * @name Constants and macros for entire DMA_TCDn_SADDR register
3674 #define HW_DMA_TCDn_SADDR_COUNT (16U)
3676 #define HW_DMA_TCDn_SADDR_ADDR(x, n) ((x) + 0x1000U + (0x20U * (n)))
3678 #define HW_DMA_TCDn_SADDR(x, n) (*(__IO hw_dma_tcdn_saddr_t *) HW_DMA_TCDn_SADDR_ADDR(x, n))
3679 #define HW_DMA_TCDn_SADDR_RD(x, n) (HW_DMA_TCDn_SADDR(x, n).U)
3680 #define HW_DMA_TCDn_SADDR_WR(x, n, v) (HW_DMA_TCDn_SADDR(x, n).U = (v))
3681 #define HW_DMA_TCDn_SADDR_SET(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) | (v)))
3682 #define HW_DMA_TCDn_SADDR_CLR(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) & ~(v)))
3683 #define HW_DMA_TCDn_SADDR_TOG(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) ^ (v)))
3687 * Constants & macros for individual DMA_TCDn_SADDR bitfields
3691 * @name Register DMA_TCDn_SADDR, field SADDR[31:0] (RW)
3693 * Memory address pointing to the source data.
3696 #define BP_DMA_TCDn_SADDR_SADDR (0U) /*!< Bit position for DMA_TCDn_SADDR_SADDR. */
3697 #define BM_DMA_TCDn_SADDR_SADDR (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_SADDR_SADDR. */
3698 #define BS_DMA_TCDn_SADDR_SADDR (32U) /*!< Bit field size in bits for DMA_TCDn_SADDR_SADDR. */
3700 /*! @brief Read current value of the DMA_TCDn_SADDR_SADDR field. */
3701 #define BR_DMA_TCDn_SADDR_SADDR(x, n) (HW_DMA_TCDn_SADDR(x, n).U)
3703 /*! @brief Format value for bitfield DMA_TCDn_SADDR_SADDR. */
3704 #define BF_DMA_TCDn_SADDR_SADDR(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_SADDR_SADDR) & BM_DMA_TCDn_SADDR_SADDR)
3706 /*! @brief Set the SADDR field to a new value. */
3707 #define BW_DMA_TCDn_SADDR_SADDR(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, v))
3709 /*******************************************************************************
3710 * HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset
3711 ******************************************************************************/
3714 * @brief HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset (RW)
3716 * Reset value: 0x0000U
3718 typedef union _hw_dma_tcdn_soff
3721 struct _hw_dma_tcdn_soff_bitfields
3723 uint16_t SOFF
: 16; /*!< [15:0] Source address signed offset */
3725 } hw_dma_tcdn_soff_t
;
3728 * @name Constants and macros for entire DMA_TCDn_SOFF register
3731 #define HW_DMA_TCDn_SOFF_COUNT (16U)
3733 #define HW_DMA_TCDn_SOFF_ADDR(x, n) ((x) + 0x1004U + (0x20U * (n)))
3735 #define HW_DMA_TCDn_SOFF(x, n) (*(__IO hw_dma_tcdn_soff_t *) HW_DMA_TCDn_SOFF_ADDR(x, n))
3736 #define HW_DMA_TCDn_SOFF_RD(x, n) (HW_DMA_TCDn_SOFF(x, n).U)
3737 #define HW_DMA_TCDn_SOFF_WR(x, n, v) (HW_DMA_TCDn_SOFF(x, n).U = (v))
3738 #define HW_DMA_TCDn_SOFF_SET(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) | (v)))
3739 #define HW_DMA_TCDn_SOFF_CLR(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) & ~(v)))
3740 #define HW_DMA_TCDn_SOFF_TOG(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) ^ (v)))
3744 * Constants & macros for individual DMA_TCDn_SOFF bitfields
3748 * @name Register DMA_TCDn_SOFF, field SOFF[15:0] (RW)
3750 * Sign-extended offset applied to the current source address to form the
3751 * next-state value as each source read is completed.
3754 #define BP_DMA_TCDn_SOFF_SOFF (0U) /*!< Bit position for DMA_TCDn_SOFF_SOFF. */
3755 #define BM_DMA_TCDn_SOFF_SOFF (0xFFFFU) /*!< Bit mask for DMA_TCDn_SOFF_SOFF. */
3756 #define BS_DMA_TCDn_SOFF_SOFF (16U) /*!< Bit field size in bits for DMA_TCDn_SOFF_SOFF. */
3758 /*! @brief Read current value of the DMA_TCDn_SOFF_SOFF field. */
3759 #define BR_DMA_TCDn_SOFF_SOFF(x, n) (HW_DMA_TCDn_SOFF(x, n).U)
3761 /*! @brief Format value for bitfield DMA_TCDn_SOFF_SOFF. */
3762 #define BF_DMA_TCDn_SOFF_SOFF(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_SOFF_SOFF) & BM_DMA_TCDn_SOFF_SOFF)
3764 /*! @brief Set the SOFF field to a new value. */
3765 #define BW_DMA_TCDn_SOFF_SOFF(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, v))
3767 /*******************************************************************************
3768 * HW_DMA_TCDn_ATTR - TCD Transfer Attributes
3769 ******************************************************************************/
3772 * @brief HW_DMA_TCDn_ATTR - TCD Transfer Attributes (RW)
3774 * Reset value: 0x0000U
3776 typedef union _hw_dma_tcdn_attr
3779 struct _hw_dma_tcdn_attr_bitfields
3781 uint16_t DSIZE
: 3; /*!< [2:0] Destination Data Transfer Size */
3782 uint16_t DMOD
: 5; /*!< [7:3] Destination Address Modulo */
3783 uint16_t SSIZE
: 3; /*!< [10:8] Source data transfer size */
3784 uint16_t SMOD
: 5; /*!< [15:11] Source Address Modulo. */
3786 } hw_dma_tcdn_attr_t
;
3789 * @name Constants and macros for entire DMA_TCDn_ATTR register
3792 #define HW_DMA_TCDn_ATTR_COUNT (16U)
3794 #define HW_DMA_TCDn_ATTR_ADDR(x, n) ((x) + 0x1006U + (0x20U * (n)))
3796 #define HW_DMA_TCDn_ATTR(x, n) (*(__IO hw_dma_tcdn_attr_t *) HW_DMA_TCDn_ATTR_ADDR(x, n))
3797 #define HW_DMA_TCDn_ATTR_RD(x, n) (HW_DMA_TCDn_ATTR(x, n).U)
3798 #define HW_DMA_TCDn_ATTR_WR(x, n, v) (HW_DMA_TCDn_ATTR(x, n).U = (v))
3799 #define HW_DMA_TCDn_ATTR_SET(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) | (v)))
3800 #define HW_DMA_TCDn_ATTR_CLR(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) & ~(v)))
3801 #define HW_DMA_TCDn_ATTR_TOG(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) ^ (v)))
3805 * Constants & macros for individual DMA_TCDn_ATTR bitfields
3809 * @name Register DMA_TCDn_ATTR, field DSIZE[2:0] (RW)
3811 * See the SSIZE definition
3814 #define BP_DMA_TCDn_ATTR_DSIZE (0U) /*!< Bit position for DMA_TCDn_ATTR_DSIZE. */
3815 #define BM_DMA_TCDn_ATTR_DSIZE (0x0007U) /*!< Bit mask for DMA_TCDn_ATTR_DSIZE. */
3816 #define BS_DMA_TCDn_ATTR_DSIZE (3U) /*!< Bit field size in bits for DMA_TCDn_ATTR_DSIZE. */
3818 /*! @brief Read current value of the DMA_TCDn_ATTR_DSIZE field. */
3819 #define BR_DMA_TCDn_ATTR_DSIZE(x, n) (HW_DMA_TCDn_ATTR(x, n).B.DSIZE)
3821 /*! @brief Format value for bitfield DMA_TCDn_ATTR_DSIZE. */
3822 #define BF_DMA_TCDn_ATTR_DSIZE(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_ATTR_DSIZE) & BM_DMA_TCDn_ATTR_DSIZE)
3824 /*! @brief Set the DSIZE field to a new value. */
3825 #define BW_DMA_TCDn_ATTR_DSIZE(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_DSIZE) | BF_DMA_TCDn_ATTR_DSIZE(v)))
3829 * @name Register DMA_TCDn_ATTR, field DMOD[7:3] (RW)
3831 * See the SMOD definition
3834 #define BP_DMA_TCDn_ATTR_DMOD (3U) /*!< Bit position for DMA_TCDn_ATTR_DMOD. */
3835 #define BM_DMA_TCDn_ATTR_DMOD (0x00F8U) /*!< Bit mask for DMA_TCDn_ATTR_DMOD. */
3836 #define BS_DMA_TCDn_ATTR_DMOD (5U) /*!< Bit field size in bits for DMA_TCDn_ATTR_DMOD. */
3838 /*! @brief Read current value of the DMA_TCDn_ATTR_DMOD field. */
3839 #define BR_DMA_TCDn_ATTR_DMOD(x, n) (HW_DMA_TCDn_ATTR(x, n).B.DMOD)
3841 /*! @brief Format value for bitfield DMA_TCDn_ATTR_DMOD. */
3842 #define BF_DMA_TCDn_ATTR_DMOD(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_ATTR_DMOD) & BM_DMA_TCDn_ATTR_DMOD)
3844 /*! @brief Set the DMOD field to a new value. */
3845 #define BW_DMA_TCDn_ATTR_DMOD(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_DMOD) | BF_DMA_TCDn_ATTR_DMOD(v)))
3849 * @name Register DMA_TCDn_ATTR, field SSIZE[10:8] (RW)
3851 * The attempted use of a Reserved encoding causes a configuration error.
3864 #define BP_DMA_TCDn_ATTR_SSIZE (8U) /*!< Bit position for DMA_TCDn_ATTR_SSIZE. */
3865 #define BM_DMA_TCDn_ATTR_SSIZE (0x0700U) /*!< Bit mask for DMA_TCDn_ATTR_SSIZE. */
3866 #define BS_DMA_TCDn_ATTR_SSIZE (3U) /*!< Bit field size in bits for DMA_TCDn_ATTR_SSIZE. */
3868 /*! @brief Read current value of the DMA_TCDn_ATTR_SSIZE field. */
3869 #define BR_DMA_TCDn_ATTR_SSIZE(x, n) (HW_DMA_TCDn_ATTR(x, n).B.SSIZE)
3871 /*! @brief Format value for bitfield DMA_TCDn_ATTR_SSIZE. */
3872 #define BF_DMA_TCDn_ATTR_SSIZE(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_ATTR_SSIZE) & BM_DMA_TCDn_ATTR_SSIZE)
3874 /*! @brief Set the SSIZE field to a new value. */
3875 #define BW_DMA_TCDn_ATTR_SSIZE(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_SSIZE) | BF_DMA_TCDn_ATTR_SSIZE(v)))
3879 * @name Register DMA_TCDn_ATTR, field SMOD[15:11] (RW)
3882 * - 0 - Source address modulo feature is disabled
3885 #define BP_DMA_TCDn_ATTR_SMOD (11U) /*!< Bit position for DMA_TCDn_ATTR_SMOD. */
3886 #define BM_DMA_TCDn_ATTR_SMOD (0xF800U) /*!< Bit mask for DMA_TCDn_ATTR_SMOD. */
3887 #define BS_DMA_TCDn_ATTR_SMOD (5U) /*!< Bit field size in bits for DMA_TCDn_ATTR_SMOD. */
3889 /*! @brief Read current value of the DMA_TCDn_ATTR_SMOD field. */
3890 #define BR_DMA_TCDn_ATTR_SMOD(x, n) (HW_DMA_TCDn_ATTR(x, n).B.SMOD)
3892 /*! @brief Format value for bitfield DMA_TCDn_ATTR_SMOD. */
3893 #define BF_DMA_TCDn_ATTR_SMOD(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_ATTR_SMOD) & BM_DMA_TCDn_ATTR_SMOD)
3895 /*! @brief Set the SMOD field to a new value. */
3896 #define BW_DMA_TCDn_ATTR_SMOD(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_SMOD) | BF_DMA_TCDn_ATTR_SMOD(v)))
3898 /*******************************************************************************
3899 * HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)
3900 ******************************************************************************/
3903 * @brief HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) (RW)
3905 * Reset value: 0x00000000U
3907 * This register, or one of the next two registers (TCD_NBYTES_MLOFFNO,
3908 * TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which
3909 * register to use depends on whether minor loop mapping is disabled, enabled but not
3910 * used for this channel, or enabled and used. TCD word 2 is defined as follows
3911 * if: Minor loop mapping is disabled (CR[EMLM] = 0) If minor loop mapping is
3912 * enabled, see the TCD_NBYTES_MLOFFNO and TCD_NBYTES_MLOFFYES register descriptions
3913 * for TCD word 2's definition.
3915 typedef union _hw_dma_tcdn_nbytes_mlno
3918 struct _hw_dma_tcdn_nbytes_mlno_bitfields
3920 uint32_t NBYTES
: 32; /*!< [31:0] Minor Byte Transfer Count */
3922 } hw_dma_tcdn_nbytes_mlno_t
;
3925 * @name Constants and macros for entire DMA_TCDn_NBYTES_MLNO register
3928 #define HW_DMA_TCDn_NBYTES_MLNO_COUNT (16U)
3930 #define HW_DMA_TCDn_NBYTES_MLNO_ADDR(x, n) ((x) + 0x1008U + (0x20U * (n)))
3932 #define HW_DMA_TCDn_NBYTES_MLNO(x, n) (*(__IO hw_dma_tcdn_nbytes_mlno_t *) HW_DMA_TCDn_NBYTES_MLNO_ADDR(x, n))
3933 #define HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U)
3934 #define HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U = (v))
3935 #define HW_DMA_TCDn_NBYTES_MLNO_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) | (v)))
3936 #define HW_DMA_TCDn_NBYTES_MLNO_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) & ~(v)))
3937 #define HW_DMA_TCDn_NBYTES_MLNO_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) ^ (v)))
3941 * Constants & macros for individual DMA_TCDn_NBYTES_MLNO bitfields
3945 * @name Register DMA_TCDn_NBYTES_MLNO, field NBYTES[31:0] (RW)
3947 * Number of bytes to be transferred in each service request of the channel. As
3948 * a channel activates, the appropriate TCD contents load into the eDMA engine,
3949 * and the appropriate reads and writes perform until the minor byte transfer
3950 * count has transferred. This is an indivisible operation and cannot be halted.
3951 * (Although, it may be stalled by using the bandwidth control field, or via
3952 * preemption.) After the minor count is exhausted, the SADDR and DADDR values are
3953 * written back into the TCD memory, the major iteration count is decremented and
3954 * restored to the TCD memory. If the major iteration count is completed, additional
3955 * processing is performed. An NBYTES value of 0x0000_0000 is interpreted as a 4
3959 #define BP_DMA_TCDn_NBYTES_MLNO_NBYTES (0U) /*!< Bit position for DMA_TCDn_NBYTES_MLNO_NBYTES. */
3960 #define BM_DMA_TCDn_NBYTES_MLNO_NBYTES (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_NBYTES_MLNO_NBYTES. */
3961 #define BS_DMA_TCDn_NBYTES_MLNO_NBYTES (32U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLNO_NBYTES. */
3963 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLNO_NBYTES field. */
3964 #define BR_DMA_TCDn_NBYTES_MLNO_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U)
3966 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLNO_NBYTES. */
3967 #define BF_DMA_TCDn_NBYTES_MLNO_NBYTES(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLNO_NBYTES) & BM_DMA_TCDn_NBYTES_MLNO_NBYTES)
3969 /*! @brief Set the NBYTES field to a new value. */
3970 #define BW_DMA_TCDn_NBYTES_MLNO_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, v))
3972 /*******************************************************************************
3973 * HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
3974 ******************************************************************************/
3977 * @brief HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (RW)
3979 * Reset value: 0x00000000U
3981 * One of three registers (this register, TCD_NBYTES_MLNO, or
3982 * TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which register to use
3983 * depends on whether minor loop mapping is disabled, enabled but not used for
3984 * this channel, or enabled and used. TCD word 2 is defined as follows if: Minor
3985 * loop mapping is enabled (CR[EMLM] = 1) and SMLOE = 0 and DMLOE = 0 If minor
3986 * loop mapping is enabled and SMLOE or DMLOE is set, then refer to the
3987 * TCD_NBYTES_MLOFFYES register description. If minor loop mapping is disabled, then refer to
3988 * the TCD_NBYTES_MLNO register description.
3990 typedef union _hw_dma_tcdn_nbytes_mloffno
3993 struct _hw_dma_tcdn_nbytes_mloffno_bitfields
3995 uint32_t NBYTES
: 30; /*!< [29:0] Minor Byte Transfer Count */
3996 uint32_t DMLOE
: 1; /*!< [30] Destination Minor Loop Offset enable */
3997 uint32_t SMLOE
: 1; /*!< [31] Source Minor Loop Offset Enable */
3999 } hw_dma_tcdn_nbytes_mloffno_t
;
4002 * @name Constants and macros for entire DMA_TCDn_NBYTES_MLOFFNO register
4005 #define HW_DMA_TCDn_NBYTES_MLOFFNO_COUNT (16U)
4007 #define HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n) ((x) + 0x1008U + (0x20U * (n)))
4009 #define HW_DMA_TCDn_NBYTES_MLOFFNO(x, n) (*(__IO hw_dma_tcdn_nbytes_mloffno_t *) HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n))
4010 #define HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) (HW_DMA_TCDn_NBYTES_MLOFFNO(x, n).U)
4011 #define HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO(x, n).U = (v))
4012 #define HW_DMA_TCDn_NBYTES_MLOFFNO_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) | (v)))
4013 #define HW_DMA_TCDn_NBYTES_MLOFFNO_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) & ~(v)))
4014 #define HW_DMA_TCDn_NBYTES_MLOFFNO_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) ^ (v)))
4018 * Constants & macros for individual DMA_TCDn_NBYTES_MLOFFNO bitfields
4022 * @name Register DMA_TCDn_NBYTES_MLOFFNO, field NBYTES[29:0] (RW)
4024 * Number of bytes to be transferred in each service request of the channel. As
4025 * a channel activates, the appropriate TCD contents load into the eDMA engine,
4026 * and the appropriate reads and writes perform until the minor byte transfer
4027 * count has transferred. This is an indivisible operation and cannot be halted;
4028 * although, it may be stalled by using the bandwidth control field, or via
4029 * preemption. After the minor count is exhausted, the SADDR and DADDR values are written
4030 * back into the TCD memory, the major iteration count is decremented and
4031 * restored to the TCD memory. If the major iteration count is completed, additional
4032 * processing is performed.
4035 #define BP_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (0U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_NBYTES. */
4036 #define BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (0x3FFFFFFFU) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_NBYTES. */
4037 #define BS_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (30U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_NBYTES. */
4039 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_NBYTES field. */
4040 #define BR_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLOFFNO(x, n).B.NBYTES)
4042 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_NBYTES. */
4043 #define BF_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFNO_NBYTES) & BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES)
4045 /*! @brief Set the NBYTES field to a new value. */
4046 #define BW_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES) | BF_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(v)))
4050 * @name Register DMA_TCDn_NBYTES_MLOFFNO, field DMLOE[30] (RW)
4052 * Selects whether the minor loop offset is applied to the destination address
4053 * upon minor loop completion.
4056 * - 0 - The minor loop offset is not applied to the DADDR
4057 * - 1 - The minor loop offset is applied to the DADDR
4060 #define BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (30U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_DMLOE. */
4061 #define BM_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (0x40000000U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_DMLOE. */
4062 #define BS_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (1U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_DMLOE. */
4064 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_DMLOE field. */
4065 #define BR_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE))
4067 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_DMLOE. */
4068 #define BF_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE) & BM_DMA_TCDn_NBYTES_MLOFFNO_DMLOE)
4070 /*! @brief Set the DMLOE field to a new value. */
4071 #define BW_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE) = (v))
4075 * @name Register DMA_TCDn_NBYTES_MLOFFNO, field SMLOE[31] (RW)
4077 * Selects whether the minor loop offset is applied to the source address upon
4078 * minor loop completion.
4081 * - 0 - The minor loop offset is not applied to the SADDR
4082 * - 1 - The minor loop offset is applied to the SADDR
4085 #define BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (31U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_SMLOE. */
4086 #define BM_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (0x80000000U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_SMLOE. */
4087 #define BS_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (1U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_SMLOE. */
4089 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_SMLOE field. */
4090 #define BR_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE))
4092 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_SMLOE. */
4093 #define BF_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE) & BM_DMA_TCDn_NBYTES_MLOFFNO_SMLOE)
4095 /*! @brief Set the SMLOE field to a new value. */
4096 #define BW_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE) = (v))
4098 /*******************************************************************************
4099 * HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
4100 ******************************************************************************/
4103 * @brief HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (RW)
4105 * Reset value: 0x00000000U
4107 * One of three registers (this register, TCD_NBYTES_MLNO, or
4108 * TCD_NBYTES_MLOFFNO), defines the number of bytes to transfer per request. Which register to use
4109 * depends on whether minor loop mapping is disabled, enabled but not used for
4110 * this channel, or enabled and used. TCD word 2 is defined as follows if: Minor
4111 * loop mapping is enabled (CR[EMLM] = 1) and Minor loop offset is enabled (SMLOE
4112 * or DMLOE = 1) If minor loop mapping is enabled and SMLOE and DMLOE are cleared,
4113 * then refer to the TCD_NBYTES_MLOFFNO register description. If minor loop
4114 * mapping is disabled, then refer to the TCD_NBYTES_MLNO register description.
4116 typedef union _hw_dma_tcdn_nbytes_mloffyes
4119 struct _hw_dma_tcdn_nbytes_mloffyes_bitfields
4121 uint32_t NBYTES
: 10; /*!< [9:0] Minor Byte Transfer Count */
4122 uint32_t MLOFF
: 20; /*!< [29:10] If SMLOE or DMLOE is set, this
4123 * field represents a sign-extended offset applied to the source or destination
4124 * address to form the next-state value after the minor loop completes. */
4125 uint32_t DMLOE
: 1; /*!< [30] Destination Minor Loop Offset enable */
4126 uint32_t SMLOE
: 1; /*!< [31] Source Minor Loop Offset Enable */
4128 } hw_dma_tcdn_nbytes_mloffyes_t
;
4131 * @name Constants and macros for entire DMA_TCDn_NBYTES_MLOFFYES register
4134 #define HW_DMA_TCDn_NBYTES_MLOFFYES_COUNT (16U)
4136 #define HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n) ((x) + 0x1008U + (0x20U * (n)))
4138 #define HW_DMA_TCDn_NBYTES_MLOFFYES(x, n) (*(__IO hw_dma_tcdn_nbytes_mloffyes_t *) HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n))
4139 #define HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).U)
4140 #define HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).U = (v))
4141 #define HW_DMA_TCDn_NBYTES_MLOFFYES_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) | (v)))
4142 #define HW_DMA_TCDn_NBYTES_MLOFFYES_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~(v)))
4143 #define HW_DMA_TCDn_NBYTES_MLOFFYES_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) ^ (v)))
4147 * Constants & macros for individual DMA_TCDn_NBYTES_MLOFFYES bitfields
4151 * @name Register DMA_TCDn_NBYTES_MLOFFYES, field NBYTES[9:0] (RW)
4153 * Number of bytes to be transferred in each service request of the channel. As
4154 * a channel activates, the appropriate TCD contents load into the eDMA engine,
4155 * and the appropriate reads and writes perform until the minor byte transfer
4156 * count has transferred. This is an indivisible operation and cannot be halted.
4157 * (Although, it may be stalled by using the bandwidth control field, or via
4158 * preemption.) After the minor count is exhausted, the SADDR and DADDR values are
4159 * written back into the TCD memory, the major iteration count is decremented and
4160 * restored to the TCD memory. If the major iteration count is completed, additional
4161 * processing is performed.
4164 #define BP_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (0U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_NBYTES. */
4165 #define BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (0x000003FFU) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_NBYTES. */
4166 #define BS_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (10U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_NBYTES. */
4168 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_NBYTES field. */
4169 #define BR_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).B.NBYTES)
4171 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_NBYTES. */
4172 #define BF_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFYES_NBYTES) & BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES)
4174 /*! @brief Set the NBYTES field to a new value. */
4175 #define BW_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES) | BF_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(v)))
4179 * @name Register DMA_TCDn_NBYTES_MLOFFYES, field MLOFF[29:10] (RW)
4182 #define BP_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (10U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_MLOFF. */
4183 #define BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (0x3FFFFC00U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_MLOFF. */
4184 #define BS_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (20U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_MLOFF. */
4186 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_MLOFF field. */
4187 #define BR_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(x, n) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).B.MLOFF)
4189 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_MLOFF. */
4190 #define BF_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFYES_MLOFF) & BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF)
4192 /*! @brief Set the MLOFF field to a new value. */
4193 #define BW_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF) | BF_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(v)))
4197 * @name Register DMA_TCDn_NBYTES_MLOFFYES, field DMLOE[30] (RW)
4199 * Selects whether the minor loop offset is applied to the destination address
4200 * upon minor loop completion.
4203 * - 0 - The minor loop offset is not applied to the DADDR
4204 * - 1 - The minor loop offset is applied to the DADDR
4207 #define BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (30U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_DMLOE. */
4208 #define BM_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (0x40000000U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_DMLOE. */
4209 #define BS_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (1U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_DMLOE. */
4211 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_DMLOE field. */
4212 #define BR_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE))
4214 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_DMLOE. */
4215 #define BF_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE) & BM_DMA_TCDn_NBYTES_MLOFFYES_DMLOE)
4217 /*! @brief Set the DMLOE field to a new value. */
4218 #define BW_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE) = (v))
4222 * @name Register DMA_TCDn_NBYTES_MLOFFYES, field SMLOE[31] (RW)
4224 * Selects whether the minor loop offset is applied to the source address upon
4225 * minor loop completion.
4228 * - 0 - The minor loop offset is not applied to the SADDR
4229 * - 1 - The minor loop offset is applied to the SADDR
4232 #define BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (31U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_SMLOE. */
4233 #define BM_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (0x80000000U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_SMLOE. */
4234 #define BS_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (1U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_SMLOE. */
4236 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_SMLOE field. */
4237 #define BR_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE))
4239 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_SMLOE. */
4240 #define BF_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE) & BM_DMA_TCDn_NBYTES_MLOFFYES_SMLOE)
4242 /*! @brief Set the SMLOE field to a new value. */
4243 #define BW_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE) = (v))
4245 /*******************************************************************************
4246 * HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment
4247 ******************************************************************************/
4250 * @brief HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment (RW)
4252 * Reset value: 0x00000000U
4254 typedef union _hw_dma_tcdn_slast
4257 struct _hw_dma_tcdn_slast_bitfields
4259 uint32_t SLAST
: 32; /*!< [31:0] Last source Address Adjustment */
4261 } hw_dma_tcdn_slast_t
;
4264 * @name Constants and macros for entire DMA_TCDn_SLAST register
4267 #define HW_DMA_TCDn_SLAST_COUNT (16U)
4269 #define HW_DMA_TCDn_SLAST_ADDR(x, n) ((x) + 0x100CU + (0x20U * (n)))
4271 #define HW_DMA_TCDn_SLAST(x, n) (*(__IO hw_dma_tcdn_slast_t *) HW_DMA_TCDn_SLAST_ADDR(x, n))
4272 #define HW_DMA_TCDn_SLAST_RD(x, n) (HW_DMA_TCDn_SLAST(x, n).U)
4273 #define HW_DMA_TCDn_SLAST_WR(x, n, v) (HW_DMA_TCDn_SLAST(x, n).U = (v))
4274 #define HW_DMA_TCDn_SLAST_SET(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) | (v)))
4275 #define HW_DMA_TCDn_SLAST_CLR(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) & ~(v)))
4276 #define HW_DMA_TCDn_SLAST_TOG(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) ^ (v)))
4280 * Constants & macros for individual DMA_TCDn_SLAST bitfields
4284 * @name Register DMA_TCDn_SLAST, field SLAST[31:0] (RW)
4286 * Adjustment value added to the source address at the completion of the major
4287 * iteration count. This value can be applied to restore the source address to the
4288 * initial value, or adjust the address to reference the next data structure.
4289 * This register uses two's complement notation; the overflow bit is discarded.
4292 #define BP_DMA_TCDn_SLAST_SLAST (0U) /*!< Bit position for DMA_TCDn_SLAST_SLAST. */
4293 #define BM_DMA_TCDn_SLAST_SLAST (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_SLAST_SLAST. */
4294 #define BS_DMA_TCDn_SLAST_SLAST (32U) /*!< Bit field size in bits for DMA_TCDn_SLAST_SLAST. */
4296 /*! @brief Read current value of the DMA_TCDn_SLAST_SLAST field. */
4297 #define BR_DMA_TCDn_SLAST_SLAST(x, n) (HW_DMA_TCDn_SLAST(x, n).U)
4299 /*! @brief Format value for bitfield DMA_TCDn_SLAST_SLAST. */
4300 #define BF_DMA_TCDn_SLAST_SLAST(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_SLAST_SLAST) & BM_DMA_TCDn_SLAST_SLAST)
4302 /*! @brief Set the SLAST field to a new value. */
4303 #define BW_DMA_TCDn_SLAST_SLAST(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, v))
4305 /*******************************************************************************
4306 * HW_DMA_TCDn_DADDR - TCD Destination Address
4307 ******************************************************************************/
4310 * @brief HW_DMA_TCDn_DADDR - TCD Destination Address (RW)
4312 * Reset value: 0x00000000U
4314 typedef union _hw_dma_tcdn_daddr
4317 struct _hw_dma_tcdn_daddr_bitfields
4319 uint32_t DADDR
: 32; /*!< [31:0] Destination Address */
4321 } hw_dma_tcdn_daddr_t
;
4324 * @name Constants and macros for entire DMA_TCDn_DADDR register
4327 #define HW_DMA_TCDn_DADDR_COUNT (16U)
4329 #define HW_DMA_TCDn_DADDR_ADDR(x, n) ((x) + 0x1010U + (0x20U * (n)))
4331 #define HW_DMA_TCDn_DADDR(x, n) (*(__IO hw_dma_tcdn_daddr_t *) HW_DMA_TCDn_DADDR_ADDR(x, n))
4332 #define HW_DMA_TCDn_DADDR_RD(x, n) (HW_DMA_TCDn_DADDR(x, n).U)
4333 #define HW_DMA_TCDn_DADDR_WR(x, n, v) (HW_DMA_TCDn_DADDR(x, n).U = (v))
4334 #define HW_DMA_TCDn_DADDR_SET(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) | (v)))
4335 #define HW_DMA_TCDn_DADDR_CLR(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) & ~(v)))
4336 #define HW_DMA_TCDn_DADDR_TOG(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) ^ (v)))
4340 * Constants & macros for individual DMA_TCDn_DADDR bitfields
4344 * @name Register DMA_TCDn_DADDR, field DADDR[31:0] (RW)
4346 * Memory address pointing to the destination data.
4349 #define BP_DMA_TCDn_DADDR_DADDR (0U) /*!< Bit position for DMA_TCDn_DADDR_DADDR. */
4350 #define BM_DMA_TCDn_DADDR_DADDR (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_DADDR_DADDR. */
4351 #define BS_DMA_TCDn_DADDR_DADDR (32U) /*!< Bit field size in bits for DMA_TCDn_DADDR_DADDR. */
4353 /*! @brief Read current value of the DMA_TCDn_DADDR_DADDR field. */
4354 #define BR_DMA_TCDn_DADDR_DADDR(x, n) (HW_DMA_TCDn_DADDR(x, n).U)
4356 /*! @brief Format value for bitfield DMA_TCDn_DADDR_DADDR. */
4357 #define BF_DMA_TCDn_DADDR_DADDR(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_DADDR_DADDR) & BM_DMA_TCDn_DADDR_DADDR)
4359 /*! @brief Set the DADDR field to a new value. */
4360 #define BW_DMA_TCDn_DADDR_DADDR(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, v))
4362 /*******************************************************************************
4363 * HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset
4364 ******************************************************************************/
4367 * @brief HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset (RW)
4369 * Reset value: 0x0000U
4371 typedef union _hw_dma_tcdn_doff
4374 struct _hw_dma_tcdn_doff_bitfields
4376 uint16_t DOFF
: 16; /*!< [15:0] Destination Address Signed offset */
4378 } hw_dma_tcdn_doff_t
;
4381 * @name Constants and macros for entire DMA_TCDn_DOFF register
4384 #define HW_DMA_TCDn_DOFF_COUNT (16U)
4386 #define HW_DMA_TCDn_DOFF_ADDR(x, n) ((x) + 0x1014U + (0x20U * (n)))
4388 #define HW_DMA_TCDn_DOFF(x, n) (*(__IO hw_dma_tcdn_doff_t *) HW_DMA_TCDn_DOFF_ADDR(x, n))
4389 #define HW_DMA_TCDn_DOFF_RD(x, n) (HW_DMA_TCDn_DOFF(x, n).U)
4390 #define HW_DMA_TCDn_DOFF_WR(x, n, v) (HW_DMA_TCDn_DOFF(x, n).U = (v))
4391 #define HW_DMA_TCDn_DOFF_SET(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) | (v)))
4392 #define HW_DMA_TCDn_DOFF_CLR(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) & ~(v)))
4393 #define HW_DMA_TCDn_DOFF_TOG(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) ^ (v)))
4397 * Constants & macros for individual DMA_TCDn_DOFF bitfields
4401 * @name Register DMA_TCDn_DOFF, field DOFF[15:0] (RW)
4403 * Sign-extended offset applied to the current destination address to form the
4404 * next-state value as each destination write is completed.
4407 #define BP_DMA_TCDn_DOFF_DOFF (0U) /*!< Bit position for DMA_TCDn_DOFF_DOFF. */
4408 #define BM_DMA_TCDn_DOFF_DOFF (0xFFFFU) /*!< Bit mask for DMA_TCDn_DOFF_DOFF. */
4409 #define BS_DMA_TCDn_DOFF_DOFF (16U) /*!< Bit field size in bits for DMA_TCDn_DOFF_DOFF. */
4411 /*! @brief Read current value of the DMA_TCDn_DOFF_DOFF field. */
4412 #define BR_DMA_TCDn_DOFF_DOFF(x, n) (HW_DMA_TCDn_DOFF(x, n).U)
4414 /*! @brief Format value for bitfield DMA_TCDn_DOFF_DOFF. */
4415 #define BF_DMA_TCDn_DOFF_DOFF(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_DOFF_DOFF) & BM_DMA_TCDn_DOFF_DOFF)
4417 /*! @brief Set the DOFF field to a new value. */
4418 #define BW_DMA_TCDn_DOFF_DOFF(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, v))
4420 /*******************************************************************************
4421 * HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
4422 ******************************************************************************/
4425 * @brief HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW)
4427 * Reset value: 0x0000U
4429 * If TCDn_CITER[ELINK] is cleared, the TCDn_CITER register is defined as
4432 typedef union _hw_dma_tcdn_citer_elinkno
4435 struct _hw_dma_tcdn_citer_elinkno_bitfields
4437 uint16_t CITER
: 15; /*!< [14:0] Current Major Iteration Count */
4438 uint16_t ELINK
: 1; /*!< [15] Enable channel-to-channel linking on
4439 * minor-loop complete */
4441 } hw_dma_tcdn_citer_elinkno_t
;
4444 * @name Constants and macros for entire DMA_TCDn_CITER_ELINKNO register
4447 #define HW_DMA_TCDn_CITER_ELINKNO_COUNT (16U)
4449 #define HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n) ((x) + 0x1016U + (0x20U * (n)))
4451 #define HW_DMA_TCDn_CITER_ELINKNO(x, n) (*(__IO hw_dma_tcdn_citer_elinkno_t *) HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n))
4452 #define HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) (HW_DMA_TCDn_CITER_ELINKNO(x, n).U)
4453 #define HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO(x, n).U = (v))
4454 #define HW_DMA_TCDn_CITER_ELINKNO_SET(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) | (v)))
4455 #define HW_DMA_TCDn_CITER_ELINKNO_CLR(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) & ~(v)))
4456 #define HW_DMA_TCDn_CITER_ELINKNO_TOG(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) ^ (v)))
4460 * Constants & macros for individual DMA_TCDn_CITER_ELINKNO bitfields
4464 * @name Register DMA_TCDn_CITER_ELINKNO, field CITER[14:0] (RW)
4466 * This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current
4467 * major loop count for the channel. It is decremented each time the minor loop is
4468 * completed and updated in the transfer control descriptor memory. After the
4469 * major iteration count is exhausted, the channel performs a number of operations
4470 * (e.g., final source and destination address calculations), optionally generating
4471 * an interrupt to signal channel completion before reloading the CITER field
4472 * from the beginning iteration count (BITER) field. When the CITER field is
4473 * initially loaded by software, it must be set to the same value as that contained in
4474 * the BITER field. If the channel is configured to execute a single service
4475 * request, the initial values of BITER and CITER should be 0x0001.
4478 #define BP_DMA_TCDn_CITER_ELINKNO_CITER (0U) /*!< Bit position for DMA_TCDn_CITER_ELINKNO_CITER. */
4479 #define BM_DMA_TCDn_CITER_ELINKNO_CITER (0x7FFFU) /*!< Bit mask for DMA_TCDn_CITER_ELINKNO_CITER. */
4480 #define BS_DMA_TCDn_CITER_ELINKNO_CITER (15U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKNO_CITER. */
4482 /*! @brief Read current value of the DMA_TCDn_CITER_ELINKNO_CITER field. */
4483 #define BR_DMA_TCDn_CITER_ELINKNO_CITER(x, n) (HW_DMA_TCDn_CITER_ELINKNO(x, n).B.CITER)
4485 /*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKNO_CITER. */
4486 #define BF_DMA_TCDn_CITER_ELINKNO_CITER(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKNO_CITER) & BM_DMA_TCDn_CITER_ELINKNO_CITER)
4488 /*! @brief Set the CITER field to a new value. */
4489 #define BW_DMA_TCDn_CITER_ELINKNO_CITER(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, (HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKNO_CITER) | BF_DMA_TCDn_CITER_ELINKNO_CITER(v)))
4493 * @name Register DMA_TCDn_CITER_ELINKNO, field ELINK[15] (RW)
4495 * As the channel completes the minor loop, this flag enables linking to another
4496 * channel, defined by the LINKCH field. The link target channel initiates a
4497 * channel service request via an internal mechanism that sets the TCDn_CSR[START]
4498 * bit of the specified channel. If channel linking is disabled, the CITER value
4499 * is extended to 15 bits in place of a link channel number. If the major loop is
4500 * exhausted, this link mechanism is suppressed in favor of the MAJORELINK
4501 * channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a
4502 * configuration error is reported.
4505 * - 0 - The channel-to-channel linking is disabled
4506 * - 1 - The channel-to-channel linking is enabled
4509 #define BP_DMA_TCDn_CITER_ELINKNO_ELINK (15U) /*!< Bit position for DMA_TCDn_CITER_ELINKNO_ELINK. */
4510 #define BM_DMA_TCDn_CITER_ELINKNO_ELINK (0x8000U) /*!< Bit mask for DMA_TCDn_CITER_ELINKNO_ELINK. */
4511 #define BS_DMA_TCDn_CITER_ELINKNO_ELINK (1U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKNO_ELINK. */
4513 /*! @brief Read current value of the DMA_TCDn_CITER_ELINKNO_ELINK field. */
4514 #define BR_DMA_TCDn_CITER_ELINKNO_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKNO_ELINK))
4516 /*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKNO_ELINK. */
4517 #define BF_DMA_TCDn_CITER_ELINKNO_ELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKNO_ELINK) & BM_DMA_TCDn_CITER_ELINKNO_ELINK)
4519 /*! @brief Set the ELINK field to a new value. */
4520 #define BW_DMA_TCDn_CITER_ELINKNO_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKNO_ELINK) = (v))
4522 /*******************************************************************************
4523 * HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
4524 ******************************************************************************/
4527 * @brief HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW)
4529 * Reset value: 0x0000U
4531 * If TCDn_CITER[ELINK] is set, the TCDn_CITER register is defined as follows.
4533 typedef union _hw_dma_tcdn_citer_elinkyes
4536 struct _hw_dma_tcdn_citer_elinkyes_bitfields
4538 uint16_t CITER
: 9; /*!< [8:0] Current Major Iteration Count */
4539 uint16_t LINKCH
: 4; /*!< [12:9] Link Channel Number */
4540 uint16_t RESERVED0
: 2; /*!< [14:13] */
4541 uint16_t ELINK
: 1; /*!< [15] Enable channel-to-channel linking on
4542 * minor-loop complete */
4544 } hw_dma_tcdn_citer_elinkyes_t
;
4547 * @name Constants and macros for entire DMA_TCDn_CITER_ELINKYES register
4550 #define HW_DMA_TCDn_CITER_ELINKYES_COUNT (16U)
4552 #define HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n) ((x) + 0x1016U + (0x20U * (n)))
4554 #define HW_DMA_TCDn_CITER_ELINKYES(x, n) (*(__IO hw_dma_tcdn_citer_elinkyes_t *) HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n))
4555 #define HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).U)
4556 #define HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES(x, n).U = (v))
4557 #define HW_DMA_TCDn_CITER_ELINKYES_SET(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) | (v)))
4558 #define HW_DMA_TCDn_CITER_ELINKYES_CLR(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~(v)))
4559 #define HW_DMA_TCDn_CITER_ELINKYES_TOG(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) ^ (v)))
4563 * Constants & macros for individual DMA_TCDn_CITER_ELINKYES bitfields
4567 * @name Register DMA_TCDn_CITER_ELINKYES, field CITER[8:0] (RW)
4569 * This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current
4570 * major loop count for the channel. It is decremented each time the minor loop is
4571 * completed and updated in the transfer control descriptor memory. After the
4572 * major iteration count is exhausted, the channel performs a number of operations
4573 * (e.g., final source and destination address calculations), optionally generating
4574 * an interrupt to signal channel completion before reloading the CITER field
4575 * from the beginning iteration count (BITER) field. When the CITER field is
4576 * initially loaded by software, it must be set to the same value as that contained in
4577 * the BITER field. If the channel is configured to execute a single service
4578 * request, the initial values of BITER and CITER should be 0x0001.
4581 #define BP_DMA_TCDn_CITER_ELINKYES_CITER (0U) /*!< Bit position for DMA_TCDn_CITER_ELINKYES_CITER. */
4582 #define BM_DMA_TCDn_CITER_ELINKYES_CITER (0x01FFU) /*!< Bit mask for DMA_TCDn_CITER_ELINKYES_CITER. */
4583 #define BS_DMA_TCDn_CITER_ELINKYES_CITER (9U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_CITER. */
4585 /*! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_CITER field. */
4586 #define BR_DMA_TCDn_CITER_ELINKYES_CITER(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).B.CITER)
4588 /*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_CITER. */
4589 #define BF_DMA_TCDn_CITER_ELINKYES_CITER(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKYES_CITER) & BM_DMA_TCDn_CITER_ELINKYES_CITER)
4591 /*! @brief Set the CITER field to a new value. */
4592 #define BW_DMA_TCDn_CITER_ELINKYES_CITER(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKYES_CITER) | BF_DMA_TCDn_CITER_ELINKYES_CITER(v)))
4596 * @name Register DMA_TCDn_CITER_ELINKYES, field LINKCH[12:9] (RW)
4598 * If channel-to-channel linking is enabled (ELINK = 1), then after the minor
4599 * loop is exhausted, the eDMA engine initiates a channel service request to the
4600 * channel defined by these four bits by setting that channel's TCDn_CSR[START] bit.
4603 #define BP_DMA_TCDn_CITER_ELINKYES_LINKCH (9U) /*!< Bit position for DMA_TCDn_CITER_ELINKYES_LINKCH. */
4604 #define BM_DMA_TCDn_CITER_ELINKYES_LINKCH (0x1E00U) /*!< Bit mask for DMA_TCDn_CITER_ELINKYES_LINKCH. */
4605 #define BS_DMA_TCDn_CITER_ELINKYES_LINKCH (4U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_LINKCH. */
4607 /*! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_LINKCH field. */
4608 #define BR_DMA_TCDn_CITER_ELINKYES_LINKCH(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).B.LINKCH)
4610 /*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_LINKCH. */
4611 #define BF_DMA_TCDn_CITER_ELINKYES_LINKCH(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKYES_LINKCH) & BM_DMA_TCDn_CITER_ELINKYES_LINKCH)
4613 /*! @brief Set the LINKCH field to a new value. */
4614 #define BW_DMA_TCDn_CITER_ELINKYES_LINKCH(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKYES_LINKCH) | BF_DMA_TCDn_CITER_ELINKYES_LINKCH(v)))
4618 * @name Register DMA_TCDn_CITER_ELINKYES, field ELINK[15] (RW)
4620 * As the channel completes the minor loop, this flag enables linking to another
4621 * channel, defined by the LINKCH field. The link target channel initiates a
4622 * channel service request via an internal mechanism that sets the TCDn_CSR[START]
4623 * bit of the specified channel. If channel linking is disabled, the CITER value
4624 * is extended to 15 bits in place of a link channel number. If the major loop is
4625 * exhausted, this link mechanism is suppressed in favor of the MAJORELINK
4626 * channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a
4627 * configuration error is reported.
4630 * - 0 - The channel-to-channel linking is disabled
4631 * - 1 - The channel-to-channel linking is enabled
4634 #define BP_DMA_TCDn_CITER_ELINKYES_ELINK (15U) /*!< Bit position for DMA_TCDn_CITER_ELINKYES_ELINK. */
4635 #define BM_DMA_TCDn_CITER_ELINKYES_ELINK (0x8000U) /*!< Bit mask for DMA_TCDn_CITER_ELINKYES_ELINK. */
4636 #define BS_DMA_TCDn_CITER_ELINKYES_ELINK (1U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_ELINK. */
4638 /*! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_ELINK field. */
4639 #define BR_DMA_TCDn_CITER_ELINKYES_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKYES_ELINK))
4641 /*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_ELINK. */
4642 #define BF_DMA_TCDn_CITER_ELINKYES_ELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKYES_ELINK) & BM_DMA_TCDn_CITER_ELINKYES_ELINK)
4644 /*! @brief Set the ELINK field to a new value. */
4645 #define BW_DMA_TCDn_CITER_ELINKYES_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKYES_ELINK) = (v))
4647 /*******************************************************************************
4648 * HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address
4649 ******************************************************************************/
4652 * @brief HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address (RW)
4654 * Reset value: 0x00000000U
4656 typedef union _hw_dma_tcdn_dlastsga
4659 struct _hw_dma_tcdn_dlastsga_bitfields
4661 uint32_t DLASTSGA
: 32; /*!< [31:0] */
4663 } hw_dma_tcdn_dlastsga_t
;
4666 * @name Constants and macros for entire DMA_TCDn_DLASTSGA register
4669 #define HW_DMA_TCDn_DLASTSGA_COUNT (16U)
4671 #define HW_DMA_TCDn_DLASTSGA_ADDR(x, n) ((x) + 0x1018U + (0x20U * (n)))
4673 #define HW_DMA_TCDn_DLASTSGA(x, n) (*(__IO hw_dma_tcdn_dlastsga_t *) HW_DMA_TCDn_DLASTSGA_ADDR(x, n))
4674 #define HW_DMA_TCDn_DLASTSGA_RD(x, n) (HW_DMA_TCDn_DLASTSGA(x, n).U)
4675 #define HW_DMA_TCDn_DLASTSGA_WR(x, n, v) (HW_DMA_TCDn_DLASTSGA(x, n).U = (v))
4676 #define HW_DMA_TCDn_DLASTSGA_SET(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) | (v)))
4677 #define HW_DMA_TCDn_DLASTSGA_CLR(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) & ~(v)))
4678 #define HW_DMA_TCDn_DLASTSGA_TOG(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) ^ (v)))
4682 * Constants & macros for individual DMA_TCDn_DLASTSGA bitfields
4686 * @name Register DMA_TCDn_DLASTSGA, field DLASTSGA[31:0] (RW)
4688 * Destination last address adjustment or the memory address for the next
4689 * transfer control descriptor to be loaded into this channel (scatter/gather). If
4690 * (TCDn_CSR[ESG] = 0), then: Adjustment value added to the destination address at
4691 * the completion of the major iteration count. This value can apply to restore the
4692 * destination address to the initial value or adjust the address to reference
4693 * the next data structure. This field uses two's complement notation for the
4694 * final destination address adjustment. Otherwise: This address points to the
4695 * beginning of a 0-modulo-32-byte region containing the next transfer control
4696 * descriptor to be loaded into this channel. This channel reload is performed as the
4697 * major iteration count completes. The scatter/gather address must be
4698 * 0-modulo-32-byte, else a configuration error is reported.
4701 #define BP_DMA_TCDn_DLASTSGA_DLASTSGA (0U) /*!< Bit position for DMA_TCDn_DLASTSGA_DLASTSGA. */
4702 #define BM_DMA_TCDn_DLASTSGA_DLASTSGA (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_DLASTSGA_DLASTSGA. */
4703 #define BS_DMA_TCDn_DLASTSGA_DLASTSGA (32U) /*!< Bit field size in bits for DMA_TCDn_DLASTSGA_DLASTSGA. */
4705 /*! @brief Read current value of the DMA_TCDn_DLASTSGA_DLASTSGA field. */
4706 #define BR_DMA_TCDn_DLASTSGA_DLASTSGA(x, n) (HW_DMA_TCDn_DLASTSGA(x, n).U)
4708 /*! @brief Format value for bitfield DMA_TCDn_DLASTSGA_DLASTSGA. */
4709 #define BF_DMA_TCDn_DLASTSGA_DLASTSGA(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_DLASTSGA_DLASTSGA) & BM_DMA_TCDn_DLASTSGA_DLASTSGA)
4711 /*! @brief Set the DLASTSGA field to a new value. */
4712 #define BW_DMA_TCDn_DLASTSGA_DLASTSGA(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, v))
4714 /*******************************************************************************
4715 * HW_DMA_TCDn_CSR - TCD Control and Status
4716 ******************************************************************************/
4719 * @brief HW_DMA_TCDn_CSR - TCD Control and Status (RW)
4721 * Reset value: 0x0000U
4723 typedef union _hw_dma_tcdn_csr
4726 struct _hw_dma_tcdn_csr_bitfields
4728 uint16_t START
: 1; /*!< [0] Channel Start */
4729 uint16_t INTMAJOR
: 1; /*!< [1] Enable an interrupt when major
4730 * iteration count completes */
4731 uint16_t INTHALF
: 1; /*!< [2] Enable an interrupt when major counter
4732 * is half complete. */
4733 uint16_t DREQ
: 1; /*!< [3] Disable Request */
4734 uint16_t ESG
: 1; /*!< [4] Enable Scatter/Gather Processing */
4735 uint16_t MAJORELINK
: 1; /*!< [5] Enable channel-to-channel linking
4736 * on major loop complete */
4737 uint16_t ACTIVE
: 1; /*!< [6] Channel Active */
4738 uint16_t DONE
: 1; /*!< [7] Channel Done */
4739 uint16_t MAJORLINKCH
: 4; /*!< [11:8] Link Channel Number */
4740 uint16_t RESERVED0
: 2; /*!< [13:12] */
4741 uint16_t BWC
: 2; /*!< [15:14] Bandwidth Control */
4743 } hw_dma_tcdn_csr_t
;
4746 * @name Constants and macros for entire DMA_TCDn_CSR register
4749 #define HW_DMA_TCDn_CSR_COUNT (16U)
4751 #define HW_DMA_TCDn_CSR_ADDR(x, n) ((x) + 0x101CU + (0x20U * (n)))
4753 #define HW_DMA_TCDn_CSR(x, n) (*(__IO hw_dma_tcdn_csr_t *) HW_DMA_TCDn_CSR_ADDR(x, n))
4754 #define HW_DMA_TCDn_CSR_RD(x, n) (HW_DMA_TCDn_CSR(x, n).U)
4755 #define HW_DMA_TCDn_CSR_WR(x, n, v) (HW_DMA_TCDn_CSR(x, n).U = (v))
4756 #define HW_DMA_TCDn_CSR_SET(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) | (v)))
4757 #define HW_DMA_TCDn_CSR_CLR(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) & ~(v)))
4758 #define HW_DMA_TCDn_CSR_TOG(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) ^ (v)))
4762 * Constants & macros for individual DMA_TCDn_CSR bitfields
4766 * @name Register DMA_TCDn_CSR, field START[0] (RW)
4768 * If this flag is set, the channel is requesting service. The eDMA hardware
4769 * automatically clears this flag after the channel begins execution.
4772 * - 0 - The channel is not explicitly started
4773 * - 1 - The channel is explicitly started via a software initiated service
4777 #define BP_DMA_TCDn_CSR_START (0U) /*!< Bit position for DMA_TCDn_CSR_START. */
4778 #define BM_DMA_TCDn_CSR_START (0x0001U) /*!< Bit mask for DMA_TCDn_CSR_START. */
4779 #define BS_DMA_TCDn_CSR_START (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_START. */
4781 /*! @brief Read current value of the DMA_TCDn_CSR_START field. */
4782 #define BR_DMA_TCDn_CSR_START(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_START))
4784 /*! @brief Format value for bitfield DMA_TCDn_CSR_START. */
4785 #define BF_DMA_TCDn_CSR_START(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_START) & BM_DMA_TCDn_CSR_START)
4787 /*! @brief Set the START field to a new value. */
4788 #define BW_DMA_TCDn_CSR_START(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_START) = (v))
4792 * @name Register DMA_TCDn_CSR, field INTMAJOR[1] (RW)
4794 * If this flag is set, the channel generates an interrupt request by setting
4795 * the appropriate bit in the INT when the current major iteration count reaches
4799 * - 0 - The end-of-major loop interrupt is disabled
4800 * - 1 - The end-of-major loop interrupt is enabled
4803 #define BP_DMA_TCDn_CSR_INTMAJOR (1U) /*!< Bit position for DMA_TCDn_CSR_INTMAJOR. */
4804 #define BM_DMA_TCDn_CSR_INTMAJOR (0x0002U) /*!< Bit mask for DMA_TCDn_CSR_INTMAJOR. */
4805 #define BS_DMA_TCDn_CSR_INTMAJOR (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_INTMAJOR. */
4807 /*! @brief Read current value of the DMA_TCDn_CSR_INTMAJOR field. */
4808 #define BR_DMA_TCDn_CSR_INTMAJOR(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTMAJOR))
4810 /*! @brief Format value for bitfield DMA_TCDn_CSR_INTMAJOR. */
4811 #define BF_DMA_TCDn_CSR_INTMAJOR(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_INTMAJOR) & BM_DMA_TCDn_CSR_INTMAJOR)
4813 /*! @brief Set the INTMAJOR field to a new value. */
4814 #define BW_DMA_TCDn_CSR_INTMAJOR(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTMAJOR) = (v))
4818 * @name Register DMA_TCDn_CSR, field INTHALF[2] (RW)
4820 * If this flag is set, the channel generates an interrupt request by setting
4821 * the appropriate bit in the INT register when the current major iteration count
4822 * reaches the halfway point. Specifically, the comparison performed by the eDMA
4823 * engine is (CITER == (BITER >> 1)). This halfway point interrupt request is
4824 * provided to support double-buffered (aka ping-pong) schemes or other types of data
4825 * movement where the processor needs an early indication of the transfer's
4826 * progress. If BITER is set, do not use INTHALF. Use INTMAJOR instead.
4829 * - 0 - The half-point interrupt is disabled
4830 * - 1 - The half-point interrupt is enabled
4833 #define BP_DMA_TCDn_CSR_INTHALF (2U) /*!< Bit position for DMA_TCDn_CSR_INTHALF. */
4834 #define BM_DMA_TCDn_CSR_INTHALF (0x0004U) /*!< Bit mask for DMA_TCDn_CSR_INTHALF. */
4835 #define BS_DMA_TCDn_CSR_INTHALF (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_INTHALF. */
4837 /*! @brief Read current value of the DMA_TCDn_CSR_INTHALF field. */
4838 #define BR_DMA_TCDn_CSR_INTHALF(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTHALF))
4840 /*! @brief Format value for bitfield DMA_TCDn_CSR_INTHALF. */
4841 #define BF_DMA_TCDn_CSR_INTHALF(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_INTHALF) & BM_DMA_TCDn_CSR_INTHALF)
4843 /*! @brief Set the INTHALF field to a new value. */
4844 #define BW_DMA_TCDn_CSR_INTHALF(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTHALF) = (v))
4848 * @name Register DMA_TCDn_CSR, field DREQ[3] (RW)
4850 * If this flag is set, the eDMA hardware automatically clears the corresponding
4851 * ERQ bit when the current major iteration count reaches zero.
4854 * - 0 - The channel's ERQ bit is not affected
4855 * - 1 - The channel's ERQ bit is cleared when the major loop is complete
4858 #define BP_DMA_TCDn_CSR_DREQ (3U) /*!< Bit position for DMA_TCDn_CSR_DREQ. */
4859 #define BM_DMA_TCDn_CSR_DREQ (0x0008U) /*!< Bit mask for DMA_TCDn_CSR_DREQ. */
4860 #define BS_DMA_TCDn_CSR_DREQ (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_DREQ. */
4862 /*! @brief Read current value of the DMA_TCDn_CSR_DREQ field. */
4863 #define BR_DMA_TCDn_CSR_DREQ(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DREQ))
4865 /*! @brief Format value for bitfield DMA_TCDn_CSR_DREQ. */
4866 #define BF_DMA_TCDn_CSR_DREQ(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_DREQ) & BM_DMA_TCDn_CSR_DREQ)
4868 /*! @brief Set the DREQ field to a new value. */
4869 #define BW_DMA_TCDn_CSR_DREQ(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DREQ) = (v))
4873 * @name Register DMA_TCDn_CSR, field ESG[4] (RW)
4875 * As the channel completes the major loop, this flag enables scatter/gather
4876 * processing in the current channel. If enabled, the eDMA engine uses DLASTSGA as a
4877 * memory pointer to a 0-modulo-32 address containing a 32-byte data structure
4878 * loaded as the transfer control descriptor into the local memory. To support the
4879 * dynamic scatter/gather coherency model, this field is forced to zero when
4880 * written to while the TCDn_CSR[DONE] bit is set.
4883 * - 0 - The current channel's TCD is normal format.
4884 * - 1 - The current channel's TCD specifies a scatter gather format. The
4885 * DLASTSGA field provides a memory pointer to the next TCD to be loaded into this
4886 * channel after the major loop completes its execution.
4889 #define BP_DMA_TCDn_CSR_ESG (4U) /*!< Bit position for DMA_TCDn_CSR_ESG. */
4890 #define BM_DMA_TCDn_CSR_ESG (0x0010U) /*!< Bit mask for DMA_TCDn_CSR_ESG. */
4891 #define BS_DMA_TCDn_CSR_ESG (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_ESG. */
4893 /*! @brief Read current value of the DMA_TCDn_CSR_ESG field. */
4894 #define BR_DMA_TCDn_CSR_ESG(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ESG))
4896 /*! @brief Format value for bitfield DMA_TCDn_CSR_ESG. */
4897 #define BF_DMA_TCDn_CSR_ESG(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_ESG) & BM_DMA_TCDn_CSR_ESG)
4899 /*! @brief Set the ESG field to a new value. */
4900 #define BW_DMA_TCDn_CSR_ESG(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ESG) = (v))
4904 * @name Register DMA_TCDn_CSR, field MAJORELINK[5] (RW)
4906 * As the channel completes the major loop, this flag enables the linking to
4907 * another channel, defined by MAJORLINKCH. The link target channel initiates a
4908 * channel service request via an internal mechanism that sets the TCDn_CSR[START]
4909 * bit of the specified channel. To support the dynamic linking coherency model,
4910 * this field is forced to zero when written to while the TCDn_CSR[DONE] bit is set.
4913 * - 0 - The channel-to-channel linking is disabled
4914 * - 1 - The channel-to-channel linking is enabled
4917 #define BP_DMA_TCDn_CSR_MAJORELINK (5U) /*!< Bit position for DMA_TCDn_CSR_MAJORELINK. */
4918 #define BM_DMA_TCDn_CSR_MAJORELINK (0x0020U) /*!< Bit mask for DMA_TCDn_CSR_MAJORELINK. */
4919 #define BS_DMA_TCDn_CSR_MAJORELINK (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_MAJORELINK. */
4921 /*! @brief Read current value of the DMA_TCDn_CSR_MAJORELINK field. */
4922 #define BR_DMA_TCDn_CSR_MAJORELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_MAJORELINK))
4924 /*! @brief Format value for bitfield DMA_TCDn_CSR_MAJORELINK. */
4925 #define BF_DMA_TCDn_CSR_MAJORELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_MAJORELINK) & BM_DMA_TCDn_CSR_MAJORELINK)
4927 /*! @brief Set the MAJORELINK field to a new value. */
4928 #define BW_DMA_TCDn_CSR_MAJORELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_MAJORELINK) = (v))
4932 * @name Register DMA_TCDn_CSR, field ACTIVE[6] (RW)
4934 * This flag signals the channel is currently in execution. It is set when
4935 * channel service begins, and the eDMA clears it as the minor loop completes or if
4936 * any error condition is detected. This bit resets to zero.
4939 #define BP_DMA_TCDn_CSR_ACTIVE (6U) /*!< Bit position for DMA_TCDn_CSR_ACTIVE. */
4940 #define BM_DMA_TCDn_CSR_ACTIVE (0x0040U) /*!< Bit mask for DMA_TCDn_CSR_ACTIVE. */
4941 #define BS_DMA_TCDn_CSR_ACTIVE (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_ACTIVE. */
4943 /*! @brief Read current value of the DMA_TCDn_CSR_ACTIVE field. */
4944 #define BR_DMA_TCDn_CSR_ACTIVE(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ACTIVE))
4946 /*! @brief Format value for bitfield DMA_TCDn_CSR_ACTIVE. */
4947 #define BF_DMA_TCDn_CSR_ACTIVE(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_ACTIVE) & BM_DMA_TCDn_CSR_ACTIVE)
4949 /*! @brief Set the ACTIVE field to a new value. */
4950 #define BW_DMA_TCDn_CSR_ACTIVE(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ACTIVE) = (v))
4954 * @name Register DMA_TCDn_CSR, field DONE[7] (RW)
4956 * This flag indicates the eDMA has completed the major loop. The eDMA engine
4957 * sets it as the CITER count reaches zero; The software clears it, or the hardware
4958 * when the channel is activated. This bit must be cleared to write the
4959 * MAJORELINK or ESG bits.
4962 #define BP_DMA_TCDn_CSR_DONE (7U) /*!< Bit position for DMA_TCDn_CSR_DONE. */
4963 #define BM_DMA_TCDn_CSR_DONE (0x0080U) /*!< Bit mask for DMA_TCDn_CSR_DONE. */
4964 #define BS_DMA_TCDn_CSR_DONE (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_DONE. */
4966 /*! @brief Read current value of the DMA_TCDn_CSR_DONE field. */
4967 #define BR_DMA_TCDn_CSR_DONE(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DONE))
4969 /*! @brief Format value for bitfield DMA_TCDn_CSR_DONE. */
4970 #define BF_DMA_TCDn_CSR_DONE(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_DONE) & BM_DMA_TCDn_CSR_DONE)
4972 /*! @brief Set the DONE field to a new value. */
4973 #define BW_DMA_TCDn_CSR_DONE(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DONE) = (v))
4977 * @name Register DMA_TCDn_CSR, field MAJORLINKCH[11:8] (RW)
4979 * If (MAJORELINK = 0) then No channel-to-channel linking (or chaining) is
4980 * performed after the major loop counter is exhausted. else After the major loop
4981 * counter is exhausted, the eDMA engine initiates a channel service request at the
4982 * channel defined by these six bits by setting that channel's TCDn_CSR[START] bit.
4985 #define BP_DMA_TCDn_CSR_MAJORLINKCH (8U) /*!< Bit position for DMA_TCDn_CSR_MAJORLINKCH. */
4986 #define BM_DMA_TCDn_CSR_MAJORLINKCH (0x0F00U) /*!< Bit mask for DMA_TCDn_CSR_MAJORLINKCH. */
4987 #define BS_DMA_TCDn_CSR_MAJORLINKCH (4U) /*!< Bit field size in bits for DMA_TCDn_CSR_MAJORLINKCH. */
4989 /*! @brief Read current value of the DMA_TCDn_CSR_MAJORLINKCH field. */
4990 #define BR_DMA_TCDn_CSR_MAJORLINKCH(x, n) (HW_DMA_TCDn_CSR(x, n).B.MAJORLINKCH)
4992 /*! @brief Format value for bitfield DMA_TCDn_CSR_MAJORLINKCH. */
4993 #define BF_DMA_TCDn_CSR_MAJORLINKCH(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_MAJORLINKCH) & BM_DMA_TCDn_CSR_MAJORLINKCH)
4995 /*! @brief Set the MAJORLINKCH field to a new value. */
4996 #define BW_DMA_TCDn_CSR_MAJORLINKCH(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, (HW_DMA_TCDn_CSR_RD(x, n) & ~BM_DMA_TCDn_CSR_MAJORLINKCH) | BF_DMA_TCDn_CSR_MAJORLINKCH(v)))
5000 * @name Register DMA_TCDn_CSR, field BWC[15:14] (RW)
5002 * Throttles the amount of bus bandwidth consumed by the eDMA. In general, as
5003 * the eDMA processes the minor loop, it continuously generates read/write
5004 * sequences until the minor count is exhausted. This field forces the eDMA to stall
5005 * after the completion of each read/write access to control the bus request
5006 * bandwidth seen by the crossbar switch. If the source and destination sizes are equal,
5007 * this field is ignored between the first and second transfers and after the
5008 * last write of each minor loop. This behavior is a side effect of reducing
5012 * - 00 - No eDMA engine stalls
5014 * - 10 - eDMA engine stalls for 4 cycles after each r/w
5015 * - 11 - eDMA engine stalls for 8 cycles after each r/w
5018 #define BP_DMA_TCDn_CSR_BWC (14U) /*!< Bit position for DMA_TCDn_CSR_BWC. */
5019 #define BM_DMA_TCDn_CSR_BWC (0xC000U) /*!< Bit mask for DMA_TCDn_CSR_BWC. */
5020 #define BS_DMA_TCDn_CSR_BWC (2U) /*!< Bit field size in bits for DMA_TCDn_CSR_BWC. */
5022 /*! @brief Read current value of the DMA_TCDn_CSR_BWC field. */
5023 #define BR_DMA_TCDn_CSR_BWC(x, n) (HW_DMA_TCDn_CSR(x, n).B.BWC)
5025 /*! @brief Format value for bitfield DMA_TCDn_CSR_BWC. */
5026 #define BF_DMA_TCDn_CSR_BWC(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_BWC) & BM_DMA_TCDn_CSR_BWC)
5028 /*! @brief Set the BWC field to a new value. */
5029 #define BW_DMA_TCDn_CSR_BWC(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, (HW_DMA_TCDn_CSR_RD(x, n) & ~BM_DMA_TCDn_CSR_BWC) | BF_DMA_TCDn_CSR_BWC(v)))
5031 /*******************************************************************************
5032 * HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
5033 ******************************************************************************/
5036 * @brief HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW)
5038 * Reset value: 0x0000U
5040 * If the TCDn_BITER[ELINK] bit is cleared, the TCDn_BITER register is defined
5043 typedef union _hw_dma_tcdn_biter_elinkno
5046 struct _hw_dma_tcdn_biter_elinkno_bitfields
5048 uint16_t BITER
: 15; /*!< [14:0] Starting Major Iteration Count */
5049 uint16_t ELINK
: 1; /*!< [15] Enables channel-to-channel linking on
5050 * minor loop complete */
5052 } hw_dma_tcdn_biter_elinkno_t
;
5055 * @name Constants and macros for entire DMA_TCDn_BITER_ELINKNO register
5058 #define HW_DMA_TCDn_BITER_ELINKNO_COUNT (16U)
5060 #define HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n) ((x) + 0x101EU + (0x20U * (n)))
5062 #define HW_DMA_TCDn_BITER_ELINKNO(x, n) (*(__IO hw_dma_tcdn_biter_elinkno_t *) HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n))
5063 #define HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) (HW_DMA_TCDn_BITER_ELINKNO(x, n).U)
5064 #define HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO(x, n).U = (v))
5065 #define HW_DMA_TCDn_BITER_ELINKNO_SET(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) | (v)))
5066 #define HW_DMA_TCDn_BITER_ELINKNO_CLR(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) & ~(v)))
5067 #define HW_DMA_TCDn_BITER_ELINKNO_TOG(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) ^ (v)))
5071 * Constants & macros for individual DMA_TCDn_BITER_ELINKNO bitfields
5075 * @name Register DMA_TCDn_BITER_ELINKNO, field BITER[14:0] (RW)
5077 * As the transfer control descriptor is first loaded by software, this 9-bit
5078 * (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER
5079 * field. As the major iteration count is exhausted, the contents of this field
5080 * are reloaded into the CITER field. When the software loads the TCD, this field
5081 * must be set equal to the corresponding CITER field; otherwise, a configuration
5082 * error is reported. As the major iteration count is exhausted, the contents of
5083 * this field is reloaded into the CITER field. If the channel is configured to
5084 * execute a single service request, the initial values of BITER and CITER should
5088 #define BP_DMA_TCDn_BITER_ELINKNO_BITER (0U) /*!< Bit position for DMA_TCDn_BITER_ELINKNO_BITER. */
5089 #define BM_DMA_TCDn_BITER_ELINKNO_BITER (0x7FFFU) /*!< Bit mask for DMA_TCDn_BITER_ELINKNO_BITER. */
5090 #define BS_DMA_TCDn_BITER_ELINKNO_BITER (15U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKNO_BITER. */
5092 /*! @brief Read current value of the DMA_TCDn_BITER_ELINKNO_BITER field. */
5093 #define BR_DMA_TCDn_BITER_ELINKNO_BITER(x, n) (HW_DMA_TCDn_BITER_ELINKNO(x, n).B.BITER)
5095 /*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKNO_BITER. */
5096 #define BF_DMA_TCDn_BITER_ELINKNO_BITER(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKNO_BITER) & BM_DMA_TCDn_BITER_ELINKNO_BITER)
5098 /*! @brief Set the BITER field to a new value. */
5099 #define BW_DMA_TCDn_BITER_ELINKNO_BITER(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, (HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKNO_BITER) | BF_DMA_TCDn_BITER_ELINKNO_BITER(v)))
5103 * @name Register DMA_TCDn_BITER_ELINKNO, field ELINK[15] (RW)
5105 * As the channel completes the minor loop, this flag enables the linking to
5106 * another channel, defined by BITER[LINKCH]. The link target channel initiates a
5107 * channel service request via an internal mechanism that sets the TCDn_CSR[START]
5108 * bit of the specified channel. If channel linking is disabled, the BITER value
5109 * extends to 15 bits in place of a link channel number. If the major loop is
5110 * exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
5111 * linking. When the software loads the TCD, this field must be set equal to the
5112 * corresponding CITER field; otherwise, a configuration error is reported. As the
5113 * major iteration count is exhausted, the contents of this field is reloaded
5114 * into the CITER field.
5117 * - 0 - The channel-to-channel linking is disabled
5118 * - 1 - The channel-to-channel linking is enabled
5121 #define BP_DMA_TCDn_BITER_ELINKNO_ELINK (15U) /*!< Bit position for DMA_TCDn_BITER_ELINKNO_ELINK. */
5122 #define BM_DMA_TCDn_BITER_ELINKNO_ELINK (0x8000U) /*!< Bit mask for DMA_TCDn_BITER_ELINKNO_ELINK. */
5123 #define BS_DMA_TCDn_BITER_ELINKNO_ELINK (1U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKNO_ELINK. */
5125 /*! @brief Read current value of the DMA_TCDn_BITER_ELINKNO_ELINK field. */
5126 #define BR_DMA_TCDn_BITER_ELINKNO_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKNO_ELINK))
5128 /*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKNO_ELINK. */
5129 #define BF_DMA_TCDn_BITER_ELINKNO_ELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKNO_ELINK) & BM_DMA_TCDn_BITER_ELINKNO_ELINK)
5131 /*! @brief Set the ELINK field to a new value. */
5132 #define BW_DMA_TCDn_BITER_ELINKNO_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKNO_ELINK) = (v))
5134 /*******************************************************************************
5135 * HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
5136 ******************************************************************************/
5139 * @brief HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW)
5141 * Reset value: 0x0000U
5143 * If the TCDn_BITER[ELINK] bit is set, the TCDn_BITER register is defined as
5146 typedef union _hw_dma_tcdn_biter_elinkyes
5149 struct _hw_dma_tcdn_biter_elinkyes_bitfields
5151 uint16_t BITER
: 9; /*!< [8:0] Starting Major Iteration Count */
5152 uint16_t LINKCH
: 4; /*!< [12:9] Link Channel Number */
5153 uint16_t RESERVED0
: 2; /*!< [14:13] */
5154 uint16_t ELINK
: 1; /*!< [15] Enables channel-to-channel linking on
5155 * minor loop complete */
5157 } hw_dma_tcdn_biter_elinkyes_t
;
5160 * @name Constants and macros for entire DMA_TCDn_BITER_ELINKYES register
5163 #define HW_DMA_TCDn_BITER_ELINKYES_COUNT (16U)
5165 #define HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n) ((x) + 0x101EU + (0x20U * (n)))
5167 #define HW_DMA_TCDn_BITER_ELINKYES(x, n) (*(__IO hw_dma_tcdn_biter_elinkyes_t *) HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n))
5168 #define HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).U)
5169 #define HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES(x, n).U = (v))
5170 #define HW_DMA_TCDn_BITER_ELINKYES_SET(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) | (v)))
5171 #define HW_DMA_TCDn_BITER_ELINKYES_CLR(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~(v)))
5172 #define HW_DMA_TCDn_BITER_ELINKYES_TOG(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) ^ (v)))
5176 * Constants & macros for individual DMA_TCDn_BITER_ELINKYES bitfields
5180 * @name Register DMA_TCDn_BITER_ELINKYES, field BITER[8:0] (RW)
5182 * As the transfer control descriptor is first loaded by software, this 9-bit
5183 * (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER
5184 * field. As the major iteration count is exhausted, the contents of this field
5185 * are reloaded into the CITER field. When the software loads the TCD, this field
5186 * must be set equal to the corresponding CITER field; otherwise, a configuration
5187 * error is reported. As the major iteration count is exhausted, the contents of
5188 * this field is reloaded into the CITER field. If the channel is configured to
5189 * execute a single service request, the initial values of BITER and CITER should
5193 #define BP_DMA_TCDn_BITER_ELINKYES_BITER (0U) /*!< Bit position for DMA_TCDn_BITER_ELINKYES_BITER. */
5194 #define BM_DMA_TCDn_BITER_ELINKYES_BITER (0x01FFU) /*!< Bit mask for DMA_TCDn_BITER_ELINKYES_BITER. */
5195 #define BS_DMA_TCDn_BITER_ELINKYES_BITER (9U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_BITER. */
5197 /*! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_BITER field. */
5198 #define BR_DMA_TCDn_BITER_ELINKYES_BITER(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).B.BITER)
5200 /*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_BITER. */
5201 #define BF_DMA_TCDn_BITER_ELINKYES_BITER(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKYES_BITER) & BM_DMA_TCDn_BITER_ELINKYES_BITER)
5203 /*! @brief Set the BITER field to a new value. */
5204 #define BW_DMA_TCDn_BITER_ELINKYES_BITER(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKYES_BITER) | BF_DMA_TCDn_BITER_ELINKYES_BITER(v)))
5208 * @name Register DMA_TCDn_BITER_ELINKYES, field LINKCH[12:9] (RW)
5210 * If channel-to-channel linking is enabled (ELINK = 1), then after the minor
5211 * loop is exhausted, the eDMA engine initiates a channel service request at the
5212 * channel defined by these four bits by setting that channel's TCDn_CSR[START]
5213 * bit. When the software loads the TCD, this field must be set equal to the
5214 * corresponding CITER field; otherwise, a configuration error is reported. As the major
5215 * iteration count is exhausted, the contents of this field is reloaded into the
5219 #define BP_DMA_TCDn_BITER_ELINKYES_LINKCH (9U) /*!< Bit position for DMA_TCDn_BITER_ELINKYES_LINKCH. */
5220 #define BM_DMA_TCDn_BITER_ELINKYES_LINKCH (0x1E00U) /*!< Bit mask for DMA_TCDn_BITER_ELINKYES_LINKCH. */
5221 #define BS_DMA_TCDn_BITER_ELINKYES_LINKCH (4U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_LINKCH. */
5223 /*! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_LINKCH field. */
5224 #define BR_DMA_TCDn_BITER_ELINKYES_LINKCH(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).B.LINKCH)
5226 /*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_LINKCH. */
5227 #define BF_DMA_TCDn_BITER_ELINKYES_LINKCH(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKYES_LINKCH) & BM_DMA_TCDn_BITER_ELINKYES_LINKCH)
5229 /*! @brief Set the LINKCH field to a new value. */
5230 #define BW_DMA_TCDn_BITER_ELINKYES_LINKCH(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKYES_LINKCH) | BF_DMA_TCDn_BITER_ELINKYES_LINKCH(v)))
5234 * @name Register DMA_TCDn_BITER_ELINKYES, field ELINK[15] (RW)
5236 * As the channel completes the minor loop, this flag enables the linking to
5237 * another channel, defined by BITER[LINKCH]. The link target channel initiates a
5238 * channel service request via an internal mechanism that sets the TCDn_CSR[START]
5239 * bit of the specified channel. If channel linking disables, the BITER value
5240 * extends to 15 bits in place of a link channel number. If the major loop is
5241 * exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
5242 * linking. When the software loads the TCD, this field must be set equal to the
5243 * corresponding CITER field; otherwise, a configuration error is reported. As the
5244 * major iteration count is exhausted, the contents of this field is reloaded into
5248 * - 0 - The channel-to-channel linking is disabled
5249 * - 1 - The channel-to-channel linking is enabled
5252 #define BP_DMA_TCDn_BITER_ELINKYES_ELINK (15U) /*!< Bit position for DMA_TCDn_BITER_ELINKYES_ELINK. */
5253 #define BM_DMA_TCDn_BITER_ELINKYES_ELINK (0x8000U) /*!< Bit mask for DMA_TCDn_BITER_ELINKYES_ELINK. */
5254 #define BS_DMA_TCDn_BITER_ELINKYES_ELINK (1U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_ELINK. */
5256 /*! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_ELINK field. */
5257 #define BR_DMA_TCDn_BITER_ELINKYES_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKYES_ELINK))
5259 /*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_ELINK. */
5260 #define BF_DMA_TCDn_BITER_ELINKYES_ELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKYES_ELINK) & BM_DMA_TCDn_BITER_ELINKYES_ELINK)
5262 /*! @brief Set the ELINK field to a new value. */
5263 #define BW_DMA_TCDn_BITER_ELINKYES_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKYES_ELINK) = (v))
5267 ** Start of section using anonymous unions
5270 #if defined(__ARMCC_VERSION)
5273 #elif defined(__CWCC__)
5275 #pragma cpp_extensions on
5276 #elif defined(__GNUC__)
5277 /* anonymous unions are enabled by default */
5278 #elif defined(__IAR_SYSTEMS_ICC__)
5279 #pragma language=extended
5281 #error Not supported compiler type
5284 /*******************************************************************************
5285 * hw_dma_t - module struct
5286 ******************************************************************************/
5288 * @brief All DMA module registers.
5291 typedef struct _hw_dma
5293 __IO hw_dma_cr_t CR
; /*!< [0x0] Control Register */
5294 __I hw_dma_es_t ES
; /*!< [0x4] Error Status Register */
5295 uint8_t _reserved0
[4];
5296 __IO hw_dma_erq_t ERQ
; /*!< [0xC] Enable Request Register */
5297 uint8_t _reserved1
[4];
5298 __IO hw_dma_eei_t EEI
; /*!< [0x14] Enable Error Interrupt Register */
5299 __O hw_dma_ceei_t CEEI
; /*!< [0x18] Clear Enable Error Interrupt Register */
5300 __O hw_dma_seei_t SEEI
; /*!< [0x19] Set Enable Error Interrupt Register */
5301 __O hw_dma_cerq_t CERQ
; /*!< [0x1A] Clear Enable Request Register */
5302 __O hw_dma_serq_t SERQ
; /*!< [0x1B] Set Enable Request Register */
5303 __O hw_dma_cdne_t CDNE
; /*!< [0x1C] Clear DONE Status Bit Register */
5304 __O hw_dma_ssrt_t SSRT
; /*!< [0x1D] Set START Bit Register */
5305 __O hw_dma_cerr_t CERR
; /*!< [0x1E] Clear Error Register */
5306 __O hw_dma_cint_t CINT
; /*!< [0x1F] Clear Interrupt Request Register */
5307 uint8_t _reserved2
[4];
5308 __IO hw_dma_int_t INT
; /*!< [0x24] Interrupt Request Register */
5309 uint8_t _reserved3
[4];
5310 __IO hw_dma_err_t ERR
; /*!< [0x2C] Error Register */
5311 uint8_t _reserved4
[4];
5312 __I hw_dma_hrs_t HRS
; /*!< [0x34] Hardware Request Status Register */
5313 uint8_t _reserved5
[200];
5314 __IO hw_dma_dchprin_t DCHPRIn
[16]; /*!< [0x100] Channel n Priority Register */
5315 uint8_t _reserved6
[3824];
5317 __IO hw_dma_tcdn_saddr_t TCDn_SADDR
; /*!< [0x1000] TCD Source Address */
5318 __IO hw_dma_tcdn_soff_t TCDn_SOFF
; /*!< [0x1004] TCD Signed Source Address Offset */
5319 __IO hw_dma_tcdn_attr_t TCDn_ATTR
; /*!< [0x1006] TCD Transfer Attributes */
5321 __IO hw_dma_tcdn_nbytes_mlno_t TCDn_NBYTES_MLNO
; /*!< [0x1008] TCD Minor Byte Count (Minor Loop Disabled) */
5322 __IO hw_dma_tcdn_nbytes_mloffno_t TCDn_NBYTES_MLOFFNO
; /*!< [0x1008] TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */
5323 __IO hw_dma_tcdn_nbytes_mloffyes_t TCDn_NBYTES_MLOFFYES
; /*!< [0x1008] TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */
5325 __IO hw_dma_tcdn_slast_t TCDn_SLAST
; /*!< [0x100C] TCD Last Source Address Adjustment */
5326 __IO hw_dma_tcdn_daddr_t TCDn_DADDR
; /*!< [0x1010] TCD Destination Address */
5327 __IO hw_dma_tcdn_doff_t TCDn_DOFF
; /*!< [0x1014] TCD Signed Destination Address Offset */
5329 __IO hw_dma_tcdn_citer_elinkno_t TCDn_CITER_ELINKNO
; /*!< [0x1016] TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
5330 __IO hw_dma_tcdn_citer_elinkyes_t TCDn_CITER_ELINKYES
; /*!< [0x1016] TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
5332 __IO hw_dma_tcdn_dlastsga_t TCDn_DLASTSGA
; /*!< [0x1018] TCD Last Destination Address Adjustment/Scatter Gather Address */
5333 __IO hw_dma_tcdn_csr_t TCDn_CSR
; /*!< [0x101C] TCD Control and Status */
5335 __IO hw_dma_tcdn_biter_elinkno_t TCDn_BITER_ELINKNO
; /*!< [0x101E] TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
5336 __IO hw_dma_tcdn_biter_elinkyes_t TCDn_BITER_ELINKYES
; /*!< [0x101E] TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
5342 /*! @brief Macro to access all DMA registers. */
5343 /*! @param x DMA module instance base address. */
5344 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
5345 * use the '&' operator, like <code>&HW_DMA(DMA_BASE)</code>. */
5346 #define HW_DMA(x) (*(hw_dma_t *)(x))
5349 ** End of section using anonymous unions
5352 #if defined(__ARMCC_VERSION)
5354 #elif defined(__CWCC__)
5356 #elif defined(__GNUC__)
5357 /* leave anonymous unions enabled */
5358 #elif defined(__IAR_SYSTEMS_ICC__)
5359 #pragma language=default
5361 #error Not supported compiler type
5364 #endif /* __HW_DMA_REGISTERS_H__ */