2 ** ###################################################################
3 ** Compilers: Keil ARM C/C++ Compiler
4 ** Freescale C/C++ for Embedded ARM
6 ** IAR ANSI C/C++ Compiler for ARM
8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
9 ** Version: rev. 2.5, 2014-02-10
13 ** Extension to the CMSIS register access layer header.
15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
16 ** All rights reserved.
18 ** Redistribution and use in source and binary forms, with or without modification,
19 ** are permitted provided that the following conditions are met:
21 ** o Redistributions of source code must retain the above copyright notice, this list
22 ** of conditions and the following disclaimer.
24 ** o Redistributions in binary form must reproduce the above copyright notice, this
25 ** list of conditions and the following disclaimer in the documentation and/or
26 ** other materials provided with the distribution.
28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
29 ** contributors may be used to endorse or promote products derived from this
30 ** software without specific prior written permission.
32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ** http: www.freescale.com
44 ** mail: support@freescale.com
47 ** - rev. 1.0 (2013-08-12)
49 ** - rev. 2.0 (2013-10-29)
50 ** Register accessor macros added to the memory map.
51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
52 ** Startup file for gcc has been updated according to CMSIS 3.2.
53 ** System initialization updated.
54 ** MCG - registers updated.
55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
56 ** - rev. 2.1 (2013-10-30)
57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
58 ** - rev. 2.2 (2013-12-09)
59 ** DMA - EARS register removed.
60 ** AIPS0, AIPS1 - MPRA register updated.
61 ** - rev. 2.3 (2014-01-24)
62 ** Update according to reference manual rev. 2
63 ** ENET, MCG, MCM, SIM, USB - registers updated
64 ** - rev. 2.4 (2014-02-10)
65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
67 ** - rev. 2.5 (2014-02-10)
68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
72 ** ###################################################################
76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
78 * This file was generated automatically and any changes may be lost.
80 #ifndef __HW_FMC_REGISTERS_H__
81 #define __HW_FMC_REGISTERS_H__
84 #include "fsl_bitaccess.h"
89 * Flash Memory Controller
91 * Registers defined in this header file:
92 * - HW_FMC_PFAPR - Flash Access Protection Register
93 * - HW_FMC_PFB0CR - Flash Bank 0 Control Register
94 * - HW_FMC_PFB1CR - Flash Bank 1 Control Register
95 * - HW_FMC_TAGVDW0Sn - Cache Tag Storage
96 * - HW_FMC_TAGVDW1Sn - Cache Tag Storage
97 * - HW_FMC_TAGVDW2Sn - Cache Tag Storage
98 * - HW_FMC_TAGVDW3Sn - Cache Tag Storage
99 * - HW_FMC_DATAW0SnU - Cache Data Storage (upper word)
100 * - HW_FMC_DATAW0SnL - Cache Data Storage (lower word)
101 * - HW_FMC_DATAW1SnU - Cache Data Storage (upper word)
102 * - HW_FMC_DATAW1SnL - Cache Data Storage (lower word)
103 * - HW_FMC_DATAW2SnU - Cache Data Storage (upper word)
104 * - HW_FMC_DATAW2SnL - Cache Data Storage (lower word)
105 * - HW_FMC_DATAW3SnU - Cache Data Storage (upper word)
106 * - HW_FMC_DATAW3SnL - Cache Data Storage (lower word)
108 * - hw_fmc_t - Struct containing all module registers.
111 #define HW_FMC_INSTANCE_COUNT (1U) /*!< Number of instances of the FMC module. */
113 /*******************************************************************************
114 * HW_FMC_PFAPR - Flash Access Protection Register
115 ******************************************************************************/
118 * @brief HW_FMC_PFAPR - Flash Access Protection Register (RW)
120 * Reset value: 0x00F8003FU
122 typedef union _hw_fmc_pfapr
125 struct _hw_fmc_pfapr_bitfields
127 uint32_t M0AP
: 2; /*!< [1:0] Master 0 Access Protection */
128 uint32_t M1AP
: 2; /*!< [3:2] Master 1 Access Protection */
129 uint32_t M2AP
: 2; /*!< [5:4] Master 2 Access Protection */
130 uint32_t M3AP
: 2; /*!< [7:6] Master 3 Access Protection */
131 uint32_t M4AP
: 2; /*!< [9:8] Master 4 Access Protection */
132 uint32_t M5AP
: 2; /*!< [11:10] Master 5 Access Protection */
133 uint32_t M6AP
: 2; /*!< [13:12] Master 6 Access Protection */
134 uint32_t M7AP
: 2; /*!< [15:14] Master 7 Access Protection */
135 uint32_t M0PFD
: 1; /*!< [16] Master 0 Prefetch Disable */
136 uint32_t M1PFD
: 1; /*!< [17] Master 1 Prefetch Disable */
137 uint32_t M2PFD
: 1; /*!< [18] Master 2 Prefetch Disable */
138 uint32_t M3PFD
: 1; /*!< [19] Master 3 Prefetch Disable */
139 uint32_t M4PFD
: 1; /*!< [20] Master 4 Prefetch Disable */
140 uint32_t M5PFD
: 1; /*!< [21] Master 5 Prefetch Disable */
141 uint32_t M6PFD
: 1; /*!< [22] Master 6 Prefetch Disable */
142 uint32_t M7PFD
: 1; /*!< [23] Master 7 Prefetch Disable */
143 uint32_t RESERVED0
: 8; /*!< [31:24] */
148 * @name Constants and macros for entire FMC_PFAPR register
151 #define HW_FMC_PFAPR_ADDR(x) ((x) + 0x0U)
153 #define HW_FMC_PFAPR(x) (*(__IO hw_fmc_pfapr_t *) HW_FMC_PFAPR_ADDR(x))
154 #define HW_FMC_PFAPR_RD(x) (HW_FMC_PFAPR(x).U)
155 #define HW_FMC_PFAPR_WR(x, v) (HW_FMC_PFAPR(x).U = (v))
156 #define HW_FMC_PFAPR_SET(x, v) (HW_FMC_PFAPR_WR(x, HW_FMC_PFAPR_RD(x) | (v)))
157 #define HW_FMC_PFAPR_CLR(x, v) (HW_FMC_PFAPR_WR(x, HW_FMC_PFAPR_RD(x) & ~(v)))
158 #define HW_FMC_PFAPR_TOG(x, v) (HW_FMC_PFAPR_WR(x, HW_FMC_PFAPR_RD(x) ^ (v)))
162 * Constants & macros for individual FMC_PFAPR bitfields
166 * @name Register FMC_PFAPR, field M0AP[1:0] (RW)
168 * This field controls whether read and write access to the flash are allowed
169 * based on the logical master number of the requesting crossbar switch master.
172 * - 00 - No access may be performed by this master
173 * - 01 - Only read accesses may be performed by this master
174 * - 10 - Only write accesses may be performed by this master
175 * - 11 - Both read and write accesses may be performed by this master
178 #define BP_FMC_PFAPR_M0AP (0U) /*!< Bit position for FMC_PFAPR_M0AP. */
179 #define BM_FMC_PFAPR_M0AP (0x00000003U) /*!< Bit mask for FMC_PFAPR_M0AP. */
180 #define BS_FMC_PFAPR_M0AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M0AP. */
182 /*! @brief Read current value of the FMC_PFAPR_M0AP field. */
183 #define BR_FMC_PFAPR_M0AP(x) (HW_FMC_PFAPR(x).B.M0AP)
185 /*! @brief Format value for bitfield FMC_PFAPR_M0AP. */
186 #define BF_FMC_PFAPR_M0AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M0AP) & BM_FMC_PFAPR_M0AP)
188 /*! @brief Set the M0AP field to a new value. */
189 #define BW_FMC_PFAPR_M0AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M0AP) | BF_FMC_PFAPR_M0AP(v)))
193 * @name Register FMC_PFAPR, field M1AP[3:2] (RW)
195 * This field controls whether read and write access to the flash are allowed
196 * based on the logical master number of the requesting crossbar switch master.
199 * - 00 - No access may be performed by this master
200 * - 01 - Only read accesses may be performed by this master
201 * - 10 - Only write accesses may be performed by this master
202 * - 11 - Both read and write accesses may be performed by this master
205 #define BP_FMC_PFAPR_M1AP (2U) /*!< Bit position for FMC_PFAPR_M1AP. */
206 #define BM_FMC_PFAPR_M1AP (0x0000000CU) /*!< Bit mask for FMC_PFAPR_M1AP. */
207 #define BS_FMC_PFAPR_M1AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M1AP. */
209 /*! @brief Read current value of the FMC_PFAPR_M1AP field. */
210 #define BR_FMC_PFAPR_M1AP(x) (HW_FMC_PFAPR(x).B.M1AP)
212 /*! @brief Format value for bitfield FMC_PFAPR_M1AP. */
213 #define BF_FMC_PFAPR_M1AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M1AP) & BM_FMC_PFAPR_M1AP)
215 /*! @brief Set the M1AP field to a new value. */
216 #define BW_FMC_PFAPR_M1AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M1AP) | BF_FMC_PFAPR_M1AP(v)))
220 * @name Register FMC_PFAPR, field M2AP[5:4] (RW)
222 * This field controls whether read and write access to the flash are allowed
223 * based on the logical master number of the requesting crossbar switch master.
226 * - 00 - No access may be performed by this master
227 * - 01 - Only read accesses may be performed by this master
228 * - 10 - Only write accesses may be performed by this master
229 * - 11 - Both read and write accesses may be performed by this master
232 #define BP_FMC_PFAPR_M2AP (4U) /*!< Bit position for FMC_PFAPR_M2AP. */
233 #define BM_FMC_PFAPR_M2AP (0x00000030U) /*!< Bit mask for FMC_PFAPR_M2AP. */
234 #define BS_FMC_PFAPR_M2AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M2AP. */
236 /*! @brief Read current value of the FMC_PFAPR_M2AP field. */
237 #define BR_FMC_PFAPR_M2AP(x) (HW_FMC_PFAPR(x).B.M2AP)
239 /*! @brief Format value for bitfield FMC_PFAPR_M2AP. */
240 #define BF_FMC_PFAPR_M2AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M2AP) & BM_FMC_PFAPR_M2AP)
242 /*! @brief Set the M2AP field to a new value. */
243 #define BW_FMC_PFAPR_M2AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M2AP) | BF_FMC_PFAPR_M2AP(v)))
247 * @name Register FMC_PFAPR, field M3AP[7:6] (RW)
249 * This field controls whether read and write access to the flash are allowed
250 * based on the logical master number of the requesting crossbar switch master.
253 * - 00 - No access may be performed by this master
254 * - 01 - Only read accesses may be performed by this master
255 * - 10 - Only write accesses may be performed by this master
256 * - 11 - Both read and write accesses may be performed by this master
259 #define BP_FMC_PFAPR_M3AP (6U) /*!< Bit position for FMC_PFAPR_M3AP. */
260 #define BM_FMC_PFAPR_M3AP (0x000000C0U) /*!< Bit mask for FMC_PFAPR_M3AP. */
261 #define BS_FMC_PFAPR_M3AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M3AP. */
263 /*! @brief Read current value of the FMC_PFAPR_M3AP field. */
264 #define BR_FMC_PFAPR_M3AP(x) (HW_FMC_PFAPR(x).B.M3AP)
266 /*! @brief Format value for bitfield FMC_PFAPR_M3AP. */
267 #define BF_FMC_PFAPR_M3AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M3AP) & BM_FMC_PFAPR_M3AP)
269 /*! @brief Set the M3AP field to a new value. */
270 #define BW_FMC_PFAPR_M3AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M3AP) | BF_FMC_PFAPR_M3AP(v)))
274 * @name Register FMC_PFAPR, field M4AP[9:8] (RW)
276 * This field controls whether read and write access to the flash are allowed
277 * based on the logical master number of the requesting crossbar switch master.
280 * - 00 - No access may be performed by this master
281 * - 01 - Only read accesses may be performed by this master
282 * - 10 - Only write accesses may be performed by this master
283 * - 11 - Both read and write accesses may be performed by this master
286 #define BP_FMC_PFAPR_M4AP (8U) /*!< Bit position for FMC_PFAPR_M4AP. */
287 #define BM_FMC_PFAPR_M4AP (0x00000300U) /*!< Bit mask for FMC_PFAPR_M4AP. */
288 #define BS_FMC_PFAPR_M4AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M4AP. */
290 /*! @brief Read current value of the FMC_PFAPR_M4AP field. */
291 #define BR_FMC_PFAPR_M4AP(x) (HW_FMC_PFAPR(x).B.M4AP)
293 /*! @brief Format value for bitfield FMC_PFAPR_M4AP. */
294 #define BF_FMC_PFAPR_M4AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M4AP) & BM_FMC_PFAPR_M4AP)
296 /*! @brief Set the M4AP field to a new value. */
297 #define BW_FMC_PFAPR_M4AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M4AP) | BF_FMC_PFAPR_M4AP(v)))
301 * @name Register FMC_PFAPR, field M5AP[11:10] (RW)
303 * This field controls whether read and write access to the flash are allowed
304 * based on the logical master number of the requesting crossbar switch master.
307 * - 00 - No access may be performed by this master
308 * - 01 - Only read accesses may be performed by this master
309 * - 10 - Only write accesses may be performed by this master
310 * - 11 - Both read and write accesses may be performed by this master
313 #define BP_FMC_PFAPR_M5AP (10U) /*!< Bit position for FMC_PFAPR_M5AP. */
314 #define BM_FMC_PFAPR_M5AP (0x00000C00U) /*!< Bit mask for FMC_PFAPR_M5AP. */
315 #define BS_FMC_PFAPR_M5AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M5AP. */
317 /*! @brief Read current value of the FMC_PFAPR_M5AP field. */
318 #define BR_FMC_PFAPR_M5AP(x) (HW_FMC_PFAPR(x).B.M5AP)
320 /*! @brief Format value for bitfield FMC_PFAPR_M5AP. */
321 #define BF_FMC_PFAPR_M5AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M5AP) & BM_FMC_PFAPR_M5AP)
323 /*! @brief Set the M5AP field to a new value. */
324 #define BW_FMC_PFAPR_M5AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M5AP) | BF_FMC_PFAPR_M5AP(v)))
328 * @name Register FMC_PFAPR, field M6AP[13:12] (RW)
330 * This field controls whether read and write access to the flash are allowed
331 * based on the logical master number of the requesting crossbar switch master.
334 * - 00 - No access may be performed by this master
335 * - 01 - Only read accesses may be performed by this master
336 * - 10 - Only write accesses may be performed by this master
337 * - 11 - Both read and write accesses may be performed by this master
340 #define BP_FMC_PFAPR_M6AP (12U) /*!< Bit position for FMC_PFAPR_M6AP. */
341 #define BM_FMC_PFAPR_M6AP (0x00003000U) /*!< Bit mask for FMC_PFAPR_M6AP. */
342 #define BS_FMC_PFAPR_M6AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M6AP. */
344 /*! @brief Read current value of the FMC_PFAPR_M6AP field. */
345 #define BR_FMC_PFAPR_M6AP(x) (HW_FMC_PFAPR(x).B.M6AP)
347 /*! @brief Format value for bitfield FMC_PFAPR_M6AP. */
348 #define BF_FMC_PFAPR_M6AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M6AP) & BM_FMC_PFAPR_M6AP)
350 /*! @brief Set the M6AP field to a new value. */
351 #define BW_FMC_PFAPR_M6AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M6AP) | BF_FMC_PFAPR_M6AP(v)))
355 * @name Register FMC_PFAPR, field M7AP[15:14] (RW)
357 * This field controls whether read and write access to the flash are allowed
358 * based on the logical master number of the requesting crossbar switch master.
361 * - 00 - No access may be performed by this master.
362 * - 01 - Only read accesses may be performed by this master.
363 * - 10 - Only write accesses may be performed by this master.
364 * - 11 - Both read and write accesses may be performed by this master.
367 #define BP_FMC_PFAPR_M7AP (14U) /*!< Bit position for FMC_PFAPR_M7AP. */
368 #define BM_FMC_PFAPR_M7AP (0x0000C000U) /*!< Bit mask for FMC_PFAPR_M7AP. */
369 #define BS_FMC_PFAPR_M7AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M7AP. */
371 /*! @brief Read current value of the FMC_PFAPR_M7AP field. */
372 #define BR_FMC_PFAPR_M7AP(x) (HW_FMC_PFAPR(x).B.M7AP)
374 /*! @brief Format value for bitfield FMC_PFAPR_M7AP. */
375 #define BF_FMC_PFAPR_M7AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M7AP) & BM_FMC_PFAPR_M7AP)
377 /*! @brief Set the M7AP field to a new value. */
378 #define BW_FMC_PFAPR_M7AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M7AP) | BF_FMC_PFAPR_M7AP(v)))
382 * @name Register FMC_PFAPR, field M0PFD[16] (RW)
384 * These bits control whether prefetching is enabled based on the logical number
385 * of the requesting crossbar switch master. This field is further qualified by
386 * the PFBnCR[BxDPE,BxIPE] bits.
389 * - 0 - Prefetching for this master is enabled.
390 * - 1 - Prefetching for this master is disabled.
393 #define BP_FMC_PFAPR_M0PFD (16U) /*!< Bit position for FMC_PFAPR_M0PFD. */
394 #define BM_FMC_PFAPR_M0PFD (0x00010000U) /*!< Bit mask for FMC_PFAPR_M0PFD. */
395 #define BS_FMC_PFAPR_M0PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M0PFD. */
397 /*! @brief Read current value of the FMC_PFAPR_M0PFD field. */
398 #define BR_FMC_PFAPR_M0PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M0PFD))
400 /*! @brief Format value for bitfield FMC_PFAPR_M0PFD. */
401 #define BF_FMC_PFAPR_M0PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M0PFD) & BM_FMC_PFAPR_M0PFD)
403 /*! @brief Set the M0PFD field to a new value. */
404 #define BW_FMC_PFAPR_M0PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M0PFD) = (v))
408 * @name Register FMC_PFAPR, field M1PFD[17] (RW)
410 * These bits control whether prefetching is enabled based on the logical number
411 * of the requesting crossbar switch master. This field is further qualified by
412 * the PFBnCR[BxDPE,BxIPE] bits.
415 * - 0 - Prefetching for this master is enabled.
416 * - 1 - Prefetching for this master is disabled.
419 #define BP_FMC_PFAPR_M1PFD (17U) /*!< Bit position for FMC_PFAPR_M1PFD. */
420 #define BM_FMC_PFAPR_M1PFD (0x00020000U) /*!< Bit mask for FMC_PFAPR_M1PFD. */
421 #define BS_FMC_PFAPR_M1PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M1PFD. */
423 /*! @brief Read current value of the FMC_PFAPR_M1PFD field. */
424 #define BR_FMC_PFAPR_M1PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M1PFD))
426 /*! @brief Format value for bitfield FMC_PFAPR_M1PFD. */
427 #define BF_FMC_PFAPR_M1PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M1PFD) & BM_FMC_PFAPR_M1PFD)
429 /*! @brief Set the M1PFD field to a new value. */
430 #define BW_FMC_PFAPR_M1PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M1PFD) = (v))
434 * @name Register FMC_PFAPR, field M2PFD[18] (RW)
436 * These bits control whether prefetching is enabled based on the logical number
437 * of the requesting crossbar switch master. This field is further qualified by
438 * the PFBnCR[BxDPE,BxIPE] bits.
441 * - 0 - Prefetching for this master is enabled.
442 * - 1 - Prefetching for this master is disabled.
445 #define BP_FMC_PFAPR_M2PFD (18U) /*!< Bit position for FMC_PFAPR_M2PFD. */
446 #define BM_FMC_PFAPR_M2PFD (0x00040000U) /*!< Bit mask for FMC_PFAPR_M2PFD. */
447 #define BS_FMC_PFAPR_M2PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M2PFD. */
449 /*! @brief Read current value of the FMC_PFAPR_M2PFD field. */
450 #define BR_FMC_PFAPR_M2PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M2PFD))
452 /*! @brief Format value for bitfield FMC_PFAPR_M2PFD. */
453 #define BF_FMC_PFAPR_M2PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M2PFD) & BM_FMC_PFAPR_M2PFD)
455 /*! @brief Set the M2PFD field to a new value. */
456 #define BW_FMC_PFAPR_M2PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M2PFD) = (v))
460 * @name Register FMC_PFAPR, field M3PFD[19] (RW)
462 * These bits control whether prefetching is enabled based on the logical number
463 * of the requesting crossbar switch master. This field is further qualified by
464 * the PFBnCR[BxDPE,BxIPE] bits.
467 * - 0 - Prefetching for this master is enabled.
468 * - 1 - Prefetching for this master is disabled.
471 #define BP_FMC_PFAPR_M3PFD (19U) /*!< Bit position for FMC_PFAPR_M3PFD. */
472 #define BM_FMC_PFAPR_M3PFD (0x00080000U) /*!< Bit mask for FMC_PFAPR_M3PFD. */
473 #define BS_FMC_PFAPR_M3PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M3PFD. */
475 /*! @brief Read current value of the FMC_PFAPR_M3PFD field. */
476 #define BR_FMC_PFAPR_M3PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M3PFD))
478 /*! @brief Format value for bitfield FMC_PFAPR_M3PFD. */
479 #define BF_FMC_PFAPR_M3PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M3PFD) & BM_FMC_PFAPR_M3PFD)
481 /*! @brief Set the M3PFD field to a new value. */
482 #define BW_FMC_PFAPR_M3PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M3PFD) = (v))
486 * @name Register FMC_PFAPR, field M4PFD[20] (RW)
488 * These bits control whether prefetching is enabled based on the logical number
489 * of the requesting crossbar switch master. This field is further qualified by
490 * the PFBnCR[BxDPE,BxIPE] bits.
493 * - 0 - Prefetching for this master is enabled.
494 * - 1 - Prefetching for this master is disabled.
497 #define BP_FMC_PFAPR_M4PFD (20U) /*!< Bit position for FMC_PFAPR_M4PFD. */
498 #define BM_FMC_PFAPR_M4PFD (0x00100000U) /*!< Bit mask for FMC_PFAPR_M4PFD. */
499 #define BS_FMC_PFAPR_M4PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M4PFD. */
501 /*! @brief Read current value of the FMC_PFAPR_M4PFD field. */
502 #define BR_FMC_PFAPR_M4PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M4PFD))
504 /*! @brief Format value for bitfield FMC_PFAPR_M4PFD. */
505 #define BF_FMC_PFAPR_M4PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M4PFD) & BM_FMC_PFAPR_M4PFD)
507 /*! @brief Set the M4PFD field to a new value. */
508 #define BW_FMC_PFAPR_M4PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M4PFD) = (v))
512 * @name Register FMC_PFAPR, field M5PFD[21] (RW)
514 * These bits control whether prefetching is enabled based on the logical number
515 * of the requesting crossbar switch master. This field is further qualified by
516 * the PFBnCR[BxDPE,BxIPE] bits.
519 * - 0 - Prefetching for this master is enabled.
520 * - 1 - Prefetching for this master is disabled.
523 #define BP_FMC_PFAPR_M5PFD (21U) /*!< Bit position for FMC_PFAPR_M5PFD. */
524 #define BM_FMC_PFAPR_M5PFD (0x00200000U) /*!< Bit mask for FMC_PFAPR_M5PFD. */
525 #define BS_FMC_PFAPR_M5PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M5PFD. */
527 /*! @brief Read current value of the FMC_PFAPR_M5PFD field. */
528 #define BR_FMC_PFAPR_M5PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M5PFD))
530 /*! @brief Format value for bitfield FMC_PFAPR_M5PFD. */
531 #define BF_FMC_PFAPR_M5PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M5PFD) & BM_FMC_PFAPR_M5PFD)
533 /*! @brief Set the M5PFD field to a new value. */
534 #define BW_FMC_PFAPR_M5PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M5PFD) = (v))
538 * @name Register FMC_PFAPR, field M6PFD[22] (RW)
540 * These bits control whether prefetching is enabled based on the logical number
541 * of the requesting crossbar switch master. This field is further qualified by
542 * the PFBnCR[BxDPE,BxIPE] bits.
545 * - 0 - Prefetching for this master is enabled.
546 * - 1 - Prefetching for this master is disabled.
549 #define BP_FMC_PFAPR_M6PFD (22U) /*!< Bit position for FMC_PFAPR_M6PFD. */
550 #define BM_FMC_PFAPR_M6PFD (0x00400000U) /*!< Bit mask for FMC_PFAPR_M6PFD. */
551 #define BS_FMC_PFAPR_M6PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M6PFD. */
553 /*! @brief Read current value of the FMC_PFAPR_M6PFD field. */
554 #define BR_FMC_PFAPR_M6PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M6PFD))
556 /*! @brief Format value for bitfield FMC_PFAPR_M6PFD. */
557 #define BF_FMC_PFAPR_M6PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M6PFD) & BM_FMC_PFAPR_M6PFD)
559 /*! @brief Set the M6PFD field to a new value. */
560 #define BW_FMC_PFAPR_M6PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M6PFD) = (v))
564 * @name Register FMC_PFAPR, field M7PFD[23] (RW)
566 * These bits control whether prefetching is enabled based on the logical number
567 * of the requesting crossbar switch master. This field is further qualified by
568 * the PFBnCR[BxDPE,BxIPE] bits.
571 * - 0 - Prefetching for this master is enabled.
572 * - 1 - Prefetching for this master is disabled.
575 #define BP_FMC_PFAPR_M7PFD (23U) /*!< Bit position for FMC_PFAPR_M7PFD. */
576 #define BM_FMC_PFAPR_M7PFD (0x00800000U) /*!< Bit mask for FMC_PFAPR_M7PFD. */
577 #define BS_FMC_PFAPR_M7PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M7PFD. */
579 /*! @brief Read current value of the FMC_PFAPR_M7PFD field. */
580 #define BR_FMC_PFAPR_M7PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M7PFD))
582 /*! @brief Format value for bitfield FMC_PFAPR_M7PFD. */
583 #define BF_FMC_PFAPR_M7PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M7PFD) & BM_FMC_PFAPR_M7PFD)
585 /*! @brief Set the M7PFD field to a new value. */
586 #define BW_FMC_PFAPR_M7PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M7PFD) = (v))
589 /*******************************************************************************
590 * HW_FMC_PFB0CR - Flash Bank 0 Control Register
591 ******************************************************************************/
594 * @brief HW_FMC_PFB0CR - Flash Bank 0 Control Register (RW)
596 * Reset value: 0x3004001FU
598 typedef union _hw_fmc_pfb0cr
601 struct _hw_fmc_pfb0cr_bitfields
603 uint32_t B0SEBE
: 1; /*!< [0] Bank 0 Single Entry Buffer Enable */
604 uint32_t B0IPE
: 1; /*!< [1] Bank 0 Instruction Prefetch Enable */
605 uint32_t B0DPE
: 1; /*!< [2] Bank 0 Data Prefetch Enable */
606 uint32_t B0ICE
: 1; /*!< [3] Bank 0 Instruction Cache Enable */
607 uint32_t B0DCE
: 1; /*!< [4] Bank 0 Data Cache Enable */
608 uint32_t CRC
: 3; /*!< [7:5] Cache Replacement Control */
609 uint32_t RESERVED0
: 9; /*!< [16:8] */
610 uint32_t B0MW
: 2; /*!< [18:17] Bank 0 Memory Width */
611 uint32_t S_B_INV
: 1; /*!< [19] Invalidate Prefetch Speculation
613 uint32_t CINV_WAY
: 4; /*!< [23:20] Cache Invalidate Way x */
614 uint32_t CLCK_WAY
: 4; /*!< [27:24] Cache Lock Way x */
615 uint32_t B0RWSC
: 4; /*!< [31:28] Bank 0 Read Wait State Control */
620 * @name Constants and macros for entire FMC_PFB0CR register
623 #define HW_FMC_PFB0CR_ADDR(x) ((x) + 0x4U)
625 #define HW_FMC_PFB0CR(x) (*(__IO hw_fmc_pfb0cr_t *) HW_FMC_PFB0CR_ADDR(x))
626 #define HW_FMC_PFB0CR_RD(x) (HW_FMC_PFB0CR(x).U)
627 #define HW_FMC_PFB0CR_WR(x, v) (HW_FMC_PFB0CR(x).U = (v))
628 #define HW_FMC_PFB0CR_SET(x, v) (HW_FMC_PFB0CR_WR(x, HW_FMC_PFB0CR_RD(x) | (v)))
629 #define HW_FMC_PFB0CR_CLR(x, v) (HW_FMC_PFB0CR_WR(x, HW_FMC_PFB0CR_RD(x) & ~(v)))
630 #define HW_FMC_PFB0CR_TOG(x, v) (HW_FMC_PFB0CR_WR(x, HW_FMC_PFB0CR_RD(x) ^ (v)))
634 * Constants & macros for individual FMC_PFB0CR bitfields
638 * @name Register FMC_PFB0CR, field B0SEBE[0] (RW)
640 * This bit controls whether the single entry page buffer is enabled in response
641 * to flash read accesses. Its operation is independent from bank 1's cache. A
642 * high-to-low transition of this enable forces the page buffer to be invalidated.
645 * - 0 - Single entry buffer is disabled.
646 * - 1 - Single entry buffer is enabled.
649 #define BP_FMC_PFB0CR_B0SEBE (0U) /*!< Bit position for FMC_PFB0CR_B0SEBE. */
650 #define BM_FMC_PFB0CR_B0SEBE (0x00000001U) /*!< Bit mask for FMC_PFB0CR_B0SEBE. */
651 #define BS_FMC_PFB0CR_B0SEBE (1U) /*!< Bit field size in bits for FMC_PFB0CR_B0SEBE. */
653 /*! @brief Read current value of the FMC_PFB0CR_B0SEBE field. */
654 #define BR_FMC_PFB0CR_B0SEBE(x) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0SEBE))
656 /*! @brief Format value for bitfield FMC_PFB0CR_B0SEBE. */
657 #define BF_FMC_PFB0CR_B0SEBE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0SEBE) & BM_FMC_PFB0CR_B0SEBE)
659 /*! @brief Set the B0SEBE field to a new value. */
660 #define BW_FMC_PFB0CR_B0SEBE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0SEBE) = (v))
664 * @name Register FMC_PFB0CR, field B0IPE[1] (RW)
666 * This bit controls whether prefetches (or speculative accesses) are initiated
667 * in response to instruction fetches.
670 * - 0 - Do not prefetch in response to instruction fetches.
671 * - 1 - Enable prefetches in response to instruction fetches.
674 #define BP_FMC_PFB0CR_B0IPE (1U) /*!< Bit position for FMC_PFB0CR_B0IPE. */
675 #define BM_FMC_PFB0CR_B0IPE (0x00000002U) /*!< Bit mask for FMC_PFB0CR_B0IPE. */
676 #define BS_FMC_PFB0CR_B0IPE (1U) /*!< Bit field size in bits for FMC_PFB0CR_B0IPE. */
678 /*! @brief Read current value of the FMC_PFB0CR_B0IPE field. */
679 #define BR_FMC_PFB0CR_B0IPE(x) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0IPE))
681 /*! @brief Format value for bitfield FMC_PFB0CR_B0IPE. */
682 #define BF_FMC_PFB0CR_B0IPE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0IPE) & BM_FMC_PFB0CR_B0IPE)
684 /*! @brief Set the B0IPE field to a new value. */
685 #define BW_FMC_PFB0CR_B0IPE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0IPE) = (v))
689 * @name Register FMC_PFB0CR, field B0DPE[2] (RW)
691 * This bit controls whether prefetches (or speculative accesses) are initiated
692 * in response to data references.
695 * - 0 - Do not prefetch in response to data references.
696 * - 1 - Enable prefetches in response to data references.
699 #define BP_FMC_PFB0CR_B0DPE (2U) /*!< Bit position for FMC_PFB0CR_B0DPE. */
700 #define BM_FMC_PFB0CR_B0DPE (0x00000004U) /*!< Bit mask for FMC_PFB0CR_B0DPE. */
701 #define BS_FMC_PFB0CR_B0DPE (1U) /*!< Bit field size in bits for FMC_PFB0CR_B0DPE. */
703 /*! @brief Read current value of the FMC_PFB0CR_B0DPE field. */
704 #define BR_FMC_PFB0CR_B0DPE(x) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0DPE))
706 /*! @brief Format value for bitfield FMC_PFB0CR_B0DPE. */
707 #define BF_FMC_PFB0CR_B0DPE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0DPE) & BM_FMC_PFB0CR_B0DPE)
709 /*! @brief Set the B0DPE field to a new value. */
710 #define BW_FMC_PFB0CR_B0DPE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0DPE) = (v))
714 * @name Register FMC_PFB0CR, field B0ICE[3] (RW)
716 * This bit controls whether instruction fetches are loaded into the cache.
719 * - 0 - Do not cache instruction fetches.
720 * - 1 - Cache instruction fetches.
723 #define BP_FMC_PFB0CR_B0ICE (3U) /*!< Bit position for FMC_PFB0CR_B0ICE. */
724 #define BM_FMC_PFB0CR_B0ICE (0x00000008U) /*!< Bit mask for FMC_PFB0CR_B0ICE. */
725 #define BS_FMC_PFB0CR_B0ICE (1U) /*!< Bit field size in bits for FMC_PFB0CR_B0ICE. */
727 /*! @brief Read current value of the FMC_PFB0CR_B0ICE field. */
728 #define BR_FMC_PFB0CR_B0ICE(x) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0ICE))
730 /*! @brief Format value for bitfield FMC_PFB0CR_B0ICE. */
731 #define BF_FMC_PFB0CR_B0ICE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0ICE) & BM_FMC_PFB0CR_B0ICE)
733 /*! @brief Set the B0ICE field to a new value. */
734 #define BW_FMC_PFB0CR_B0ICE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0ICE) = (v))
738 * @name Register FMC_PFB0CR, field B0DCE[4] (RW)
740 * This bit controls whether data references are loaded into the cache.
743 * - 0 - Do not cache data references.
744 * - 1 - Cache data references.
747 #define BP_FMC_PFB0CR_B0DCE (4U) /*!< Bit position for FMC_PFB0CR_B0DCE. */
748 #define BM_FMC_PFB0CR_B0DCE (0x00000010U) /*!< Bit mask for FMC_PFB0CR_B0DCE. */
749 #define BS_FMC_PFB0CR_B0DCE (1U) /*!< Bit field size in bits for FMC_PFB0CR_B0DCE. */
751 /*! @brief Read current value of the FMC_PFB0CR_B0DCE field. */
752 #define BR_FMC_PFB0CR_B0DCE(x) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0DCE))
754 /*! @brief Format value for bitfield FMC_PFB0CR_B0DCE. */
755 #define BF_FMC_PFB0CR_B0DCE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0DCE) & BM_FMC_PFB0CR_B0DCE)
757 /*! @brief Set the B0DCE field to a new value. */
758 #define BW_FMC_PFB0CR_B0DCE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0DCE) = (v))
762 * @name Register FMC_PFB0CR, field CRC[7:5] (RW)
764 * This 3-bit field defines the replacement algorithm for accesses that are
768 * - 000 - LRU replacement algorithm per set across all four ways
770 * - 010 - Independent LRU with ways [0-1] for ifetches, [2-3] for data
771 * - 011 - Independent LRU with ways [0-2] for ifetches, [3] for data
775 #define BP_FMC_PFB0CR_CRC (5U) /*!< Bit position for FMC_PFB0CR_CRC. */
776 #define BM_FMC_PFB0CR_CRC (0x000000E0U) /*!< Bit mask for FMC_PFB0CR_CRC. */
777 #define BS_FMC_PFB0CR_CRC (3U) /*!< Bit field size in bits for FMC_PFB0CR_CRC. */
779 /*! @brief Read current value of the FMC_PFB0CR_CRC field. */
780 #define BR_FMC_PFB0CR_CRC(x) (HW_FMC_PFB0CR(x).B.CRC)
782 /*! @brief Format value for bitfield FMC_PFB0CR_CRC. */
783 #define BF_FMC_PFB0CR_CRC(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_CRC) & BM_FMC_PFB0CR_CRC)
785 /*! @brief Set the CRC field to a new value. */
786 #define BW_FMC_PFB0CR_CRC(x, v) (HW_FMC_PFB0CR_WR(x, (HW_FMC_PFB0CR_RD(x) & ~BM_FMC_PFB0CR_CRC) | BF_FMC_PFB0CR_CRC(v)))
790 * @name Register FMC_PFB0CR, field B0MW[18:17] (RO)
792 * This read-only field defines the width of the bank 0 memory.
801 #define BP_FMC_PFB0CR_B0MW (17U) /*!< Bit position for FMC_PFB0CR_B0MW. */
802 #define BM_FMC_PFB0CR_B0MW (0x00060000U) /*!< Bit mask for FMC_PFB0CR_B0MW. */
803 #define BS_FMC_PFB0CR_B0MW (2U) /*!< Bit field size in bits for FMC_PFB0CR_B0MW. */
805 /*! @brief Read current value of the FMC_PFB0CR_B0MW field. */
806 #define BR_FMC_PFB0CR_B0MW(x) (HW_FMC_PFB0CR(x).B.B0MW)
810 * @name Register FMC_PFB0CR, field S_B_INV[19] (WORZ)
812 * This bit determines if the FMC's prefetch speculation buffer and the single
813 * entry page buffer are to be invalidated (cleared). When this bit is written,
814 * the speculation buffer and single entry buffer are immediately cleared. This bit
815 * always reads as zero.
818 * - 0 - Speculation buffer and single entry buffer are not affected.
819 * - 1 - Invalidate (clear) speculation buffer and single entry buffer.
822 #define BP_FMC_PFB0CR_S_B_INV (19U) /*!< Bit position for FMC_PFB0CR_S_B_INV. */
823 #define BM_FMC_PFB0CR_S_B_INV (0x00080000U) /*!< Bit mask for FMC_PFB0CR_S_B_INV. */
824 #define BS_FMC_PFB0CR_S_B_INV (1U) /*!< Bit field size in bits for FMC_PFB0CR_S_B_INV. */
826 /*! @brief Format value for bitfield FMC_PFB0CR_S_B_INV. */
827 #define BF_FMC_PFB0CR_S_B_INV(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_S_B_INV) & BM_FMC_PFB0CR_S_B_INV)
829 /*! @brief Set the S_B_INV field to a new value. */
830 #define BW_FMC_PFB0CR_S_B_INV(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_S_B_INV) = (v))
834 * @name Register FMC_PFB0CR, field CINV_WAY[23:20] (WORZ)
836 * These bits determine if the given cache way is to be invalidated (cleared).
837 * When a bit within this field is written, the corresponding cache way is
838 * immediately invalidated: the way's tag, data, and valid contents are cleared. This
839 * field always reads as zero. Cache invalidation takes precedence over locking.
840 * The cache is invalidated by system reset. System software is required to
841 * maintain memory coherency when any segment of the flash memory is programmed or
842 * erased. Accordingly, cache invalidations must occur after a programming or erase
843 * event is completed and before the new memory image is accessed. The bit setting
844 * definitions are for each bit in the field.
847 * - 0 - No cache way invalidation for the corresponding cache
848 * - 1 - Invalidate cache way for the corresponding cache: clear the tag, data,
849 * and vld bits of ways selected
852 #define BP_FMC_PFB0CR_CINV_WAY (20U) /*!< Bit position for FMC_PFB0CR_CINV_WAY. */
853 #define BM_FMC_PFB0CR_CINV_WAY (0x00F00000U) /*!< Bit mask for FMC_PFB0CR_CINV_WAY. */
854 #define BS_FMC_PFB0CR_CINV_WAY (4U) /*!< Bit field size in bits for FMC_PFB0CR_CINV_WAY. */
856 /*! @brief Format value for bitfield FMC_PFB0CR_CINV_WAY. */
857 #define BF_FMC_PFB0CR_CINV_WAY(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_CINV_WAY) & BM_FMC_PFB0CR_CINV_WAY)
859 /*! @brief Set the CINV_WAY field to a new value. */
860 #define BW_FMC_PFB0CR_CINV_WAY(x, v) (HW_FMC_PFB0CR_WR(x, (HW_FMC_PFB0CR_RD(x) & ~BM_FMC_PFB0CR_CINV_WAY) | BF_FMC_PFB0CR_CINV_WAY(v)))
864 * @name Register FMC_PFB0CR, field CLCK_WAY[27:24] (RW)
866 * These bits determine if the given cache way is locked such that its contents
867 * will not be displaced by future misses. The bit setting definitions are for
868 * each bit in the field.
871 * - 0 - Cache way is unlocked and may be displaced
872 * - 1 - Cache way is locked and its contents are not displaced
875 #define BP_FMC_PFB0CR_CLCK_WAY (24U) /*!< Bit position for FMC_PFB0CR_CLCK_WAY. */
876 #define BM_FMC_PFB0CR_CLCK_WAY (0x0F000000U) /*!< Bit mask for FMC_PFB0CR_CLCK_WAY. */
877 #define BS_FMC_PFB0CR_CLCK_WAY (4U) /*!< Bit field size in bits for FMC_PFB0CR_CLCK_WAY. */
879 /*! @brief Read current value of the FMC_PFB0CR_CLCK_WAY field. */
880 #define BR_FMC_PFB0CR_CLCK_WAY(x) (HW_FMC_PFB0CR(x).B.CLCK_WAY)
882 /*! @brief Format value for bitfield FMC_PFB0CR_CLCK_WAY. */
883 #define BF_FMC_PFB0CR_CLCK_WAY(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_CLCK_WAY) & BM_FMC_PFB0CR_CLCK_WAY)
885 /*! @brief Set the CLCK_WAY field to a new value. */
886 #define BW_FMC_PFB0CR_CLCK_WAY(x, v) (HW_FMC_PFB0CR_WR(x, (HW_FMC_PFB0CR_RD(x) & ~BM_FMC_PFB0CR_CLCK_WAY) | BF_FMC_PFB0CR_CLCK_WAY(v)))
890 * @name Register FMC_PFB0CR, field B0RWSC[31:28] (RO)
892 * This read-only field defines the number of wait states required to access the
893 * bank 0 flash memory. The relationship between the read access time of the
894 * flash array (expressed in system clock cycles) and RWSC is defined as: Access
895 * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates
896 * this value based on the ratio of the system clock speed to the flash clock
897 * speed. For example, when this ratio is 4:1, the field's value is 3h.
900 #define BP_FMC_PFB0CR_B0RWSC (28U) /*!< Bit position for FMC_PFB0CR_B0RWSC. */
901 #define BM_FMC_PFB0CR_B0RWSC (0xF0000000U) /*!< Bit mask for FMC_PFB0CR_B0RWSC. */
902 #define BS_FMC_PFB0CR_B0RWSC (4U) /*!< Bit field size in bits for FMC_PFB0CR_B0RWSC. */
904 /*! @brief Read current value of the FMC_PFB0CR_B0RWSC field. */
905 #define BR_FMC_PFB0CR_B0RWSC(x) (HW_FMC_PFB0CR(x).B.B0RWSC)
908 /*******************************************************************************
909 * HW_FMC_PFB1CR - Flash Bank 1 Control Register
910 ******************************************************************************/
913 * @brief HW_FMC_PFB1CR - Flash Bank 1 Control Register (RW)
915 * Reset value: 0x3004001FU
917 * This register has a format similar to that for PFB0CR, except it controls the
918 * operation of flash bank 1, and the "global" cache control fields are empty.
920 typedef union _hw_fmc_pfb1cr
923 struct _hw_fmc_pfb1cr_bitfields
925 uint32_t B1SEBE
: 1; /*!< [0] Bank 1 Single Entry Buffer Enable */
926 uint32_t B1IPE
: 1; /*!< [1] Bank 1 Instruction Prefetch Enable */
927 uint32_t B1DPE
: 1; /*!< [2] Bank 1 Data Prefetch Enable */
928 uint32_t B1ICE
: 1; /*!< [3] Bank 1 Instruction Cache Enable */
929 uint32_t B1DCE
: 1; /*!< [4] Bank 1 Data Cache Enable */
930 uint32_t RESERVED0
: 12; /*!< [16:5] */
931 uint32_t B1MW
: 2; /*!< [18:17] Bank 1 Memory Width */
932 uint32_t RESERVED1
: 9; /*!< [27:19] */
933 uint32_t B1RWSC
: 4; /*!< [31:28] Bank 1 Read Wait State Control */
938 * @name Constants and macros for entire FMC_PFB1CR register
941 #define HW_FMC_PFB1CR_ADDR(x) ((x) + 0x8U)
943 #define HW_FMC_PFB1CR(x) (*(__IO hw_fmc_pfb1cr_t *) HW_FMC_PFB1CR_ADDR(x))
944 #define HW_FMC_PFB1CR_RD(x) (HW_FMC_PFB1CR(x).U)
945 #define HW_FMC_PFB1CR_WR(x, v) (HW_FMC_PFB1CR(x).U = (v))
946 #define HW_FMC_PFB1CR_SET(x, v) (HW_FMC_PFB1CR_WR(x, HW_FMC_PFB1CR_RD(x) | (v)))
947 #define HW_FMC_PFB1CR_CLR(x, v) (HW_FMC_PFB1CR_WR(x, HW_FMC_PFB1CR_RD(x) & ~(v)))
948 #define HW_FMC_PFB1CR_TOG(x, v) (HW_FMC_PFB1CR_WR(x, HW_FMC_PFB1CR_RD(x) ^ (v)))
952 * Constants & macros for individual FMC_PFB1CR bitfields
956 * @name Register FMC_PFB1CR, field B1SEBE[0] (RW)
958 * This bit controls whether the single entry buffer is enabled in response to
959 * flash read accesses. Its operation is independent from bank 0's cache. A
960 * high-to-low transition of this enable forces the page buffer to be invalidated.
963 * - 0 - Single entry buffer is disabled.
964 * - 1 - Single entry buffer is enabled.
967 #define BP_FMC_PFB1CR_B1SEBE (0U) /*!< Bit position for FMC_PFB1CR_B1SEBE. */
968 #define BM_FMC_PFB1CR_B1SEBE (0x00000001U) /*!< Bit mask for FMC_PFB1CR_B1SEBE. */
969 #define BS_FMC_PFB1CR_B1SEBE (1U) /*!< Bit field size in bits for FMC_PFB1CR_B1SEBE. */
971 /*! @brief Read current value of the FMC_PFB1CR_B1SEBE field. */
972 #define BR_FMC_PFB1CR_B1SEBE(x) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1SEBE))
974 /*! @brief Format value for bitfield FMC_PFB1CR_B1SEBE. */
975 #define BF_FMC_PFB1CR_B1SEBE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1SEBE) & BM_FMC_PFB1CR_B1SEBE)
977 /*! @brief Set the B1SEBE field to a new value. */
978 #define BW_FMC_PFB1CR_B1SEBE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1SEBE) = (v))
982 * @name Register FMC_PFB1CR, field B1IPE[1] (RW)
984 * This bit controls whether prefetches (or speculative accesses) are initiated
985 * in response to instruction fetches.
988 * - 0 - Do not prefetch in response to instruction fetches.
989 * - 1 - Enable prefetches in response to instruction fetches.
992 #define BP_FMC_PFB1CR_B1IPE (1U) /*!< Bit position for FMC_PFB1CR_B1IPE. */
993 #define BM_FMC_PFB1CR_B1IPE (0x00000002U) /*!< Bit mask for FMC_PFB1CR_B1IPE. */
994 #define BS_FMC_PFB1CR_B1IPE (1U) /*!< Bit field size in bits for FMC_PFB1CR_B1IPE. */
996 /*! @brief Read current value of the FMC_PFB1CR_B1IPE field. */
997 #define BR_FMC_PFB1CR_B1IPE(x) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1IPE))
999 /*! @brief Format value for bitfield FMC_PFB1CR_B1IPE. */
1000 #define BF_FMC_PFB1CR_B1IPE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1IPE) & BM_FMC_PFB1CR_B1IPE)
1002 /*! @brief Set the B1IPE field to a new value. */
1003 #define BW_FMC_PFB1CR_B1IPE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1IPE) = (v))
1007 * @name Register FMC_PFB1CR, field B1DPE[2] (RW)
1009 * This bit controls whether prefetches (or speculative accesses) are initiated
1010 * in response to data references.
1013 * - 0 - Do not prefetch in response to data references.
1014 * - 1 - Enable prefetches in response to data references.
1017 #define BP_FMC_PFB1CR_B1DPE (2U) /*!< Bit position for FMC_PFB1CR_B1DPE. */
1018 #define BM_FMC_PFB1CR_B1DPE (0x00000004U) /*!< Bit mask for FMC_PFB1CR_B1DPE. */
1019 #define BS_FMC_PFB1CR_B1DPE (1U) /*!< Bit field size in bits for FMC_PFB1CR_B1DPE. */
1021 /*! @brief Read current value of the FMC_PFB1CR_B1DPE field. */
1022 #define BR_FMC_PFB1CR_B1DPE(x) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1DPE))
1024 /*! @brief Format value for bitfield FMC_PFB1CR_B1DPE. */
1025 #define BF_FMC_PFB1CR_B1DPE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1DPE) & BM_FMC_PFB1CR_B1DPE)
1027 /*! @brief Set the B1DPE field to a new value. */
1028 #define BW_FMC_PFB1CR_B1DPE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1DPE) = (v))
1032 * @name Register FMC_PFB1CR, field B1ICE[3] (RW)
1034 * This bit controls whether instruction fetches are loaded into the cache.
1037 * - 0 - Do not cache instruction fetches.
1038 * - 1 - Cache instruction fetches.
1041 #define BP_FMC_PFB1CR_B1ICE (3U) /*!< Bit position for FMC_PFB1CR_B1ICE. */
1042 #define BM_FMC_PFB1CR_B1ICE (0x00000008U) /*!< Bit mask for FMC_PFB1CR_B1ICE. */
1043 #define BS_FMC_PFB1CR_B1ICE (1U) /*!< Bit field size in bits for FMC_PFB1CR_B1ICE. */
1045 /*! @brief Read current value of the FMC_PFB1CR_B1ICE field. */
1046 #define BR_FMC_PFB1CR_B1ICE(x) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1ICE))
1048 /*! @brief Format value for bitfield FMC_PFB1CR_B1ICE. */
1049 #define BF_FMC_PFB1CR_B1ICE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1ICE) & BM_FMC_PFB1CR_B1ICE)
1051 /*! @brief Set the B1ICE field to a new value. */
1052 #define BW_FMC_PFB1CR_B1ICE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1ICE) = (v))
1056 * @name Register FMC_PFB1CR, field B1DCE[4] (RW)
1058 * This bit controls whether data references are loaded into the cache.
1061 * - 0 - Do not cache data references.
1062 * - 1 - Cache data references.
1065 #define BP_FMC_PFB1CR_B1DCE (4U) /*!< Bit position for FMC_PFB1CR_B1DCE. */
1066 #define BM_FMC_PFB1CR_B1DCE (0x00000010U) /*!< Bit mask for FMC_PFB1CR_B1DCE. */
1067 #define BS_FMC_PFB1CR_B1DCE (1U) /*!< Bit field size in bits for FMC_PFB1CR_B1DCE. */
1069 /*! @brief Read current value of the FMC_PFB1CR_B1DCE field. */
1070 #define BR_FMC_PFB1CR_B1DCE(x) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1DCE))
1072 /*! @brief Format value for bitfield FMC_PFB1CR_B1DCE. */
1073 #define BF_FMC_PFB1CR_B1DCE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1DCE) & BM_FMC_PFB1CR_B1DCE)
1075 /*! @brief Set the B1DCE field to a new value. */
1076 #define BW_FMC_PFB1CR_B1DCE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1DCE) = (v))
1080 * @name Register FMC_PFB1CR, field B1MW[18:17] (RO)
1082 * This read-only field defines the width of the bank 1 memory.
1091 #define BP_FMC_PFB1CR_B1MW (17U) /*!< Bit position for FMC_PFB1CR_B1MW. */
1092 #define BM_FMC_PFB1CR_B1MW (0x00060000U) /*!< Bit mask for FMC_PFB1CR_B1MW. */
1093 #define BS_FMC_PFB1CR_B1MW (2U) /*!< Bit field size in bits for FMC_PFB1CR_B1MW. */
1095 /*! @brief Read current value of the FMC_PFB1CR_B1MW field. */
1096 #define BR_FMC_PFB1CR_B1MW(x) (HW_FMC_PFB1CR(x).B.B1MW)
1100 * @name Register FMC_PFB1CR, field B1RWSC[31:28] (RO)
1102 * This read-only field defines the number of wait states required to access the
1103 * bank 1 flash memory. The relationship between the read access time of the
1104 * flash array (expressed in system clock cycles) and RWSC is defined as: Access
1105 * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates
1106 * this value based on the ratio of the system clock speed to the flash clock
1107 * speed. For example, when this ratio is 4:1, the field's value is 3h.
1110 #define BP_FMC_PFB1CR_B1RWSC (28U) /*!< Bit position for FMC_PFB1CR_B1RWSC. */
1111 #define BM_FMC_PFB1CR_B1RWSC (0xF0000000U) /*!< Bit mask for FMC_PFB1CR_B1RWSC. */
1112 #define BS_FMC_PFB1CR_B1RWSC (4U) /*!< Bit field size in bits for FMC_PFB1CR_B1RWSC. */
1114 /*! @brief Read current value of the FMC_PFB1CR_B1RWSC field. */
1115 #define BR_FMC_PFB1CR_B1RWSC(x) (HW_FMC_PFB1CR(x).B.B1RWSC)
1118 /*******************************************************************************
1119 * HW_FMC_TAGVDW0Sn - Cache Tag Storage
1120 ******************************************************************************/
1123 * @brief HW_FMC_TAGVDW0Sn - Cache Tag Storage (RW)
1125 * Reset value: 0x00000000U
1127 * The cache is a 4-way, set-associative cache with 4 sets. The ways are
1128 * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
1129 * denotes the set. This section represents tag/vld information for all sets in the
1132 typedef union _hw_fmc_tagvdw0sn
1135 struct _hw_fmc_tagvdw0sn_bitfields
1137 uint32_t valid
: 1; /*!< [0] 1-bit valid for cache entry */
1138 uint32_t RESERVED0
: 4; /*!< [4:1] */
1139 uint32_t tag
: 14; /*!< [18:5] 14-bit tag for cache entry */
1140 uint32_t RESERVED1
: 13; /*!< [31:19] */
1142 } hw_fmc_tagvdw0sn_t
;
1145 * @name Constants and macros for entire FMC_TAGVDW0Sn register
1148 #define HW_FMC_TAGVDW0Sn_COUNT (4U)
1150 #define HW_FMC_TAGVDW0Sn_ADDR(x, n) ((x) + 0x100U + (0x4U * (n)))
1152 #define HW_FMC_TAGVDW0Sn(x, n) (*(__IO hw_fmc_tagvdw0sn_t *) HW_FMC_TAGVDW0Sn_ADDR(x, n))
1153 #define HW_FMC_TAGVDW0Sn_RD(x, n) (HW_FMC_TAGVDW0Sn(x, n).U)
1154 #define HW_FMC_TAGVDW0Sn_WR(x, n, v) (HW_FMC_TAGVDW0Sn(x, n).U = (v))
1155 #define HW_FMC_TAGVDW0Sn_SET(x, n, v) (HW_FMC_TAGVDW0Sn_WR(x, n, HW_FMC_TAGVDW0Sn_RD(x, n) | (v)))
1156 #define HW_FMC_TAGVDW0Sn_CLR(x, n, v) (HW_FMC_TAGVDW0Sn_WR(x, n, HW_FMC_TAGVDW0Sn_RD(x, n) & ~(v)))
1157 #define HW_FMC_TAGVDW0Sn_TOG(x, n, v) (HW_FMC_TAGVDW0Sn_WR(x, n, HW_FMC_TAGVDW0Sn_RD(x, n) ^ (v)))
1161 * Constants & macros for individual FMC_TAGVDW0Sn bitfields
1165 * @name Register FMC_TAGVDW0Sn, field valid[0] (RW)
1168 #define BP_FMC_TAGVDW0Sn_valid (0U) /*!< Bit position for FMC_TAGVDW0Sn_valid. */
1169 #define BM_FMC_TAGVDW0Sn_valid (0x00000001U) /*!< Bit mask for FMC_TAGVDW0Sn_valid. */
1170 #define BS_FMC_TAGVDW0Sn_valid (1U) /*!< Bit field size in bits for FMC_TAGVDW0Sn_valid. */
1172 /*! @brief Read current value of the FMC_TAGVDW0Sn_valid field. */
1173 #define BR_FMC_TAGVDW0Sn_valid(x, n) (BITBAND_ACCESS32(HW_FMC_TAGVDW0Sn_ADDR(x, n), BP_FMC_TAGVDW0Sn_valid))
1175 /*! @brief Format value for bitfield FMC_TAGVDW0Sn_valid. */
1176 #define BF_FMC_TAGVDW0Sn_valid(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW0Sn_valid) & BM_FMC_TAGVDW0Sn_valid)
1178 /*! @brief Set the valid field to a new value. */
1179 #define BW_FMC_TAGVDW0Sn_valid(x, n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW0Sn_ADDR(x, n), BP_FMC_TAGVDW0Sn_valid) = (v))
1183 * @name Register FMC_TAGVDW0Sn, field tag[18:5] (RW)
1186 #define BP_FMC_TAGVDW0Sn_tag (5U) /*!< Bit position for FMC_TAGVDW0Sn_tag. */
1187 #define BM_FMC_TAGVDW0Sn_tag (0x0007FFE0U) /*!< Bit mask for FMC_TAGVDW0Sn_tag. */
1188 #define BS_FMC_TAGVDW0Sn_tag (14U) /*!< Bit field size in bits for FMC_TAGVDW0Sn_tag. */
1190 /*! @brief Read current value of the FMC_TAGVDW0Sn_tag field. */
1191 #define BR_FMC_TAGVDW0Sn_tag(x, n) (HW_FMC_TAGVDW0Sn(x, n).B.tag)
1193 /*! @brief Format value for bitfield FMC_TAGVDW0Sn_tag. */
1194 #define BF_FMC_TAGVDW0Sn_tag(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW0Sn_tag) & BM_FMC_TAGVDW0Sn_tag)
1196 /*! @brief Set the tag field to a new value. */
1197 #define BW_FMC_TAGVDW0Sn_tag(x, n, v) (HW_FMC_TAGVDW0Sn_WR(x, n, (HW_FMC_TAGVDW0Sn_RD(x, n) & ~BM_FMC_TAGVDW0Sn_tag) | BF_FMC_TAGVDW0Sn_tag(v)))
1200 /*******************************************************************************
1201 * HW_FMC_TAGVDW1Sn - Cache Tag Storage
1202 ******************************************************************************/
1205 * @brief HW_FMC_TAGVDW1Sn - Cache Tag Storage (RW)
1207 * Reset value: 0x00000000U
1209 * The cache is a 4-way, set-associative cache with 4 sets. The ways are
1210 * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
1211 * denotes the set. This section represents tag/vld information for all sets in the
1214 typedef union _hw_fmc_tagvdw1sn
1217 struct _hw_fmc_tagvdw1sn_bitfields
1219 uint32_t valid
: 1; /*!< [0] 1-bit valid for cache entry */
1220 uint32_t RESERVED0
: 4; /*!< [4:1] */
1221 uint32_t tag
: 14; /*!< [18:5] 14-bit tag for cache entry */
1222 uint32_t RESERVED1
: 13; /*!< [31:19] */
1224 } hw_fmc_tagvdw1sn_t
;
1227 * @name Constants and macros for entire FMC_TAGVDW1Sn register
1230 #define HW_FMC_TAGVDW1Sn_COUNT (4U)
1232 #define HW_FMC_TAGVDW1Sn_ADDR(x, n) ((x) + 0x110U + (0x4U * (n)))
1234 #define HW_FMC_TAGVDW1Sn(x, n) (*(__IO hw_fmc_tagvdw1sn_t *) HW_FMC_TAGVDW1Sn_ADDR(x, n))
1235 #define HW_FMC_TAGVDW1Sn_RD(x, n) (HW_FMC_TAGVDW1Sn(x, n).U)
1236 #define HW_FMC_TAGVDW1Sn_WR(x, n, v) (HW_FMC_TAGVDW1Sn(x, n).U = (v))
1237 #define HW_FMC_TAGVDW1Sn_SET(x, n, v) (HW_FMC_TAGVDW1Sn_WR(x, n, HW_FMC_TAGVDW1Sn_RD(x, n) | (v)))
1238 #define HW_FMC_TAGVDW1Sn_CLR(x, n, v) (HW_FMC_TAGVDW1Sn_WR(x, n, HW_FMC_TAGVDW1Sn_RD(x, n) & ~(v)))
1239 #define HW_FMC_TAGVDW1Sn_TOG(x, n, v) (HW_FMC_TAGVDW1Sn_WR(x, n, HW_FMC_TAGVDW1Sn_RD(x, n) ^ (v)))
1243 * Constants & macros for individual FMC_TAGVDW1Sn bitfields
1247 * @name Register FMC_TAGVDW1Sn, field valid[0] (RW)
1250 #define BP_FMC_TAGVDW1Sn_valid (0U) /*!< Bit position for FMC_TAGVDW1Sn_valid. */
1251 #define BM_FMC_TAGVDW1Sn_valid (0x00000001U) /*!< Bit mask for FMC_TAGVDW1Sn_valid. */
1252 #define BS_FMC_TAGVDW1Sn_valid (1U) /*!< Bit field size in bits for FMC_TAGVDW1Sn_valid. */
1254 /*! @brief Read current value of the FMC_TAGVDW1Sn_valid field. */
1255 #define BR_FMC_TAGVDW1Sn_valid(x, n) (BITBAND_ACCESS32(HW_FMC_TAGVDW1Sn_ADDR(x, n), BP_FMC_TAGVDW1Sn_valid))
1257 /*! @brief Format value for bitfield FMC_TAGVDW1Sn_valid. */
1258 #define BF_FMC_TAGVDW1Sn_valid(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW1Sn_valid) & BM_FMC_TAGVDW1Sn_valid)
1260 /*! @brief Set the valid field to a new value. */
1261 #define BW_FMC_TAGVDW1Sn_valid(x, n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW1Sn_ADDR(x, n), BP_FMC_TAGVDW1Sn_valid) = (v))
1265 * @name Register FMC_TAGVDW1Sn, field tag[18:5] (RW)
1268 #define BP_FMC_TAGVDW1Sn_tag (5U) /*!< Bit position for FMC_TAGVDW1Sn_tag. */
1269 #define BM_FMC_TAGVDW1Sn_tag (0x0007FFE0U) /*!< Bit mask for FMC_TAGVDW1Sn_tag. */
1270 #define BS_FMC_TAGVDW1Sn_tag (14U) /*!< Bit field size in bits for FMC_TAGVDW1Sn_tag. */
1272 /*! @brief Read current value of the FMC_TAGVDW1Sn_tag field. */
1273 #define BR_FMC_TAGVDW1Sn_tag(x, n) (HW_FMC_TAGVDW1Sn(x, n).B.tag)
1275 /*! @brief Format value for bitfield FMC_TAGVDW1Sn_tag. */
1276 #define BF_FMC_TAGVDW1Sn_tag(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW1Sn_tag) & BM_FMC_TAGVDW1Sn_tag)
1278 /*! @brief Set the tag field to a new value. */
1279 #define BW_FMC_TAGVDW1Sn_tag(x, n, v) (HW_FMC_TAGVDW1Sn_WR(x, n, (HW_FMC_TAGVDW1Sn_RD(x, n) & ~BM_FMC_TAGVDW1Sn_tag) | BF_FMC_TAGVDW1Sn_tag(v)))
1282 /*******************************************************************************
1283 * HW_FMC_TAGVDW2Sn - Cache Tag Storage
1284 ******************************************************************************/
1287 * @brief HW_FMC_TAGVDW2Sn - Cache Tag Storage (RW)
1289 * Reset value: 0x00000000U
1291 * The cache is a 4-way, set-associative cache with 4 sets. The ways are
1292 * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
1293 * denotes the set. This section represents tag/vld information for all sets in the
1296 typedef union _hw_fmc_tagvdw2sn
1299 struct _hw_fmc_tagvdw2sn_bitfields
1301 uint32_t valid
: 1; /*!< [0] 1-bit valid for cache entry */
1302 uint32_t RESERVED0
: 4; /*!< [4:1] */
1303 uint32_t tag
: 14; /*!< [18:5] 14-bit tag for cache entry */
1304 uint32_t RESERVED1
: 13; /*!< [31:19] */
1306 } hw_fmc_tagvdw2sn_t
;
1309 * @name Constants and macros for entire FMC_TAGVDW2Sn register
1312 #define HW_FMC_TAGVDW2Sn_COUNT (4U)
1314 #define HW_FMC_TAGVDW2Sn_ADDR(x, n) ((x) + 0x120U + (0x4U * (n)))
1316 #define HW_FMC_TAGVDW2Sn(x, n) (*(__IO hw_fmc_tagvdw2sn_t *) HW_FMC_TAGVDW2Sn_ADDR(x, n))
1317 #define HW_FMC_TAGVDW2Sn_RD(x, n) (HW_FMC_TAGVDW2Sn(x, n).U)
1318 #define HW_FMC_TAGVDW2Sn_WR(x, n, v) (HW_FMC_TAGVDW2Sn(x, n).U = (v))
1319 #define HW_FMC_TAGVDW2Sn_SET(x, n, v) (HW_FMC_TAGVDW2Sn_WR(x, n, HW_FMC_TAGVDW2Sn_RD(x, n) | (v)))
1320 #define HW_FMC_TAGVDW2Sn_CLR(x, n, v) (HW_FMC_TAGVDW2Sn_WR(x, n, HW_FMC_TAGVDW2Sn_RD(x, n) & ~(v)))
1321 #define HW_FMC_TAGVDW2Sn_TOG(x, n, v) (HW_FMC_TAGVDW2Sn_WR(x, n, HW_FMC_TAGVDW2Sn_RD(x, n) ^ (v)))
1325 * Constants & macros for individual FMC_TAGVDW2Sn bitfields
1329 * @name Register FMC_TAGVDW2Sn, field valid[0] (RW)
1332 #define BP_FMC_TAGVDW2Sn_valid (0U) /*!< Bit position for FMC_TAGVDW2Sn_valid. */
1333 #define BM_FMC_TAGVDW2Sn_valid (0x00000001U) /*!< Bit mask for FMC_TAGVDW2Sn_valid. */
1334 #define BS_FMC_TAGVDW2Sn_valid (1U) /*!< Bit field size in bits for FMC_TAGVDW2Sn_valid. */
1336 /*! @brief Read current value of the FMC_TAGVDW2Sn_valid field. */
1337 #define BR_FMC_TAGVDW2Sn_valid(x, n) (BITBAND_ACCESS32(HW_FMC_TAGVDW2Sn_ADDR(x, n), BP_FMC_TAGVDW2Sn_valid))
1339 /*! @brief Format value for bitfield FMC_TAGVDW2Sn_valid. */
1340 #define BF_FMC_TAGVDW2Sn_valid(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW2Sn_valid) & BM_FMC_TAGVDW2Sn_valid)
1342 /*! @brief Set the valid field to a new value. */
1343 #define BW_FMC_TAGVDW2Sn_valid(x, n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW2Sn_ADDR(x, n), BP_FMC_TAGVDW2Sn_valid) = (v))
1347 * @name Register FMC_TAGVDW2Sn, field tag[18:5] (RW)
1350 #define BP_FMC_TAGVDW2Sn_tag (5U) /*!< Bit position for FMC_TAGVDW2Sn_tag. */
1351 #define BM_FMC_TAGVDW2Sn_tag (0x0007FFE0U) /*!< Bit mask for FMC_TAGVDW2Sn_tag. */
1352 #define BS_FMC_TAGVDW2Sn_tag (14U) /*!< Bit field size in bits for FMC_TAGVDW2Sn_tag. */
1354 /*! @brief Read current value of the FMC_TAGVDW2Sn_tag field. */
1355 #define BR_FMC_TAGVDW2Sn_tag(x, n) (HW_FMC_TAGVDW2Sn(x, n).B.tag)
1357 /*! @brief Format value for bitfield FMC_TAGVDW2Sn_tag. */
1358 #define BF_FMC_TAGVDW2Sn_tag(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW2Sn_tag) & BM_FMC_TAGVDW2Sn_tag)
1360 /*! @brief Set the tag field to a new value. */
1361 #define BW_FMC_TAGVDW2Sn_tag(x, n, v) (HW_FMC_TAGVDW2Sn_WR(x, n, (HW_FMC_TAGVDW2Sn_RD(x, n) & ~BM_FMC_TAGVDW2Sn_tag) | BF_FMC_TAGVDW2Sn_tag(v)))
1364 /*******************************************************************************
1365 * HW_FMC_TAGVDW3Sn - Cache Tag Storage
1366 ******************************************************************************/
1369 * @brief HW_FMC_TAGVDW3Sn - Cache Tag Storage (RW)
1371 * Reset value: 0x00000000U
1373 * The cache is a 4-way, set-associative cache with 4 sets. The ways are
1374 * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
1375 * denotes the set. This section represents tag/vld information for all sets in the
1378 typedef union _hw_fmc_tagvdw3sn
1381 struct _hw_fmc_tagvdw3sn_bitfields
1383 uint32_t valid
: 1; /*!< [0] 1-bit valid for cache entry */
1384 uint32_t RESERVED0
: 4; /*!< [4:1] */
1385 uint32_t tag
: 14; /*!< [18:5] 14-bit tag for cache entry */
1386 uint32_t RESERVED1
: 13; /*!< [31:19] */
1388 } hw_fmc_tagvdw3sn_t
;
1391 * @name Constants and macros for entire FMC_TAGVDW3Sn register
1394 #define HW_FMC_TAGVDW3Sn_COUNT (4U)
1396 #define HW_FMC_TAGVDW3Sn_ADDR(x, n) ((x) + 0x130U + (0x4U * (n)))
1398 #define HW_FMC_TAGVDW3Sn(x, n) (*(__IO hw_fmc_tagvdw3sn_t *) HW_FMC_TAGVDW3Sn_ADDR(x, n))
1399 #define HW_FMC_TAGVDW3Sn_RD(x, n) (HW_FMC_TAGVDW3Sn(x, n).U)
1400 #define HW_FMC_TAGVDW3Sn_WR(x, n, v) (HW_FMC_TAGVDW3Sn(x, n).U = (v))
1401 #define HW_FMC_TAGVDW3Sn_SET(x, n, v) (HW_FMC_TAGVDW3Sn_WR(x, n, HW_FMC_TAGVDW3Sn_RD(x, n) | (v)))
1402 #define HW_FMC_TAGVDW3Sn_CLR(x, n, v) (HW_FMC_TAGVDW3Sn_WR(x, n, HW_FMC_TAGVDW3Sn_RD(x, n) & ~(v)))
1403 #define HW_FMC_TAGVDW3Sn_TOG(x, n, v) (HW_FMC_TAGVDW3Sn_WR(x, n, HW_FMC_TAGVDW3Sn_RD(x, n) ^ (v)))
1407 * Constants & macros for individual FMC_TAGVDW3Sn bitfields
1411 * @name Register FMC_TAGVDW3Sn, field valid[0] (RW)
1414 #define BP_FMC_TAGVDW3Sn_valid (0U) /*!< Bit position for FMC_TAGVDW3Sn_valid. */
1415 #define BM_FMC_TAGVDW3Sn_valid (0x00000001U) /*!< Bit mask for FMC_TAGVDW3Sn_valid. */
1416 #define BS_FMC_TAGVDW3Sn_valid (1U) /*!< Bit field size in bits for FMC_TAGVDW3Sn_valid. */
1418 /*! @brief Read current value of the FMC_TAGVDW3Sn_valid field. */
1419 #define BR_FMC_TAGVDW3Sn_valid(x, n) (BITBAND_ACCESS32(HW_FMC_TAGVDW3Sn_ADDR(x, n), BP_FMC_TAGVDW3Sn_valid))
1421 /*! @brief Format value for bitfield FMC_TAGVDW3Sn_valid. */
1422 #define BF_FMC_TAGVDW3Sn_valid(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW3Sn_valid) & BM_FMC_TAGVDW3Sn_valid)
1424 /*! @brief Set the valid field to a new value. */
1425 #define BW_FMC_TAGVDW3Sn_valid(x, n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW3Sn_ADDR(x, n), BP_FMC_TAGVDW3Sn_valid) = (v))
1429 * @name Register FMC_TAGVDW3Sn, field tag[18:5] (RW)
1432 #define BP_FMC_TAGVDW3Sn_tag (5U) /*!< Bit position for FMC_TAGVDW3Sn_tag. */
1433 #define BM_FMC_TAGVDW3Sn_tag (0x0007FFE0U) /*!< Bit mask for FMC_TAGVDW3Sn_tag. */
1434 #define BS_FMC_TAGVDW3Sn_tag (14U) /*!< Bit field size in bits for FMC_TAGVDW3Sn_tag. */
1436 /*! @brief Read current value of the FMC_TAGVDW3Sn_tag field. */
1437 #define BR_FMC_TAGVDW3Sn_tag(x, n) (HW_FMC_TAGVDW3Sn(x, n).B.tag)
1439 /*! @brief Format value for bitfield FMC_TAGVDW3Sn_tag. */
1440 #define BF_FMC_TAGVDW3Sn_tag(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW3Sn_tag) & BM_FMC_TAGVDW3Sn_tag)
1442 /*! @brief Set the tag field to a new value. */
1443 #define BW_FMC_TAGVDW3Sn_tag(x, n, v) (HW_FMC_TAGVDW3Sn_WR(x, n, (HW_FMC_TAGVDW3Sn_RD(x, n) & ~BM_FMC_TAGVDW3Sn_tag) | BF_FMC_TAGVDW3Sn_tag(v)))
1446 /*******************************************************************************
1447 * HW_FMC_DATAW0SnU - Cache Data Storage (upper word)
1448 ******************************************************************************/
1451 * @brief HW_FMC_DATAW0SnU - Cache Data Storage (upper word) (RW)
1453 * Reset value: 0x00000000U
1455 * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
1456 * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
1457 * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
1458 * lower word, respectively. This section represents data for the upper word (bits
1459 * [63:32]) of all sets in the indicated way.
1461 typedef union _hw_fmc_dataw0snu
1464 struct _hw_fmc_dataw0snu_bitfields
1466 uint32_t data
: 32; /*!< [31:0] Bits [63:32] of data entry */
1468 } hw_fmc_dataw0snu_t
;
1471 * @name Constants and macros for entire FMC_DATAW0SnU register
1474 #define HW_FMC_DATAW0SnU_COUNT (4U)
1476 #define HW_FMC_DATAW0SnU_ADDR(x, n) ((x) + 0x200U + (0x8U * (n)))
1478 #define HW_FMC_DATAW0SnU(x, n) (*(__IO hw_fmc_dataw0snu_t *) HW_FMC_DATAW0SnU_ADDR(x, n))
1479 #define HW_FMC_DATAW0SnU_RD(x, n) (HW_FMC_DATAW0SnU(x, n).U)
1480 #define HW_FMC_DATAW0SnU_WR(x, n, v) (HW_FMC_DATAW0SnU(x, n).U = (v))
1481 #define HW_FMC_DATAW0SnU_SET(x, n, v) (HW_FMC_DATAW0SnU_WR(x, n, HW_FMC_DATAW0SnU_RD(x, n) | (v)))
1482 #define HW_FMC_DATAW0SnU_CLR(x, n, v) (HW_FMC_DATAW0SnU_WR(x, n, HW_FMC_DATAW0SnU_RD(x, n) & ~(v)))
1483 #define HW_FMC_DATAW0SnU_TOG(x, n, v) (HW_FMC_DATAW0SnU_WR(x, n, HW_FMC_DATAW0SnU_RD(x, n) ^ (v)))
1487 * Constants & macros for individual FMC_DATAW0SnU bitfields
1491 * @name Register FMC_DATAW0SnU, field data[31:0] (RW)
1494 #define BP_FMC_DATAW0SnU_data (0U) /*!< Bit position for FMC_DATAW0SnU_data. */
1495 #define BM_FMC_DATAW0SnU_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW0SnU_data. */
1496 #define BS_FMC_DATAW0SnU_data (32U) /*!< Bit field size in bits for FMC_DATAW0SnU_data. */
1498 /*! @brief Read current value of the FMC_DATAW0SnU_data field. */
1499 #define BR_FMC_DATAW0SnU_data(x, n) (HW_FMC_DATAW0SnU(x, n).U)
1501 /*! @brief Format value for bitfield FMC_DATAW0SnU_data. */
1502 #define BF_FMC_DATAW0SnU_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW0SnU_data) & BM_FMC_DATAW0SnU_data)
1504 /*! @brief Set the data field to a new value. */
1505 #define BW_FMC_DATAW0SnU_data(x, n, v) (HW_FMC_DATAW0SnU_WR(x, n, v))
1507 /*******************************************************************************
1508 * HW_FMC_DATAW0SnL - Cache Data Storage (lower word)
1509 ******************************************************************************/
1512 * @brief HW_FMC_DATAW0SnL - Cache Data Storage (lower word) (RW)
1514 * Reset value: 0x00000000U
1516 * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
1517 * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
1518 * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
1519 * lower word, respectively. This section represents data for the lower word (bits
1520 * [31:0]) of all sets in the indicated way.
1522 typedef union _hw_fmc_dataw0snl
1525 struct _hw_fmc_dataw0snl_bitfields
1527 uint32_t data
: 32; /*!< [31:0] Bits [31:0] of data entry */
1529 } hw_fmc_dataw0snl_t
;
1532 * @name Constants and macros for entire FMC_DATAW0SnL register
1535 #define HW_FMC_DATAW0SnL_COUNT (4U)
1537 #define HW_FMC_DATAW0SnL_ADDR(x, n) ((x) + 0x204U + (0x8U * (n)))
1539 #define HW_FMC_DATAW0SnL(x, n) (*(__IO hw_fmc_dataw0snl_t *) HW_FMC_DATAW0SnL_ADDR(x, n))
1540 #define HW_FMC_DATAW0SnL_RD(x, n) (HW_FMC_DATAW0SnL(x, n).U)
1541 #define HW_FMC_DATAW0SnL_WR(x, n, v) (HW_FMC_DATAW0SnL(x, n).U = (v))
1542 #define HW_FMC_DATAW0SnL_SET(x, n, v) (HW_FMC_DATAW0SnL_WR(x, n, HW_FMC_DATAW0SnL_RD(x, n) | (v)))
1543 #define HW_FMC_DATAW0SnL_CLR(x, n, v) (HW_FMC_DATAW0SnL_WR(x, n, HW_FMC_DATAW0SnL_RD(x, n) & ~(v)))
1544 #define HW_FMC_DATAW0SnL_TOG(x, n, v) (HW_FMC_DATAW0SnL_WR(x, n, HW_FMC_DATAW0SnL_RD(x, n) ^ (v)))
1548 * Constants & macros for individual FMC_DATAW0SnL bitfields
1552 * @name Register FMC_DATAW0SnL, field data[31:0] (RW)
1555 #define BP_FMC_DATAW0SnL_data (0U) /*!< Bit position for FMC_DATAW0SnL_data. */
1556 #define BM_FMC_DATAW0SnL_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW0SnL_data. */
1557 #define BS_FMC_DATAW0SnL_data (32U) /*!< Bit field size in bits for FMC_DATAW0SnL_data. */
1559 /*! @brief Read current value of the FMC_DATAW0SnL_data field. */
1560 #define BR_FMC_DATAW0SnL_data(x, n) (HW_FMC_DATAW0SnL(x, n).U)
1562 /*! @brief Format value for bitfield FMC_DATAW0SnL_data. */
1563 #define BF_FMC_DATAW0SnL_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW0SnL_data) & BM_FMC_DATAW0SnL_data)
1565 /*! @brief Set the data field to a new value. */
1566 #define BW_FMC_DATAW0SnL_data(x, n, v) (HW_FMC_DATAW0SnL_WR(x, n, v))
1569 /*******************************************************************************
1570 * HW_FMC_DATAW1SnU - Cache Data Storage (upper word)
1571 ******************************************************************************/
1574 * @brief HW_FMC_DATAW1SnU - Cache Data Storage (upper word) (RW)
1576 * Reset value: 0x00000000U
1578 * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
1579 * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
1580 * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
1581 * lower word, respectively. This section represents data for the upper word (bits
1582 * [63:32]) of all sets in the indicated way.
1584 typedef union _hw_fmc_dataw1snu
1587 struct _hw_fmc_dataw1snu_bitfields
1589 uint32_t data
: 32; /*!< [31:0] Bits [63:32] of data entry */
1591 } hw_fmc_dataw1snu_t
;
1594 * @name Constants and macros for entire FMC_DATAW1SnU register
1597 #define HW_FMC_DATAW1SnU_COUNT (4U)
1599 #define HW_FMC_DATAW1SnU_ADDR(x, n) ((x) + 0x220U + (0x8U * (n)))
1601 #define HW_FMC_DATAW1SnU(x, n) (*(__IO hw_fmc_dataw1snu_t *) HW_FMC_DATAW1SnU_ADDR(x, n))
1602 #define HW_FMC_DATAW1SnU_RD(x, n) (HW_FMC_DATAW1SnU(x, n).U)
1603 #define HW_FMC_DATAW1SnU_WR(x, n, v) (HW_FMC_DATAW1SnU(x, n).U = (v))
1604 #define HW_FMC_DATAW1SnU_SET(x, n, v) (HW_FMC_DATAW1SnU_WR(x, n, HW_FMC_DATAW1SnU_RD(x, n) | (v)))
1605 #define HW_FMC_DATAW1SnU_CLR(x, n, v) (HW_FMC_DATAW1SnU_WR(x, n, HW_FMC_DATAW1SnU_RD(x, n) & ~(v)))
1606 #define HW_FMC_DATAW1SnU_TOG(x, n, v) (HW_FMC_DATAW1SnU_WR(x, n, HW_FMC_DATAW1SnU_RD(x, n) ^ (v)))
1610 * Constants & macros for individual FMC_DATAW1SnU bitfields
1614 * @name Register FMC_DATAW1SnU, field data[31:0] (RW)
1617 #define BP_FMC_DATAW1SnU_data (0U) /*!< Bit position for FMC_DATAW1SnU_data. */
1618 #define BM_FMC_DATAW1SnU_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW1SnU_data. */
1619 #define BS_FMC_DATAW1SnU_data (32U) /*!< Bit field size in bits for FMC_DATAW1SnU_data. */
1621 /*! @brief Read current value of the FMC_DATAW1SnU_data field. */
1622 #define BR_FMC_DATAW1SnU_data(x, n) (HW_FMC_DATAW1SnU(x, n).U)
1624 /*! @brief Format value for bitfield FMC_DATAW1SnU_data. */
1625 #define BF_FMC_DATAW1SnU_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW1SnU_data) & BM_FMC_DATAW1SnU_data)
1627 /*! @brief Set the data field to a new value. */
1628 #define BW_FMC_DATAW1SnU_data(x, n, v) (HW_FMC_DATAW1SnU_WR(x, n, v))
1630 /*******************************************************************************
1631 * HW_FMC_DATAW1SnL - Cache Data Storage (lower word)
1632 ******************************************************************************/
1635 * @brief HW_FMC_DATAW1SnL - Cache Data Storage (lower word) (RW)
1637 * Reset value: 0x00000000U
1639 * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
1640 * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
1641 * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
1642 * lower word, respectively. This section represents data for the lower word (bits
1643 * [31:0]) of all sets in the indicated way.
1645 typedef union _hw_fmc_dataw1snl
1648 struct _hw_fmc_dataw1snl_bitfields
1650 uint32_t data
: 32; /*!< [31:0] Bits [31:0] of data entry */
1652 } hw_fmc_dataw1snl_t
;
1655 * @name Constants and macros for entire FMC_DATAW1SnL register
1658 #define HW_FMC_DATAW1SnL_COUNT (4U)
1660 #define HW_FMC_DATAW1SnL_ADDR(x, n) ((x) + 0x224U + (0x8U * (n)))
1662 #define HW_FMC_DATAW1SnL(x, n) (*(__IO hw_fmc_dataw1snl_t *) HW_FMC_DATAW1SnL_ADDR(x, n))
1663 #define HW_FMC_DATAW1SnL_RD(x, n) (HW_FMC_DATAW1SnL(x, n).U)
1664 #define HW_FMC_DATAW1SnL_WR(x, n, v) (HW_FMC_DATAW1SnL(x, n).U = (v))
1665 #define HW_FMC_DATAW1SnL_SET(x, n, v) (HW_FMC_DATAW1SnL_WR(x, n, HW_FMC_DATAW1SnL_RD(x, n) | (v)))
1666 #define HW_FMC_DATAW1SnL_CLR(x, n, v) (HW_FMC_DATAW1SnL_WR(x, n, HW_FMC_DATAW1SnL_RD(x, n) & ~(v)))
1667 #define HW_FMC_DATAW1SnL_TOG(x, n, v) (HW_FMC_DATAW1SnL_WR(x, n, HW_FMC_DATAW1SnL_RD(x, n) ^ (v)))
1671 * Constants & macros for individual FMC_DATAW1SnL bitfields
1675 * @name Register FMC_DATAW1SnL, field data[31:0] (RW)
1678 #define BP_FMC_DATAW1SnL_data (0U) /*!< Bit position for FMC_DATAW1SnL_data. */
1679 #define BM_FMC_DATAW1SnL_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW1SnL_data. */
1680 #define BS_FMC_DATAW1SnL_data (32U) /*!< Bit field size in bits for FMC_DATAW1SnL_data. */
1682 /*! @brief Read current value of the FMC_DATAW1SnL_data field. */
1683 #define BR_FMC_DATAW1SnL_data(x, n) (HW_FMC_DATAW1SnL(x, n).U)
1685 /*! @brief Format value for bitfield FMC_DATAW1SnL_data. */
1686 #define BF_FMC_DATAW1SnL_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW1SnL_data) & BM_FMC_DATAW1SnL_data)
1688 /*! @brief Set the data field to a new value. */
1689 #define BW_FMC_DATAW1SnL_data(x, n, v) (HW_FMC_DATAW1SnL_WR(x, n, v))
1692 /*******************************************************************************
1693 * HW_FMC_DATAW2SnU - Cache Data Storage (upper word)
1694 ******************************************************************************/
1697 * @brief HW_FMC_DATAW2SnU - Cache Data Storage (upper word) (RW)
1699 * Reset value: 0x00000000U
1701 * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
1702 * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
1703 * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
1704 * lower word, respectively. This section represents data for the upper word (bits
1705 * [63:32]) of all sets in the indicated way.
1707 typedef union _hw_fmc_dataw2snu
1710 struct _hw_fmc_dataw2snu_bitfields
1712 uint32_t data
: 32; /*!< [31:0] Bits [63:32] of data entry */
1714 } hw_fmc_dataw2snu_t
;
1717 * @name Constants and macros for entire FMC_DATAW2SnU register
1720 #define HW_FMC_DATAW2SnU_COUNT (4U)
1722 #define HW_FMC_DATAW2SnU_ADDR(x, n) ((x) + 0x240U + (0x8U * (n)))
1724 #define HW_FMC_DATAW2SnU(x, n) (*(__IO hw_fmc_dataw2snu_t *) HW_FMC_DATAW2SnU_ADDR(x, n))
1725 #define HW_FMC_DATAW2SnU_RD(x, n) (HW_FMC_DATAW2SnU(x, n).U)
1726 #define HW_FMC_DATAW2SnU_WR(x, n, v) (HW_FMC_DATAW2SnU(x, n).U = (v))
1727 #define HW_FMC_DATAW2SnU_SET(x, n, v) (HW_FMC_DATAW2SnU_WR(x, n, HW_FMC_DATAW2SnU_RD(x, n) | (v)))
1728 #define HW_FMC_DATAW2SnU_CLR(x, n, v) (HW_FMC_DATAW2SnU_WR(x, n, HW_FMC_DATAW2SnU_RD(x, n) & ~(v)))
1729 #define HW_FMC_DATAW2SnU_TOG(x, n, v) (HW_FMC_DATAW2SnU_WR(x, n, HW_FMC_DATAW2SnU_RD(x, n) ^ (v)))
1733 * Constants & macros for individual FMC_DATAW2SnU bitfields
1737 * @name Register FMC_DATAW2SnU, field data[31:0] (RW)
1740 #define BP_FMC_DATAW2SnU_data (0U) /*!< Bit position for FMC_DATAW2SnU_data. */
1741 #define BM_FMC_DATAW2SnU_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW2SnU_data. */
1742 #define BS_FMC_DATAW2SnU_data (32U) /*!< Bit field size in bits for FMC_DATAW2SnU_data. */
1744 /*! @brief Read current value of the FMC_DATAW2SnU_data field. */
1745 #define BR_FMC_DATAW2SnU_data(x, n) (HW_FMC_DATAW2SnU(x, n).U)
1747 /*! @brief Format value for bitfield FMC_DATAW2SnU_data. */
1748 #define BF_FMC_DATAW2SnU_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW2SnU_data) & BM_FMC_DATAW2SnU_data)
1750 /*! @brief Set the data field to a new value. */
1751 #define BW_FMC_DATAW2SnU_data(x, n, v) (HW_FMC_DATAW2SnU_WR(x, n, v))
1753 /*******************************************************************************
1754 * HW_FMC_DATAW2SnL - Cache Data Storage (lower word)
1755 ******************************************************************************/
1758 * @brief HW_FMC_DATAW2SnL - Cache Data Storage (lower word) (RW)
1760 * Reset value: 0x00000000U
1762 * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
1763 * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
1764 * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
1765 * lower word, respectively. This section represents data for the lower word (bits
1766 * [31:0]) of all sets in the indicated way.
1768 typedef union _hw_fmc_dataw2snl
1771 struct _hw_fmc_dataw2snl_bitfields
1773 uint32_t data
: 32; /*!< [31:0] Bits [31:0] of data entry */
1775 } hw_fmc_dataw2snl_t
;
1778 * @name Constants and macros for entire FMC_DATAW2SnL register
1781 #define HW_FMC_DATAW2SnL_COUNT (4U)
1783 #define HW_FMC_DATAW2SnL_ADDR(x, n) ((x) + 0x244U + (0x8U * (n)))
1785 #define HW_FMC_DATAW2SnL(x, n) (*(__IO hw_fmc_dataw2snl_t *) HW_FMC_DATAW2SnL_ADDR(x, n))
1786 #define HW_FMC_DATAW2SnL_RD(x, n) (HW_FMC_DATAW2SnL(x, n).U)
1787 #define HW_FMC_DATAW2SnL_WR(x, n, v) (HW_FMC_DATAW2SnL(x, n).U = (v))
1788 #define HW_FMC_DATAW2SnL_SET(x, n, v) (HW_FMC_DATAW2SnL_WR(x, n, HW_FMC_DATAW2SnL_RD(x, n) | (v)))
1789 #define HW_FMC_DATAW2SnL_CLR(x, n, v) (HW_FMC_DATAW2SnL_WR(x, n, HW_FMC_DATAW2SnL_RD(x, n) & ~(v)))
1790 #define HW_FMC_DATAW2SnL_TOG(x, n, v) (HW_FMC_DATAW2SnL_WR(x, n, HW_FMC_DATAW2SnL_RD(x, n) ^ (v)))
1794 * Constants & macros for individual FMC_DATAW2SnL bitfields
1798 * @name Register FMC_DATAW2SnL, field data[31:0] (RW)
1801 #define BP_FMC_DATAW2SnL_data (0U) /*!< Bit position for FMC_DATAW2SnL_data. */
1802 #define BM_FMC_DATAW2SnL_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW2SnL_data. */
1803 #define BS_FMC_DATAW2SnL_data (32U) /*!< Bit field size in bits for FMC_DATAW2SnL_data. */
1805 /*! @brief Read current value of the FMC_DATAW2SnL_data field. */
1806 #define BR_FMC_DATAW2SnL_data(x, n) (HW_FMC_DATAW2SnL(x, n).U)
1808 /*! @brief Format value for bitfield FMC_DATAW2SnL_data. */
1809 #define BF_FMC_DATAW2SnL_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW2SnL_data) & BM_FMC_DATAW2SnL_data)
1811 /*! @brief Set the data field to a new value. */
1812 #define BW_FMC_DATAW2SnL_data(x, n, v) (HW_FMC_DATAW2SnL_WR(x, n, v))
1815 /*******************************************************************************
1816 * HW_FMC_DATAW3SnU - Cache Data Storage (upper word)
1817 ******************************************************************************/
1820 * @brief HW_FMC_DATAW3SnU - Cache Data Storage (upper word) (RW)
1822 * Reset value: 0x00000000U
1824 * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
1825 * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
1826 * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
1827 * lower word, respectively. This section represents data for the upper word (bits
1828 * [63:32]) of all sets in the indicated way.
1830 typedef union _hw_fmc_dataw3snu
1833 struct _hw_fmc_dataw3snu_bitfields
1835 uint32_t data
: 32; /*!< [31:0] Bits [63:32] of data entry */
1837 } hw_fmc_dataw3snu_t
;
1840 * @name Constants and macros for entire FMC_DATAW3SnU register
1843 #define HW_FMC_DATAW3SnU_COUNT (4U)
1845 #define HW_FMC_DATAW3SnU_ADDR(x, n) ((x) + 0x260U + (0x8U * (n)))
1847 #define HW_FMC_DATAW3SnU(x, n) (*(__IO hw_fmc_dataw3snu_t *) HW_FMC_DATAW3SnU_ADDR(x, n))
1848 #define HW_FMC_DATAW3SnU_RD(x, n) (HW_FMC_DATAW3SnU(x, n).U)
1849 #define HW_FMC_DATAW3SnU_WR(x, n, v) (HW_FMC_DATAW3SnU(x, n).U = (v))
1850 #define HW_FMC_DATAW3SnU_SET(x, n, v) (HW_FMC_DATAW3SnU_WR(x, n, HW_FMC_DATAW3SnU_RD(x, n) | (v)))
1851 #define HW_FMC_DATAW3SnU_CLR(x, n, v) (HW_FMC_DATAW3SnU_WR(x, n, HW_FMC_DATAW3SnU_RD(x, n) & ~(v)))
1852 #define HW_FMC_DATAW3SnU_TOG(x, n, v) (HW_FMC_DATAW3SnU_WR(x, n, HW_FMC_DATAW3SnU_RD(x, n) ^ (v)))
1856 * Constants & macros for individual FMC_DATAW3SnU bitfields
1860 * @name Register FMC_DATAW3SnU, field data[31:0] (RW)
1863 #define BP_FMC_DATAW3SnU_data (0U) /*!< Bit position for FMC_DATAW3SnU_data. */
1864 #define BM_FMC_DATAW3SnU_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW3SnU_data. */
1865 #define BS_FMC_DATAW3SnU_data (32U) /*!< Bit field size in bits for FMC_DATAW3SnU_data. */
1867 /*! @brief Read current value of the FMC_DATAW3SnU_data field. */
1868 #define BR_FMC_DATAW3SnU_data(x, n) (HW_FMC_DATAW3SnU(x, n).U)
1870 /*! @brief Format value for bitfield FMC_DATAW3SnU_data. */
1871 #define BF_FMC_DATAW3SnU_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW3SnU_data) & BM_FMC_DATAW3SnU_data)
1873 /*! @brief Set the data field to a new value. */
1874 #define BW_FMC_DATAW3SnU_data(x, n, v) (HW_FMC_DATAW3SnU_WR(x, n, v))
1876 /*******************************************************************************
1877 * HW_FMC_DATAW3SnL - Cache Data Storage (lower word)
1878 ******************************************************************************/
1881 * @brief HW_FMC_DATAW3SnL - Cache Data Storage (lower word) (RW)
1883 * Reset value: 0x00000000U
1885 * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
1886 * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
1887 * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
1888 * lower word, respectively. This section represents data for the lower word (bits
1889 * [31:0]) of all sets in the indicated way.
1891 typedef union _hw_fmc_dataw3snl
1894 struct _hw_fmc_dataw3snl_bitfields
1896 uint32_t data
: 32; /*!< [31:0] Bits [31:0] of data entry */
1898 } hw_fmc_dataw3snl_t
;
1901 * @name Constants and macros for entire FMC_DATAW3SnL register
1904 #define HW_FMC_DATAW3SnL_COUNT (4U)
1906 #define HW_FMC_DATAW3SnL_ADDR(x, n) ((x) + 0x264U + (0x8U * (n)))
1908 #define HW_FMC_DATAW3SnL(x, n) (*(__IO hw_fmc_dataw3snl_t *) HW_FMC_DATAW3SnL_ADDR(x, n))
1909 #define HW_FMC_DATAW3SnL_RD(x, n) (HW_FMC_DATAW3SnL(x, n).U)
1910 #define HW_FMC_DATAW3SnL_WR(x, n, v) (HW_FMC_DATAW3SnL(x, n).U = (v))
1911 #define HW_FMC_DATAW3SnL_SET(x, n, v) (HW_FMC_DATAW3SnL_WR(x, n, HW_FMC_DATAW3SnL_RD(x, n) | (v)))
1912 #define HW_FMC_DATAW3SnL_CLR(x, n, v) (HW_FMC_DATAW3SnL_WR(x, n, HW_FMC_DATAW3SnL_RD(x, n) & ~(v)))
1913 #define HW_FMC_DATAW3SnL_TOG(x, n, v) (HW_FMC_DATAW3SnL_WR(x, n, HW_FMC_DATAW3SnL_RD(x, n) ^ (v)))
1917 * Constants & macros for individual FMC_DATAW3SnL bitfields
1921 * @name Register FMC_DATAW3SnL, field data[31:0] (RW)
1924 #define BP_FMC_DATAW3SnL_data (0U) /*!< Bit position for FMC_DATAW3SnL_data. */
1925 #define BM_FMC_DATAW3SnL_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW3SnL_data. */
1926 #define BS_FMC_DATAW3SnL_data (32U) /*!< Bit field size in bits for FMC_DATAW3SnL_data. */
1928 /*! @brief Read current value of the FMC_DATAW3SnL_data field. */
1929 #define BR_FMC_DATAW3SnL_data(x, n) (HW_FMC_DATAW3SnL(x, n).U)
1931 /*! @brief Format value for bitfield FMC_DATAW3SnL_data. */
1932 #define BF_FMC_DATAW3SnL_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW3SnL_data) & BM_FMC_DATAW3SnL_data)
1934 /*! @brief Set the data field to a new value. */
1935 #define BW_FMC_DATAW3SnL_data(x, n, v) (HW_FMC_DATAW3SnL_WR(x, n, v))
1938 /*******************************************************************************
1939 * hw_fmc_t - module struct
1940 ******************************************************************************/
1942 * @brief All FMC module registers.
1945 typedef struct _hw_fmc
1947 __IO hw_fmc_pfapr_t PFAPR
; /*!< [0x0] Flash Access Protection Register */
1948 __IO hw_fmc_pfb0cr_t PFB0CR
; /*!< [0x4] Flash Bank 0 Control Register */
1949 __IO hw_fmc_pfb1cr_t PFB1CR
; /*!< [0x8] Flash Bank 1 Control Register */
1950 uint8_t _reserved0
[244];
1951 __IO hw_fmc_tagvdw0sn_t TAGVDW0Sn
[4]; /*!< [0x100] Cache Tag Storage */
1952 __IO hw_fmc_tagvdw1sn_t TAGVDW1Sn
[4]; /*!< [0x110] Cache Tag Storage */
1953 __IO hw_fmc_tagvdw2sn_t TAGVDW2Sn
[4]; /*!< [0x120] Cache Tag Storage */
1954 __IO hw_fmc_tagvdw3sn_t TAGVDW3Sn
[4]; /*!< [0x130] Cache Tag Storage */
1955 uint8_t _reserved1
[192];
1957 __IO hw_fmc_dataw0snu_t DATAW0SnU
; /*!< [0x200] Cache Data Storage (upper word) */
1958 __IO hw_fmc_dataw0snl_t DATAW0SnL
; /*!< [0x204] Cache Data Storage (lower word) */
1961 __IO hw_fmc_dataw1snu_t DATAW1SnU
; /*!< [0x220] Cache Data Storage (upper word) */
1962 __IO hw_fmc_dataw1snl_t DATAW1SnL
; /*!< [0x224] Cache Data Storage (lower word) */
1965 __IO hw_fmc_dataw2snu_t DATAW2SnU
; /*!< [0x240] Cache Data Storage (upper word) */
1966 __IO hw_fmc_dataw2snl_t DATAW2SnL
; /*!< [0x244] Cache Data Storage (lower word) */
1969 __IO hw_fmc_dataw3snu_t DATAW3SnU
; /*!< [0x260] Cache Data Storage (upper word) */
1970 __IO hw_fmc_dataw3snl_t DATAW3SnL
; /*!< [0x264] Cache Data Storage (lower word) */
1975 /*! @brief Macro to access all FMC registers. */
1976 /*! @param x FMC module instance base address. */
1977 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
1978 * use the '&' operator, like <code>&HW_FMC(FMC_BASE)</code>. */
1979 #define HW_FMC(x) (*(hw_fmc_t *)(x))
1981 #endif /* __HW_FMC_REGISTERS_H__ */