2 ** ###################################################################
3 ** Compilers: Keil ARM C/C++ Compiler
4 ** Freescale C/C++ for Embedded ARM
6 ** IAR ANSI C/C++ Compiler for ARM
8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
9 ** Version: rev. 2.5, 2014-02-10
13 ** Extension to the CMSIS register access layer header.
15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
16 ** All rights reserved.
18 ** Redistribution and use in source and binary forms, with or without modification,
19 ** are permitted provided that the following conditions are met:
21 ** o Redistributions of source code must retain the above copyright notice, this list
22 ** of conditions and the following disclaimer.
24 ** o Redistributions in binary form must reproduce the above copyright notice, this
25 ** list of conditions and the following disclaimer in the documentation and/or
26 ** other materials provided with the distribution.
28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
29 ** contributors may be used to endorse or promote products derived from this
30 ** software without specific prior written permission.
32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ** http: www.freescale.com
44 ** mail: support@freescale.com
47 ** - rev. 1.0 (2013-08-12)
49 ** - rev. 2.0 (2013-10-29)
50 ** Register accessor macros added to the memory map.
51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
52 ** Startup file for gcc has been updated according to CMSIS 3.2.
53 ** System initialization updated.
54 ** MCG - registers updated.
55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
56 ** - rev. 2.1 (2013-10-30)
57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
58 ** - rev. 2.2 (2013-12-09)
59 ** DMA - EARS register removed.
60 ** AIPS0, AIPS1 - MPRA register updated.
61 ** - rev. 2.3 (2014-01-24)
62 ** Update according to reference manual rev. 2
63 ** ENET, MCG, MCM, SIM, USB - registers updated
64 ** - rev. 2.4 (2014-02-10)
65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
67 ** - rev. 2.5 (2014-02-10)
68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
72 ** ###################################################################
76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
78 * This file was generated automatically and any changes may be lost.
80 #ifndef __HW_FTFE_REGISTERS_H__
81 #define __HW_FTFE_REGISTERS_H__
84 #include "fsl_bitaccess.h"
89 * Flash Memory Interface
91 * Registers defined in this header file:
92 * - HW_FTFE_FSTAT - Flash Status Register
93 * - HW_FTFE_FCNFG - Flash Configuration Register
94 * - HW_FTFE_FSEC - Flash Security Register
95 * - HW_FTFE_FOPT - Flash Option Register
96 * - HW_FTFE_FCCOB3 - Flash Common Command Object Registers
97 * - HW_FTFE_FCCOB2 - Flash Common Command Object Registers
98 * - HW_FTFE_FCCOB1 - Flash Common Command Object Registers
99 * - HW_FTFE_FCCOB0 - Flash Common Command Object Registers
100 * - HW_FTFE_FCCOB7 - Flash Common Command Object Registers
101 * - HW_FTFE_FCCOB6 - Flash Common Command Object Registers
102 * - HW_FTFE_FCCOB5 - Flash Common Command Object Registers
103 * - HW_FTFE_FCCOB4 - Flash Common Command Object Registers
104 * - HW_FTFE_FCCOBB - Flash Common Command Object Registers
105 * - HW_FTFE_FCCOBA - Flash Common Command Object Registers
106 * - HW_FTFE_FCCOB9 - Flash Common Command Object Registers
107 * - HW_FTFE_FCCOB8 - Flash Common Command Object Registers
108 * - HW_FTFE_FPROT3 - Program Flash Protection Registers
109 * - HW_FTFE_FPROT2 - Program Flash Protection Registers
110 * - HW_FTFE_FPROT1 - Program Flash Protection Registers
111 * - HW_FTFE_FPROT0 - Program Flash Protection Registers
112 * - HW_FTFE_FEPROT - EEPROM Protection Register
113 * - HW_FTFE_FDPROT - Data Flash Protection Register
115 * - hw_ftfe_t - Struct containing all module registers.
118 #define HW_FTFE_INSTANCE_COUNT (1U) /*!< Number of instances of the FTFE module. */
120 /*******************************************************************************
121 * HW_FTFE_FSTAT - Flash Status Register
122 ******************************************************************************/
125 * @brief HW_FTFE_FSTAT - Flash Status Register (RW)
129 * The FSTAT register reports the operational status of the FTFE module. The
130 * CCIF, RDCOLERR, ACCERR, and FPVIOL bits are readable and writable. The MGSTAT0
131 * bit is read only. The unassigned bits read 0 and are not writable. When set, the
132 * Access Error (ACCERR) and Flash Protection Violation (FPVIOL) bits in this
133 * register prevent the launch of any more commands or writes to the FlexRAM (when
134 * EEERDY is set) until the flag is cleared (by writing a one to it).
136 typedef union _hw_ftfe_fstat
139 struct _hw_ftfe_fstat_bitfields
141 uint8_t MGSTAT0
: 1; /*!< [0] Memory Controller Command Completion
143 uint8_t RESERVED0
: 3; /*!< [3:1] */
144 uint8_t FPVIOL
: 1; /*!< [4] Flash Protection Violation Flag */
145 uint8_t ACCERR
: 1; /*!< [5] Flash Access Error Flag */
146 uint8_t RDCOLERR
: 1; /*!< [6] FTFE Read Collision Error Flag */
147 uint8_t CCIF
: 1; /*!< [7] Command Complete Interrupt Flag */
152 * @name Constants and macros for entire FTFE_FSTAT register
155 #define HW_FTFE_FSTAT_ADDR(x) ((x) + 0x0U)
157 #define HW_FTFE_FSTAT(x) (*(__IO hw_ftfe_fstat_t *) HW_FTFE_FSTAT_ADDR(x))
158 #define HW_FTFE_FSTAT_RD(x) (HW_FTFE_FSTAT(x).U)
159 #define HW_FTFE_FSTAT_WR(x, v) (HW_FTFE_FSTAT(x).U = (v))
160 #define HW_FTFE_FSTAT_SET(x, v) (HW_FTFE_FSTAT_WR(x, HW_FTFE_FSTAT_RD(x) | (v)))
161 #define HW_FTFE_FSTAT_CLR(x, v) (HW_FTFE_FSTAT_WR(x, HW_FTFE_FSTAT_RD(x) & ~(v)))
162 #define HW_FTFE_FSTAT_TOG(x, v) (HW_FTFE_FSTAT_WR(x, HW_FTFE_FSTAT_RD(x) ^ (v)))
166 * Constants & macros for individual FTFE_FSTAT bitfields
170 * @name Register FTFE_FSTAT, field MGSTAT0[0] (RO)
172 * The MGSTAT0 status flag is set if an error is detected during execution of an
173 * FTFE command or during the flash reset sequence. As a status flag, this bit
174 * cannot (and need not) be cleared by the user like the other error flags in this
175 * register. The value of the MGSTAT0 bit for "command-N" is valid only at the
176 * end of the "command-N" execution when CCIF=1 and before the next command has
177 * been launched. At some point during the execution of "command-N+1," the previous
178 * result is discarded and any previous error is cleared.
181 #define BP_FTFE_FSTAT_MGSTAT0 (0U) /*!< Bit position for FTFE_FSTAT_MGSTAT0. */
182 #define BM_FTFE_FSTAT_MGSTAT0 (0x01U) /*!< Bit mask for FTFE_FSTAT_MGSTAT0. */
183 #define BS_FTFE_FSTAT_MGSTAT0 (1U) /*!< Bit field size in bits for FTFE_FSTAT_MGSTAT0. */
185 /*! @brief Read current value of the FTFE_FSTAT_MGSTAT0 field. */
186 #define BR_FTFE_FSTAT_MGSTAT0(x) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_MGSTAT0))
190 * @name Register FTFE_FSTAT, field FPVIOL[4] (W1C)
192 * The FPVIOL error bit indicates an attempt was made to program or erase an
193 * address in a protected area of program flash or data flash memory during a
194 * command write sequence or a write was attempted to a protected area of the FlexRAM
195 * while enabled for EEPROM. While FPVIOL is set, the CCIF flag cannot be cleared
196 * to launch a command. The FPVIOL bit is cleared by writing a 1 to it. Writing a
197 * 0 to the FPVIOL bit has no effect.
200 * - 0 - No protection violation detected
201 * - 1 - Protection violation detected
204 #define BP_FTFE_FSTAT_FPVIOL (4U) /*!< Bit position for FTFE_FSTAT_FPVIOL. */
205 #define BM_FTFE_FSTAT_FPVIOL (0x10U) /*!< Bit mask for FTFE_FSTAT_FPVIOL. */
206 #define BS_FTFE_FSTAT_FPVIOL (1U) /*!< Bit field size in bits for FTFE_FSTAT_FPVIOL. */
208 /*! @brief Read current value of the FTFE_FSTAT_FPVIOL field. */
209 #define BR_FTFE_FSTAT_FPVIOL(x) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_FPVIOL))
211 /*! @brief Format value for bitfield FTFE_FSTAT_FPVIOL. */
212 #define BF_FTFE_FSTAT_FPVIOL(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FSTAT_FPVIOL) & BM_FTFE_FSTAT_FPVIOL)
214 /*! @brief Set the FPVIOL field to a new value. */
215 #define BW_FTFE_FSTAT_FPVIOL(x, v) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_FPVIOL) = (v))
219 * @name Register FTFE_FSTAT, field ACCERR[5] (W1C)
221 * The ACCERR error bit indicates an illegal access has occurred to an FTFE
222 * resource caused by a violation of the command write sequence or issuing an illegal
223 * FTFE command. While ACCERR is set, the CCIF flag cannot be cleared to launch
224 * a command. The ACCERR bit is cleared by writing a 1 to it. Writing a 0 to the
225 * ACCERR bit has no effect.
228 * - 0 - No access error detected
229 * - 1 - Access error detected
232 #define BP_FTFE_FSTAT_ACCERR (5U) /*!< Bit position for FTFE_FSTAT_ACCERR. */
233 #define BM_FTFE_FSTAT_ACCERR (0x20U) /*!< Bit mask for FTFE_FSTAT_ACCERR. */
234 #define BS_FTFE_FSTAT_ACCERR (1U) /*!< Bit field size in bits for FTFE_FSTAT_ACCERR. */
236 /*! @brief Read current value of the FTFE_FSTAT_ACCERR field. */
237 #define BR_FTFE_FSTAT_ACCERR(x) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_ACCERR))
239 /*! @brief Format value for bitfield FTFE_FSTAT_ACCERR. */
240 #define BF_FTFE_FSTAT_ACCERR(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FSTAT_ACCERR) & BM_FTFE_FSTAT_ACCERR)
242 /*! @brief Set the ACCERR field to a new value. */
243 #define BW_FTFE_FSTAT_ACCERR(x, v) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_ACCERR) = (v))
247 * @name Register FTFE_FSTAT, field RDCOLERR[6] (W1C)
249 * The RDCOLERR error bit indicates that the MCU attempted a read from an FTFE
250 * resource that was being manipulated by an FTFE command (CCIF=0). Any
251 * simultaneous access is detected as a collision error by the block arbitration logic. The
252 * read data in this case cannot be guaranteed. The RDCOLERR bit is cleared by
253 * writing a 1 to it. Writing a 0 to RDCOLERR has no effect.
256 * - 0 - No collision error detected
257 * - 1 - Collision error detected
260 #define BP_FTFE_FSTAT_RDCOLERR (6U) /*!< Bit position for FTFE_FSTAT_RDCOLERR. */
261 #define BM_FTFE_FSTAT_RDCOLERR (0x40U) /*!< Bit mask for FTFE_FSTAT_RDCOLERR. */
262 #define BS_FTFE_FSTAT_RDCOLERR (1U) /*!< Bit field size in bits for FTFE_FSTAT_RDCOLERR. */
264 /*! @brief Read current value of the FTFE_FSTAT_RDCOLERR field. */
265 #define BR_FTFE_FSTAT_RDCOLERR(x) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_RDCOLERR))
267 /*! @brief Format value for bitfield FTFE_FSTAT_RDCOLERR. */
268 #define BF_FTFE_FSTAT_RDCOLERR(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FSTAT_RDCOLERR) & BM_FTFE_FSTAT_RDCOLERR)
270 /*! @brief Set the RDCOLERR field to a new value. */
271 #define BW_FTFE_FSTAT_RDCOLERR(x, v) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_RDCOLERR) = (v))
275 * @name Register FTFE_FSTAT, field CCIF[7] (W1C)
277 * The CCIF flag indicates that a FTFE command or EEPROM file system operation
278 * has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a
279 * command, and CCIF stays low until command completion or command violation. The
280 * CCIF flag is also cleared by a successful write to FlexRAM while enabled for EEE,
281 * and CCIF stays low until the EEPROM file system has created the associated
282 * EEPROM data record. The CCIF bit is reset to 0 but is set to 1 by the memory
283 * controller at the end of the reset initialization sequence. Depending on how
284 * quickly the read occurs after reset release, the user may or may not see the 0
285 * hardware reset value.
288 * - 0 - FTFE command or EEPROM file system operation in progress
289 * - 1 - FTFE command or EEPROM file system operation has completed
292 #define BP_FTFE_FSTAT_CCIF (7U) /*!< Bit position for FTFE_FSTAT_CCIF. */
293 #define BM_FTFE_FSTAT_CCIF (0x80U) /*!< Bit mask for FTFE_FSTAT_CCIF. */
294 #define BS_FTFE_FSTAT_CCIF (1U) /*!< Bit field size in bits for FTFE_FSTAT_CCIF. */
296 /*! @brief Read current value of the FTFE_FSTAT_CCIF field. */
297 #define BR_FTFE_FSTAT_CCIF(x) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_CCIF))
299 /*! @brief Format value for bitfield FTFE_FSTAT_CCIF. */
300 #define BF_FTFE_FSTAT_CCIF(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FSTAT_CCIF) & BM_FTFE_FSTAT_CCIF)
302 /*! @brief Set the CCIF field to a new value. */
303 #define BW_FTFE_FSTAT_CCIF(x, v) (BITBAND_ACCESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_CCIF) = (v))
306 /*******************************************************************************
307 * HW_FTFE_FCNFG - Flash Configuration Register
308 ******************************************************************************/
311 * @brief HW_FTFE_FCNFG - Flash Configuration Register (RW)
315 * This register provides information on the current functional state of the
316 * FTFE module. The erase control bits (ERSAREQ and ERSSUSP) have write
317 * restrictions. SWAP, PFLSH, RAMRDY, and EEERDY are read-only status bits. The unassigned
318 * bits read as noted and are not writable. The reset values for the SWAP, PFLSH,
319 * RAMRDY, and EEERDY bits are determined during the reset sequence.
321 typedef union _hw_ftfe_fcnfg
324 struct _hw_ftfe_fcnfg_bitfields
326 uint8_t EEERDY
: 1; /*!< [0] */
327 uint8_t RAMRDY
: 1; /*!< [1] RAM Ready */
328 uint8_t PFLSH
: 1; /*!< [2] FTFE configuration */
329 uint8_t SWAP
: 1; /*!< [3] Swap */
330 uint8_t ERSSUSP
: 1; /*!< [4] Erase Suspend */
331 uint8_t ERSAREQ
: 1; /*!< [5] Erase All Request */
332 uint8_t RDCOLLIE
: 1; /*!< [6] Read Collision Error Interrupt Enable
334 uint8_t CCIE
: 1; /*!< [7] Command Complete Interrupt Enable */
339 * @name Constants and macros for entire FTFE_FCNFG register
342 #define HW_FTFE_FCNFG_ADDR(x) ((x) + 0x1U)
344 #define HW_FTFE_FCNFG(x) (*(__IO hw_ftfe_fcnfg_t *) HW_FTFE_FCNFG_ADDR(x))
345 #define HW_FTFE_FCNFG_RD(x) (HW_FTFE_FCNFG(x).U)
346 #define HW_FTFE_FCNFG_WR(x, v) (HW_FTFE_FCNFG(x).U = (v))
347 #define HW_FTFE_FCNFG_SET(x, v) (HW_FTFE_FCNFG_WR(x, HW_FTFE_FCNFG_RD(x) | (v)))
348 #define HW_FTFE_FCNFG_CLR(x, v) (HW_FTFE_FCNFG_WR(x, HW_FTFE_FCNFG_RD(x) & ~(v)))
349 #define HW_FTFE_FCNFG_TOG(x, v) (HW_FTFE_FCNFG_WR(x, HW_FTFE_FCNFG_RD(x) ^ (v)))
353 * Constants & macros for individual FTFE_FCNFG bitfields
357 * @name Register FTFE_FCNFG, field EEERDY[0] (RO)
359 * For devices with FlexNVM: This flag indicates if the EEPROM backup data has
360 * been copied to the FlexRAM and is therefore available for read access. During
361 * the reset sequence, the EEERDY flag remains clear while CCIF=0 and only sets if
362 * the FlexNVM block is partitioned for EEPROM. For devices without FlexNVM:
363 * This bit is reserved.
366 * - 0 - For devices with FlexNVM: FlexRAM is not available for EEPROM operation.
367 * - 1 - For devices with FlexNVM: FlexRAM is available for EEPROM operations
368 * where: reads from the FlexRAM return data previously written to the FlexRAM
369 * in EEPROM mode and writes launch an EEPROM operation to store the written
370 * data in the FlexRAM and EEPROM backup.
373 #define BP_FTFE_FCNFG_EEERDY (0U) /*!< Bit position for FTFE_FCNFG_EEERDY. */
374 #define BM_FTFE_FCNFG_EEERDY (0x01U) /*!< Bit mask for FTFE_FCNFG_EEERDY. */
375 #define BS_FTFE_FCNFG_EEERDY (1U) /*!< Bit field size in bits for FTFE_FCNFG_EEERDY. */
377 /*! @brief Read current value of the FTFE_FCNFG_EEERDY field. */
378 #define BR_FTFE_FCNFG_EEERDY(x) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_EEERDY))
382 * @name Register FTFE_FCNFG, field RAMRDY[1] (RO)
384 * This flag indicates the current status of the FlexRAM/ programming
385 * acceleration RAM. For devices with FlexNVM: The state of the RAMRDY flag is normally
386 * controlled by the Set FlexRAM Function command. During the reset sequence, the
387 * RAMRDY flag is cleared if the FlexNVM block is partitioned for EEPROM and will
388 * be set if the FlexNVM block is not partitioned for EEPROM . The RAMRDY flag is
389 * cleared if the Program Partition command is run to partition the FlexNVM block
390 * for EEPROM. The RAMRDY flag sets after completion of the Erase All Blocks
391 * command or execution of the erase-all operation triggered external to the FTFE.
392 * For devices without FlexNVM: This bit should always be set.
395 * - 0 - For devices with FlexNVM: FlexRAM is not available for traditional RAM
396 * access. For devices without FlexNVM: Programming acceleration RAM is not
398 * - 1 - For devices with FlexNVM: FlexRAM is available as traditional RAM only;
399 * writes to the FlexRAM do not trigger EEPROM operations. For devices
400 * without FlexNVM: Programming acceleration RAM is available.
403 #define BP_FTFE_FCNFG_RAMRDY (1U) /*!< Bit position for FTFE_FCNFG_RAMRDY. */
404 #define BM_FTFE_FCNFG_RAMRDY (0x02U) /*!< Bit mask for FTFE_FCNFG_RAMRDY. */
405 #define BS_FTFE_FCNFG_RAMRDY (1U) /*!< Bit field size in bits for FTFE_FCNFG_RAMRDY. */
407 /*! @brief Read current value of the FTFE_FCNFG_RAMRDY field. */
408 #define BR_FTFE_FCNFG_RAMRDY(x) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_RAMRDY))
412 * @name Register FTFE_FCNFG, field PFLSH[2] (RO)
415 * - 0 - For devices with FlexNVM: FTFE configuration supports two program flash
416 * blocks and two FlexNVM blocks For devices with program flash only:
418 * - 1 - For devices with FlexNVM: Reserved For devices with program flash only:
419 * FTFE configuration supports four program flash blocks
422 #define BP_FTFE_FCNFG_PFLSH (2U) /*!< Bit position for FTFE_FCNFG_PFLSH. */
423 #define BM_FTFE_FCNFG_PFLSH (0x04U) /*!< Bit mask for FTFE_FCNFG_PFLSH. */
424 #define BS_FTFE_FCNFG_PFLSH (1U) /*!< Bit field size in bits for FTFE_FCNFG_PFLSH. */
426 /*! @brief Read current value of the FTFE_FCNFG_PFLSH field. */
427 #define BR_FTFE_FCNFG_PFLSH(x) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_PFLSH))
431 * @name Register FTFE_FCNFG, field SWAP[3] (RO)
433 * The SWAP flag indicates which half of the program flash space is located at
434 * relative address 0x0000. The state of the SWAP flag is set by the FTFE during
435 * the reset sequence. See for information on swap management.
438 * - 0 - For devices with FlexNVM: Program flash 0 block is located at relative
439 * address 0x0000 For devices with program flash only: Program flash 0 block
440 * is located at relative address 0x0000
441 * - 1 - For devices with FlexNVM: Reserved For devices with program flash only:
442 * Program flash 1 block is located at relative address 0x0000
445 #define BP_FTFE_FCNFG_SWAP (3U) /*!< Bit position for FTFE_FCNFG_SWAP. */
446 #define BM_FTFE_FCNFG_SWAP (0x08U) /*!< Bit mask for FTFE_FCNFG_SWAP. */
447 #define BS_FTFE_FCNFG_SWAP (1U) /*!< Bit field size in bits for FTFE_FCNFG_SWAP. */
449 /*! @brief Read current value of the FTFE_FCNFG_SWAP field. */
450 #define BR_FTFE_FCNFG_SWAP(x) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_SWAP))
454 * @name Register FTFE_FCNFG, field ERSSUSP[4] (RW)
456 * The ERSSUSP bit allows the user to suspend (interrupt) the Erase Flash Sector
457 * command while it is executing.
460 * - 0 - No suspend requested
461 * - 1 - Suspend the current Erase Flash Sector command execution.
464 #define BP_FTFE_FCNFG_ERSSUSP (4U) /*!< Bit position for FTFE_FCNFG_ERSSUSP. */
465 #define BM_FTFE_FCNFG_ERSSUSP (0x10U) /*!< Bit mask for FTFE_FCNFG_ERSSUSP. */
466 #define BS_FTFE_FCNFG_ERSSUSP (1U) /*!< Bit field size in bits for FTFE_FCNFG_ERSSUSP. */
468 /*! @brief Read current value of the FTFE_FCNFG_ERSSUSP field. */
469 #define BR_FTFE_FCNFG_ERSSUSP(x) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_ERSSUSP))
471 /*! @brief Format value for bitfield FTFE_FCNFG_ERSSUSP. */
472 #define BF_FTFE_FCNFG_ERSSUSP(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCNFG_ERSSUSP) & BM_FTFE_FCNFG_ERSSUSP)
474 /*! @brief Set the ERSSUSP field to a new value. */
475 #define BW_FTFE_FCNFG_ERSSUSP(x, v) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_ERSSUSP) = (v))
479 * @name Register FTFE_FCNFG, field ERSAREQ[5] (RO)
481 * This bit issues a request to the memory controller to execute the Erase All
482 * Blocks command and release security. ERSAREQ is not directly writable but is
483 * under indirect user control. Refer to the device's Chip Configuration details on
484 * how to request this command. The ERSAREQ bit sets when an erase all request
485 * is triggered external to the FTFE and CCIF is set (no command is currently
486 * being executed). ERSAREQ is cleared by the FTFE when the operation completes.
489 * - 0 - No request or request complete
490 * - 1 - Request to: run the Erase All Blocks command, verify the erased state,
491 * program the security byte in the Flash Configuration Field to the unsecure
492 * state, and release MCU security by setting the FSEC[SEC] field to the
496 #define BP_FTFE_FCNFG_ERSAREQ (5U) /*!< Bit position for FTFE_FCNFG_ERSAREQ. */
497 #define BM_FTFE_FCNFG_ERSAREQ (0x20U) /*!< Bit mask for FTFE_FCNFG_ERSAREQ. */
498 #define BS_FTFE_FCNFG_ERSAREQ (1U) /*!< Bit field size in bits for FTFE_FCNFG_ERSAREQ. */
500 /*! @brief Read current value of the FTFE_FCNFG_ERSAREQ field. */
501 #define BR_FTFE_FCNFG_ERSAREQ(x) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_ERSAREQ))
505 * @name Register FTFE_FCNFG, field RDCOLLIE[6] (RW)
507 * The RDCOLLIE bit controls interrupt generation when an FTFE read collision
511 * - 0 - Read collision error interrupt disabled
512 * - 1 - Read collision error interrupt enabled. An interrupt request is
513 * generated whenever an FTFE read collision error is detected (see the description
514 * of FSTAT[RDCOLERR]).
517 #define BP_FTFE_FCNFG_RDCOLLIE (6U) /*!< Bit position for FTFE_FCNFG_RDCOLLIE. */
518 #define BM_FTFE_FCNFG_RDCOLLIE (0x40U) /*!< Bit mask for FTFE_FCNFG_RDCOLLIE. */
519 #define BS_FTFE_FCNFG_RDCOLLIE (1U) /*!< Bit field size in bits for FTFE_FCNFG_RDCOLLIE. */
521 /*! @brief Read current value of the FTFE_FCNFG_RDCOLLIE field. */
522 #define BR_FTFE_FCNFG_RDCOLLIE(x) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_RDCOLLIE))
524 /*! @brief Format value for bitfield FTFE_FCNFG_RDCOLLIE. */
525 #define BF_FTFE_FCNFG_RDCOLLIE(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCNFG_RDCOLLIE) & BM_FTFE_FCNFG_RDCOLLIE)
527 /*! @brief Set the RDCOLLIE field to a new value. */
528 #define BW_FTFE_FCNFG_RDCOLLIE(x, v) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_RDCOLLIE) = (v))
532 * @name Register FTFE_FCNFG, field CCIE[7] (RW)
534 * The CCIE bit controls interrupt generation when an FTFE command completes.
537 * - 0 - Command complete interrupt disabled
538 * - 1 - Command complete interrupt enabled. An interrupt request is generated
539 * whenever the FSTAT[CCIF] flag is set.
542 #define BP_FTFE_FCNFG_CCIE (7U) /*!< Bit position for FTFE_FCNFG_CCIE. */
543 #define BM_FTFE_FCNFG_CCIE (0x80U) /*!< Bit mask for FTFE_FCNFG_CCIE. */
544 #define BS_FTFE_FCNFG_CCIE (1U) /*!< Bit field size in bits for FTFE_FCNFG_CCIE. */
546 /*! @brief Read current value of the FTFE_FCNFG_CCIE field. */
547 #define BR_FTFE_FCNFG_CCIE(x) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_CCIE))
549 /*! @brief Format value for bitfield FTFE_FCNFG_CCIE. */
550 #define BF_FTFE_FCNFG_CCIE(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCNFG_CCIE) & BM_FTFE_FCNFG_CCIE)
552 /*! @brief Set the CCIE field to a new value. */
553 #define BW_FTFE_FCNFG_CCIE(x, v) (BITBAND_ACCESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_CCIE) = (v))
556 /*******************************************************************************
557 * HW_FTFE_FSEC - Flash Security Register
558 ******************************************************************************/
561 * @brief HW_FTFE_FSEC - Flash Security Register (RO)
565 * This read-only register holds all bits associated with the security of the
566 * MCU and FTFE module. During the reset sequence, the register is loaded with the
567 * contents of the flash security byte in the Flash Configuration Field located
568 * in program flash memory. The Flash basis for the values is signified by X in
571 typedef union _hw_ftfe_fsec
574 struct _hw_ftfe_fsec_bitfields
576 uint8_t SEC
: 2; /*!< [1:0] Flash Security */
577 uint8_t FSLACC
: 2; /*!< [3:2] Freescale Failure Analysis Access Code
579 uint8_t MEEN
: 2; /*!< [5:4] Mass Erase Enable Bits */
580 uint8_t KEYEN
: 2; /*!< [7:6] Backdoor Key Security Enable */
585 * @name Constants and macros for entire FTFE_FSEC register
588 #define HW_FTFE_FSEC_ADDR(x) ((x) + 0x2U)
590 #define HW_FTFE_FSEC(x) (*(__I hw_ftfe_fsec_t *) HW_FTFE_FSEC_ADDR(x))
591 #define HW_FTFE_FSEC_RD(x) (HW_FTFE_FSEC(x).U)
595 * Constants & macros for individual FTFE_FSEC bitfields
599 * @name Register FTFE_FSEC, field SEC[1:0] (RO)
601 * These bits define the security state of the MCU. In the secure state, the MCU
602 * limits access to FTFE module resources. The limitations are defined per
603 * device and are detailed in the Chip Configuration details. If the FTFE module is
604 * unsecured using backdoor key access, the SEC bits are forced to 10b.
607 * - 00 - MCU security status is secure
608 * - 01 - MCU security status is secure
609 * - 10 - MCU security status is unsecure (The standard shipping condition of
610 * the FTFE is unsecure.)
611 * - 11 - MCU security status is secure
614 #define BP_FTFE_FSEC_SEC (0U) /*!< Bit position for FTFE_FSEC_SEC. */
615 #define BM_FTFE_FSEC_SEC (0x03U) /*!< Bit mask for FTFE_FSEC_SEC. */
616 #define BS_FTFE_FSEC_SEC (2U) /*!< Bit field size in bits for FTFE_FSEC_SEC. */
618 /*! @brief Read current value of the FTFE_FSEC_SEC field. */
619 #define BR_FTFE_FSEC_SEC(x) (HW_FTFE_FSEC(x).B.SEC)
623 * @name Register FTFE_FSEC, field FSLACC[3:2] (RO)
625 * These bits enable or disable access to the flash memory contents during
626 * returned part failure analysis at Freescale. When SEC is secure and FSLACC is
627 * denied, access to the program flash contents is denied and any failure analysis
628 * performed by Freescale factory test must begin with a full erase to unsecure the
629 * part. When access is granted (SEC is unsecure, or SEC is secure and FSLACC is
630 * granted), Freescale factory testing has visibility of the current flash
631 * contents. The state of the FSLACC bits is only relevant when the SEC bits are set to
632 * secure. When the SEC field is set to unsecure, the FSLACC setting does not
636 * - 00 - Freescale factory access granted
637 * - 01 - Freescale factory access denied
638 * - 10 - Freescale factory access denied
639 * - 11 - Freescale factory access granted
642 #define BP_FTFE_FSEC_FSLACC (2U) /*!< Bit position for FTFE_FSEC_FSLACC. */
643 #define BM_FTFE_FSEC_FSLACC (0x0CU) /*!< Bit mask for FTFE_FSEC_FSLACC. */
644 #define BS_FTFE_FSEC_FSLACC (2U) /*!< Bit field size in bits for FTFE_FSEC_FSLACC. */
646 /*! @brief Read current value of the FTFE_FSEC_FSLACC field. */
647 #define BR_FTFE_FSEC_FSLACC(x) (HW_FTFE_FSEC(x).B.FSLACC)
651 * @name Register FTFE_FSEC, field MEEN[5:4] (RO)
653 * Enables and disables mass erase capability of the FTFE module. The state of
654 * the MEEN bits is only relevant when the SEC bits are set to secure outside of
655 * NVM Normal Mode. When the SEC field is set to unsecure, the MEEN setting does
659 * - 00 - Mass erase is enabled
660 * - 01 - Mass erase is enabled
661 * - 10 - Mass erase is disabled
662 * - 11 - Mass erase is enabled
665 #define BP_FTFE_FSEC_MEEN (4U) /*!< Bit position for FTFE_FSEC_MEEN. */
666 #define BM_FTFE_FSEC_MEEN (0x30U) /*!< Bit mask for FTFE_FSEC_MEEN. */
667 #define BS_FTFE_FSEC_MEEN (2U) /*!< Bit field size in bits for FTFE_FSEC_MEEN. */
669 /*! @brief Read current value of the FTFE_FSEC_MEEN field. */
670 #define BR_FTFE_FSEC_MEEN(x) (HW_FTFE_FSEC(x).B.MEEN)
674 * @name Register FTFE_FSEC, field KEYEN[7:6] (RO)
676 * These bits enable and disable backdoor key access to the FTFE module.
679 * - 00 - Backdoor key access disabled
680 * - 01 - Backdoor key access disabled (preferred KEYEN state to disable
681 * backdoor key access)
682 * - 10 - Backdoor key access enabled
683 * - 11 - Backdoor key access disabled
686 #define BP_FTFE_FSEC_KEYEN (6U) /*!< Bit position for FTFE_FSEC_KEYEN. */
687 #define BM_FTFE_FSEC_KEYEN (0xC0U) /*!< Bit mask for FTFE_FSEC_KEYEN. */
688 #define BS_FTFE_FSEC_KEYEN (2U) /*!< Bit field size in bits for FTFE_FSEC_KEYEN. */
690 /*! @brief Read current value of the FTFE_FSEC_KEYEN field. */
691 #define BR_FTFE_FSEC_KEYEN(x) (HW_FTFE_FSEC(x).B.KEYEN)
694 /*******************************************************************************
695 * HW_FTFE_FOPT - Flash Option Register
696 ******************************************************************************/
699 * @brief HW_FTFE_FOPT - Flash Option Register (RO)
703 * The flash option register allows the MCU to customize its operations by
704 * examining the state of these read-only bits, which are loaded from NVM at reset.
705 * The function of the bits is defined in the device's Chip Configuration details.
706 * All bits in the register are read-only. During the reset sequence, the
707 * register is loaded from the flash nonvolatile option byte in the Flash Configuration
708 * Field located in program flash memory. The flash basis for the values is
709 * signified by X in the reset value.
711 typedef union _hw_ftfe_fopt
714 struct _hw_ftfe_fopt_bitfields
716 uint8_t OPT
: 8; /*!< [7:0] Nonvolatile Option */
721 * @name Constants and macros for entire FTFE_FOPT register
724 #define HW_FTFE_FOPT_ADDR(x) ((x) + 0x3U)
726 #define HW_FTFE_FOPT(x) (*(__I hw_ftfe_fopt_t *) HW_FTFE_FOPT_ADDR(x))
727 #define HW_FTFE_FOPT_RD(x) (HW_FTFE_FOPT(x).U)
731 * Constants & macros for individual FTFE_FOPT bitfields
735 * @name Register FTFE_FOPT, field OPT[7:0] (RO)
737 * These bits are loaded from flash to this register at reset. Refer to the
738 * device's Chip Configuration details for the definition and use of these bits.
741 #define BP_FTFE_FOPT_OPT (0U) /*!< Bit position for FTFE_FOPT_OPT. */
742 #define BM_FTFE_FOPT_OPT (0xFFU) /*!< Bit mask for FTFE_FOPT_OPT. */
743 #define BS_FTFE_FOPT_OPT (8U) /*!< Bit field size in bits for FTFE_FOPT_OPT. */
745 /*! @brief Read current value of the FTFE_FOPT_OPT field. */
746 #define BR_FTFE_FOPT_OPT(x) (HW_FTFE_FOPT(x).U)
749 /*******************************************************************************
750 * HW_FTFE_FCCOB3 - Flash Common Command Object Registers
751 ******************************************************************************/
754 * @brief HW_FTFE_FCCOB3 - Flash Common Command Object Registers (RW)
758 * The FCCOB register group provides 12 bytes for command codes and parameters.
759 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
760 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
762 typedef union _hw_ftfe_fccob3
765 struct _hw_ftfe_fccob3_bitfields
767 uint8_t CCOBn
: 8; /*!< [7:0] */
772 * @name Constants and macros for entire FTFE_FCCOB3 register
775 #define HW_FTFE_FCCOB3_ADDR(x) ((x) + 0x4U)
777 #define HW_FTFE_FCCOB3(x) (*(__IO hw_ftfe_fccob3_t *) HW_FTFE_FCCOB3_ADDR(x))
778 #define HW_FTFE_FCCOB3_RD(x) (HW_FTFE_FCCOB3(x).U)
779 #define HW_FTFE_FCCOB3_WR(x, v) (HW_FTFE_FCCOB3(x).U = (v))
780 #define HW_FTFE_FCCOB3_SET(x, v) (HW_FTFE_FCCOB3_WR(x, HW_FTFE_FCCOB3_RD(x) | (v)))
781 #define HW_FTFE_FCCOB3_CLR(x, v) (HW_FTFE_FCCOB3_WR(x, HW_FTFE_FCCOB3_RD(x) & ~(v)))
782 #define HW_FTFE_FCCOB3_TOG(x, v) (HW_FTFE_FCCOB3_WR(x, HW_FTFE_FCCOB3_RD(x) ^ (v)))
786 * Constants & macros for individual FTFE_FCCOB3 bitfields
790 * @name Register FTFE_FCCOB3, field CCOBn[7:0] (RW)
792 * The FCCOB register provides a command code and relevant parameters to the
793 * memory controller. The individual registers that compose the FCCOB data set can
794 * be written in any order, but you must provide all needed values, which vary
795 * from command to command. First, set up all required FCCOB fields and then
796 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
797 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
798 * by the user until the command completes (CCIF returns to 1). No command
799 * buffering or queueing is provided; the next command can be loaded only after the
800 * current command completes. Some commands return information to the FCCOB
801 * registers. Any values returned to FCCOB are available for reading after the
802 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
803 * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
804 * the command code. This 8-bit value defines the command to be executed. The
805 * command code is followed by the parameters required for this specific FTFE command,
806 * typically an address and/or data values. The command parameter table is
807 * written in terms of FCCOB Number (which is equivalent to the byte number). This
808 * number is a reference to the FCCOB register name and is not the register address.
809 * FCCOB NumberRefers to FCCOB register name, not register address Typical
810 * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
811 * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
812 * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
813 * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
814 * register group uses a big endian addressing convention. For all command parameter
815 * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
816 * register number. The FCCOB register group may be read and written as
817 * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
820 #define BP_FTFE_FCCOB3_CCOBn (0U) /*!< Bit position for FTFE_FCCOB3_CCOBn. */
821 #define BM_FTFE_FCCOB3_CCOBn (0xFFU) /*!< Bit mask for FTFE_FCCOB3_CCOBn. */
822 #define BS_FTFE_FCCOB3_CCOBn (8U) /*!< Bit field size in bits for FTFE_FCCOB3_CCOBn. */
824 /*! @brief Read current value of the FTFE_FCCOB3_CCOBn field. */
825 #define BR_FTFE_FCCOB3_CCOBn(x) (HW_FTFE_FCCOB3(x).U)
827 /*! @brief Format value for bitfield FTFE_FCCOB3_CCOBn. */
828 #define BF_FTFE_FCCOB3_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB3_CCOBn) & BM_FTFE_FCCOB3_CCOBn)
830 /*! @brief Set the CCOBn field to a new value. */
831 #define BW_FTFE_FCCOB3_CCOBn(x, v) (HW_FTFE_FCCOB3_WR(x, v))
834 /*******************************************************************************
835 * HW_FTFE_FCCOB2 - Flash Common Command Object Registers
836 ******************************************************************************/
839 * @brief HW_FTFE_FCCOB2 - Flash Common Command Object Registers (RW)
843 * The FCCOB register group provides 12 bytes for command codes and parameters.
844 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
845 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
847 typedef union _hw_ftfe_fccob2
850 struct _hw_ftfe_fccob2_bitfields
852 uint8_t CCOBn
: 8; /*!< [7:0] */
857 * @name Constants and macros for entire FTFE_FCCOB2 register
860 #define HW_FTFE_FCCOB2_ADDR(x) ((x) + 0x5U)
862 #define HW_FTFE_FCCOB2(x) (*(__IO hw_ftfe_fccob2_t *) HW_FTFE_FCCOB2_ADDR(x))
863 #define HW_FTFE_FCCOB2_RD(x) (HW_FTFE_FCCOB2(x).U)
864 #define HW_FTFE_FCCOB2_WR(x, v) (HW_FTFE_FCCOB2(x).U = (v))
865 #define HW_FTFE_FCCOB2_SET(x, v) (HW_FTFE_FCCOB2_WR(x, HW_FTFE_FCCOB2_RD(x) | (v)))
866 #define HW_FTFE_FCCOB2_CLR(x, v) (HW_FTFE_FCCOB2_WR(x, HW_FTFE_FCCOB2_RD(x) & ~(v)))
867 #define HW_FTFE_FCCOB2_TOG(x, v) (HW_FTFE_FCCOB2_WR(x, HW_FTFE_FCCOB2_RD(x) ^ (v)))
871 * Constants & macros for individual FTFE_FCCOB2 bitfields
875 * @name Register FTFE_FCCOB2, field CCOBn[7:0] (RW)
877 * The FCCOB register provides a command code and relevant parameters to the
878 * memory controller. The individual registers that compose the FCCOB data set can
879 * be written in any order, but you must provide all needed values, which vary
880 * from command to command. First, set up all required FCCOB fields and then
881 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
882 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
883 * by the user until the command completes (CCIF returns to 1). No command
884 * buffering or queueing is provided; the next command can be loaded only after the
885 * current command completes. Some commands return information to the FCCOB
886 * registers. Any values returned to FCCOB are available for reading after the
887 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
888 * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
889 * the command code. This 8-bit value defines the command to be executed. The
890 * command code is followed by the parameters required for this specific FTFE command,
891 * typically an address and/or data values. The command parameter table is
892 * written in terms of FCCOB Number (which is equivalent to the byte number). This
893 * number is a reference to the FCCOB register name and is not the register address.
894 * FCCOB NumberRefers to FCCOB register name, not register address Typical
895 * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
896 * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
897 * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
898 * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
899 * register group uses a big endian addressing convention. For all command parameter
900 * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
901 * register number. The FCCOB register group may be read and written as
902 * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
905 #define BP_FTFE_FCCOB2_CCOBn (0U) /*!< Bit position for FTFE_FCCOB2_CCOBn. */
906 #define BM_FTFE_FCCOB2_CCOBn (0xFFU) /*!< Bit mask for FTFE_FCCOB2_CCOBn. */
907 #define BS_FTFE_FCCOB2_CCOBn (8U) /*!< Bit field size in bits for FTFE_FCCOB2_CCOBn. */
909 /*! @brief Read current value of the FTFE_FCCOB2_CCOBn field. */
910 #define BR_FTFE_FCCOB2_CCOBn(x) (HW_FTFE_FCCOB2(x).U)
912 /*! @brief Format value for bitfield FTFE_FCCOB2_CCOBn. */
913 #define BF_FTFE_FCCOB2_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB2_CCOBn) & BM_FTFE_FCCOB2_CCOBn)
915 /*! @brief Set the CCOBn field to a new value. */
916 #define BW_FTFE_FCCOB2_CCOBn(x, v) (HW_FTFE_FCCOB2_WR(x, v))
919 /*******************************************************************************
920 * HW_FTFE_FCCOB1 - Flash Common Command Object Registers
921 ******************************************************************************/
924 * @brief HW_FTFE_FCCOB1 - Flash Common Command Object Registers (RW)
928 * The FCCOB register group provides 12 bytes for command codes and parameters.
929 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
930 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
932 typedef union _hw_ftfe_fccob1
935 struct _hw_ftfe_fccob1_bitfields
937 uint8_t CCOBn
: 8; /*!< [7:0] */
942 * @name Constants and macros for entire FTFE_FCCOB1 register
945 #define HW_FTFE_FCCOB1_ADDR(x) ((x) + 0x6U)
947 #define HW_FTFE_FCCOB1(x) (*(__IO hw_ftfe_fccob1_t *) HW_FTFE_FCCOB1_ADDR(x))
948 #define HW_FTFE_FCCOB1_RD(x) (HW_FTFE_FCCOB1(x).U)
949 #define HW_FTFE_FCCOB1_WR(x, v) (HW_FTFE_FCCOB1(x).U = (v))
950 #define HW_FTFE_FCCOB1_SET(x, v) (HW_FTFE_FCCOB1_WR(x, HW_FTFE_FCCOB1_RD(x) | (v)))
951 #define HW_FTFE_FCCOB1_CLR(x, v) (HW_FTFE_FCCOB1_WR(x, HW_FTFE_FCCOB1_RD(x) & ~(v)))
952 #define HW_FTFE_FCCOB1_TOG(x, v) (HW_FTFE_FCCOB1_WR(x, HW_FTFE_FCCOB1_RD(x) ^ (v)))
956 * Constants & macros for individual FTFE_FCCOB1 bitfields
960 * @name Register FTFE_FCCOB1, field CCOBn[7:0] (RW)
962 * The FCCOB register provides a command code and relevant parameters to the
963 * memory controller. The individual registers that compose the FCCOB data set can
964 * be written in any order, but you must provide all needed values, which vary
965 * from command to command. First, set up all required FCCOB fields and then
966 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
967 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
968 * by the user until the command completes (CCIF returns to 1). No command
969 * buffering or queueing is provided; the next command can be loaded only after the
970 * current command completes. Some commands return information to the FCCOB
971 * registers. Any values returned to FCCOB are available for reading after the
972 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
973 * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
974 * the command code. This 8-bit value defines the command to be executed. The
975 * command code is followed by the parameters required for this specific FTFE command,
976 * typically an address and/or data values. The command parameter table is
977 * written in terms of FCCOB Number (which is equivalent to the byte number). This
978 * number is a reference to the FCCOB register name and is not the register address.
979 * FCCOB NumberRefers to FCCOB register name, not register address Typical
980 * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
981 * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
982 * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
983 * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
984 * register group uses a big endian addressing convention. For all command parameter
985 * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
986 * register number. The FCCOB register group may be read and written as
987 * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
990 #define BP_FTFE_FCCOB1_CCOBn (0U) /*!< Bit position for FTFE_FCCOB1_CCOBn. */
991 #define BM_FTFE_FCCOB1_CCOBn (0xFFU) /*!< Bit mask for FTFE_FCCOB1_CCOBn. */
992 #define BS_FTFE_FCCOB1_CCOBn (8U) /*!< Bit field size in bits for FTFE_FCCOB1_CCOBn. */
994 /*! @brief Read current value of the FTFE_FCCOB1_CCOBn field. */
995 #define BR_FTFE_FCCOB1_CCOBn(x) (HW_FTFE_FCCOB1(x).U)
997 /*! @brief Format value for bitfield FTFE_FCCOB1_CCOBn. */
998 #define BF_FTFE_FCCOB1_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB1_CCOBn) & BM_FTFE_FCCOB1_CCOBn)
1000 /*! @brief Set the CCOBn field to a new value. */
1001 #define BW_FTFE_FCCOB1_CCOBn(x, v) (HW_FTFE_FCCOB1_WR(x, v))
1004 /*******************************************************************************
1005 * HW_FTFE_FCCOB0 - Flash Common Command Object Registers
1006 ******************************************************************************/
1009 * @brief HW_FTFE_FCCOB0 - Flash Common Command Object Registers (RW)
1011 * Reset value: 0x00U
1013 * The FCCOB register group provides 12 bytes for command codes and parameters.
1014 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
1015 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
1017 typedef union _hw_ftfe_fccob0
1020 struct _hw_ftfe_fccob0_bitfields
1022 uint8_t CCOBn
: 8; /*!< [7:0] */
1027 * @name Constants and macros for entire FTFE_FCCOB0 register
1030 #define HW_FTFE_FCCOB0_ADDR(x) ((x) + 0x7U)
1032 #define HW_FTFE_FCCOB0(x) (*(__IO hw_ftfe_fccob0_t *) HW_FTFE_FCCOB0_ADDR(x))
1033 #define HW_FTFE_FCCOB0_RD(x) (HW_FTFE_FCCOB0(x).U)
1034 #define HW_FTFE_FCCOB0_WR(x, v) (HW_FTFE_FCCOB0(x).U = (v))
1035 #define HW_FTFE_FCCOB0_SET(x, v) (HW_FTFE_FCCOB0_WR(x, HW_FTFE_FCCOB0_RD(x) | (v)))
1036 #define HW_FTFE_FCCOB0_CLR(x, v) (HW_FTFE_FCCOB0_WR(x, HW_FTFE_FCCOB0_RD(x) & ~(v)))
1037 #define HW_FTFE_FCCOB0_TOG(x, v) (HW_FTFE_FCCOB0_WR(x, HW_FTFE_FCCOB0_RD(x) ^ (v)))
1041 * Constants & macros for individual FTFE_FCCOB0 bitfields
1045 * @name Register FTFE_FCCOB0, field CCOBn[7:0] (RW)
1047 * The FCCOB register provides a command code and relevant parameters to the
1048 * memory controller. The individual registers that compose the FCCOB data set can
1049 * be written in any order, but you must provide all needed values, which vary
1050 * from command to command. First, set up all required FCCOB fields and then
1051 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
1052 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
1053 * by the user until the command completes (CCIF returns to 1). No command
1054 * buffering or queueing is provided; the next command can be loaded only after the
1055 * current command completes. Some commands return information to the FCCOB
1056 * registers. Any values returned to FCCOB are available for reading after the
1057 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
1058 * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
1059 * the command code. This 8-bit value defines the command to be executed. The
1060 * command code is followed by the parameters required for this specific FTFE command,
1061 * typically an address and/or data values. The command parameter table is
1062 * written in terms of FCCOB Number (which is equivalent to the byte number). This
1063 * number is a reference to the FCCOB register name and is not the register address.
1064 * FCCOB NumberRefers to FCCOB register name, not register address Typical
1065 * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
1066 * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
1067 * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
1068 * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
1069 * register group uses a big endian addressing convention. For all command parameter
1070 * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
1071 * register number. The FCCOB register group may be read and written as
1072 * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
1075 #define BP_FTFE_FCCOB0_CCOBn (0U) /*!< Bit position for FTFE_FCCOB0_CCOBn. */
1076 #define BM_FTFE_FCCOB0_CCOBn (0xFFU) /*!< Bit mask for FTFE_FCCOB0_CCOBn. */
1077 #define BS_FTFE_FCCOB0_CCOBn (8U) /*!< Bit field size in bits for FTFE_FCCOB0_CCOBn. */
1079 /*! @brief Read current value of the FTFE_FCCOB0_CCOBn field. */
1080 #define BR_FTFE_FCCOB0_CCOBn(x) (HW_FTFE_FCCOB0(x).U)
1082 /*! @brief Format value for bitfield FTFE_FCCOB0_CCOBn. */
1083 #define BF_FTFE_FCCOB0_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB0_CCOBn) & BM_FTFE_FCCOB0_CCOBn)
1085 /*! @brief Set the CCOBn field to a new value. */
1086 #define BW_FTFE_FCCOB0_CCOBn(x, v) (HW_FTFE_FCCOB0_WR(x, v))
1089 /*******************************************************************************
1090 * HW_FTFE_FCCOB7 - Flash Common Command Object Registers
1091 ******************************************************************************/
1094 * @brief HW_FTFE_FCCOB7 - Flash Common Command Object Registers (RW)
1096 * Reset value: 0x00U
1098 * The FCCOB register group provides 12 bytes for command codes and parameters.
1099 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
1100 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
1102 typedef union _hw_ftfe_fccob7
1105 struct _hw_ftfe_fccob7_bitfields
1107 uint8_t CCOBn
: 8; /*!< [7:0] */
1112 * @name Constants and macros for entire FTFE_FCCOB7 register
1115 #define HW_FTFE_FCCOB7_ADDR(x) ((x) + 0x8U)
1117 #define HW_FTFE_FCCOB7(x) (*(__IO hw_ftfe_fccob7_t *) HW_FTFE_FCCOB7_ADDR(x))
1118 #define HW_FTFE_FCCOB7_RD(x) (HW_FTFE_FCCOB7(x).U)
1119 #define HW_FTFE_FCCOB7_WR(x, v) (HW_FTFE_FCCOB7(x).U = (v))
1120 #define HW_FTFE_FCCOB7_SET(x, v) (HW_FTFE_FCCOB7_WR(x, HW_FTFE_FCCOB7_RD(x) | (v)))
1121 #define HW_FTFE_FCCOB7_CLR(x, v) (HW_FTFE_FCCOB7_WR(x, HW_FTFE_FCCOB7_RD(x) & ~(v)))
1122 #define HW_FTFE_FCCOB7_TOG(x, v) (HW_FTFE_FCCOB7_WR(x, HW_FTFE_FCCOB7_RD(x) ^ (v)))
1126 * Constants & macros for individual FTFE_FCCOB7 bitfields
1130 * @name Register FTFE_FCCOB7, field CCOBn[7:0] (RW)
1132 * The FCCOB register provides a command code and relevant parameters to the
1133 * memory controller. The individual registers that compose the FCCOB data set can
1134 * be written in any order, but you must provide all needed values, which vary
1135 * from command to command. First, set up all required FCCOB fields and then
1136 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
1137 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
1138 * by the user until the command completes (CCIF returns to 1). No command
1139 * buffering or queueing is provided; the next command can be loaded only after the
1140 * current command completes. Some commands return information to the FCCOB
1141 * registers. Any values returned to FCCOB are available for reading after the
1142 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
1143 * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
1144 * the command code. This 8-bit value defines the command to be executed. The
1145 * command code is followed by the parameters required for this specific FTFE command,
1146 * typically an address and/or data values. The command parameter table is
1147 * written in terms of FCCOB Number (which is equivalent to the byte number). This
1148 * number is a reference to the FCCOB register name and is not the register address.
1149 * FCCOB NumberRefers to FCCOB register name, not register address Typical
1150 * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
1151 * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
1152 * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
1153 * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
1154 * register group uses a big endian addressing convention. For all command parameter
1155 * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
1156 * register number. The FCCOB register group may be read and written as
1157 * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
1160 #define BP_FTFE_FCCOB7_CCOBn (0U) /*!< Bit position for FTFE_FCCOB7_CCOBn. */
1161 #define BM_FTFE_FCCOB7_CCOBn (0xFFU) /*!< Bit mask for FTFE_FCCOB7_CCOBn. */
1162 #define BS_FTFE_FCCOB7_CCOBn (8U) /*!< Bit field size in bits for FTFE_FCCOB7_CCOBn. */
1164 /*! @brief Read current value of the FTFE_FCCOB7_CCOBn field. */
1165 #define BR_FTFE_FCCOB7_CCOBn(x) (HW_FTFE_FCCOB7(x).U)
1167 /*! @brief Format value for bitfield FTFE_FCCOB7_CCOBn. */
1168 #define BF_FTFE_FCCOB7_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB7_CCOBn) & BM_FTFE_FCCOB7_CCOBn)
1170 /*! @brief Set the CCOBn field to a new value. */
1171 #define BW_FTFE_FCCOB7_CCOBn(x, v) (HW_FTFE_FCCOB7_WR(x, v))
1174 /*******************************************************************************
1175 * HW_FTFE_FCCOB6 - Flash Common Command Object Registers
1176 ******************************************************************************/
1179 * @brief HW_FTFE_FCCOB6 - Flash Common Command Object Registers (RW)
1181 * Reset value: 0x00U
1183 * The FCCOB register group provides 12 bytes for command codes and parameters.
1184 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
1185 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
1187 typedef union _hw_ftfe_fccob6
1190 struct _hw_ftfe_fccob6_bitfields
1192 uint8_t CCOBn
: 8; /*!< [7:0] */
1197 * @name Constants and macros for entire FTFE_FCCOB6 register
1200 #define HW_FTFE_FCCOB6_ADDR(x) ((x) + 0x9U)
1202 #define HW_FTFE_FCCOB6(x) (*(__IO hw_ftfe_fccob6_t *) HW_FTFE_FCCOB6_ADDR(x))
1203 #define HW_FTFE_FCCOB6_RD(x) (HW_FTFE_FCCOB6(x).U)
1204 #define HW_FTFE_FCCOB6_WR(x, v) (HW_FTFE_FCCOB6(x).U = (v))
1205 #define HW_FTFE_FCCOB6_SET(x, v) (HW_FTFE_FCCOB6_WR(x, HW_FTFE_FCCOB6_RD(x) | (v)))
1206 #define HW_FTFE_FCCOB6_CLR(x, v) (HW_FTFE_FCCOB6_WR(x, HW_FTFE_FCCOB6_RD(x) & ~(v)))
1207 #define HW_FTFE_FCCOB6_TOG(x, v) (HW_FTFE_FCCOB6_WR(x, HW_FTFE_FCCOB6_RD(x) ^ (v)))
1211 * Constants & macros for individual FTFE_FCCOB6 bitfields
1215 * @name Register FTFE_FCCOB6, field CCOBn[7:0] (RW)
1217 * The FCCOB register provides a command code and relevant parameters to the
1218 * memory controller. The individual registers that compose the FCCOB data set can
1219 * be written in any order, but you must provide all needed values, which vary
1220 * from command to command. First, set up all required FCCOB fields and then
1221 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
1222 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
1223 * by the user until the command completes (CCIF returns to 1). No command
1224 * buffering or queueing is provided; the next command can be loaded only after the
1225 * current command completes. Some commands return information to the FCCOB
1226 * registers. Any values returned to FCCOB are available for reading after the
1227 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
1228 * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
1229 * the command code. This 8-bit value defines the command to be executed. The
1230 * command code is followed by the parameters required for this specific FTFE command,
1231 * typically an address and/or data values. The command parameter table is
1232 * written in terms of FCCOB Number (which is equivalent to the byte number). This
1233 * number is a reference to the FCCOB register name and is not the register address.
1234 * FCCOB NumberRefers to FCCOB register name, not register address Typical
1235 * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
1236 * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
1237 * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
1238 * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
1239 * register group uses a big endian addressing convention. For all command parameter
1240 * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
1241 * register number. The FCCOB register group may be read and written as
1242 * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
1245 #define BP_FTFE_FCCOB6_CCOBn (0U) /*!< Bit position for FTFE_FCCOB6_CCOBn. */
1246 #define BM_FTFE_FCCOB6_CCOBn (0xFFU) /*!< Bit mask for FTFE_FCCOB6_CCOBn. */
1247 #define BS_FTFE_FCCOB6_CCOBn (8U) /*!< Bit field size in bits for FTFE_FCCOB6_CCOBn. */
1249 /*! @brief Read current value of the FTFE_FCCOB6_CCOBn field. */
1250 #define BR_FTFE_FCCOB6_CCOBn(x) (HW_FTFE_FCCOB6(x).U)
1252 /*! @brief Format value for bitfield FTFE_FCCOB6_CCOBn. */
1253 #define BF_FTFE_FCCOB6_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB6_CCOBn) & BM_FTFE_FCCOB6_CCOBn)
1255 /*! @brief Set the CCOBn field to a new value. */
1256 #define BW_FTFE_FCCOB6_CCOBn(x, v) (HW_FTFE_FCCOB6_WR(x, v))
1259 /*******************************************************************************
1260 * HW_FTFE_FCCOB5 - Flash Common Command Object Registers
1261 ******************************************************************************/
1264 * @brief HW_FTFE_FCCOB5 - Flash Common Command Object Registers (RW)
1266 * Reset value: 0x00U
1268 * The FCCOB register group provides 12 bytes for command codes and parameters.
1269 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
1270 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
1272 typedef union _hw_ftfe_fccob5
1275 struct _hw_ftfe_fccob5_bitfields
1277 uint8_t CCOBn
: 8; /*!< [7:0] */
1282 * @name Constants and macros for entire FTFE_FCCOB5 register
1285 #define HW_FTFE_FCCOB5_ADDR(x) ((x) + 0xAU)
1287 #define HW_FTFE_FCCOB5(x) (*(__IO hw_ftfe_fccob5_t *) HW_FTFE_FCCOB5_ADDR(x))
1288 #define HW_FTFE_FCCOB5_RD(x) (HW_FTFE_FCCOB5(x).U)
1289 #define HW_FTFE_FCCOB5_WR(x, v) (HW_FTFE_FCCOB5(x).U = (v))
1290 #define HW_FTFE_FCCOB5_SET(x, v) (HW_FTFE_FCCOB5_WR(x, HW_FTFE_FCCOB5_RD(x) | (v)))
1291 #define HW_FTFE_FCCOB5_CLR(x, v) (HW_FTFE_FCCOB5_WR(x, HW_FTFE_FCCOB5_RD(x) & ~(v)))
1292 #define HW_FTFE_FCCOB5_TOG(x, v) (HW_FTFE_FCCOB5_WR(x, HW_FTFE_FCCOB5_RD(x) ^ (v)))
1296 * Constants & macros for individual FTFE_FCCOB5 bitfields
1300 * @name Register FTFE_FCCOB5, field CCOBn[7:0] (RW)
1302 * The FCCOB register provides a command code and relevant parameters to the
1303 * memory controller. The individual registers that compose the FCCOB data set can
1304 * be written in any order, but you must provide all needed values, which vary
1305 * from command to command. First, set up all required FCCOB fields and then
1306 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
1307 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
1308 * by the user until the command completes (CCIF returns to 1). No command
1309 * buffering or queueing is provided; the next command can be loaded only after the
1310 * current command completes. Some commands return information to the FCCOB
1311 * registers. Any values returned to FCCOB are available for reading after the
1312 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
1313 * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
1314 * the command code. This 8-bit value defines the command to be executed. The
1315 * command code is followed by the parameters required for this specific FTFE command,
1316 * typically an address and/or data values. The command parameter table is
1317 * written in terms of FCCOB Number (which is equivalent to the byte number). This
1318 * number is a reference to the FCCOB register name and is not the register address.
1319 * FCCOB NumberRefers to FCCOB register name, not register address Typical
1320 * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
1321 * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
1322 * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
1323 * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
1324 * register group uses a big endian addressing convention. For all command parameter
1325 * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
1326 * register number. The FCCOB register group may be read and written as
1327 * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
1330 #define BP_FTFE_FCCOB5_CCOBn (0U) /*!< Bit position for FTFE_FCCOB5_CCOBn. */
1331 #define BM_FTFE_FCCOB5_CCOBn (0xFFU) /*!< Bit mask for FTFE_FCCOB5_CCOBn. */
1332 #define BS_FTFE_FCCOB5_CCOBn (8U) /*!< Bit field size in bits for FTFE_FCCOB5_CCOBn. */
1334 /*! @brief Read current value of the FTFE_FCCOB5_CCOBn field. */
1335 #define BR_FTFE_FCCOB5_CCOBn(x) (HW_FTFE_FCCOB5(x).U)
1337 /*! @brief Format value for bitfield FTFE_FCCOB5_CCOBn. */
1338 #define BF_FTFE_FCCOB5_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB5_CCOBn) & BM_FTFE_FCCOB5_CCOBn)
1340 /*! @brief Set the CCOBn field to a new value. */
1341 #define BW_FTFE_FCCOB5_CCOBn(x, v) (HW_FTFE_FCCOB5_WR(x, v))
1344 /*******************************************************************************
1345 * HW_FTFE_FCCOB4 - Flash Common Command Object Registers
1346 ******************************************************************************/
1349 * @brief HW_FTFE_FCCOB4 - Flash Common Command Object Registers (RW)
1351 * Reset value: 0x00U
1353 * The FCCOB register group provides 12 bytes for command codes and parameters.
1354 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
1355 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
1357 typedef union _hw_ftfe_fccob4
1360 struct _hw_ftfe_fccob4_bitfields
1362 uint8_t CCOBn
: 8; /*!< [7:0] */
1367 * @name Constants and macros for entire FTFE_FCCOB4 register
1370 #define HW_FTFE_FCCOB4_ADDR(x) ((x) + 0xBU)
1372 #define HW_FTFE_FCCOB4(x) (*(__IO hw_ftfe_fccob4_t *) HW_FTFE_FCCOB4_ADDR(x))
1373 #define HW_FTFE_FCCOB4_RD(x) (HW_FTFE_FCCOB4(x).U)
1374 #define HW_FTFE_FCCOB4_WR(x, v) (HW_FTFE_FCCOB4(x).U = (v))
1375 #define HW_FTFE_FCCOB4_SET(x, v) (HW_FTFE_FCCOB4_WR(x, HW_FTFE_FCCOB4_RD(x) | (v)))
1376 #define HW_FTFE_FCCOB4_CLR(x, v) (HW_FTFE_FCCOB4_WR(x, HW_FTFE_FCCOB4_RD(x) & ~(v)))
1377 #define HW_FTFE_FCCOB4_TOG(x, v) (HW_FTFE_FCCOB4_WR(x, HW_FTFE_FCCOB4_RD(x) ^ (v)))
1381 * Constants & macros for individual FTFE_FCCOB4 bitfields
1385 * @name Register FTFE_FCCOB4, field CCOBn[7:0] (RW)
1387 * The FCCOB register provides a command code and relevant parameters to the
1388 * memory controller. The individual registers that compose the FCCOB data set can
1389 * be written in any order, but you must provide all needed values, which vary
1390 * from command to command. First, set up all required FCCOB fields and then
1391 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
1392 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
1393 * by the user until the command completes (CCIF returns to 1). No command
1394 * buffering or queueing is provided; the next command can be loaded only after the
1395 * current command completes. Some commands return information to the FCCOB
1396 * registers. Any values returned to FCCOB are available for reading after the
1397 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
1398 * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
1399 * the command code. This 8-bit value defines the command to be executed. The
1400 * command code is followed by the parameters required for this specific FTFE command,
1401 * typically an address and/or data values. The command parameter table is
1402 * written in terms of FCCOB Number (which is equivalent to the byte number). This
1403 * number is a reference to the FCCOB register name and is not the register address.
1404 * FCCOB NumberRefers to FCCOB register name, not register address Typical
1405 * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
1406 * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
1407 * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
1408 * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
1409 * register group uses a big endian addressing convention. For all command parameter
1410 * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
1411 * register number. The FCCOB register group may be read and written as
1412 * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
1415 #define BP_FTFE_FCCOB4_CCOBn (0U) /*!< Bit position for FTFE_FCCOB4_CCOBn. */
1416 #define BM_FTFE_FCCOB4_CCOBn (0xFFU) /*!< Bit mask for FTFE_FCCOB4_CCOBn. */
1417 #define BS_FTFE_FCCOB4_CCOBn (8U) /*!< Bit field size in bits for FTFE_FCCOB4_CCOBn. */
1419 /*! @brief Read current value of the FTFE_FCCOB4_CCOBn field. */
1420 #define BR_FTFE_FCCOB4_CCOBn(x) (HW_FTFE_FCCOB4(x).U)
1422 /*! @brief Format value for bitfield FTFE_FCCOB4_CCOBn. */
1423 #define BF_FTFE_FCCOB4_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB4_CCOBn) & BM_FTFE_FCCOB4_CCOBn)
1425 /*! @brief Set the CCOBn field to a new value. */
1426 #define BW_FTFE_FCCOB4_CCOBn(x, v) (HW_FTFE_FCCOB4_WR(x, v))
1429 /*******************************************************************************
1430 * HW_FTFE_FCCOBB - Flash Common Command Object Registers
1431 ******************************************************************************/
1434 * @brief HW_FTFE_FCCOBB - Flash Common Command Object Registers (RW)
1436 * Reset value: 0x00U
1438 * The FCCOB register group provides 12 bytes for command codes and parameters.
1439 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
1440 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
1442 typedef union _hw_ftfe_fccobb
1445 struct _hw_ftfe_fccobb_bitfields
1447 uint8_t CCOBn
: 8; /*!< [7:0] */
1452 * @name Constants and macros for entire FTFE_FCCOBB register
1455 #define HW_FTFE_FCCOBB_ADDR(x) ((x) + 0xCU)
1457 #define HW_FTFE_FCCOBB(x) (*(__IO hw_ftfe_fccobb_t *) HW_FTFE_FCCOBB_ADDR(x))
1458 #define HW_FTFE_FCCOBB_RD(x) (HW_FTFE_FCCOBB(x).U)
1459 #define HW_FTFE_FCCOBB_WR(x, v) (HW_FTFE_FCCOBB(x).U = (v))
1460 #define HW_FTFE_FCCOBB_SET(x, v) (HW_FTFE_FCCOBB_WR(x, HW_FTFE_FCCOBB_RD(x) | (v)))
1461 #define HW_FTFE_FCCOBB_CLR(x, v) (HW_FTFE_FCCOBB_WR(x, HW_FTFE_FCCOBB_RD(x) & ~(v)))
1462 #define HW_FTFE_FCCOBB_TOG(x, v) (HW_FTFE_FCCOBB_WR(x, HW_FTFE_FCCOBB_RD(x) ^ (v)))
1466 * Constants & macros for individual FTFE_FCCOBB bitfields
1470 * @name Register FTFE_FCCOBB, field CCOBn[7:0] (RW)
1472 * The FCCOB register provides a command code and relevant parameters to the
1473 * memory controller. The individual registers that compose the FCCOB data set can
1474 * be written in any order, but you must provide all needed values, which vary
1475 * from command to command. First, set up all required FCCOB fields and then
1476 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
1477 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
1478 * by the user until the command completes (CCIF returns to 1). No command
1479 * buffering or queueing is provided; the next command can be loaded only after the
1480 * current command completes. Some commands return information to the FCCOB
1481 * registers. Any values returned to FCCOB are available for reading after the
1482 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
1483 * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
1484 * the command code. This 8-bit value defines the command to be executed. The
1485 * command code is followed by the parameters required for this specific FTFE command,
1486 * typically an address and/or data values. The command parameter table is
1487 * written in terms of FCCOB Number (which is equivalent to the byte number). This
1488 * number is a reference to the FCCOB register name and is not the register address.
1489 * FCCOB NumberRefers to FCCOB register name, not register address Typical
1490 * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
1491 * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
1492 * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
1493 * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
1494 * register group uses a big endian addressing convention. For all command parameter
1495 * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
1496 * register number. The FCCOB register group may be read and written as
1497 * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
1500 #define BP_FTFE_FCCOBB_CCOBn (0U) /*!< Bit position for FTFE_FCCOBB_CCOBn. */
1501 #define BM_FTFE_FCCOBB_CCOBn (0xFFU) /*!< Bit mask for FTFE_FCCOBB_CCOBn. */
1502 #define BS_FTFE_FCCOBB_CCOBn (8U) /*!< Bit field size in bits for FTFE_FCCOBB_CCOBn. */
1504 /*! @brief Read current value of the FTFE_FCCOBB_CCOBn field. */
1505 #define BR_FTFE_FCCOBB_CCOBn(x) (HW_FTFE_FCCOBB(x).U)
1507 /*! @brief Format value for bitfield FTFE_FCCOBB_CCOBn. */
1508 #define BF_FTFE_FCCOBB_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOBB_CCOBn) & BM_FTFE_FCCOBB_CCOBn)
1510 /*! @brief Set the CCOBn field to a new value. */
1511 #define BW_FTFE_FCCOBB_CCOBn(x, v) (HW_FTFE_FCCOBB_WR(x, v))
1514 /*******************************************************************************
1515 * HW_FTFE_FCCOBA - Flash Common Command Object Registers
1516 ******************************************************************************/
1519 * @brief HW_FTFE_FCCOBA - Flash Common Command Object Registers (RW)
1521 * Reset value: 0x00U
1523 * The FCCOB register group provides 12 bytes for command codes and parameters.
1524 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
1525 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
1527 typedef union _hw_ftfe_fccoba
1530 struct _hw_ftfe_fccoba_bitfields
1532 uint8_t CCOBn
: 8; /*!< [7:0] */
1537 * @name Constants and macros for entire FTFE_FCCOBA register
1540 #define HW_FTFE_FCCOBA_ADDR(x) ((x) + 0xDU)
1542 #define HW_FTFE_FCCOBA(x) (*(__IO hw_ftfe_fccoba_t *) HW_FTFE_FCCOBA_ADDR(x))
1543 #define HW_FTFE_FCCOBA_RD(x) (HW_FTFE_FCCOBA(x).U)
1544 #define HW_FTFE_FCCOBA_WR(x, v) (HW_FTFE_FCCOBA(x).U = (v))
1545 #define HW_FTFE_FCCOBA_SET(x, v) (HW_FTFE_FCCOBA_WR(x, HW_FTFE_FCCOBA_RD(x) | (v)))
1546 #define HW_FTFE_FCCOBA_CLR(x, v) (HW_FTFE_FCCOBA_WR(x, HW_FTFE_FCCOBA_RD(x) & ~(v)))
1547 #define HW_FTFE_FCCOBA_TOG(x, v) (HW_FTFE_FCCOBA_WR(x, HW_FTFE_FCCOBA_RD(x) ^ (v)))
1551 * Constants & macros for individual FTFE_FCCOBA bitfields
1555 * @name Register FTFE_FCCOBA, field CCOBn[7:0] (RW)
1557 * The FCCOB register provides a command code and relevant parameters to the
1558 * memory controller. The individual registers that compose the FCCOB data set can
1559 * be written in any order, but you must provide all needed values, which vary
1560 * from command to command. First, set up all required FCCOB fields and then
1561 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
1562 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
1563 * by the user until the command completes (CCIF returns to 1). No command
1564 * buffering or queueing is provided; the next command can be loaded only after the
1565 * current command completes. Some commands return information to the FCCOB
1566 * registers. Any values returned to FCCOB are available for reading after the
1567 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
1568 * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
1569 * the command code. This 8-bit value defines the command to be executed. The
1570 * command code is followed by the parameters required for this specific FTFE command,
1571 * typically an address and/or data values. The command parameter table is
1572 * written in terms of FCCOB Number (which is equivalent to the byte number). This
1573 * number is a reference to the FCCOB register name and is not the register address.
1574 * FCCOB NumberRefers to FCCOB register name, not register address Typical
1575 * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
1576 * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
1577 * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
1578 * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
1579 * register group uses a big endian addressing convention. For all command parameter
1580 * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
1581 * register number. The FCCOB register group may be read and written as
1582 * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
1585 #define BP_FTFE_FCCOBA_CCOBn (0U) /*!< Bit position for FTFE_FCCOBA_CCOBn. */
1586 #define BM_FTFE_FCCOBA_CCOBn (0xFFU) /*!< Bit mask for FTFE_FCCOBA_CCOBn. */
1587 #define BS_FTFE_FCCOBA_CCOBn (8U) /*!< Bit field size in bits for FTFE_FCCOBA_CCOBn. */
1589 /*! @brief Read current value of the FTFE_FCCOBA_CCOBn field. */
1590 #define BR_FTFE_FCCOBA_CCOBn(x) (HW_FTFE_FCCOBA(x).U)
1592 /*! @brief Format value for bitfield FTFE_FCCOBA_CCOBn. */
1593 #define BF_FTFE_FCCOBA_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOBA_CCOBn) & BM_FTFE_FCCOBA_CCOBn)
1595 /*! @brief Set the CCOBn field to a new value. */
1596 #define BW_FTFE_FCCOBA_CCOBn(x, v) (HW_FTFE_FCCOBA_WR(x, v))
1599 /*******************************************************************************
1600 * HW_FTFE_FCCOB9 - Flash Common Command Object Registers
1601 ******************************************************************************/
1604 * @brief HW_FTFE_FCCOB9 - Flash Common Command Object Registers (RW)
1606 * Reset value: 0x00U
1608 * The FCCOB register group provides 12 bytes for command codes and parameters.
1609 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
1610 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
1612 typedef union _hw_ftfe_fccob9
1615 struct _hw_ftfe_fccob9_bitfields
1617 uint8_t CCOBn
: 8; /*!< [7:0] */
1622 * @name Constants and macros for entire FTFE_FCCOB9 register
1625 #define HW_FTFE_FCCOB9_ADDR(x) ((x) + 0xEU)
1627 #define HW_FTFE_FCCOB9(x) (*(__IO hw_ftfe_fccob9_t *) HW_FTFE_FCCOB9_ADDR(x))
1628 #define HW_FTFE_FCCOB9_RD(x) (HW_FTFE_FCCOB9(x).U)
1629 #define HW_FTFE_FCCOB9_WR(x, v) (HW_FTFE_FCCOB9(x).U = (v))
1630 #define HW_FTFE_FCCOB9_SET(x, v) (HW_FTFE_FCCOB9_WR(x, HW_FTFE_FCCOB9_RD(x) | (v)))
1631 #define HW_FTFE_FCCOB9_CLR(x, v) (HW_FTFE_FCCOB9_WR(x, HW_FTFE_FCCOB9_RD(x) & ~(v)))
1632 #define HW_FTFE_FCCOB9_TOG(x, v) (HW_FTFE_FCCOB9_WR(x, HW_FTFE_FCCOB9_RD(x) ^ (v)))
1636 * Constants & macros for individual FTFE_FCCOB9 bitfields
1640 * @name Register FTFE_FCCOB9, field CCOBn[7:0] (RW)
1642 * The FCCOB register provides a command code and relevant parameters to the
1643 * memory controller. The individual registers that compose the FCCOB data set can
1644 * be written in any order, but you must provide all needed values, which vary
1645 * from command to command. First, set up all required FCCOB fields and then
1646 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
1647 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
1648 * by the user until the command completes (CCIF returns to 1). No command
1649 * buffering or queueing is provided; the next command can be loaded only after the
1650 * current command completes. Some commands return information to the FCCOB
1651 * registers. Any values returned to FCCOB are available for reading after the
1652 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
1653 * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
1654 * the command code. This 8-bit value defines the command to be executed. The
1655 * command code is followed by the parameters required for this specific FTFE command,
1656 * typically an address and/or data values. The command parameter table is
1657 * written in terms of FCCOB Number (which is equivalent to the byte number). This
1658 * number is a reference to the FCCOB register name and is not the register address.
1659 * FCCOB NumberRefers to FCCOB register name, not register address Typical
1660 * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
1661 * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
1662 * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
1663 * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
1664 * register group uses a big endian addressing convention. For all command parameter
1665 * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
1666 * register number. The FCCOB register group may be read and written as
1667 * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
1670 #define BP_FTFE_FCCOB9_CCOBn (0U) /*!< Bit position for FTFE_FCCOB9_CCOBn. */
1671 #define BM_FTFE_FCCOB9_CCOBn (0xFFU) /*!< Bit mask for FTFE_FCCOB9_CCOBn. */
1672 #define BS_FTFE_FCCOB9_CCOBn (8U) /*!< Bit field size in bits for FTFE_FCCOB9_CCOBn. */
1674 /*! @brief Read current value of the FTFE_FCCOB9_CCOBn field. */
1675 #define BR_FTFE_FCCOB9_CCOBn(x) (HW_FTFE_FCCOB9(x).U)
1677 /*! @brief Format value for bitfield FTFE_FCCOB9_CCOBn. */
1678 #define BF_FTFE_FCCOB9_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB9_CCOBn) & BM_FTFE_FCCOB9_CCOBn)
1680 /*! @brief Set the CCOBn field to a new value. */
1681 #define BW_FTFE_FCCOB9_CCOBn(x, v) (HW_FTFE_FCCOB9_WR(x, v))
1684 /*******************************************************************************
1685 * HW_FTFE_FCCOB8 - Flash Common Command Object Registers
1686 ******************************************************************************/
1689 * @brief HW_FTFE_FCCOB8 - Flash Common Command Object Registers (RW)
1691 * Reset value: 0x00U
1693 * The FCCOB register group provides 12 bytes for command codes and parameters.
1694 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
1695 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
1697 typedef union _hw_ftfe_fccob8
1700 struct _hw_ftfe_fccob8_bitfields
1702 uint8_t CCOBn
: 8; /*!< [7:0] */
1707 * @name Constants and macros for entire FTFE_FCCOB8 register
1710 #define HW_FTFE_FCCOB8_ADDR(x) ((x) + 0xFU)
1712 #define HW_FTFE_FCCOB8(x) (*(__IO hw_ftfe_fccob8_t *) HW_FTFE_FCCOB8_ADDR(x))
1713 #define HW_FTFE_FCCOB8_RD(x) (HW_FTFE_FCCOB8(x).U)
1714 #define HW_FTFE_FCCOB8_WR(x, v) (HW_FTFE_FCCOB8(x).U = (v))
1715 #define HW_FTFE_FCCOB8_SET(x, v) (HW_FTFE_FCCOB8_WR(x, HW_FTFE_FCCOB8_RD(x) | (v)))
1716 #define HW_FTFE_FCCOB8_CLR(x, v) (HW_FTFE_FCCOB8_WR(x, HW_FTFE_FCCOB8_RD(x) & ~(v)))
1717 #define HW_FTFE_FCCOB8_TOG(x, v) (HW_FTFE_FCCOB8_WR(x, HW_FTFE_FCCOB8_RD(x) ^ (v)))
1721 * Constants & macros for individual FTFE_FCCOB8 bitfields
1725 * @name Register FTFE_FCCOB8, field CCOBn[7:0] (RW)
1727 * The FCCOB register provides a command code and relevant parameters to the
1728 * memory controller. The individual registers that compose the FCCOB data set can
1729 * be written in any order, but you must provide all needed values, which vary
1730 * from command to command. First, set up all required FCCOB fields and then
1731 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
1732 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
1733 * by the user until the command completes (CCIF returns to 1). No command
1734 * buffering or queueing is provided; the next command can be loaded only after the
1735 * current command completes. Some commands return information to the FCCOB
1736 * registers. Any values returned to FCCOB are available for reading after the
1737 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
1738 * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
1739 * the command code. This 8-bit value defines the command to be executed. The
1740 * command code is followed by the parameters required for this specific FTFE command,
1741 * typically an address and/or data values. The command parameter table is
1742 * written in terms of FCCOB Number (which is equivalent to the byte number). This
1743 * number is a reference to the FCCOB register name and is not the register address.
1744 * FCCOB NumberRefers to FCCOB register name, not register address Typical
1745 * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
1746 * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
1747 * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
1748 * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
1749 * register group uses a big endian addressing convention. For all command parameter
1750 * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
1751 * register number. The FCCOB register group may be read and written as
1752 * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
1755 #define BP_FTFE_FCCOB8_CCOBn (0U) /*!< Bit position for FTFE_FCCOB8_CCOBn. */
1756 #define BM_FTFE_FCCOB8_CCOBn (0xFFU) /*!< Bit mask for FTFE_FCCOB8_CCOBn. */
1757 #define BS_FTFE_FCCOB8_CCOBn (8U) /*!< Bit field size in bits for FTFE_FCCOB8_CCOBn. */
1759 /*! @brief Read current value of the FTFE_FCCOB8_CCOBn field. */
1760 #define BR_FTFE_FCCOB8_CCOBn(x) (HW_FTFE_FCCOB8(x).U)
1762 /*! @brief Format value for bitfield FTFE_FCCOB8_CCOBn. */
1763 #define BF_FTFE_FCCOB8_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB8_CCOBn) & BM_FTFE_FCCOB8_CCOBn)
1765 /*! @brief Set the CCOBn field to a new value. */
1766 #define BW_FTFE_FCCOB8_CCOBn(x, v) (HW_FTFE_FCCOB8_WR(x, v))
1769 /*******************************************************************************
1770 * HW_FTFE_FPROT3 - Program Flash Protection Registers
1771 ******************************************************************************/
1774 * @brief HW_FTFE_FPROT3 - Program Flash Protection Registers (RW)
1776 * Reset value: 0x00U
1778 * The FPROT registers define which program flash regions are protected from
1779 * program and erase operations. Protected flash regions cannot have their content
1780 * changed; that is, these regions cannot be programmed and cannot be erased by
1781 * any FTFE command. Unprotected regions can be changed by program and erase
1782 * operations. The four FPROT registers allow up to 32 protectable regions of equal
1783 * memory size. Program flash protection register Program flash protection bits
1784 * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
1785 * the reset sequence, the FPROT registers are loaded with the contents of the
1786 * program flash protection bytes in the Flash Configuration Field as indicated in
1787 * the following table. Program flash protection register Flash Configuration Field
1788 * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
1789 * change the program flash protection that is loaded during the reset sequence,
1790 * unprotect the sector of program flash memory that contains the Flash
1791 * Configuration Field. Then, reprogram the program flash protection byte.
1793 typedef union _hw_ftfe_fprot3
1796 struct _hw_ftfe_fprot3_bitfields
1798 uint8_t PROT
: 8; /*!< [7:0] Program Flash Region Protect */
1803 * @name Constants and macros for entire FTFE_FPROT3 register
1806 #define HW_FTFE_FPROT3_ADDR(x) ((x) + 0x10U)
1808 #define HW_FTFE_FPROT3(x) (*(__IO hw_ftfe_fprot3_t *) HW_FTFE_FPROT3_ADDR(x))
1809 #define HW_FTFE_FPROT3_RD(x) (HW_FTFE_FPROT3(x).U)
1810 #define HW_FTFE_FPROT3_WR(x, v) (HW_FTFE_FPROT3(x).U = (v))
1811 #define HW_FTFE_FPROT3_SET(x, v) (HW_FTFE_FPROT3_WR(x, HW_FTFE_FPROT3_RD(x) | (v)))
1812 #define HW_FTFE_FPROT3_CLR(x, v) (HW_FTFE_FPROT3_WR(x, HW_FTFE_FPROT3_RD(x) & ~(v)))
1813 #define HW_FTFE_FPROT3_TOG(x, v) (HW_FTFE_FPROT3_WR(x, HW_FTFE_FPROT3_RD(x) ^ (v)))
1817 * Constants & macros for individual FTFE_FPROT3 bitfields
1821 * @name Register FTFE_FPROT3, field PROT[7:0] (RW)
1823 * Each program flash region can be protected from program and erase operations
1824 * by setting the associated PROT bit. In NVM Normal mode: The protection can
1825 * only be increased, meaning that currently unprotected memory can be protected,
1826 * but currently protected memory cannot be unprotected. Since unprotected regions
1827 * are marked with a 1 and protected regions use a 0, only writes changing 1s to
1828 * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit
1829 * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with
1830 * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are
1831 * writable without restriction. Unprotected areas can be protected and protected
1832 * areas can be unprotected. The user must never write to any FPROT register while
1833 * a command is running (CCIF=0). Trying to alter data in any protected area in
1834 * the program flash memory results in a protection violation error and sets the
1835 * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible
1836 * if it contains any protected region.
1839 * - 0 - Program flash region is protected.
1840 * - 1 - Program flash region is not protected
1843 #define BP_FTFE_FPROT3_PROT (0U) /*!< Bit position for FTFE_FPROT3_PROT. */
1844 #define BM_FTFE_FPROT3_PROT (0xFFU) /*!< Bit mask for FTFE_FPROT3_PROT. */
1845 #define BS_FTFE_FPROT3_PROT (8U) /*!< Bit field size in bits for FTFE_FPROT3_PROT. */
1847 /*! @brief Read current value of the FTFE_FPROT3_PROT field. */
1848 #define BR_FTFE_FPROT3_PROT(x) (HW_FTFE_FPROT3(x).U)
1850 /*! @brief Format value for bitfield FTFE_FPROT3_PROT. */
1851 #define BF_FTFE_FPROT3_PROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FPROT3_PROT) & BM_FTFE_FPROT3_PROT)
1853 /*! @brief Set the PROT field to a new value. */
1854 #define BW_FTFE_FPROT3_PROT(x, v) (HW_FTFE_FPROT3_WR(x, v))
1857 /*******************************************************************************
1858 * HW_FTFE_FPROT2 - Program Flash Protection Registers
1859 ******************************************************************************/
1862 * @brief HW_FTFE_FPROT2 - Program Flash Protection Registers (RW)
1864 * Reset value: 0x00U
1866 * The FPROT registers define which program flash regions are protected from
1867 * program and erase operations. Protected flash regions cannot have their content
1868 * changed; that is, these regions cannot be programmed and cannot be erased by
1869 * any FTFE command. Unprotected regions can be changed by program and erase
1870 * operations. The four FPROT registers allow up to 32 protectable regions of equal
1871 * memory size. Program flash protection register Program flash protection bits
1872 * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
1873 * the reset sequence, the FPROT registers are loaded with the contents of the
1874 * program flash protection bytes in the Flash Configuration Field as indicated in
1875 * the following table. Program flash protection register Flash Configuration Field
1876 * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
1877 * change the program flash protection that is loaded during the reset sequence,
1878 * unprotect the sector of program flash memory that contains the Flash
1879 * Configuration Field. Then, reprogram the program flash protection byte.
1881 typedef union _hw_ftfe_fprot2
1884 struct _hw_ftfe_fprot2_bitfields
1886 uint8_t PROT
: 8; /*!< [7:0] Program Flash Region Protect */
1891 * @name Constants and macros for entire FTFE_FPROT2 register
1894 #define HW_FTFE_FPROT2_ADDR(x) ((x) + 0x11U)
1896 #define HW_FTFE_FPROT2(x) (*(__IO hw_ftfe_fprot2_t *) HW_FTFE_FPROT2_ADDR(x))
1897 #define HW_FTFE_FPROT2_RD(x) (HW_FTFE_FPROT2(x).U)
1898 #define HW_FTFE_FPROT2_WR(x, v) (HW_FTFE_FPROT2(x).U = (v))
1899 #define HW_FTFE_FPROT2_SET(x, v) (HW_FTFE_FPROT2_WR(x, HW_FTFE_FPROT2_RD(x) | (v)))
1900 #define HW_FTFE_FPROT2_CLR(x, v) (HW_FTFE_FPROT2_WR(x, HW_FTFE_FPROT2_RD(x) & ~(v)))
1901 #define HW_FTFE_FPROT2_TOG(x, v) (HW_FTFE_FPROT2_WR(x, HW_FTFE_FPROT2_RD(x) ^ (v)))
1905 * Constants & macros for individual FTFE_FPROT2 bitfields
1909 * @name Register FTFE_FPROT2, field PROT[7:0] (RW)
1911 * Each program flash region can be protected from program and erase operations
1912 * by setting the associated PROT bit. In NVM Normal mode: The protection can
1913 * only be increased, meaning that currently unprotected memory can be protected,
1914 * but currently protected memory cannot be unprotected. Since unprotected regions
1915 * are marked with a 1 and protected regions use a 0, only writes changing 1s to
1916 * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit
1917 * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with
1918 * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are
1919 * writable without restriction. Unprotected areas can be protected and protected
1920 * areas can be unprotected. The user must never write to any FPROT register while
1921 * a command is running (CCIF=0). Trying to alter data in any protected area in
1922 * the program flash memory results in a protection violation error and sets the
1923 * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible
1924 * if it contains any protected region.
1927 * - 0 - Program flash region is protected.
1928 * - 1 - Program flash region is not protected
1931 #define BP_FTFE_FPROT2_PROT (0U) /*!< Bit position for FTFE_FPROT2_PROT. */
1932 #define BM_FTFE_FPROT2_PROT (0xFFU) /*!< Bit mask for FTFE_FPROT2_PROT. */
1933 #define BS_FTFE_FPROT2_PROT (8U) /*!< Bit field size in bits for FTFE_FPROT2_PROT. */
1935 /*! @brief Read current value of the FTFE_FPROT2_PROT field. */
1936 #define BR_FTFE_FPROT2_PROT(x) (HW_FTFE_FPROT2(x).U)
1938 /*! @brief Format value for bitfield FTFE_FPROT2_PROT. */
1939 #define BF_FTFE_FPROT2_PROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FPROT2_PROT) & BM_FTFE_FPROT2_PROT)
1941 /*! @brief Set the PROT field to a new value. */
1942 #define BW_FTFE_FPROT2_PROT(x, v) (HW_FTFE_FPROT2_WR(x, v))
1945 /*******************************************************************************
1946 * HW_FTFE_FPROT1 - Program Flash Protection Registers
1947 ******************************************************************************/
1950 * @brief HW_FTFE_FPROT1 - Program Flash Protection Registers (RW)
1952 * Reset value: 0x00U
1954 * The FPROT registers define which program flash regions are protected from
1955 * program and erase operations. Protected flash regions cannot have their content
1956 * changed; that is, these regions cannot be programmed and cannot be erased by
1957 * any FTFE command. Unprotected regions can be changed by program and erase
1958 * operations. The four FPROT registers allow up to 32 protectable regions of equal
1959 * memory size. Program flash protection register Program flash protection bits
1960 * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
1961 * the reset sequence, the FPROT registers are loaded with the contents of the
1962 * program flash protection bytes in the Flash Configuration Field as indicated in
1963 * the following table. Program flash protection register Flash Configuration Field
1964 * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
1965 * change the program flash protection that is loaded during the reset sequence,
1966 * unprotect the sector of program flash memory that contains the Flash
1967 * Configuration Field. Then, reprogram the program flash protection byte.
1969 typedef union _hw_ftfe_fprot1
1972 struct _hw_ftfe_fprot1_bitfields
1974 uint8_t PROT
: 8; /*!< [7:0] Program Flash Region Protect */
1979 * @name Constants and macros for entire FTFE_FPROT1 register
1982 #define HW_FTFE_FPROT1_ADDR(x) ((x) + 0x12U)
1984 #define HW_FTFE_FPROT1(x) (*(__IO hw_ftfe_fprot1_t *) HW_FTFE_FPROT1_ADDR(x))
1985 #define HW_FTFE_FPROT1_RD(x) (HW_FTFE_FPROT1(x).U)
1986 #define HW_FTFE_FPROT1_WR(x, v) (HW_FTFE_FPROT1(x).U = (v))
1987 #define HW_FTFE_FPROT1_SET(x, v) (HW_FTFE_FPROT1_WR(x, HW_FTFE_FPROT1_RD(x) | (v)))
1988 #define HW_FTFE_FPROT1_CLR(x, v) (HW_FTFE_FPROT1_WR(x, HW_FTFE_FPROT1_RD(x) & ~(v)))
1989 #define HW_FTFE_FPROT1_TOG(x, v) (HW_FTFE_FPROT1_WR(x, HW_FTFE_FPROT1_RD(x) ^ (v)))
1993 * Constants & macros for individual FTFE_FPROT1 bitfields
1997 * @name Register FTFE_FPROT1, field PROT[7:0] (RW)
1999 * Each program flash region can be protected from program and erase operations
2000 * by setting the associated PROT bit. In NVM Normal mode: The protection can
2001 * only be increased, meaning that currently unprotected memory can be protected,
2002 * but currently protected memory cannot be unprotected. Since unprotected regions
2003 * are marked with a 1 and protected regions use a 0, only writes changing 1s to
2004 * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit
2005 * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with
2006 * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are
2007 * writable without restriction. Unprotected areas can be protected and protected
2008 * areas can be unprotected. The user must never write to any FPROT register while
2009 * a command is running (CCIF=0). Trying to alter data in any protected area in
2010 * the program flash memory results in a protection violation error and sets the
2011 * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible
2012 * if it contains any protected region.
2015 * - 0 - Program flash region is protected.
2016 * - 1 - Program flash region is not protected
2019 #define BP_FTFE_FPROT1_PROT (0U) /*!< Bit position for FTFE_FPROT1_PROT. */
2020 #define BM_FTFE_FPROT1_PROT (0xFFU) /*!< Bit mask for FTFE_FPROT1_PROT. */
2021 #define BS_FTFE_FPROT1_PROT (8U) /*!< Bit field size in bits for FTFE_FPROT1_PROT. */
2023 /*! @brief Read current value of the FTFE_FPROT1_PROT field. */
2024 #define BR_FTFE_FPROT1_PROT(x) (HW_FTFE_FPROT1(x).U)
2026 /*! @brief Format value for bitfield FTFE_FPROT1_PROT. */
2027 #define BF_FTFE_FPROT1_PROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FPROT1_PROT) & BM_FTFE_FPROT1_PROT)
2029 /*! @brief Set the PROT field to a new value. */
2030 #define BW_FTFE_FPROT1_PROT(x, v) (HW_FTFE_FPROT1_WR(x, v))
2033 /*******************************************************************************
2034 * HW_FTFE_FPROT0 - Program Flash Protection Registers
2035 ******************************************************************************/
2038 * @brief HW_FTFE_FPROT0 - Program Flash Protection Registers (RW)
2040 * Reset value: 0x00U
2042 * The FPROT registers define which program flash regions are protected from
2043 * program and erase operations. Protected flash regions cannot have their content
2044 * changed; that is, these regions cannot be programmed and cannot be erased by
2045 * any FTFE command. Unprotected regions can be changed by program and erase
2046 * operations. The four FPROT registers allow up to 32 protectable regions of equal
2047 * memory size. Program flash protection register Program flash protection bits
2048 * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
2049 * the reset sequence, the FPROT registers are loaded with the contents of the
2050 * program flash protection bytes in the Flash Configuration Field as indicated in
2051 * the following table. Program flash protection register Flash Configuration Field
2052 * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
2053 * change the program flash protection that is loaded during the reset sequence,
2054 * unprotect the sector of program flash memory that contains the Flash
2055 * Configuration Field. Then, reprogram the program flash protection byte.
2057 typedef union _hw_ftfe_fprot0
2060 struct _hw_ftfe_fprot0_bitfields
2062 uint8_t PROT
: 8; /*!< [7:0] Program Flash Region Protect */
2067 * @name Constants and macros for entire FTFE_FPROT0 register
2070 #define HW_FTFE_FPROT0_ADDR(x) ((x) + 0x13U)
2072 #define HW_FTFE_FPROT0(x) (*(__IO hw_ftfe_fprot0_t *) HW_FTFE_FPROT0_ADDR(x))
2073 #define HW_FTFE_FPROT0_RD(x) (HW_FTFE_FPROT0(x).U)
2074 #define HW_FTFE_FPROT0_WR(x, v) (HW_FTFE_FPROT0(x).U = (v))
2075 #define HW_FTFE_FPROT0_SET(x, v) (HW_FTFE_FPROT0_WR(x, HW_FTFE_FPROT0_RD(x) | (v)))
2076 #define HW_FTFE_FPROT0_CLR(x, v) (HW_FTFE_FPROT0_WR(x, HW_FTFE_FPROT0_RD(x) & ~(v)))
2077 #define HW_FTFE_FPROT0_TOG(x, v) (HW_FTFE_FPROT0_WR(x, HW_FTFE_FPROT0_RD(x) ^ (v)))
2081 * Constants & macros for individual FTFE_FPROT0 bitfields
2085 * @name Register FTFE_FPROT0, field PROT[7:0] (RW)
2087 * Each program flash region can be protected from program and erase operations
2088 * by setting the associated PROT bit. In NVM Normal mode: The protection can
2089 * only be increased, meaning that currently unprotected memory can be protected,
2090 * but currently protected memory cannot be unprotected. Since unprotected regions
2091 * are marked with a 1 and protected regions use a 0, only writes changing 1s to
2092 * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit
2093 * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with
2094 * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are
2095 * writable without restriction. Unprotected areas can be protected and protected
2096 * areas can be unprotected. The user must never write to any FPROT register while
2097 * a command is running (CCIF=0). Trying to alter data in any protected area in
2098 * the program flash memory results in a protection violation error and sets the
2099 * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible
2100 * if it contains any protected region.
2103 * - 0 - Program flash region is protected.
2104 * - 1 - Program flash region is not protected
2107 #define BP_FTFE_FPROT0_PROT (0U) /*!< Bit position for FTFE_FPROT0_PROT. */
2108 #define BM_FTFE_FPROT0_PROT (0xFFU) /*!< Bit mask for FTFE_FPROT0_PROT. */
2109 #define BS_FTFE_FPROT0_PROT (8U) /*!< Bit field size in bits for FTFE_FPROT0_PROT. */
2111 /*! @brief Read current value of the FTFE_FPROT0_PROT field. */
2112 #define BR_FTFE_FPROT0_PROT(x) (HW_FTFE_FPROT0(x).U)
2114 /*! @brief Format value for bitfield FTFE_FPROT0_PROT. */
2115 #define BF_FTFE_FPROT0_PROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FPROT0_PROT) & BM_FTFE_FPROT0_PROT)
2117 /*! @brief Set the PROT field to a new value. */
2118 #define BW_FTFE_FPROT0_PROT(x, v) (HW_FTFE_FPROT0_WR(x, v))
2121 /*******************************************************************************
2122 * HW_FTFE_FEPROT - EEPROM Protection Register
2123 ******************************************************************************/
2126 * @brief HW_FTFE_FEPROT - EEPROM Protection Register (RW)
2128 * Reset value: 0x00U
2130 * For devices with FlexNVM: The FEPROT register defines which EEPROM regions of
2131 * the FlexRAM are protected against program and erase operations. Protected
2132 * EEPROM regions cannot have their content changed by writing to it. Unprotected
2133 * regions can be changed by writing to the FlexRAM. For devices with program flash
2134 * only: This register is reserved and not used.
2136 typedef union _hw_ftfe_feprot
2139 struct _hw_ftfe_feprot_bitfields
2141 uint8_t EPROT
: 8; /*!< [7:0] EEPROM Region Protect */
2146 * @name Constants and macros for entire FTFE_FEPROT register
2149 #define HW_FTFE_FEPROT_ADDR(x) ((x) + 0x16U)
2151 #define HW_FTFE_FEPROT(x) (*(__IO hw_ftfe_feprot_t *) HW_FTFE_FEPROT_ADDR(x))
2152 #define HW_FTFE_FEPROT_RD(x) (HW_FTFE_FEPROT(x).U)
2153 #define HW_FTFE_FEPROT_WR(x, v) (HW_FTFE_FEPROT(x).U = (v))
2154 #define HW_FTFE_FEPROT_SET(x, v) (HW_FTFE_FEPROT_WR(x, HW_FTFE_FEPROT_RD(x) | (v)))
2155 #define HW_FTFE_FEPROT_CLR(x, v) (HW_FTFE_FEPROT_WR(x, HW_FTFE_FEPROT_RD(x) & ~(v)))
2156 #define HW_FTFE_FEPROT_TOG(x, v) (HW_FTFE_FEPROT_WR(x, HW_FTFE_FEPROT_RD(x) ^ (v)))
2160 * Constants & macros for individual FTFE_FEPROT bitfields
2164 * @name Register FTFE_FEPROT, field EPROT[7:0] (RW)
2166 * For devices with program flash only: Reserved For devices with FlexNVM:
2167 * Individual EEPROM regions can be protected from alteration by setting the
2168 * associated EPROT bit. The EPROT bits are not used when the FlexNVM Partition Code is
2169 * set to data flash only. When the FlexNVM Partition Code is set to data flash and
2170 * EEPROM or EEPROM only, each EPROT bit covers one-eighth of the configured
2171 * EEPROM data (see the EEPROM Data Set Size parameter description). In NVM Normal
2172 * mode: The protection can only be increased. This means that
2173 * currently-unprotected memory can be protected, but currently-protected memory cannot be
2174 * unprotected. Since unprotected regions are marked with a 1 and protected regions use a
2175 * 0, only writes changing 1s to 0s are accepted. This 1-to-0 transition check is
2176 * performed on a bit-by-bit basis. Those FEPROT bits with 1-to-0 transitions
2177 * are accepted while all bits with 0-to-1 transitions are ignored. In NVM Special
2178 * mode: All bits of the FEPROT register are writable without restriction.
2179 * Unprotected areas can be protected and protected areas can be unprotected. Never
2180 * write to the FEPROT register while a command is running (CCIF=0). Reset: During
2181 * the reset sequence, the FEPROT register is loaded with the contents of the
2182 * FlexRAM protection byte in the Flash Configuration Field located in program flash.
2183 * The flash basis for the reset values is signified by X in the register
2184 * diagram. To change the EEPROM protection that will be loaded during the reset
2185 * sequence, the sector of program flash that contains the Flash Configuration Field
2186 * must be unprotected; then the EEPROM protection byte must be erased and
2187 * reprogrammed. Trying to alter data by writing to any protected area in the EEPROM
2188 * results in a protection violation error and sets the FSTAT[FPVIOL] bit.
2191 * - 0 - For devices with program flash only: Reserved For devices with FlexNVM:
2192 * EEPROM region is protected
2193 * - 1 - For devices with program flash only: Reserved For devices with FlexNVM:
2194 * EEPROM region is not protected
2197 #define BP_FTFE_FEPROT_EPROT (0U) /*!< Bit position for FTFE_FEPROT_EPROT. */
2198 #define BM_FTFE_FEPROT_EPROT (0xFFU) /*!< Bit mask for FTFE_FEPROT_EPROT. */
2199 #define BS_FTFE_FEPROT_EPROT (8U) /*!< Bit field size in bits for FTFE_FEPROT_EPROT. */
2201 /*! @brief Read current value of the FTFE_FEPROT_EPROT field. */
2202 #define BR_FTFE_FEPROT_EPROT(x) (HW_FTFE_FEPROT(x).U)
2204 /*! @brief Format value for bitfield FTFE_FEPROT_EPROT. */
2205 #define BF_FTFE_FEPROT_EPROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FEPROT_EPROT) & BM_FTFE_FEPROT_EPROT)
2207 /*! @brief Set the EPROT field to a new value. */
2208 #define BW_FTFE_FEPROT_EPROT(x, v) (HW_FTFE_FEPROT_WR(x, v))
2211 /*******************************************************************************
2212 * HW_FTFE_FDPROT - Data Flash Protection Register
2213 ******************************************************************************/
2216 * @brief HW_FTFE_FDPROT - Data Flash Protection Register (RW)
2218 * Reset value: 0x00U
2220 * The FDPROT register defines which data flash regions are protected against
2221 * program and erase operations. Protected Flash regions cannot have their content
2222 * changed; that is, these regions cannot be programmed and cannot be erased by
2223 * any FTFE command. Unprotected regions can be changed by both program and erase
2226 typedef union _hw_ftfe_fdprot
2229 struct _hw_ftfe_fdprot_bitfields
2231 uint8_t DPROT
: 8; /*!< [7:0] Data Flash Region Protect */
2236 * @name Constants and macros for entire FTFE_FDPROT register
2239 #define HW_FTFE_FDPROT_ADDR(x) ((x) + 0x17U)
2241 #define HW_FTFE_FDPROT(x) (*(__IO hw_ftfe_fdprot_t *) HW_FTFE_FDPROT_ADDR(x))
2242 #define HW_FTFE_FDPROT_RD(x) (HW_FTFE_FDPROT(x).U)
2243 #define HW_FTFE_FDPROT_WR(x, v) (HW_FTFE_FDPROT(x).U = (v))
2244 #define HW_FTFE_FDPROT_SET(x, v) (HW_FTFE_FDPROT_WR(x, HW_FTFE_FDPROT_RD(x) | (v)))
2245 #define HW_FTFE_FDPROT_CLR(x, v) (HW_FTFE_FDPROT_WR(x, HW_FTFE_FDPROT_RD(x) & ~(v)))
2246 #define HW_FTFE_FDPROT_TOG(x, v) (HW_FTFE_FDPROT_WR(x, HW_FTFE_FDPROT_RD(x) ^ (v)))
2250 * Constants & macros for individual FTFE_FDPROT bitfields
2254 * @name Register FTFE_FDPROT, field DPROT[7:0] (RW)
2256 * Individual data flash regions can be protected from program and erase
2257 * operations by setting the associated DPROT bit. Each DPROT bit protects one-eighth of
2258 * the partitioned data flash memory space. The granularity of data flash
2259 * protection cannot be less than the data flash sector size. If an unused DPROT bit is
2260 * set, the Erase all Blocks command does not execute and sets the FSTAT[FPVIOL]
2261 * bit. In NVM Normal mode: The protection can only be increased, meaning that
2262 * currently unprotected memory can be protected but currently protected memory
2263 * cannot be unprotected. Since unprotected regions are marked with a 1 and
2264 * protected regions use a 0, only writes changing 1s to 0s are accepted. This 1-to-0
2265 * transition check is performed on a bit-by-bit basis. Those FDPROT bits with
2266 * 1-to-0 transitions are accepted while all bits with 0-to-1 transitions are
2267 * ignored. In NVM Special mode: All bits of the FDPROT register are writable without
2268 * restriction. Unprotected areas can be protected and protected areas can be
2269 * unprotected. The user must never write to the FDPROT register while a command is
2270 * running (CCIF=0). Reset: During the reset sequence, the FDPROT register is
2271 * loaded with the contents of the data flash protection byte in the Flash
2272 * Configuration Field located in program flash memory. The flash basis for the reset values
2273 * is signified by X in the register diagram. To change the data flash
2274 * protection that will be loaded during the reset sequence, unprotect the sector of
2275 * program flash that contains the Flash Configuration Field. Then, erase and
2276 * reprogram the data flash protection byte. Trying to alter data with the program and
2277 * erase commands in any protected area in the data flash memory results in a
2278 * protection violation error and sets the FSTAT[FPVIOL] bit. A block erase of any
2279 * data flash memory block (see the Erase Flash Block command description) is not
2280 * possible if the data flash block contains any protected region or if the FlexNVM
2281 * memory has been partitioned for EEPROM.
2284 * - 0 - Data Flash region is protected
2285 * - 1 - Data Flash region is not protected
2288 #define BP_FTFE_FDPROT_DPROT (0U) /*!< Bit position for FTFE_FDPROT_DPROT. */
2289 #define BM_FTFE_FDPROT_DPROT (0xFFU) /*!< Bit mask for FTFE_FDPROT_DPROT. */
2290 #define BS_FTFE_FDPROT_DPROT (8U) /*!< Bit field size in bits for FTFE_FDPROT_DPROT. */
2292 /*! @brief Read current value of the FTFE_FDPROT_DPROT field. */
2293 #define BR_FTFE_FDPROT_DPROT(x) (HW_FTFE_FDPROT(x).U)
2295 /*! @brief Format value for bitfield FTFE_FDPROT_DPROT. */
2296 #define BF_FTFE_FDPROT_DPROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FDPROT_DPROT) & BM_FTFE_FDPROT_DPROT)
2298 /*! @brief Set the DPROT field to a new value. */
2299 #define BW_FTFE_FDPROT_DPROT(x, v) (HW_FTFE_FDPROT_WR(x, v))
2302 /*******************************************************************************
2303 * hw_ftfe_t - module struct
2304 ******************************************************************************/
2306 * @brief All FTFE module registers.
2309 typedef struct _hw_ftfe
2311 __IO hw_ftfe_fstat_t FSTAT
; /*!< [0x0] Flash Status Register */
2312 __IO hw_ftfe_fcnfg_t FCNFG
; /*!< [0x1] Flash Configuration Register */
2313 __I hw_ftfe_fsec_t FSEC
; /*!< [0x2] Flash Security Register */
2314 __I hw_ftfe_fopt_t FOPT
; /*!< [0x3] Flash Option Register */
2315 __IO hw_ftfe_fccob3_t FCCOB3
; /*!< [0x4] Flash Common Command Object Registers */
2316 __IO hw_ftfe_fccob2_t FCCOB2
; /*!< [0x5] Flash Common Command Object Registers */
2317 __IO hw_ftfe_fccob1_t FCCOB1
; /*!< [0x6] Flash Common Command Object Registers */
2318 __IO hw_ftfe_fccob0_t FCCOB0
; /*!< [0x7] Flash Common Command Object Registers */
2319 __IO hw_ftfe_fccob7_t FCCOB7
; /*!< [0x8] Flash Common Command Object Registers */
2320 __IO hw_ftfe_fccob6_t FCCOB6
; /*!< [0x9] Flash Common Command Object Registers */
2321 __IO hw_ftfe_fccob5_t FCCOB5
; /*!< [0xA] Flash Common Command Object Registers */
2322 __IO hw_ftfe_fccob4_t FCCOB4
; /*!< [0xB] Flash Common Command Object Registers */
2323 __IO hw_ftfe_fccobb_t FCCOBB
; /*!< [0xC] Flash Common Command Object Registers */
2324 __IO hw_ftfe_fccoba_t FCCOBA
; /*!< [0xD] Flash Common Command Object Registers */
2325 __IO hw_ftfe_fccob9_t FCCOB9
; /*!< [0xE] Flash Common Command Object Registers */
2326 __IO hw_ftfe_fccob8_t FCCOB8
; /*!< [0xF] Flash Common Command Object Registers */
2327 __IO hw_ftfe_fprot3_t FPROT3
; /*!< [0x10] Program Flash Protection Registers */
2328 __IO hw_ftfe_fprot2_t FPROT2
; /*!< [0x11] Program Flash Protection Registers */
2329 __IO hw_ftfe_fprot1_t FPROT1
; /*!< [0x12] Program Flash Protection Registers */
2330 __IO hw_ftfe_fprot0_t FPROT0
; /*!< [0x13] Program Flash Protection Registers */
2331 uint8_t _reserved0
[2];
2332 __IO hw_ftfe_feprot_t FEPROT
; /*!< [0x16] EEPROM Protection Register */
2333 __IO hw_ftfe_fdprot_t FDPROT
; /*!< [0x17] Data Flash Protection Register */
2337 /*! @brief Macro to access all FTFE registers. */
2338 /*! @param x FTFE module instance base address. */
2339 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
2340 * use the '&' operator, like <code>&HW_FTFE(FTFE_BASE)</code>. */
2341 #define HW_FTFE(x) (*(hw_ftfe_t *)(x))
2343 #endif /* __HW_FTFE_REGISTERS_H__ */