tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_gpio.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
   9 **     Version:             rev. 2.5, 2014-02-10
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-08-12)
  48 **         Initial version.
  49 **     - rev. 2.0 (2013-10-29)
  50 **         Register accessor macros added to the memory map.
  51 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  52 **         Startup file for gcc has been updated according to CMSIS 3.2.
  53 **         System initialization updated.
  54 **         MCG - registers updated.
  55 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-09)
  59 **         DMA - EARS register removed.
  60 **         AIPS0, AIPS1 - MPRA register updated.
  61 **     - rev. 2.3 (2014-01-24)
  62 **         Update according to reference manual rev. 2
  63 **         ENET, MCG, MCM, SIM, USB - registers updated
  64 **     - rev. 2.4 (2014-02-10)
  65 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  66 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  67 **     - rev. 2.5 (2014-02-10)
  68 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  69 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  70 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  71 **
  72 ** ###################################################################
  73 */
  74
  75 /*
  76  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  77  *
  78  * This file was generated automatically and any changes may be lost.
  79  */
  80 #ifndef __HW_GPIO_REGISTERS_H__
  81 #define __HW_GPIO_REGISTERS_H__
  82
  83 #include "MK64F12.h"
  84 #include "fsl_bitaccess.h"
  85
  86 /*
  87  * MK64F12 GPIO
  88  *
  89  * General Purpose Input/Output
  90  *
  91  * Registers defined in this header file:
  92  * - HW_GPIO_PDOR - Port Data Output Register
  93  * - HW_GPIO_PSOR - Port Set Output Register
  94  * - HW_GPIO_PCOR - Port Clear Output Register
  95  * - HW_GPIO_PTOR - Port Toggle Output Register
  96  * - HW_GPIO_PDIR - Port Data Input Register
  97  * - HW_GPIO_PDDR - Port Data Direction Register
  98  *
  99  * - hw_gpio_t - Struct containing all module registers.
 100  */
 101
 102 #define HW_GPIO_INSTANCE_COUNT (5U) /*!< Number of instances of the GPIO module. */
 103 #define HW_GPIOA (0U) /*!< Instance number for GPIOA. */
 104 #define HW_GPIOB (1U) /*!< Instance number for GPIOB. */
 105 #define HW_GPIOC (2U) /*!< Instance number for GPIOC. */
 106 #define HW_GPIOD (3U) /*!< Instance number for GPIOD. */
 107 #define HW_GPIOE (4U) /*!< Instance number for GPIOE. */
 108
 109 /*******************************************************************************
 110  * HW_GPIO_PDOR - Port Data Output Register
 111  ******************************************************************************/
 112
 113 /*!
 114  * @brief HW_GPIO_PDOR - Port Data Output Register (RW)
 115  *
 116  * Reset value: 0x00000000U
 117  *
 118  * This register configures the logic levels that are driven on each
 119  * general-purpose output pins. Do not modify pin configuration registers associated with
 120  * pins not available in your selected package. All unbonded pins not available in
 121  * your package will default to DISABLE state for lowest power consumption.
 122  */
 123 typedef union _hw_gpio_pdor
 124 {
 125     uint32_t U;
 126     struct _hw_gpio_pdor_bitfields
 127     {
 128         uint32_t PDO : 32;             /*!< [31:0] Port Data Output */
 129     } B;
 130 } hw_gpio_pdor_t;
 131
 132 /*!
 133  * @name Constants and macros for entire GPIO_PDOR register
 134  */
 135 /*@{*/
 136 #define HW_GPIO_PDOR_ADDR(x)     ((x) + 0x0U)
 137
 138 #define HW_GPIO_PDOR(x)          (*(__IO hw_gpio_pdor_t *) HW_GPIO_PDOR_ADDR(x))
 139 #define HW_GPIO_PDOR_RD(x)       (HW_GPIO_PDOR(x).U)
 140 #define HW_GPIO_PDOR_WR(x, v)    (HW_GPIO_PDOR(x).U = (v))
 141 #define HW_GPIO_PDOR_SET(x, v)   (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) |  (v)))
 142 #define HW_GPIO_PDOR_CLR(x, v)   (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) & ~(v)))
 143 #define HW_GPIO_PDOR_TOG(x, v)   (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) ^  (v)))
 144 /*@}*/
 145
 146 /*
 147  * Constants & macros for individual GPIO_PDOR bitfields
 148  */
 149
 150 /*!
 151  * @name Register GPIO_PDOR, field PDO[31:0] (RW)
 152  *
 153  * Register bits for unbonded pins return a undefined value when read.
 154  *
 155  * Values:
 156  * - 0 - Logic level 0 is driven on pin, provided pin is configured for
 157  *     general-purpose output.
 158  * - 1 - Logic level 1 is driven on pin, provided pin is configured for
 159  *     general-purpose output.
 160  */
 161 /*@{*/
 162 #define BP_GPIO_PDOR_PDO     (0U)          /*!< Bit position for GPIO_PDOR_PDO. */
 163 #define BM_GPIO_PDOR_PDO     (0xFFFFFFFFU) /*!< Bit mask for GPIO_PDOR_PDO. */
 164 #define BS_GPIO_PDOR_PDO     (32U)         /*!< Bit field size in bits for GPIO_PDOR_PDO. */
 165
 166 /*! @brief Read current value of the GPIO_PDOR_PDO field. */
 167 #define BR_GPIO_PDOR_PDO(x)  (HW_GPIO_PDOR(x).U)
 168
 169 /*! @brief Format value for bitfield GPIO_PDOR_PDO. */
 170 #define BF_GPIO_PDOR_PDO(v)  ((uint32_t)((uint32_t)(v) << BP_GPIO_PDOR_PDO) & BM_GPIO_PDOR_PDO)
 171
 172 /*! @brief Set the PDO field to a new value. */
 173 #define BW_GPIO_PDOR_PDO(x, v) (HW_GPIO_PDOR_WR(x, v))
 174 /*@}*/
 175
 176 /*******************************************************************************
 177  * HW_GPIO_PSOR - Port Set Output Register
 178  ******************************************************************************/
 179
 180 /*!
 181  * @brief HW_GPIO_PSOR - Port Set Output Register (WORZ)
 182  *
 183  * Reset value: 0x00000000U
 184  *
 185  * This register configures whether to set the fields of the PDOR.
 186  */
 187 typedef union _hw_gpio_psor
 188 {
 189     uint32_t U;
 190     struct _hw_gpio_psor_bitfields
 191     {
 192         uint32_t PTSO : 32;            /*!< [31:0] Port Set Output */
 193     } B;
 194 } hw_gpio_psor_t;
 195
 196 /*!
 197  * @name Constants and macros for entire GPIO_PSOR register
 198  */
 199 /*@{*/
 200 #define HW_GPIO_PSOR_ADDR(x)     ((x) + 0x4U)
 201
 202 #define HW_GPIO_PSOR(x)          (*(__O hw_gpio_psor_t *) HW_GPIO_PSOR_ADDR(x))
 203 #define HW_GPIO_PSOR_RD(x)       (HW_GPIO_PSOR(x).U)
 204 #define HW_GPIO_PSOR_WR(x, v)    (HW_GPIO_PSOR(x).U = (v))
 205 /*@}*/
 206
 207 /*
 208  * Constants & macros for individual GPIO_PSOR bitfields
 209  */
 210
 211 /*!
 212  * @name Register GPIO_PSOR, field PTSO[31:0] (WORZ)
 213  *
 214  * Writing to this register will update the contents of the corresponding bit in
 215  * the PDOR as follows:
 216  *
 217  * Values:
 218  * - 0 - Corresponding bit in PDORn does not change.
 219  * - 1 - Corresponding bit in PDORn is set to logic 1.
 220  */
 221 /*@{*/
 222 #define BP_GPIO_PSOR_PTSO    (0U)          /*!< Bit position for GPIO_PSOR_PTSO. */
 223 #define BM_GPIO_PSOR_PTSO    (0xFFFFFFFFU) /*!< Bit mask for GPIO_PSOR_PTSO. */
 224 #define BS_GPIO_PSOR_PTSO    (32U)         /*!< Bit field size in bits for GPIO_PSOR_PTSO. */
 225
 226 /*! @brief Format value for bitfield GPIO_PSOR_PTSO. */
 227 #define BF_GPIO_PSOR_PTSO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PSOR_PTSO) & BM_GPIO_PSOR_PTSO)
 228
 229 /*! @brief Set the PTSO field to a new value. */
 230 #define BW_GPIO_PSOR_PTSO(x, v) (HW_GPIO_PSOR_WR(x, v))
 231 /*@}*/
 232
 233 /*******************************************************************************
 234  * HW_GPIO_PCOR - Port Clear Output Register
 235  ******************************************************************************/
 236
 237 /*!
 238  * @brief HW_GPIO_PCOR - Port Clear Output Register (WORZ)
 239  *
 240  * Reset value: 0x00000000U
 241  *
 242  * This register configures whether to clear the fields of PDOR.
 243  */
 244 typedef union _hw_gpio_pcor
 245 {
 246     uint32_t U;
 247     struct _hw_gpio_pcor_bitfields
 248     {
 249         uint32_t PTCO : 32;            /*!< [31:0] Port Clear Output */
 250     } B;
 251 } hw_gpio_pcor_t;
 252
 253 /*!
 254  * @name Constants and macros for entire GPIO_PCOR register
 255  */
 256 /*@{*/
 257 #define HW_GPIO_PCOR_ADDR(x)     ((x) + 0x8U)
 258
 259 #define HW_GPIO_PCOR(x)          (*(__O hw_gpio_pcor_t *) HW_GPIO_PCOR_ADDR(x))
 260 #define HW_GPIO_PCOR_RD(x)       (HW_GPIO_PCOR(x).U)
 261 #define HW_GPIO_PCOR_WR(x, v)    (HW_GPIO_PCOR(x).U = (v))
 262 /*@}*/
 263
 264 /*
 265  * Constants & macros for individual GPIO_PCOR bitfields
 266  */
 267
 268 /*!
 269  * @name Register GPIO_PCOR, field PTCO[31:0] (WORZ)
 270  *
 271  * Writing to this register will update the contents of the corresponding bit in
 272  * the Port Data Output Register (PDOR) as follows:
 273  *
 274  * Values:
 275  * - 0 - Corresponding bit in PDORn does not change.
 276  * - 1 - Corresponding bit in PDORn is cleared to logic 0.
 277  */
 278 /*@{*/
 279 #define BP_GPIO_PCOR_PTCO    (0U)          /*!< Bit position for GPIO_PCOR_PTCO. */
 280 #define BM_GPIO_PCOR_PTCO    (0xFFFFFFFFU) /*!< Bit mask for GPIO_PCOR_PTCO. */
 281 #define BS_GPIO_PCOR_PTCO    (32U)         /*!< Bit field size in bits for GPIO_PCOR_PTCO. */
 282
 283 /*! @brief Format value for bitfield GPIO_PCOR_PTCO. */
 284 #define BF_GPIO_PCOR_PTCO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PCOR_PTCO) & BM_GPIO_PCOR_PTCO)
 285
 286 /*! @brief Set the PTCO field to a new value. */
 287 #define BW_GPIO_PCOR_PTCO(x, v) (HW_GPIO_PCOR_WR(x, v))
 288 /*@}*/
 289
 290 /*******************************************************************************
 291  * HW_GPIO_PTOR - Port Toggle Output Register
 292  ******************************************************************************/
 293
 294 /*!
 295  * @brief HW_GPIO_PTOR - Port Toggle Output Register (WORZ)
 296  *
 297  * Reset value: 0x00000000U
 298  */
 299 typedef union _hw_gpio_ptor
 300 {
 301     uint32_t U;
 302     struct _hw_gpio_ptor_bitfields
 303     {
 304         uint32_t PTTO : 32;            /*!< [31:0] Port Toggle Output */
 305     } B;
 306 } hw_gpio_ptor_t;
 307
 308 /*!
 309  * @name Constants and macros for entire GPIO_PTOR register
 310  */
 311 /*@{*/
 312 #define HW_GPIO_PTOR_ADDR(x)     ((x) + 0xCU)
 313
 314 #define HW_GPIO_PTOR(x)          (*(__O hw_gpio_ptor_t *) HW_GPIO_PTOR_ADDR(x))
 315 #define HW_GPIO_PTOR_RD(x)       (HW_GPIO_PTOR(x).U)
 316 #define HW_GPIO_PTOR_WR(x, v)    (HW_GPIO_PTOR(x).U = (v))
 317 /*@}*/
 318
 319 /*
 320  * Constants & macros for individual GPIO_PTOR bitfields
 321  */
 322
 323 /*!
 324  * @name Register GPIO_PTOR, field PTTO[31:0] (WORZ)
 325  *
 326  * Writing to this register will update the contents of the corresponding bit in
 327  * the PDOR as follows:
 328  *
 329  * Values:
 330  * - 0 - Corresponding bit in PDORn does not change.
 331  * - 1 - Corresponding bit in PDORn is set to the inverse of its existing logic
 332  *     state.
 333  */
 334 /*@{*/
 335 #define BP_GPIO_PTOR_PTTO    (0U)          /*!< Bit position for GPIO_PTOR_PTTO. */
 336 #define BM_GPIO_PTOR_PTTO    (0xFFFFFFFFU) /*!< Bit mask for GPIO_PTOR_PTTO. */
 337 #define BS_GPIO_PTOR_PTTO    (32U)         /*!< Bit field size in bits for GPIO_PTOR_PTTO. */
 338
 339 /*! @brief Format value for bitfield GPIO_PTOR_PTTO. */
 340 #define BF_GPIO_PTOR_PTTO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PTOR_PTTO) & BM_GPIO_PTOR_PTTO)
 341
 342 /*! @brief Set the PTTO field to a new value. */
 343 #define BW_GPIO_PTOR_PTTO(x, v) (HW_GPIO_PTOR_WR(x, v))
 344 /*@}*/
 345
 346 /*******************************************************************************
 347  * HW_GPIO_PDIR - Port Data Input Register
 348  ******************************************************************************/
 349
 350 /*!
 351  * @brief HW_GPIO_PDIR - Port Data Input Register (RO)
 352  *
 353  * Reset value: 0x00000000U
 354  *
 355  * Do not modify pin configuration registers associated with pins not available
 356  * in your selected package. All unbonded pins not available in your package will
 357  * default to DISABLE state for lowest power consumption.
 358  */
 359 typedef union _hw_gpio_pdir
 360 {
 361     uint32_t U;
 362     struct _hw_gpio_pdir_bitfields
 363     {
 364         uint32_t PDI : 32;             /*!< [31:0] Port Data Input */
 365     } B;
 366 } hw_gpio_pdir_t;
 367
 368 /*!
 369  * @name Constants and macros for entire GPIO_PDIR register
 370  */
 371 /*@{*/
 372 #define HW_GPIO_PDIR_ADDR(x)     ((x) + 0x10U)
 373
 374 #define HW_GPIO_PDIR(x)          (*(__I hw_gpio_pdir_t *) HW_GPIO_PDIR_ADDR(x))
 375 #define HW_GPIO_PDIR_RD(x)       (HW_GPIO_PDIR(x).U)
 376 /*@}*/
 377
 378 /*
 379  * Constants & macros for individual GPIO_PDIR bitfields
 380  */
 381
 382 /*!
 383  * @name Register GPIO_PDIR, field PDI[31:0] (RO)
 384  *
 385  * Reads 0 at the unimplemented pins for a particular device. Pins that are not
 386  * configured for a digital function read 0. If the Port Control and Interrupt
 387  * module is disabled, then the corresponding bit in PDIR does not update.
 388  *
 389  * Values:
 390  * - 0 - Pin logic level is logic 0, or is not configured for use by digital
 391  *     function.
 392  * - 1 - Pin logic level is logic 1.
 393  */
 394 /*@{*/
 395 #define BP_GPIO_PDIR_PDI     (0U)          /*!< Bit position for GPIO_PDIR_PDI. */
 396 #define BM_GPIO_PDIR_PDI     (0xFFFFFFFFU) /*!< Bit mask for GPIO_PDIR_PDI. */
 397 #define BS_GPIO_PDIR_PDI     (32U)         /*!< Bit field size in bits for GPIO_PDIR_PDI. */
 398
 399 /*! @brief Read current value of the GPIO_PDIR_PDI field. */
 400 #define BR_GPIO_PDIR_PDI(x)  (HW_GPIO_PDIR(x).U)
 401 /*@}*/
 402
 403 /*******************************************************************************
 404  * HW_GPIO_PDDR - Port Data Direction Register
 405  ******************************************************************************/
 406
 407 /*!
 408  * @brief HW_GPIO_PDDR - Port Data Direction Register (RW)
 409  *
 410  * Reset value: 0x00000000U
 411  *
 412  * The PDDR configures the individual port pins for input or output.
 413  */
 414 typedef union _hw_gpio_pddr
 415 {
 416     uint32_t U;
 417     struct _hw_gpio_pddr_bitfields
 418     {
 419         uint32_t PDD : 32;             /*!< [31:0] Port Data Direction */
 420     } B;
 421 } hw_gpio_pddr_t;
 422
 423 /*!
 424  * @name Constants and macros for entire GPIO_PDDR register
 425  */
 426 /*@{*/
 427 #define HW_GPIO_PDDR_ADDR(x)     ((x) + 0x14U)
 428
 429 #define HW_GPIO_PDDR(x)          (*(__IO hw_gpio_pddr_t *) HW_GPIO_PDDR_ADDR(x))
 430 #define HW_GPIO_PDDR_RD(x)       (HW_GPIO_PDDR(x).U)
 431 #define HW_GPIO_PDDR_WR(x, v)    (HW_GPIO_PDDR(x).U = (v))
 432 #define HW_GPIO_PDDR_SET(x, v)   (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) |  (v)))
 433 #define HW_GPIO_PDDR_CLR(x, v)   (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) & ~(v)))
 434 #define HW_GPIO_PDDR_TOG(x, v)   (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) ^  (v)))
 435 /*@}*/
 436
 437 /*
 438  * Constants & macros for individual GPIO_PDDR bitfields
 439  */
 440
 441 /*!
 442  * @name Register GPIO_PDDR, field PDD[31:0] (RW)
 443  *
 444  * Configures individual port pins for input or output.
 445  *
 446  * Values:
 447  * - 0 - Pin is configured as general-purpose input, for the GPIO function.
 448  * - 1 - Pin is configured as general-purpose output, for the GPIO function.
 449  */
 450 /*@{*/
 451 #define BP_GPIO_PDDR_PDD     (0U)          /*!< Bit position for GPIO_PDDR_PDD. */
 452 #define BM_GPIO_PDDR_PDD     (0xFFFFFFFFU) /*!< Bit mask for GPIO_PDDR_PDD. */
 453 #define BS_GPIO_PDDR_PDD     (32U)         /*!< Bit field size in bits for GPIO_PDDR_PDD. */
 454
 455 /*! @brief Read current value of the GPIO_PDDR_PDD field. */
 456 #define BR_GPIO_PDDR_PDD(x)  (HW_GPIO_PDDR(x).U)
 457
 458 /*! @brief Format value for bitfield GPIO_PDDR_PDD. */
 459 #define BF_GPIO_PDDR_PDD(v)  ((uint32_t)((uint32_t)(v) << BP_GPIO_PDDR_PDD) & BM_GPIO_PDDR_PDD)
 460
 461 /*! @brief Set the PDD field to a new value. */
 462 #define BW_GPIO_PDDR_PDD(x, v) (HW_GPIO_PDDR_WR(x, v))
 463 /*@}*/
 464
 465 /*******************************************************************************
 466  * hw_gpio_t - module struct
 467  ******************************************************************************/
 468 /*!
 469  * @brief All GPIO module registers.
 470  */
 471 #pragma pack(1)
 472 typedef struct _hw_gpio
 473 {
 474     __IO hw_gpio_pdor_t PDOR;              /*!< [0x0] Port Data Output Register */
 475     __O hw_gpio_psor_t PSOR;               /*!< [0x4] Port Set Output Register */
 476     __O hw_gpio_pcor_t PCOR;               /*!< [0x8] Port Clear Output Register */
 477     __O hw_gpio_ptor_t PTOR;               /*!< [0xC] Port Toggle Output Register */
 478     __I hw_gpio_pdir_t PDIR;               /*!< [0x10] Port Data Input Register */
 479     __IO hw_gpio_pddr_t PDDR;              /*!< [0x14] Port Data Direction Register */
 480 } hw_gpio_t;
 481 #pragma pack()
 482
 483 /*! @brief Macro to access all GPIO registers. */
 484 /*! @param x GPIO module instance base address. */
 485 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
 486  *     use the '&' operator, like <code>&HW_GPIO(GPIOA_BASE)</code>. */
 487 #define HW_GPIO(x)     (*(hw_gpio_t *)(x))
 488
 489 #endif /* __HW_GPIO_REGISTERS_H__ */
 490 /* EOF */