tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_i2c.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
   9 **     Version:             rev. 2.5, 2014-02-10
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-08-12)
  48 **         Initial version.
  49 **     - rev. 2.0 (2013-10-29)
  50 **         Register accessor macros added to the memory map.
  51 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  52 **         Startup file for gcc has been updated according to CMSIS 3.2.
  53 **         System initialization updated.
  54 **         MCG - registers updated.
  55 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-09)
  59 **         DMA - EARS register removed.
  60 **         AIPS0, AIPS1 - MPRA register updated.
  61 **     - rev. 2.3 (2014-01-24)
  62 **         Update according to reference manual rev. 2
  63 **         ENET, MCG, MCM, SIM, USB - registers updated
  64 **     - rev. 2.4 (2014-02-10)
  65 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  66 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  67 **     - rev. 2.5 (2014-02-10)
  68 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  69 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  70 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  71 **
  72 ** ###################################################################
  73 */
  74
  75 /*
  76  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  77  *
  78  * This file was generated automatically and any changes may be lost.
  79  */
  80 #ifndef __HW_I2C_REGISTERS_H__
  81 #define __HW_I2C_REGISTERS_H__
  82
  83 #include "MK64F12.h"
  84 #include "fsl_bitaccess.h"
  85
  86 /*
  87  * MK64F12 I2C
  88  *
  89  * Inter-Integrated Circuit
  90  *
  91  * Registers defined in this header file:
  92  * - HW_I2C_A1 - I2C Address Register 1
  93  * - HW_I2C_F - I2C Frequency Divider register
  94  * - HW_I2C_C1 - I2C Control Register 1
  95  * - HW_I2C_S - I2C Status register
  96  * - HW_I2C_D - I2C Data I/O register
  97  * - HW_I2C_C2 - I2C Control Register 2
  98  * - HW_I2C_FLT - I2C Programmable Input Glitch Filter register
  99  * - HW_I2C_RA - I2C Range Address register
 100  * - HW_I2C_SMB - I2C SMBus Control and Status register
 101  * - HW_I2C_A2 - I2C Address Register 2
 102  * - HW_I2C_SLTH - I2C SCL Low Timeout Register High
 103  * - HW_I2C_SLTL - I2C SCL Low Timeout Register Low
 104  *
 105  * - hw_i2c_t - Struct containing all module registers.
 106  */
 107
 108 #define HW_I2C_INSTANCE_COUNT (3U) /*!< Number of instances of the I2C module. */
 109 #define HW_I2C0 (0U) /*!< Instance number for I2C0. */
 110 #define HW_I2C1 (1U) /*!< Instance number for I2C1. */
 111 #define HW_I2C2 (2U) /*!< Instance number for I2C2. */
 112
 113 /*******************************************************************************
 114  * HW_I2C_A1 - I2C Address Register 1
 115  ******************************************************************************/
 116
 117 /*!
 118  * @brief HW_I2C_A1 - I2C Address Register 1 (RW)
 119  *
 120  * Reset value: 0x00U
 121  *
 122  * This register contains the slave address to be used by the I2C module.
 123  */
 124 typedef union _hw_i2c_a1
 125 {
 126     uint8_t U;
 127     struct _hw_i2c_a1_bitfields
 128     {
 129         uint8_t RESERVED0 : 1;         /*!< [0]  */
 130         uint8_t AD : 7;                /*!< [7:1] Address */
 131     } B;
 132 } hw_i2c_a1_t;
 133
 134 /*!
 135  * @name Constants and macros for entire I2C_A1 register
 136  */
 137 /*@{*/
 138 #define HW_I2C_A1_ADDR(x)        ((x) + 0x0U)
 139
 140 #define HW_I2C_A1(x)             (*(__IO hw_i2c_a1_t *) HW_I2C_A1_ADDR(x))
 141 #define HW_I2C_A1_RD(x)          (HW_I2C_A1(x).U)
 142 #define HW_I2C_A1_WR(x, v)       (HW_I2C_A1(x).U = (v))
 143 #define HW_I2C_A1_SET(x, v)      (HW_I2C_A1_WR(x, HW_I2C_A1_RD(x) |  (v)))
 144 #define HW_I2C_A1_CLR(x, v)      (HW_I2C_A1_WR(x, HW_I2C_A1_RD(x) & ~(v)))
 145 #define HW_I2C_A1_TOG(x, v)      (HW_I2C_A1_WR(x, HW_I2C_A1_RD(x) ^  (v)))
 146 /*@}*/
 147
 148 /*
 149  * Constants & macros for individual I2C_A1 bitfields
 150  */
 151
 152 /*!
 153  * @name Register I2C_A1, field AD[7:1] (RW)
 154  *
 155  * Contains the primary slave address used by the I2C module when it is
 156  * addressed as a slave. This field is used in the 7-bit address scheme and the lower
 157  * seven bits in the 10-bit address scheme.
 158  */
 159 /*@{*/
 160 #define BP_I2C_A1_AD         (1U)          /*!< Bit position for I2C_A1_AD. */
 161 #define BM_I2C_A1_AD         (0xFEU)       /*!< Bit mask for I2C_A1_AD. */
 162 #define BS_I2C_A1_AD         (7U)          /*!< Bit field size in bits for I2C_A1_AD. */
 163
 164 /*! @brief Read current value of the I2C_A1_AD field. */
 165 #define BR_I2C_A1_AD(x)      (HW_I2C_A1(x).B.AD)
 166
 167 /*! @brief Format value for bitfield I2C_A1_AD. */
 168 #define BF_I2C_A1_AD(v)      ((uint8_t)((uint8_t)(v) << BP_I2C_A1_AD) & BM_I2C_A1_AD)
 169
 170 /*! @brief Set the AD field to a new value. */
 171 #define BW_I2C_A1_AD(x, v)   (HW_I2C_A1_WR(x, (HW_I2C_A1_RD(x) & ~BM_I2C_A1_AD) | BF_I2C_A1_AD(v)))
 172 /*@}*/
 173
 174 /*******************************************************************************
 175  * HW_I2C_F - I2C Frequency Divider register
 176  ******************************************************************************/
 177
 178 /*!
 179  * @brief HW_I2C_F - I2C Frequency Divider register (RW)
 180  *
 181  * Reset value: 0x00U
 182  */
 183 typedef union _hw_i2c_f
 184 {
 185     uint8_t U;
 186     struct _hw_i2c_f_bitfields
 187     {
 188         uint8_t ICR : 6;               /*!< [5:0] ClockRate */
 189         uint8_t MULT : 2;              /*!< [7:6] Multiplier Factor */
 190     } B;
 191 } hw_i2c_f_t;
 192
 193 /*!
 194  * @name Constants and macros for entire I2C_F register
 195  */
 196 /*@{*/
 197 #define HW_I2C_F_ADDR(x)         ((x) + 0x1U)
 198
 199 #define HW_I2C_F(x)              (*(__IO hw_i2c_f_t *) HW_I2C_F_ADDR(x))
 200 #define HW_I2C_F_RD(x)           (HW_I2C_F(x).U)
 201 #define HW_I2C_F_WR(x, v)        (HW_I2C_F(x).U = (v))
 202 #define HW_I2C_F_SET(x, v)       (HW_I2C_F_WR(x, HW_I2C_F_RD(x) |  (v)))
 203 #define HW_I2C_F_CLR(x, v)       (HW_I2C_F_WR(x, HW_I2C_F_RD(x) & ~(v)))
 204 #define HW_I2C_F_TOG(x, v)       (HW_I2C_F_WR(x, HW_I2C_F_RD(x) ^  (v)))
 205 /*@}*/
 206
 207 /*
 208  * Constants & macros for individual I2C_F bitfields
 209  */
 210
 211 /*!
 212  * @name Register I2C_F, field ICR[5:0] (RW)
 213  *
 214  * Prescales the I2C module clock for bit rate selection. This field and the
 215  * MULT field determine the I2C baud rate, the SDA hold time, the SCL start hold
 216  * time, and the SCL stop hold time. For a list of values corresponding to each ICR
 217  * setting, see I2C divider and hold values. The SCL divider multiplied by
 218  * multiplier factor (mul) determines the I2C baud rate. I2C baud rate = I2C module
 219  * clock speed (Hz)/(mul * SCL divider) The SDA hold time is the delay from the
 220  * falling edge of SCL (I2C clock) to the changing of SDA (I2C data). SDA hold time =
 221  * I2C module clock period (s) * mul * SDA hold value The SCL start hold time is
 222  * the delay from the falling edge of SDA (I2C data) while SCL is high (start
 223  * condition) to the falling edge of SCL (I2C clock). SCL start hold time = I2C
 224  * module clock period (s) * mul * SCL start hold value The SCL stop hold time is
 225  * the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C
 226  * data) while SCL is high (stop condition). SCL stop hold time = I2C module
 227  * clock period (s) * mul * SCL stop hold value For example, if the I2C module clock
 228  * speed is 8 MHz, the following table shows the possible hold time values with
 229  * different ICR and MULT selections to achieve an I2C baud rate of 100 kbit/s.
 230  * MULT ICR Hold times (us) SDA SCL Start SCL Stop 2h 00h 3.500 3.000 5.500 1h 07h
 231  * 2.500 4.000 5.250 1h 0Bh 2.250 4.000 5.250 0h 14h 2.125 4.250 5.125 0h 18h
 232  * 1.125 4.750 5.125
 233  */
 234 /*@{*/
 235 #define BP_I2C_F_ICR         (0U)          /*!< Bit position for I2C_F_ICR. */
 236 #define BM_I2C_F_ICR         (0x3FU)       /*!< Bit mask for I2C_F_ICR. */
 237 #define BS_I2C_F_ICR         (6U)          /*!< Bit field size in bits for I2C_F_ICR. */
 238
 239 /*! @brief Read current value of the I2C_F_ICR field. */
 240 #define BR_I2C_F_ICR(x)      (HW_I2C_F(x).B.ICR)
 241
 242 /*! @brief Format value for bitfield I2C_F_ICR. */
 243 #define BF_I2C_F_ICR(v)      ((uint8_t)((uint8_t)(v) << BP_I2C_F_ICR) & BM_I2C_F_ICR)
 244
 245 /*! @brief Set the ICR field to a new value. */
 246 #define BW_I2C_F_ICR(x, v)   (HW_I2C_F_WR(x, (HW_I2C_F_RD(x) & ~BM_I2C_F_ICR) | BF_I2C_F_ICR(v)))
 247 /*@}*/
 248
 249 /*!
 250  * @name Register I2C_F, field MULT[7:6] (RW)
 251  *
 252  * Defines the multiplier factor (mul). This factor is used along with the SCL
 253  * divider to generate the I2C baud rate.
 254  *
 255  * Values:
 256  * - 00 - mul = 1
 257  * - 01 - mul = 2
 258  * - 10 - mul = 4
 259  * - 11 - Reserved
 260  */
 261 /*@{*/
 262 #define BP_I2C_F_MULT        (6U)          /*!< Bit position for I2C_F_MULT. */
 263 #define BM_I2C_F_MULT        (0xC0U)       /*!< Bit mask for I2C_F_MULT. */
 264 #define BS_I2C_F_MULT        (2U)          /*!< Bit field size in bits for I2C_F_MULT. */
 265
 266 /*! @brief Read current value of the I2C_F_MULT field. */
 267 #define BR_I2C_F_MULT(x)     (HW_I2C_F(x).B.MULT)
 268
 269 /*! @brief Format value for bitfield I2C_F_MULT. */
 270 #define BF_I2C_F_MULT(v)     ((uint8_t)((uint8_t)(v) << BP_I2C_F_MULT) & BM_I2C_F_MULT)
 271
 272 /*! @brief Set the MULT field to a new value. */
 273 #define BW_I2C_F_MULT(x, v)  (HW_I2C_F_WR(x, (HW_I2C_F_RD(x) & ~BM_I2C_F_MULT) | BF_I2C_F_MULT(v)))
 274 /*@}*/
 275
 276 /*******************************************************************************
 277  * HW_I2C_C1 - I2C Control Register 1
 278  ******************************************************************************/
 279
 280 /*!
 281  * @brief HW_I2C_C1 - I2C Control Register 1 (RW)
 282  *
 283  * Reset value: 0x00U
 284  */
 285 typedef union _hw_i2c_c1
 286 {
 287     uint8_t U;
 288     struct _hw_i2c_c1_bitfields
 289     {
 290         uint8_t DMAEN : 1;             /*!< [0] DMA Enable */
 291         uint8_t WUEN : 1;              /*!< [1] Wakeup Enable */
 292         uint8_t RSTA : 1;              /*!< [2] Repeat START */
 293         uint8_t TXAK : 1;              /*!< [3] Transmit Acknowledge Enable */
 294         uint8_t TX : 1;                /*!< [4] Transmit Mode Select */
 295         uint8_t MST : 1;               /*!< [5] Master Mode Select */
 296         uint8_t IICIE : 1;             /*!< [6] I2C Interrupt Enable */
 297         uint8_t IICEN : 1;             /*!< [7] I2C Enable */
 298     } B;
 299 } hw_i2c_c1_t;
 300
 301 /*!
 302  * @name Constants and macros for entire I2C_C1 register
 303  */
 304 /*@{*/
 305 #define HW_I2C_C1_ADDR(x)        ((x) + 0x2U)
 306
 307 #define HW_I2C_C1(x)             (*(__IO hw_i2c_c1_t *) HW_I2C_C1_ADDR(x))
 308 #define HW_I2C_C1_RD(x)          (HW_I2C_C1(x).U)
 309 #define HW_I2C_C1_WR(x, v)       (HW_I2C_C1(x).U = (v))
 310 #define HW_I2C_C1_SET(x, v)      (HW_I2C_C1_WR(x, HW_I2C_C1_RD(x) |  (v)))
 311 #define HW_I2C_C1_CLR(x, v)      (HW_I2C_C1_WR(x, HW_I2C_C1_RD(x) & ~(v)))
 312 #define HW_I2C_C1_TOG(x, v)      (HW_I2C_C1_WR(x, HW_I2C_C1_RD(x) ^  (v)))
 313 /*@}*/
 314
 315 /*
 316  * Constants & macros for individual I2C_C1 bitfields
 317  */
 318
 319 /*!
 320  * @name Register I2C_C1, field DMAEN[0] (RW)
 321  *
 322  * Enables or disables the DMA function.
 323  *
 324  * Values:
 325  * - 0 - All DMA signalling disabled.
 326  * - 1 - DMA transfer is enabled. While SMB[FACK] = 0, the following conditions
 327  *     trigger the DMA request: a data byte is received, and either address or
 328  *     data is transmitted. (ACK/NACK is automatic) the first byte received matches
 329  *     the A1 register or is a general call address. If any address matching
 330  *     occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known
 331  *     from master to slave, then it is not required to check S[SRW]. With this
 332  *     assumption, DMA can also be used in this case. In other cases, if the master
 333  *     reads data from the slave, then it is required to rewrite the C1 register
 334  *     operation. With this assumption, DMA cannot be used. When FACK = 1, an
 335  *     address or a data byte is transmitted.
 336  */
 337 /*@{*/
 338 #define BP_I2C_C1_DMAEN      (0U)          /*!< Bit position for I2C_C1_DMAEN. */
 339 #define BM_I2C_C1_DMAEN      (0x01U)       /*!< Bit mask for I2C_C1_DMAEN. */
 340 #define BS_I2C_C1_DMAEN      (1U)          /*!< Bit field size in bits for I2C_C1_DMAEN. */
 341
 342 /*! @brief Read current value of the I2C_C1_DMAEN field. */
 343 #define BR_I2C_C1_DMAEN(x)   (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_DMAEN))
 344
 345 /*! @brief Format value for bitfield I2C_C1_DMAEN. */
 346 #define BF_I2C_C1_DMAEN(v)   ((uint8_t)((uint8_t)(v) << BP_I2C_C1_DMAEN) & BM_I2C_C1_DMAEN)
 347
 348 /*! @brief Set the DMAEN field to a new value. */
 349 #define BW_I2C_C1_DMAEN(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_DMAEN) = (v))
 350 /*@}*/
 351
 352 /*!
 353  * @name Register I2C_C1, field WUEN[1] (RW)
 354  *
 355  * The I2C module can wake the MCU from low power mode with no peripheral bus
 356  * running when slave address matching occurs.
 357  *
 358  * Values:
 359  * - 0 - Normal operation. No interrupt generated when address matching in low
 360  *     power mode.
 361  * - 1 - Enables the wakeup function in low power mode.
 362  */
 363 /*@{*/
 364 #define BP_I2C_C1_WUEN       (1U)          /*!< Bit position for I2C_C1_WUEN. */
 365 #define BM_I2C_C1_WUEN       (0x02U)       /*!< Bit mask for I2C_C1_WUEN. */
 366 #define BS_I2C_C1_WUEN       (1U)          /*!< Bit field size in bits for I2C_C1_WUEN. */
 367
 368 /*! @brief Read current value of the I2C_C1_WUEN field. */
 369 #define BR_I2C_C1_WUEN(x)    (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_WUEN))
 370
 371 /*! @brief Format value for bitfield I2C_C1_WUEN. */
 372 #define BF_I2C_C1_WUEN(v)    ((uint8_t)((uint8_t)(v) << BP_I2C_C1_WUEN) & BM_I2C_C1_WUEN)
 373
 374 /*! @brief Set the WUEN field to a new value. */
 375 #define BW_I2C_C1_WUEN(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_WUEN) = (v))
 376 /*@}*/
 377
 378 /*!
 379  * @name Register I2C_C1, field RSTA[2] (WORZ)
 380  *
 381  * Writing 1 to this bit generates a repeated START condition provided it is the
 382  * current master. This bit will always be read as 0. Attempting a repeat at the
 383  * wrong time results in loss of arbitration.
 384  */
 385 /*@{*/
 386 #define BP_I2C_C1_RSTA       (2U)          /*!< Bit position for I2C_C1_RSTA. */
 387 #define BM_I2C_C1_RSTA       (0x04U)       /*!< Bit mask for I2C_C1_RSTA. */
 388 #define BS_I2C_C1_RSTA       (1U)          /*!< Bit field size in bits for I2C_C1_RSTA. */
 389
 390 /*! @brief Format value for bitfield I2C_C1_RSTA. */
 391 #define BF_I2C_C1_RSTA(v)    ((uint8_t)((uint8_t)(v) << BP_I2C_C1_RSTA) & BM_I2C_C1_RSTA)
 392
 393 /*! @brief Set the RSTA field to a new value. */
 394 #define BW_I2C_C1_RSTA(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_RSTA) = (v))
 395 /*@}*/
 396
 397 /*!
 398  * @name Register I2C_C1, field TXAK[3] (RW)
 399  *
 400  * Specifies the value driven onto the SDA during data acknowledge cycles for
 401  * both master and slave receivers. The value of SMB[FACK] affects NACK/ACK
 402  * generation. SCL is held low until TXAK is written.
 403  *
 404  * Values:
 405  * - 0 - An acknowledge signal is sent to the bus on the following receiving
 406  *     byte (if FACK is cleared) or the current receiving byte (if FACK is set).
 407  * - 1 - No acknowledge signal is sent to the bus on the following receiving
 408  *     data byte (if FACK is cleared) or the current receiving data byte (if FACK is
 409  *     set).
 410  */
 411 /*@{*/
 412 #define BP_I2C_C1_TXAK       (3U)          /*!< Bit position for I2C_C1_TXAK. */
 413 #define BM_I2C_C1_TXAK       (0x08U)       /*!< Bit mask for I2C_C1_TXAK. */
 414 #define BS_I2C_C1_TXAK       (1U)          /*!< Bit field size in bits for I2C_C1_TXAK. */
 415
 416 /*! @brief Read current value of the I2C_C1_TXAK field. */
 417 #define BR_I2C_C1_TXAK(x)    (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TXAK))
 418
 419 /*! @brief Format value for bitfield I2C_C1_TXAK. */
 420 #define BF_I2C_C1_TXAK(v)    ((uint8_t)((uint8_t)(v) << BP_I2C_C1_TXAK) & BM_I2C_C1_TXAK)
 421
 422 /*! @brief Set the TXAK field to a new value. */
 423 #define BW_I2C_C1_TXAK(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TXAK) = (v))
 424 /*@}*/
 425
 426 /*!
 427  * @name Register I2C_C1, field TX[4] (RW)
 428  *
 429  * Selects the direction of master and slave transfers. In master mode this bit
 430  * must be set according to the type of transfer required. Therefore, for address
 431  * cycles, this bit is always set. When addressed as a slave this bit must be
 432  * set by software according to the SRW bit in the status register.
 433  *
 434  * Values:
 435  * - 0 - Receive
 436  * - 1 - Transmit
 437  */
 438 /*@{*/
 439 #define BP_I2C_C1_TX         (4U)          /*!< Bit position for I2C_C1_TX. */
 440 #define BM_I2C_C1_TX         (0x10U)       /*!< Bit mask for I2C_C1_TX. */
 441 #define BS_I2C_C1_TX         (1U)          /*!< Bit field size in bits for I2C_C1_TX. */
 442
 443 /*! @brief Read current value of the I2C_C1_TX field. */
 444 #define BR_I2C_C1_TX(x)      (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TX))
 445
 446 /*! @brief Format value for bitfield I2C_C1_TX. */
 447 #define BF_I2C_C1_TX(v)      ((uint8_t)((uint8_t)(v) << BP_I2C_C1_TX) & BM_I2C_C1_TX)
 448
 449 /*! @brief Set the TX field to a new value. */
 450 #define BW_I2C_C1_TX(x, v)   (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TX) = (v))
 451 /*@}*/
 452
 453 /*!
 454  * @name Register I2C_C1, field MST[5] (RW)
 455  *
 456  * When MST is changed from 0 to 1, a START signal is generated on the bus and
 457  * master mode is selected. When this bit changes from 1 to 0, a STOP signal is
 458  * generated and the mode of operation changes from master to slave.
 459  *
 460  * Values:
 461  * - 0 - Slave mode
 462  * - 1 - Master mode
 463  */
 464 /*@{*/
 465 #define BP_I2C_C1_MST        (5U)          /*!< Bit position for I2C_C1_MST. */
 466 #define BM_I2C_C1_MST        (0x20U)       /*!< Bit mask for I2C_C1_MST. */
 467 #define BS_I2C_C1_MST        (1U)          /*!< Bit field size in bits for I2C_C1_MST. */
 468
 469 /*! @brief Read current value of the I2C_C1_MST field. */
 470 #define BR_I2C_C1_MST(x)     (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_MST))
 471
 472 /*! @brief Format value for bitfield I2C_C1_MST. */
 473 #define BF_I2C_C1_MST(v)     ((uint8_t)((uint8_t)(v) << BP_I2C_C1_MST) & BM_I2C_C1_MST)
 474
 475 /*! @brief Set the MST field to a new value. */
 476 #define BW_I2C_C1_MST(x, v)  (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_MST) = (v))
 477 /*@}*/
 478
 479 /*!
 480  * @name Register I2C_C1, field IICIE[6] (RW)
 481  *
 482  * Enables I2C interrupt requests.
 483  *
 484  * Values:
 485  * - 0 - Disabled
 486  * - 1 - Enabled
 487  */
 488 /*@{*/
 489 #define BP_I2C_C1_IICIE      (6U)          /*!< Bit position for I2C_C1_IICIE. */
 490 #define BM_I2C_C1_IICIE      (0x40U)       /*!< Bit mask for I2C_C1_IICIE. */
 491 #define BS_I2C_C1_IICIE      (1U)          /*!< Bit field size in bits for I2C_C1_IICIE. */
 492
 493 /*! @brief Read current value of the I2C_C1_IICIE field. */
 494 #define BR_I2C_C1_IICIE(x)   (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICIE))
 495
 496 /*! @brief Format value for bitfield I2C_C1_IICIE. */
 497 #define BF_I2C_C1_IICIE(v)   ((uint8_t)((uint8_t)(v) << BP_I2C_C1_IICIE) & BM_I2C_C1_IICIE)
 498
 499 /*! @brief Set the IICIE field to a new value. */
 500 #define BW_I2C_C1_IICIE(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICIE) = (v))
 501 /*@}*/
 502
 503 /*!
 504  * @name Register I2C_C1, field IICEN[7] (RW)
 505  *
 506  * Enables I2C module operation.
 507  *
 508  * Values:
 509  * - 0 - Disabled
 510  * - 1 - Enabled
 511  */
 512 /*@{*/
 513 #define BP_I2C_C1_IICEN      (7U)          /*!< Bit position for I2C_C1_IICEN. */
 514 #define BM_I2C_C1_IICEN      (0x80U)       /*!< Bit mask for I2C_C1_IICEN. */
 515 #define BS_I2C_C1_IICEN      (1U)          /*!< Bit field size in bits for I2C_C1_IICEN. */
 516
 517 /*! @brief Read current value of the I2C_C1_IICEN field. */
 518 #define BR_I2C_C1_IICEN(x)   (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICEN))
 519
 520 /*! @brief Format value for bitfield I2C_C1_IICEN. */
 521 #define BF_I2C_C1_IICEN(v)   ((uint8_t)((uint8_t)(v) << BP_I2C_C1_IICEN) & BM_I2C_C1_IICEN)
 522
 523 /*! @brief Set the IICEN field to a new value. */
 524 #define BW_I2C_C1_IICEN(x, v) (BITBAND_ACCESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICEN) = (v))
 525 /*@}*/
 526
 527 /*******************************************************************************
 528  * HW_I2C_S - I2C Status register
 529  ******************************************************************************/
 530
 531 /*!
 532  * @brief HW_I2C_S - I2C Status register (RW)
 533  *
 534  * Reset value: 0x80U
 535  */
 536 typedef union _hw_i2c_s
 537 {
 538     uint8_t U;
 539     struct _hw_i2c_s_bitfields
 540     {
 541         uint8_t RXAK : 1;              /*!< [0] Receive Acknowledge */
 542         uint8_t IICIF : 1;             /*!< [1] Interrupt Flag */
 543         uint8_t SRW : 1;               /*!< [2] Slave Read/Write */
 544         uint8_t RAM : 1;               /*!< [3] Range Address Match */
 545         uint8_t ARBL : 1;              /*!< [4] Arbitration Lost */
 546         uint8_t BUSY : 1;              /*!< [5] Bus Busy */
 547         uint8_t IAAS : 1;              /*!< [6] Addressed As A Slave */
 548         uint8_t TCF : 1;               /*!< [7] Transfer Complete Flag */
 549     } B;
 550 } hw_i2c_s_t;
 551
 552 /*!
 553  * @name Constants and macros for entire I2C_S register
 554  */
 555 /*@{*/
 556 #define HW_I2C_S_ADDR(x)         ((x) + 0x3U)
 557
 558 #define HW_I2C_S(x)              (*(__IO hw_i2c_s_t *) HW_I2C_S_ADDR(x))
 559 #define HW_I2C_S_RD(x)           (HW_I2C_S(x).U)
 560 #define HW_I2C_S_WR(x, v)        (HW_I2C_S(x).U = (v))
 561 #define HW_I2C_S_SET(x, v)       (HW_I2C_S_WR(x, HW_I2C_S_RD(x) |  (v)))
 562 #define HW_I2C_S_CLR(x, v)       (HW_I2C_S_WR(x, HW_I2C_S_RD(x) & ~(v)))
 563 #define HW_I2C_S_TOG(x, v)       (HW_I2C_S_WR(x, HW_I2C_S_RD(x) ^  (v)))
 564 /*@}*/
 565
 566 /*
 567  * Constants & macros for individual I2C_S bitfields
 568  */
 569
 570 /*!
 571  * @name Register I2C_S, field RXAK[0] (RO)
 572  *
 573  * Values:
 574  * - 0 - Acknowledge signal was received after the completion of one byte of
 575  *     data transmission on the bus
 576  * - 1 - No acknowledge signal detected
 577  */
 578 /*@{*/
 579 #define BP_I2C_S_RXAK        (0U)          /*!< Bit position for I2C_S_RXAK. */
 580 #define BM_I2C_S_RXAK        (0x01U)       /*!< Bit mask for I2C_S_RXAK. */
 581 #define BS_I2C_S_RXAK        (1U)          /*!< Bit field size in bits for I2C_S_RXAK. */
 582
 583 /*! @brief Read current value of the I2C_S_RXAK field. */
 584 #define BR_I2C_S_RXAK(x)     (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_RXAK))
 585 /*@}*/
 586
 587 /*!
 588  * @name Register I2C_S, field IICIF[1] (W1C)
 589  *
 590  * This bit sets when an interrupt is pending. This bit must be cleared by
 591  * software by writing 1 to it, such as in the interrupt routine. One of the following
 592  * events can set this bit: One byte transfer, including ACK/NACK bit, completes
 593  * if FACK is 0. An ACK or NACK is sent on the bus by writing 0 or 1 to TXAK
 594  * after this bit is set in receive mode. One byte transfer, excluding ACK/NACK bit,
 595  * completes if FACK is 1. Match of slave address to calling address including
 596  * primary slave address, range slave address , alert response address, second
 597  * slave address, or general call address. Arbitration lost In SMBus mode, any
 598  * timeouts except SCL and SDA high timeouts I2C bus stop or start detection if the
 599  * SSIE bit in the Input Glitch Filter register is 1 To clear the I2C bus stop or
 600  * start detection interrupt: In the interrupt service routine, first clear the
 601  * STOPF or STARTF bit in the Input Glitch Filter register by writing 1 to it, and
 602  * then clear the IICIF bit. If this sequence is reversed, the IICIF bit is
 603  * asserted again.
 604  *
 605  * Values:
 606  * - 0 - No interrupt pending
 607  * - 1 - Interrupt pending
 608  */
 609 /*@{*/
 610 #define BP_I2C_S_IICIF       (1U)          /*!< Bit position for I2C_S_IICIF. */
 611 #define BM_I2C_S_IICIF       (0x02U)       /*!< Bit mask for I2C_S_IICIF. */
 612 #define BS_I2C_S_IICIF       (1U)          /*!< Bit field size in bits for I2C_S_IICIF. */
 613
 614 /*! @brief Read current value of the I2C_S_IICIF field. */
 615 #define BR_I2C_S_IICIF(x)    (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IICIF))
 616
 617 /*! @brief Format value for bitfield I2C_S_IICIF. */
 618 #define BF_I2C_S_IICIF(v)    ((uint8_t)((uint8_t)(v) << BP_I2C_S_IICIF) & BM_I2C_S_IICIF)
 619
 620 /*! @brief Set the IICIF field to a new value. */
 621 #define BW_I2C_S_IICIF(x, v) (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IICIF) = (v))
 622 /*@}*/
 623
 624 /*!
 625  * @name Register I2C_S, field SRW[2] (RO)
 626  *
 627  * When addressed as a slave, SRW indicates the value of the R/W command bit of
 628  * the calling address sent to the master.
 629  *
 630  * Values:
 631  * - 0 - Slave receive, master writing to slave
 632  * - 1 - Slave transmit, master reading from slave
 633  */
 634 /*@{*/
 635 #define BP_I2C_S_SRW         (2U)          /*!< Bit position for I2C_S_SRW. */
 636 #define BM_I2C_S_SRW         (0x04U)       /*!< Bit mask for I2C_S_SRW. */
 637 #define BS_I2C_S_SRW         (1U)          /*!< Bit field size in bits for I2C_S_SRW. */
 638
 639 /*! @brief Read current value of the I2C_S_SRW field. */
 640 #define BR_I2C_S_SRW(x)      (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_SRW))
 641 /*@}*/
 642
 643 /*!
 644  * @name Register I2C_S, field RAM[3] (RW)
 645  *
 646  * This bit is set to 1 by any of the following conditions, if I2C_C2[RMEN] = 1:
 647  * Any nonzero calling address is received that matches the address in the RA
 648  * register. The calling address is within the range of values of the A1 and RA
 649  * registers. For the RAM bit to be set to 1 correctly, C1[IICIE] must be set to 1.
 650  * Writing the C1 register with any value clears this bit to 0.
 651  *
 652  * Values:
 653  * - 0 - Not addressed
 654  * - 1 - Addressed as a slave
 655  */
 656 /*@{*/
 657 #define BP_I2C_S_RAM         (3U)          /*!< Bit position for I2C_S_RAM. */
 658 #define BM_I2C_S_RAM         (0x08U)       /*!< Bit mask for I2C_S_RAM. */
 659 #define BS_I2C_S_RAM         (1U)          /*!< Bit field size in bits for I2C_S_RAM. */
 660
 661 /*! @brief Read current value of the I2C_S_RAM field. */
 662 #define BR_I2C_S_RAM(x)      (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_RAM))
 663
 664 /*! @brief Format value for bitfield I2C_S_RAM. */
 665 #define BF_I2C_S_RAM(v)      ((uint8_t)((uint8_t)(v) << BP_I2C_S_RAM) & BM_I2C_S_RAM)
 666
 667 /*! @brief Set the RAM field to a new value. */
 668 #define BW_I2C_S_RAM(x, v)   (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_RAM) = (v))
 669 /*@}*/
 670
 671 /*!
 672  * @name Register I2C_S, field ARBL[4] (W1C)
 673  *
 674  * This bit is set by hardware when the arbitration procedure is lost. The ARBL
 675  * bit must be cleared by software, by writing 1 to it.
 676  *
 677  * Values:
 678  * - 0 - Standard bus operation.
 679  * - 1 - Loss of arbitration.
 680  */
 681 /*@{*/
 682 #define BP_I2C_S_ARBL        (4U)          /*!< Bit position for I2C_S_ARBL. */
 683 #define BM_I2C_S_ARBL        (0x10U)       /*!< Bit mask for I2C_S_ARBL. */
 684 #define BS_I2C_S_ARBL        (1U)          /*!< Bit field size in bits for I2C_S_ARBL. */
 685
 686 /*! @brief Read current value of the I2C_S_ARBL field. */
 687 #define BR_I2C_S_ARBL(x)     (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_ARBL))
 688
 689 /*! @brief Format value for bitfield I2C_S_ARBL. */
 690 #define BF_I2C_S_ARBL(v)     ((uint8_t)((uint8_t)(v) << BP_I2C_S_ARBL) & BM_I2C_S_ARBL)
 691
 692 /*! @brief Set the ARBL field to a new value. */
 693 #define BW_I2C_S_ARBL(x, v)  (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_ARBL) = (v))
 694 /*@}*/
 695
 696 /*!
 697  * @name Register I2C_S, field BUSY[5] (RO)
 698  *
 699  * Indicates the status of the bus regardless of slave or master mode. This bit
 700  * is set when a START signal is detected and cleared when a STOP signal is
 701  * detected.
 702  *
 703  * Values:
 704  * - 0 - Bus is idle
 705  * - 1 - Bus is busy
 706  */
 707 /*@{*/
 708 #define BP_I2C_S_BUSY        (5U)          /*!< Bit position for I2C_S_BUSY. */
 709 #define BM_I2C_S_BUSY        (0x20U)       /*!< Bit mask for I2C_S_BUSY. */
 710 #define BS_I2C_S_BUSY        (1U)          /*!< Bit field size in bits for I2C_S_BUSY. */
 711
 712 /*! @brief Read current value of the I2C_S_BUSY field. */
 713 #define BR_I2C_S_BUSY(x)     (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_BUSY))
 714 /*@}*/
 715
 716 /*!
 717  * @name Register I2C_S, field IAAS[6] (RW)
 718  *
 719  * This bit is set by one of the following conditions: The calling address
 720  * matches the programmed primary slave address in the A1 register, or matches the
 721  * range address in the RA register (which must be set to a nonzero value and under
 722  * the condition I2C_C2[RMEN] = 1). C2[GCAEN] is set and a general call is
 723  * received. SMB[SIICAEN] is set and the calling address matches the second programmed
 724  * slave address. ALERTEN is set and an SMBus alert response address is received
 725  * RMEN is set and an address is received that is within the range between the
 726  * values of the A1 and RA registers. IAAS sets before the ACK bit. The CPU must
 727  * check the SRW bit and set TX/RX accordingly. Writing the C1 register with any
 728  * value clears this bit.
 729  *
 730  * Values:
 731  * - 0 - Not addressed
 732  * - 1 - Addressed as a slave
 733  */
 734 /*@{*/
 735 #define BP_I2C_S_IAAS        (6U)          /*!< Bit position for I2C_S_IAAS. */
 736 #define BM_I2C_S_IAAS        (0x40U)       /*!< Bit mask for I2C_S_IAAS. */
 737 #define BS_I2C_S_IAAS        (1U)          /*!< Bit field size in bits for I2C_S_IAAS. */
 738
 739 /*! @brief Read current value of the I2C_S_IAAS field. */
 740 #define BR_I2C_S_IAAS(x)     (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IAAS))
 741
 742 /*! @brief Format value for bitfield I2C_S_IAAS. */
 743 #define BF_I2C_S_IAAS(v)     ((uint8_t)((uint8_t)(v) << BP_I2C_S_IAAS) & BM_I2C_S_IAAS)
 744
 745 /*! @brief Set the IAAS field to a new value. */
 746 #define BW_I2C_S_IAAS(x, v)  (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IAAS) = (v))
 747 /*@}*/
 748
 749 /*!
 750  * @name Register I2C_S, field TCF[7] (RO)
 751  *
 752  * Acknowledges a byte transfer; TCF sets on the completion of a byte transfer.
 753  * This bit is valid only during or immediately following a transfer to or from
 754  * the I2C module. TCF is cleared by reading the I2C data register in receive mode
 755  * or by writing to the I2C data register in transmit mode.
 756  *
 757  * Values:
 758  * - 0 - Transfer in progress
 759  * - 1 - Transfer complete
 760  */
 761 /*@{*/
 762 #define BP_I2C_S_TCF         (7U)          /*!< Bit position for I2C_S_TCF. */
 763 #define BM_I2C_S_TCF         (0x80U)       /*!< Bit mask for I2C_S_TCF. */
 764 #define BS_I2C_S_TCF         (1U)          /*!< Bit field size in bits for I2C_S_TCF. */
 765
 766 /*! @brief Read current value of the I2C_S_TCF field. */
 767 #define BR_I2C_S_TCF(x)      (BITBAND_ACCESS8(HW_I2C_S_ADDR(x), BP_I2C_S_TCF))
 768 /*@}*/
 769
 770 /*******************************************************************************
 771  * HW_I2C_D - I2C Data I/O register
 772  ******************************************************************************/
 773
 774 /*!
 775  * @brief HW_I2C_D - I2C Data I/O register (RW)
 776  *
 777  * Reset value: 0x00U
 778  */
 779 typedef union _hw_i2c_d
 780 {
 781     uint8_t U;
 782     struct _hw_i2c_d_bitfields
 783     {
 784         uint8_t DATA : 8;              /*!< [7:0] Data */
 785     } B;
 786 } hw_i2c_d_t;
 787
 788 /*!
 789  * @name Constants and macros for entire I2C_D register
 790  */
 791 /*@{*/
 792 #define HW_I2C_D_ADDR(x)         ((x) + 0x4U)
 793
 794 #define HW_I2C_D(x)              (*(__IO hw_i2c_d_t *) HW_I2C_D_ADDR(x))
 795 #define HW_I2C_D_RD(x)           (HW_I2C_D(x).U)
 796 #define HW_I2C_D_WR(x, v)        (HW_I2C_D(x).U = (v))
 797 #define HW_I2C_D_SET(x, v)       (HW_I2C_D_WR(x, HW_I2C_D_RD(x) |  (v)))
 798 #define HW_I2C_D_CLR(x, v)       (HW_I2C_D_WR(x, HW_I2C_D_RD(x) & ~(v)))
 799 #define HW_I2C_D_TOG(x, v)       (HW_I2C_D_WR(x, HW_I2C_D_RD(x) ^  (v)))
 800 /*@}*/
 801
 802 /*
 803  * Constants & macros for individual I2C_D bitfields
 804  */
 805
 806 /*!
 807  * @name Register I2C_D, field DATA[7:0] (RW)
 808  *
 809  * In master transmit mode, when data is written to this register, a data
 810  * transfer is initiated. The most significant bit is sent first. In master receive
 811  * mode, reading this register initiates receiving of the next byte of data. When
 812  * making the transition out of master receive mode, switch the I2C mode before
 813  * reading the Data register to prevent an inadvertent initiation of a master
 814  * receive data transfer. In slave mode, the same functions are available after an
 815  * address match occurs. The C1[TX] bit must correctly reflect the desired direction
 816  * of transfer in master and slave modes for the transmission to begin. For
 817  * example, if the I2C module is configured for master transmit but a master receive
 818  * is desired, reading the Data register does not initiate the receive. Reading
 819  * the Data register returns the last byte received while the I2C module is
 820  * configured in master receive or slave receive mode. The Data register does not
 821  * reflect every byte that is transmitted on the I2C bus, and neither can software
 822  * verify that a byte has been written to the Data register correctly by reading it
 823  * back. In master transmit mode, the first byte of data written to the Data
 824  * register following assertion of MST (start bit) or assertion of RSTA (repeated
 825  * start bit) is used for the address transfer and must consist of the calling
 826  * address (in bits 7-1) concatenated with the required R/W bit (in position bit 0).
 827  */
 828 /*@{*/
 829 #define BP_I2C_D_DATA        (0U)          /*!< Bit position for I2C_D_DATA. */
 830 #define BM_I2C_D_DATA        (0xFFU)       /*!< Bit mask for I2C_D_DATA. */
 831 #define BS_I2C_D_DATA        (8U)          /*!< Bit field size in bits for I2C_D_DATA. */
 832
 833 /*! @brief Read current value of the I2C_D_DATA field. */
 834 #define BR_I2C_D_DATA(x)     (HW_I2C_D(x).U)
 835
 836 /*! @brief Format value for bitfield I2C_D_DATA. */
 837 #define BF_I2C_D_DATA(v)     ((uint8_t)((uint8_t)(v) << BP_I2C_D_DATA) & BM_I2C_D_DATA)
 838
 839 /*! @brief Set the DATA field to a new value. */
 840 #define BW_I2C_D_DATA(x, v)  (HW_I2C_D_WR(x, v))
 841 /*@}*/
 842
 843 /*******************************************************************************
 844  * HW_I2C_C2 - I2C Control Register 2
 845  ******************************************************************************/
 846
 847 /*!
 848  * @brief HW_I2C_C2 - I2C Control Register 2 (RW)
 849  *
 850  * Reset value: 0x00U
 851  */
 852 typedef union _hw_i2c_c2
 853 {
 854     uint8_t U;
 855     struct _hw_i2c_c2_bitfields
 856     {
 857         uint8_t AD : 3;                /*!< [2:0] Slave Address */
 858         uint8_t RMEN : 1;              /*!< [3] Range Address Matching Enable */
 859         uint8_t SBRC : 1;              /*!< [4] Slave Baud Rate Control */
 860         uint8_t HDRS : 1;              /*!< [5] High Drive Select */
 861         uint8_t ADEXT : 1;             /*!< [6] Address Extension */
 862         uint8_t GCAEN : 1;             /*!< [7] General Call Address Enable */
 863     } B;
 864 } hw_i2c_c2_t;
 865
 866 /*!
 867  * @name Constants and macros for entire I2C_C2 register
 868  */
 869 /*@{*/
 870 #define HW_I2C_C2_ADDR(x)        ((x) + 0x5U)
 871
 872 #define HW_I2C_C2(x)             (*(__IO hw_i2c_c2_t *) HW_I2C_C2_ADDR(x))
 873 #define HW_I2C_C2_RD(x)          (HW_I2C_C2(x).U)
 874 #define HW_I2C_C2_WR(x, v)       (HW_I2C_C2(x).U = (v))
 875 #define HW_I2C_C2_SET(x, v)      (HW_I2C_C2_WR(x, HW_I2C_C2_RD(x) |  (v)))
 876 #define HW_I2C_C2_CLR(x, v)      (HW_I2C_C2_WR(x, HW_I2C_C2_RD(x) & ~(v)))
 877 #define HW_I2C_C2_TOG(x, v)      (HW_I2C_C2_WR(x, HW_I2C_C2_RD(x) ^  (v)))
 878 /*@}*/
 879
 880 /*
 881  * Constants & macros for individual I2C_C2 bitfields
 882  */
 883
 884 /*!
 885  * @name Register I2C_C2, field AD[2:0] (RW)
 886  *
 887  * Contains the upper three bits of the slave address in the 10-bit address
 888  * scheme. This field is valid only while the ADEXT bit is set.
 889  */
 890 /*@{*/
 891 #define BP_I2C_C2_AD         (0U)          /*!< Bit position for I2C_C2_AD. */
 892 #define BM_I2C_C2_AD         (0x07U)       /*!< Bit mask for I2C_C2_AD. */
 893 #define BS_I2C_C2_AD         (3U)          /*!< Bit field size in bits for I2C_C2_AD. */
 894
 895 /*! @brief Read current value of the I2C_C2_AD field. */
 896 #define BR_I2C_C2_AD(x)      (HW_I2C_C2(x).B.AD)
 897
 898 /*! @brief Format value for bitfield I2C_C2_AD. */
 899 #define BF_I2C_C2_AD(v)      ((uint8_t)((uint8_t)(v) << BP_I2C_C2_AD) & BM_I2C_C2_AD)
 900
 901 /*! @brief Set the AD field to a new value. */
 902 #define BW_I2C_C2_AD(x, v)   (HW_I2C_C2_WR(x, (HW_I2C_C2_RD(x) & ~BM_I2C_C2_AD) | BF_I2C_C2_AD(v)))
 903 /*@}*/
 904
 905 /*!
 906  * @name Register I2C_C2, field RMEN[3] (RW)
 907  *
 908  * This bit controls the slave address matching for addresses between the values
 909  * of the A1 and RA registers. When this bit is set, a slave address matching
 910  * occurs for any address greater than the value of the A1 register and less than
 911  * or equal to the value of the RA register.
 912  *
 913  * Values:
 914  * - 0 - Range mode disabled. No address matching occurs for an address within
 915  *     the range of values of the A1 and RA registers.
 916  * - 1 - Range mode enabled. Address matching occurs when a slave receives an
 917  *     address within the range of values of the A1 and RA registers.
 918  */
 919 /*@{*/
 920 #define BP_I2C_C2_RMEN       (3U)          /*!< Bit position for I2C_C2_RMEN. */
 921 #define BM_I2C_C2_RMEN       (0x08U)       /*!< Bit mask for I2C_C2_RMEN. */
 922 #define BS_I2C_C2_RMEN       (1U)          /*!< Bit field size in bits for I2C_C2_RMEN. */
 923
 924 /*! @brief Read current value of the I2C_C2_RMEN field. */
 925 #define BR_I2C_C2_RMEN(x)    (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_RMEN))
 926
 927 /*! @brief Format value for bitfield I2C_C2_RMEN. */
 928 #define BF_I2C_C2_RMEN(v)    ((uint8_t)((uint8_t)(v) << BP_I2C_C2_RMEN) & BM_I2C_C2_RMEN)
 929
 930 /*! @brief Set the RMEN field to a new value. */
 931 #define BW_I2C_C2_RMEN(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_RMEN) = (v))
 932 /*@}*/
 933
 934 /*!
 935  * @name Register I2C_C2, field SBRC[4] (RW)
 936  *
 937  * Enables independent slave mode baud rate at maximum frequency, which forces
 938  * clock stretching on SCL in very fast I2C modes. To a slave, an example of a
 939  * "very fast" mode is when the master transfers at 40 kbit/s but the slave can
 940  * capture the master's data at only 10 kbit/s.
 941  *
 942  * Values:
 943  * - 0 - The slave baud rate follows the master baud rate and clock stretching
 944  *     may occur
 945  * - 1 - Slave baud rate is independent of the master baud rate
 946  */
 947 /*@{*/
 948 #define BP_I2C_C2_SBRC       (4U)          /*!< Bit position for I2C_C2_SBRC. */
 949 #define BM_I2C_C2_SBRC       (0x10U)       /*!< Bit mask for I2C_C2_SBRC. */
 950 #define BS_I2C_C2_SBRC       (1U)          /*!< Bit field size in bits for I2C_C2_SBRC. */
 951
 952 /*! @brief Read current value of the I2C_C2_SBRC field. */
 953 #define BR_I2C_C2_SBRC(x)    (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_SBRC))
 954
 955 /*! @brief Format value for bitfield I2C_C2_SBRC. */
 956 #define BF_I2C_C2_SBRC(v)    ((uint8_t)((uint8_t)(v) << BP_I2C_C2_SBRC) & BM_I2C_C2_SBRC)
 957
 958 /*! @brief Set the SBRC field to a new value. */
 959 #define BW_I2C_C2_SBRC(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_SBRC) = (v))
 960 /*@}*/
 961
 962 /*!
 963  * @name Register I2C_C2, field HDRS[5] (RW)
 964  *
 965  * Controls the drive capability of the I2C pads.
 966  *
 967  * Values:
 968  * - 0 - Normal drive mode
 969  * - 1 - High drive mode
 970  */
 971 /*@{*/
 972 #define BP_I2C_C2_HDRS       (5U)          /*!< Bit position for I2C_C2_HDRS. */
 973 #define BM_I2C_C2_HDRS       (0x20U)       /*!< Bit mask for I2C_C2_HDRS. */
 974 #define BS_I2C_C2_HDRS       (1U)          /*!< Bit field size in bits for I2C_C2_HDRS. */
 975
 976 /*! @brief Read current value of the I2C_C2_HDRS field. */
 977 #define BR_I2C_C2_HDRS(x)    (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_HDRS))
 978
 979 /*! @brief Format value for bitfield I2C_C2_HDRS. */
 980 #define BF_I2C_C2_HDRS(v)    ((uint8_t)((uint8_t)(v) << BP_I2C_C2_HDRS) & BM_I2C_C2_HDRS)
 981
 982 /*! @brief Set the HDRS field to a new value. */
 983 #define BW_I2C_C2_HDRS(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_HDRS) = (v))
 984 /*@}*/
 985
 986 /*!
 987  * @name Register I2C_C2, field ADEXT[6] (RW)
 988  *
 989  * Controls the number of bits used for the slave address.
 990  *
 991  * Values:
 992  * - 0 - 7-bit address scheme
 993  * - 1 - 10-bit address scheme
 994  */
 995 /*@{*/
 996 #define BP_I2C_C2_ADEXT      (6U)          /*!< Bit position for I2C_C2_ADEXT. */
 997 #define BM_I2C_C2_ADEXT      (0x40U)       /*!< Bit mask for I2C_C2_ADEXT. */
 998 #define BS_I2C_C2_ADEXT      (1U)          /*!< Bit field size in bits for I2C_C2_ADEXT. */
 999
1000 /*! @brief Read current value of the I2C_C2_ADEXT field. */
1001 #define BR_I2C_C2_ADEXT(x)   (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_ADEXT))
1002
1003 /*! @brief Format value for bitfield I2C_C2_ADEXT. */
1004 #define BF_I2C_C2_ADEXT(v)   ((uint8_t)((uint8_t)(v) << BP_I2C_C2_ADEXT) & BM_I2C_C2_ADEXT)
1005
1006 /*! @brief Set the ADEXT field to a new value. */
1007 #define BW_I2C_C2_ADEXT(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_ADEXT) = (v))
1008 /*@}*/
1009
1010 /*!
1011  * @name Register I2C_C2, field GCAEN[7] (RW)
1012  *
1013  * Enables general call address.
1014  *
1015  * Values:
1016  * - 0 - Disabled
1017  * - 1 - Enabled
1018  */
1019 /*@{*/
1020 #define BP_I2C_C2_GCAEN      (7U)          /*!< Bit position for I2C_C2_GCAEN. */
1021 #define BM_I2C_C2_GCAEN      (0x80U)       /*!< Bit mask for I2C_C2_GCAEN. */
1022 #define BS_I2C_C2_GCAEN      (1U)          /*!< Bit field size in bits for I2C_C2_GCAEN. */
1023
1024 /*! @brief Read current value of the I2C_C2_GCAEN field. */
1025 #define BR_I2C_C2_GCAEN(x)   (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_GCAEN))
1026
1027 /*! @brief Format value for bitfield I2C_C2_GCAEN. */
1028 #define BF_I2C_C2_GCAEN(v)   ((uint8_t)((uint8_t)(v) << BP_I2C_C2_GCAEN) & BM_I2C_C2_GCAEN)
1029
1030 /*! @brief Set the GCAEN field to a new value. */
1031 #define BW_I2C_C2_GCAEN(x, v) (BITBAND_ACCESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_GCAEN) = (v))
1032 /*@}*/
1033
1034 /*******************************************************************************
1035  * HW_I2C_FLT - I2C Programmable Input Glitch Filter register
1036  ******************************************************************************/
1037
1038 /*!
1039  * @brief HW_I2C_FLT - I2C Programmable Input Glitch Filter register (RW)
1040  *
1041  * Reset value: 0x00U
1042  */
1043 typedef union _hw_i2c_flt
1044 {
1045     uint8_t U;
1046     struct _hw_i2c_flt_bitfields
1047     {
1048         uint8_t FLT : 4;               /*!< [3:0] I2C Programmable Filter Factor */
1049         uint8_t STARTF : 1;            /*!< [4] I2C Bus Start Detect Flag */
1050         uint8_t SSIE : 1;              /*!< [5] I2C Bus Stop or Start Interrupt Enable */
1051         uint8_t STOPF : 1;             /*!< [6] I2C Bus Stop Detect Flag */
1052         uint8_t SHEN : 1;              /*!< [7] Stop Hold Enable */
1053     } B;
1054 } hw_i2c_flt_t;
1055
1056 /*!
1057  * @name Constants and macros for entire I2C_FLT register
1058  */
1059 /*@{*/
1060 #define HW_I2C_FLT_ADDR(x)       ((x) + 0x6U)
1061
1062 #define HW_I2C_FLT(x)            (*(__IO hw_i2c_flt_t *) HW_I2C_FLT_ADDR(x))
1063 #define HW_I2C_FLT_RD(x)         (HW_I2C_FLT(x).U)
1064 #define HW_I2C_FLT_WR(x, v)      (HW_I2C_FLT(x).U = (v))
1065 #define HW_I2C_FLT_SET(x, v)     (HW_I2C_FLT_WR(x, HW_I2C_FLT_RD(x) |  (v)))
1066 #define HW_I2C_FLT_CLR(x, v)     (HW_I2C_FLT_WR(x, HW_I2C_FLT_RD(x) & ~(v)))
1067 #define HW_I2C_FLT_TOG(x, v)     (HW_I2C_FLT_WR(x, HW_I2C_FLT_RD(x) ^  (v)))
1068 /*@}*/
1069
1070 /*
1071  * Constants & macros for individual I2C_FLT bitfields
1072  */
1073
1074 /*!
1075  * @name Register I2C_FLT, field FLT[3:0] (RW)
1076  *
1077  * Controls the width of the glitch, in terms of I2C module clock cycles, that
1078  * the filter must absorb. For any glitch whose size is less than or equal to this
1079  * width setting, the filter does not allow the glitch to pass.
1080  *
1081  * Values:
1082  * - 0 - No filter/bypass
1083  */
1084 /*@{*/
1085 #define BP_I2C_FLT_FLT       (0U)          /*!< Bit position for I2C_FLT_FLT. */
1086 #define BM_I2C_FLT_FLT       (0x0FU)       /*!< Bit mask for I2C_FLT_FLT. */
1087 #define BS_I2C_FLT_FLT       (4U)          /*!< Bit field size in bits for I2C_FLT_FLT. */
1088
1089 /*! @brief Read current value of the I2C_FLT_FLT field. */
1090 #define BR_I2C_FLT_FLT(x)    (HW_I2C_FLT(x).B.FLT)
1091
1092 /*! @brief Format value for bitfield I2C_FLT_FLT. */
1093 #define BF_I2C_FLT_FLT(v)    ((uint8_t)((uint8_t)(v) << BP_I2C_FLT_FLT) & BM_I2C_FLT_FLT)
1094
1095 /*! @brief Set the FLT field to a new value. */
1096 #define BW_I2C_FLT_FLT(x, v) (HW_I2C_FLT_WR(x, (HW_I2C_FLT_RD(x) & ~BM_I2C_FLT_FLT) | BF_I2C_FLT_FLT(v)))
1097 /*@}*/
1098
1099 /*!
1100  * @name Register I2C_FLT, field STARTF[4] (W1C)
1101  *
1102  * Hardware sets this bit when the I2C bus's start status is detected. The
1103  * STARTF bit must be cleared by writing 1 to it.
1104  *
1105  * Values:
1106  * - 0 - No start happens on I2C bus
1107  * - 1 - Start detected on I2C bus
1108  */
1109 /*@{*/
1110 #define BP_I2C_FLT_STARTF    (4U)          /*!< Bit position for I2C_FLT_STARTF. */
1111 #define BM_I2C_FLT_STARTF    (0x10U)       /*!< Bit mask for I2C_FLT_STARTF. */
1112 #define BS_I2C_FLT_STARTF    (1U)          /*!< Bit field size in bits for I2C_FLT_STARTF. */
1113
1114 /*! @brief Read current value of the I2C_FLT_STARTF field. */
1115 #define BR_I2C_FLT_STARTF(x) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STARTF))
1116
1117 /*! @brief Format value for bitfield I2C_FLT_STARTF. */
1118 #define BF_I2C_FLT_STARTF(v) ((uint8_t)((uint8_t)(v) << BP_I2C_FLT_STARTF) & BM_I2C_FLT_STARTF)
1119
1120 /*! @brief Set the STARTF field to a new value. */
1121 #define BW_I2C_FLT_STARTF(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STARTF) = (v))
1122 /*@}*/
1123
1124 /*!
1125  * @name Register I2C_FLT, field SSIE[5] (RW)
1126  *
1127  * This bit enables the interrupt for I2C bus stop or start detection. To clear
1128  * the I2C bus stop or start detection interrupt: In the interrupt service
1129  * routine, first clear the STOPF or STARTF bit by writing 1 to it, and then clear the
1130  * IICIF bit in the status register. If this sequence is reversed, the IICIF bit
1131  * is asserted again.
1132  *
1133  * Values:
1134  * - 0 - Stop or start detection interrupt is disabled
1135  * - 1 - Stop or start detection interrupt is enabled
1136  */
1137 /*@{*/
1138 #define BP_I2C_FLT_SSIE      (5U)          /*!< Bit position for I2C_FLT_SSIE. */
1139 #define BM_I2C_FLT_SSIE      (0x20U)       /*!< Bit mask for I2C_FLT_SSIE. */
1140 #define BS_I2C_FLT_SSIE      (1U)          /*!< Bit field size in bits for I2C_FLT_SSIE. */
1141
1142 /*! @brief Read current value of the I2C_FLT_SSIE field. */
1143 #define BR_I2C_FLT_SSIE(x)   (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SSIE))
1144
1145 /*! @brief Format value for bitfield I2C_FLT_SSIE. */
1146 #define BF_I2C_FLT_SSIE(v)   ((uint8_t)((uint8_t)(v) << BP_I2C_FLT_SSIE) & BM_I2C_FLT_SSIE)
1147
1148 /*! @brief Set the SSIE field to a new value. */
1149 #define BW_I2C_FLT_SSIE(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SSIE) = (v))
1150 /*@}*/
1151
1152 /*!
1153  * @name Register I2C_FLT, field STOPF[6] (W1C)
1154  *
1155  * Hardware sets this bit when the I2C bus's stop status is detected. The STOPF
1156  * bit must be cleared by writing 1 to it.
1157  *
1158  * Values:
1159  * - 0 - No stop happens on I2C bus
1160  * - 1 - Stop detected on I2C bus
1161  */
1162 /*@{*/
1163 #define BP_I2C_FLT_STOPF     (6U)          /*!< Bit position for I2C_FLT_STOPF. */
1164 #define BM_I2C_FLT_STOPF     (0x40U)       /*!< Bit mask for I2C_FLT_STOPF. */
1165 #define BS_I2C_FLT_STOPF     (1U)          /*!< Bit field size in bits for I2C_FLT_STOPF. */
1166
1167 /*! @brief Read current value of the I2C_FLT_STOPF field. */
1168 #define BR_I2C_FLT_STOPF(x)  (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STOPF))
1169
1170 /*! @brief Format value for bitfield I2C_FLT_STOPF. */
1171 #define BF_I2C_FLT_STOPF(v)  ((uint8_t)((uint8_t)(v) << BP_I2C_FLT_STOPF) & BM_I2C_FLT_STOPF)
1172
1173 /*! @brief Set the STOPF field to a new value. */
1174 #define BW_I2C_FLT_STOPF(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STOPF) = (v))
1175 /*@}*/
1176
1177 /*!
1178  * @name Register I2C_FLT, field SHEN[7] (RW)
1179  *
1180  * Set this bit to hold off entry to stop mode when any data transmission or
1181  * reception is occurring. The following scenario explains the holdoff
1182  * functionality: The I2C module is configured for a basic transfer, and the SHEN bit is set
1183  * to 1. A transfer begins. The MCU signals the I2C module to enter stop mode. The
1184  * byte currently being transferred, including both address and data, completes
1185  * its transfer. The I2C slave or master acknowledges that the in-transfer byte
1186  * completed its transfer and acknowledges the request to enter stop mode. After
1187  * receiving the I2C module's acknowledgment of the request to enter stop mode,
1188  * the MCU determines whether to shut off the I2C module's clock. If the SHEN bit
1189  * is set to 1 and the I2C module is in an idle or disabled state when the MCU
1190  * signals to enter stop mode, the module immediately acknowledges the request to
1191  * enter stop mode. If SHEN is cleared to 0 and the overall data transmission or
1192  * reception that was suspended by stop mode entry was incomplete: To resume the
1193  * overall transmission or reception after the MCU exits stop mode, software must
1194  * reinitialize the transfer by resending the address of the slave. If the I2C
1195  * Control Register 1's IICIE bit was set to 1 before the MCU entered stop mode,
1196  * system software will receive the interrupt triggered by the I2C Status Register's
1197  * TCF bit after the MCU wakes from the stop mode.
1198  *
1199  * Values:
1200  * - 0 - Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
1201  * - 1 - Stop holdoff is enabled.
1202  */
1203 /*@{*/
1204 #define BP_I2C_FLT_SHEN      (7U)          /*!< Bit position for I2C_FLT_SHEN. */
1205 #define BM_I2C_FLT_SHEN      (0x80U)       /*!< Bit mask for I2C_FLT_SHEN. */
1206 #define BS_I2C_FLT_SHEN      (1U)          /*!< Bit field size in bits for I2C_FLT_SHEN. */
1207
1208 /*! @brief Read current value of the I2C_FLT_SHEN field. */
1209 #define BR_I2C_FLT_SHEN(x)   (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SHEN))
1210
1211 /*! @brief Format value for bitfield I2C_FLT_SHEN. */
1212 #define BF_I2C_FLT_SHEN(v)   ((uint8_t)((uint8_t)(v) << BP_I2C_FLT_SHEN) & BM_I2C_FLT_SHEN)
1213
1214 /*! @brief Set the SHEN field to a new value. */
1215 #define BW_I2C_FLT_SHEN(x, v) (BITBAND_ACCESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SHEN) = (v))
1216 /*@}*/
1217
1218 /*******************************************************************************
1219  * HW_I2C_RA - I2C Range Address register
1220  ******************************************************************************/
1221
1222 /*!
1223  * @brief HW_I2C_RA - I2C Range Address register (RW)
1224  *
1225  * Reset value: 0x00U
1226  */
1227 typedef union _hw_i2c_ra
1228 {
1229     uint8_t U;
1230     struct _hw_i2c_ra_bitfields
1231     {
1232         uint8_t RESERVED0 : 1;         /*!< [0]  */
1233         uint8_t RAD : 7;               /*!< [7:1] Range Slave Address */
1234     } B;
1235 } hw_i2c_ra_t;
1236
1237 /*!
1238  * @name Constants and macros for entire I2C_RA register
1239  */
1240 /*@{*/
1241 #define HW_I2C_RA_ADDR(x)        ((x) + 0x7U)
1242
1243 #define HW_I2C_RA(x)             (*(__IO hw_i2c_ra_t *) HW_I2C_RA_ADDR(x))
1244 #define HW_I2C_RA_RD(x)          (HW_I2C_RA(x).U)
1245 #define HW_I2C_RA_WR(x, v)       (HW_I2C_RA(x).U = (v))
1246 #define HW_I2C_RA_SET(x, v)      (HW_I2C_RA_WR(x, HW_I2C_RA_RD(x) |  (v)))
1247 #define HW_I2C_RA_CLR(x, v)      (HW_I2C_RA_WR(x, HW_I2C_RA_RD(x) & ~(v)))
1248 #define HW_I2C_RA_TOG(x, v)      (HW_I2C_RA_WR(x, HW_I2C_RA_RD(x) ^  (v)))
1249 /*@}*/
1250
1251 /*
1252  * Constants & macros for individual I2C_RA bitfields
1253  */
1254
1255 /*!
1256  * @name Register I2C_RA, field RAD[7:1] (RW)
1257  *
1258  * This field contains the slave address to be used by the I2C module. The field
1259  * is used in the 7-bit address scheme. If I2C_C2[RMEN] is set to 1, any nonzero
1260  * value write enables this register. This register value can be considered as a
1261  * maximum boundary in the range matching mode.
1262  */
1263 /*@{*/
1264 #define BP_I2C_RA_RAD        (1U)          /*!< Bit position for I2C_RA_RAD. */
1265 #define BM_I2C_RA_RAD        (0xFEU)       /*!< Bit mask for I2C_RA_RAD. */
1266 #define BS_I2C_RA_RAD        (7U)          /*!< Bit field size in bits for I2C_RA_RAD. */
1267
1268 /*! @brief Read current value of the I2C_RA_RAD field. */
1269 #define BR_I2C_RA_RAD(x)     (HW_I2C_RA(x).B.RAD)
1270
1271 /*! @brief Format value for bitfield I2C_RA_RAD. */
1272 #define BF_I2C_RA_RAD(v)     ((uint8_t)((uint8_t)(v) << BP_I2C_RA_RAD) & BM_I2C_RA_RAD)
1273
1274 /*! @brief Set the RAD field to a new value. */
1275 #define BW_I2C_RA_RAD(x, v)  (HW_I2C_RA_WR(x, (HW_I2C_RA_RD(x) & ~BM_I2C_RA_RAD) | BF_I2C_RA_RAD(v)))
1276 /*@}*/
1277
1278 /*******************************************************************************
1279  * HW_I2C_SMB - I2C SMBus Control and Status register
1280  ******************************************************************************/
1281
1282 /*!
1283  * @brief HW_I2C_SMB - I2C SMBus Control and Status register (RW)
1284  *
1285  * Reset value: 0x00U
1286  *
1287  * When the SCL and SDA signals are held high for a length of time greater than
1288  * the high timeout period, the SHTF1 flag sets. Before reaching this threshold,
1289  * while the system is detecting how long these signals are being held high, a
1290  * master assumes that the bus is free. However, the SHTF1 bit is set to 1 in the
1291  * bus transmission process with the idle bus state. When the TCKSEL bit is set,
1292  * there is no need to monitor the SHTF1 bit because the bus speed is too high to
1293  * match the protocol of SMBus.
1294  */
1295 typedef union _hw_i2c_smb
1296 {
1297     uint8_t U;
1298     struct _hw_i2c_smb_bitfields
1299     {
1300         uint8_t SHTF2IE : 1;           /*!< [0] SHTF2 Interrupt Enable */
1301         uint8_t SHTF2 : 1;             /*!< [1] SCL High Timeout Flag 2 */
1302         uint8_t SHTF1 : 1;             /*!< [2] SCL High Timeout Flag 1 */
1303         uint8_t SLTF : 1;              /*!< [3] SCL Low Timeout Flag */
1304         uint8_t TCKSEL : 1;            /*!< [4] Timeout Counter Clock Select */
1305         uint8_t SIICAEN : 1;           /*!< [5] Second I2C Address Enable */
1306         uint8_t ALERTEN : 1;           /*!< [6] SMBus Alert Response Address Enable */
1307         uint8_t FACK : 1;              /*!< [7] Fast NACK/ACK Enable */
1308     } B;
1309 } hw_i2c_smb_t;
1310
1311 /*!
1312  * @name Constants and macros for entire I2C_SMB register
1313  */
1314 /*@{*/
1315 #define HW_I2C_SMB_ADDR(x)       ((x) + 0x8U)
1316
1317 #define HW_I2C_SMB(x)            (*(__IO hw_i2c_smb_t *) HW_I2C_SMB_ADDR(x))
1318 #define HW_I2C_SMB_RD(x)         (HW_I2C_SMB(x).U)
1319 #define HW_I2C_SMB_WR(x, v)      (HW_I2C_SMB(x).U = (v))
1320 #define HW_I2C_SMB_SET(x, v)     (HW_I2C_SMB_WR(x, HW_I2C_SMB_RD(x) |  (v)))
1321 #define HW_I2C_SMB_CLR(x, v)     (HW_I2C_SMB_WR(x, HW_I2C_SMB_RD(x) & ~(v)))
1322 #define HW_I2C_SMB_TOG(x, v)     (HW_I2C_SMB_WR(x, HW_I2C_SMB_RD(x) ^  (v)))
1323 /*@}*/
1324
1325 /*
1326  * Constants & macros for individual I2C_SMB bitfields
1327  */
1328
1329 /*!
1330  * @name Register I2C_SMB, field SHTF2IE[0] (RW)
1331  *
1332  * Enables SCL high and SDA low timeout interrupt.
1333  *
1334  * Values:
1335  * - 0 - SHTF2 interrupt is disabled
1336  * - 1 - SHTF2 interrupt is enabled
1337  */
1338 /*@{*/
1339 #define BP_I2C_SMB_SHTF2IE   (0U)          /*!< Bit position for I2C_SMB_SHTF2IE. */
1340 #define BM_I2C_SMB_SHTF2IE   (0x01U)       /*!< Bit mask for I2C_SMB_SHTF2IE. */
1341 #define BS_I2C_SMB_SHTF2IE   (1U)          /*!< Bit field size in bits for I2C_SMB_SHTF2IE. */
1342
1343 /*! @brief Read current value of the I2C_SMB_SHTF2IE field. */
1344 #define BR_I2C_SMB_SHTF2IE(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2IE))
1345
1346 /*! @brief Format value for bitfield I2C_SMB_SHTF2IE. */
1347 #define BF_I2C_SMB_SHTF2IE(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_SHTF2IE) & BM_I2C_SMB_SHTF2IE)
1348
1349 /*! @brief Set the SHTF2IE field to a new value. */
1350 #define BW_I2C_SMB_SHTF2IE(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2IE) = (v))
1351 /*@}*/
1352
1353 /*!
1354  * @name Register I2C_SMB, field SHTF2[1] (W1C)
1355  *
1356  * This bit sets when SCL is held high and SDA is held low more than clock *
1357  * LoValue / 512. Software clears this bit by writing 1 to it.
1358  *
1359  * Values:
1360  * - 0 - No SCL high and SDA low timeout occurs
1361  * - 1 - SCL high and SDA low timeout occurs
1362  */
1363 /*@{*/
1364 #define BP_I2C_SMB_SHTF2     (1U)          /*!< Bit position for I2C_SMB_SHTF2. */
1365 #define BM_I2C_SMB_SHTF2     (0x02U)       /*!< Bit mask for I2C_SMB_SHTF2. */
1366 #define BS_I2C_SMB_SHTF2     (1U)          /*!< Bit field size in bits for I2C_SMB_SHTF2. */
1367
1368 /*! @brief Read current value of the I2C_SMB_SHTF2 field. */
1369 #define BR_I2C_SMB_SHTF2(x)  (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2))
1370
1371 /*! @brief Format value for bitfield I2C_SMB_SHTF2. */
1372 #define BF_I2C_SMB_SHTF2(v)  ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_SHTF2) & BM_I2C_SMB_SHTF2)
1373
1374 /*! @brief Set the SHTF2 field to a new value. */
1375 #define BW_I2C_SMB_SHTF2(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2) = (v))
1376 /*@}*/
1377
1378 /*!
1379  * @name Register I2C_SMB, field SHTF1[2] (RO)
1380  *
1381  * This read-only bit sets when SCL and SDA are held high more than clock *
1382  * LoValue / 512, which indicates the bus is free. This bit is cleared automatically.
1383  *
1384  * Values:
1385  * - 0 - No SCL high and SDA high timeout occurs
1386  * - 1 - SCL high and SDA high timeout occurs
1387  */
1388 /*@{*/
1389 #define BP_I2C_SMB_SHTF1     (2U)          /*!< Bit position for I2C_SMB_SHTF1. */
1390 #define BM_I2C_SMB_SHTF1     (0x04U)       /*!< Bit mask for I2C_SMB_SHTF1. */
1391 #define BS_I2C_SMB_SHTF1     (1U)          /*!< Bit field size in bits for I2C_SMB_SHTF1. */
1392
1393 /*! @brief Read current value of the I2C_SMB_SHTF1 field. */
1394 #define BR_I2C_SMB_SHTF1(x)  (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF1))
1395 /*@}*/
1396
1397 /*!
1398  * @name Register I2C_SMB, field SLTF[3] (W1C)
1399  *
1400  * This bit is set when the SLT register (consisting of the SLTH and SLTL
1401  * registers) is loaded with a non-zero value (LoValue) and an SCL low timeout occurs.
1402  * Software clears this bit by writing a logic 1 to it. The low timeout function
1403  * is disabled when the SLT register's value is 0.
1404  *
1405  * Values:
1406  * - 0 - No low timeout occurs
1407  * - 1 - Low timeout occurs
1408  */
1409 /*@{*/
1410 #define BP_I2C_SMB_SLTF      (3U)          /*!< Bit position for I2C_SMB_SLTF. */
1411 #define BM_I2C_SMB_SLTF      (0x08U)       /*!< Bit mask for I2C_SMB_SLTF. */
1412 #define BS_I2C_SMB_SLTF      (1U)          /*!< Bit field size in bits for I2C_SMB_SLTF. */
1413
1414 /*! @brief Read current value of the I2C_SMB_SLTF field. */
1415 #define BR_I2C_SMB_SLTF(x)   (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SLTF))
1416
1417 /*! @brief Format value for bitfield I2C_SMB_SLTF. */
1418 #define BF_I2C_SMB_SLTF(v)   ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_SLTF) & BM_I2C_SMB_SLTF)
1419
1420 /*! @brief Set the SLTF field to a new value. */
1421 #define BW_I2C_SMB_SLTF(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SLTF) = (v))
1422 /*@}*/
1423
1424 /*!
1425  * @name Register I2C_SMB, field TCKSEL[4] (RW)
1426  *
1427  * Selects the clock source of the timeout counter.
1428  *
1429  * Values:
1430  * - 0 - Timeout counter counts at the frequency of the I2C module clock / 64
1431  * - 1 - Timeout counter counts at the frequency of the I2C module clock
1432  */
1433 /*@{*/
1434 #define BP_I2C_SMB_TCKSEL    (4U)          /*!< Bit position for I2C_SMB_TCKSEL. */
1435 #define BM_I2C_SMB_TCKSEL    (0x10U)       /*!< Bit mask for I2C_SMB_TCKSEL. */
1436 #define BS_I2C_SMB_TCKSEL    (1U)          /*!< Bit field size in bits for I2C_SMB_TCKSEL. */
1437
1438 /*! @brief Read current value of the I2C_SMB_TCKSEL field. */
1439 #define BR_I2C_SMB_TCKSEL(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_TCKSEL))
1440
1441 /*! @brief Format value for bitfield I2C_SMB_TCKSEL. */
1442 #define BF_I2C_SMB_TCKSEL(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_TCKSEL) & BM_I2C_SMB_TCKSEL)
1443
1444 /*! @brief Set the TCKSEL field to a new value. */
1445 #define BW_I2C_SMB_TCKSEL(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_TCKSEL) = (v))
1446 /*@}*/
1447
1448 /*!
1449  * @name Register I2C_SMB, field SIICAEN[5] (RW)
1450  *
1451  * Enables or disables SMBus device default address.
1452  *
1453  * Values:
1454  * - 0 - I2C address register 2 matching is disabled
1455  * - 1 - I2C address register 2 matching is enabled
1456  */
1457 /*@{*/
1458 #define BP_I2C_SMB_SIICAEN   (5U)          /*!< Bit position for I2C_SMB_SIICAEN. */
1459 #define BM_I2C_SMB_SIICAEN   (0x20U)       /*!< Bit mask for I2C_SMB_SIICAEN. */
1460 #define BS_I2C_SMB_SIICAEN   (1U)          /*!< Bit field size in bits for I2C_SMB_SIICAEN. */
1461
1462 /*! @brief Read current value of the I2C_SMB_SIICAEN field. */
1463 #define BR_I2C_SMB_SIICAEN(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SIICAEN))
1464
1465 /*! @brief Format value for bitfield I2C_SMB_SIICAEN. */
1466 #define BF_I2C_SMB_SIICAEN(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_SIICAEN) & BM_I2C_SMB_SIICAEN)
1467
1468 /*! @brief Set the SIICAEN field to a new value. */
1469 #define BW_I2C_SMB_SIICAEN(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SIICAEN) = (v))
1470 /*@}*/
1471
1472 /*!
1473  * @name Register I2C_SMB, field ALERTEN[6] (RW)
1474  *
1475  * Enables or disables SMBus alert response address matching. After the host
1476  * responds to a device that used the alert response address, you must use software
1477  * to put the device's address on the bus. The alert protocol is described in the
1478  * SMBus specification.
1479  *
1480  * Values:
1481  * - 0 - SMBus alert response address matching is disabled
1482  * - 1 - SMBus alert response address matching is enabled
1483  */
1484 /*@{*/
1485 #define BP_I2C_SMB_ALERTEN   (6U)          /*!< Bit position for I2C_SMB_ALERTEN. */
1486 #define BM_I2C_SMB_ALERTEN   (0x40U)       /*!< Bit mask for I2C_SMB_ALERTEN. */
1487 #define BS_I2C_SMB_ALERTEN   (1U)          /*!< Bit field size in bits for I2C_SMB_ALERTEN. */
1488
1489 /*! @brief Read current value of the I2C_SMB_ALERTEN field. */
1490 #define BR_I2C_SMB_ALERTEN(x) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_ALERTEN))
1491
1492 /*! @brief Format value for bitfield I2C_SMB_ALERTEN. */
1493 #define BF_I2C_SMB_ALERTEN(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_ALERTEN) & BM_I2C_SMB_ALERTEN)
1494
1495 /*! @brief Set the ALERTEN field to a new value. */
1496 #define BW_I2C_SMB_ALERTEN(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_ALERTEN) = (v))
1497 /*@}*/
1498
1499 /*!
1500  * @name Register I2C_SMB, field FACK[7] (RW)
1501  *
1502  * For SMBus packet error checking, the CPU must be able to issue an ACK or NACK
1503  * according to the result of receiving data byte.
1504  *
1505  * Values:
1506  * - 0 - An ACK or NACK is sent on the following receiving data byte
1507  * - 1 - Writing 0 to TXAK after receiving a data byte generates an ACK. Writing
1508  *     1 to TXAK after receiving a data byte generates a NACK.
1509  */
1510 /*@{*/
1511 #define BP_I2C_SMB_FACK      (7U)          /*!< Bit position for I2C_SMB_FACK. */
1512 #define BM_I2C_SMB_FACK      (0x80U)       /*!< Bit mask for I2C_SMB_FACK. */
1513 #define BS_I2C_SMB_FACK      (1U)          /*!< Bit field size in bits for I2C_SMB_FACK. */
1514
1515 /*! @brief Read current value of the I2C_SMB_FACK field. */
1516 #define BR_I2C_SMB_FACK(x)   (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_FACK))
1517
1518 /*! @brief Format value for bitfield I2C_SMB_FACK. */
1519 #define BF_I2C_SMB_FACK(v)   ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_FACK) & BM_I2C_SMB_FACK)
1520
1521 /*! @brief Set the FACK field to a new value. */
1522 #define BW_I2C_SMB_FACK(x, v) (BITBAND_ACCESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_FACK) = (v))
1523 /*@}*/
1524
1525 /*******************************************************************************
1526  * HW_I2C_A2 - I2C Address Register 2
1527  ******************************************************************************/
1528
1529 /*!
1530  * @brief HW_I2C_A2 - I2C Address Register 2 (RW)
1531  *
1532  * Reset value: 0xC2U
1533  */
1534 typedef union _hw_i2c_a2
1535 {
1536     uint8_t U;
1537     struct _hw_i2c_a2_bitfields
1538     {
1539         uint8_t RESERVED0 : 1;         /*!< [0]  */
1540         uint8_t SAD : 7;               /*!< [7:1] SMBus Address */
1541     } B;
1542 } hw_i2c_a2_t;
1543
1544 /*!
1545  * @name Constants and macros for entire I2C_A2 register
1546  */
1547 /*@{*/
1548 #define HW_I2C_A2_ADDR(x)        ((x) + 0x9U)
1549
1550 #define HW_I2C_A2(x)             (*(__IO hw_i2c_a2_t *) HW_I2C_A2_ADDR(x))
1551 #define HW_I2C_A2_RD(x)          (HW_I2C_A2(x).U)
1552 #define HW_I2C_A2_WR(x, v)       (HW_I2C_A2(x).U = (v))
1553 #define HW_I2C_A2_SET(x, v)      (HW_I2C_A2_WR(x, HW_I2C_A2_RD(x) |  (v)))
1554 #define HW_I2C_A2_CLR(x, v)      (HW_I2C_A2_WR(x, HW_I2C_A2_RD(x) & ~(v)))
1555 #define HW_I2C_A2_TOG(x, v)      (HW_I2C_A2_WR(x, HW_I2C_A2_RD(x) ^  (v)))
1556 /*@}*/
1557
1558 /*
1559  * Constants & macros for individual I2C_A2 bitfields
1560  */
1561
1562 /*!
1563  * @name Register I2C_A2, field SAD[7:1] (RW)
1564  *
1565  * Contains the slave address used by the SMBus. This field is used on the
1566  * device default address or other related addresses.
1567  */
1568 /*@{*/
1569 #define BP_I2C_A2_SAD        (1U)          /*!< Bit position for I2C_A2_SAD. */
1570 #define BM_I2C_A2_SAD        (0xFEU)       /*!< Bit mask for I2C_A2_SAD. */
1571 #define BS_I2C_A2_SAD        (7U)          /*!< Bit field size in bits for I2C_A2_SAD. */
1572
1573 /*! @brief Read current value of the I2C_A2_SAD field. */
1574 #define BR_I2C_A2_SAD(x)     (HW_I2C_A2(x).B.SAD)
1575
1576 /*! @brief Format value for bitfield I2C_A2_SAD. */
1577 #define BF_I2C_A2_SAD(v)     ((uint8_t)((uint8_t)(v) << BP_I2C_A2_SAD) & BM_I2C_A2_SAD)
1578
1579 /*! @brief Set the SAD field to a new value. */
1580 #define BW_I2C_A2_SAD(x, v)  (HW_I2C_A2_WR(x, (HW_I2C_A2_RD(x) & ~BM_I2C_A2_SAD) | BF_I2C_A2_SAD(v)))
1581 /*@}*/
1582
1583 /*******************************************************************************
1584  * HW_I2C_SLTH - I2C SCL Low Timeout Register High
1585  ******************************************************************************/
1586
1587 /*!
1588  * @brief HW_I2C_SLTH - I2C SCL Low Timeout Register High (RW)
1589  *
1590  * Reset value: 0x00U
1591  */
1592 typedef union _hw_i2c_slth
1593 {
1594     uint8_t U;
1595     struct _hw_i2c_slth_bitfields
1596     {
1597         uint8_t SSLT : 8;              /*!< [7:0]  */
1598     } B;
1599 } hw_i2c_slth_t;
1600
1601 /*!
1602  * @name Constants and macros for entire I2C_SLTH register
1603  */
1604 /*@{*/
1605 #define HW_I2C_SLTH_ADDR(x)      ((x) + 0xAU)
1606
1607 #define HW_I2C_SLTH(x)           (*(__IO hw_i2c_slth_t *) HW_I2C_SLTH_ADDR(x))
1608 #define HW_I2C_SLTH_RD(x)        (HW_I2C_SLTH(x).U)
1609 #define HW_I2C_SLTH_WR(x, v)     (HW_I2C_SLTH(x).U = (v))
1610 #define HW_I2C_SLTH_SET(x, v)    (HW_I2C_SLTH_WR(x, HW_I2C_SLTH_RD(x) |  (v)))
1611 #define HW_I2C_SLTH_CLR(x, v)    (HW_I2C_SLTH_WR(x, HW_I2C_SLTH_RD(x) & ~(v)))
1612 #define HW_I2C_SLTH_TOG(x, v)    (HW_I2C_SLTH_WR(x, HW_I2C_SLTH_RD(x) ^  (v)))
1613 /*@}*/
1614
1615 /*
1616  * Constants & macros for individual I2C_SLTH bitfields
1617  */
1618
1619 /*!
1620  * @name Register I2C_SLTH, field SSLT[7:0] (RW)
1621  *
1622  * Most significant byte of SCL low timeout value that determines the timeout
1623  * period of SCL low.
1624  */
1625 /*@{*/
1626 #define BP_I2C_SLTH_SSLT     (0U)          /*!< Bit position for I2C_SLTH_SSLT. */
1627 #define BM_I2C_SLTH_SSLT     (0xFFU)       /*!< Bit mask for I2C_SLTH_SSLT. */
1628 #define BS_I2C_SLTH_SSLT     (8U)          /*!< Bit field size in bits for I2C_SLTH_SSLT. */
1629
1630 /*! @brief Read current value of the I2C_SLTH_SSLT field. */
1631 #define BR_I2C_SLTH_SSLT(x)  (HW_I2C_SLTH(x).U)
1632
1633 /*! @brief Format value for bitfield I2C_SLTH_SSLT. */
1634 #define BF_I2C_SLTH_SSLT(v)  ((uint8_t)((uint8_t)(v) << BP_I2C_SLTH_SSLT) & BM_I2C_SLTH_SSLT)
1635
1636 /*! @brief Set the SSLT field to a new value. */
1637 #define BW_I2C_SLTH_SSLT(x, v) (HW_I2C_SLTH_WR(x, v))
1638 /*@}*/
1639
1640 /*******************************************************************************
1641  * HW_I2C_SLTL - I2C SCL Low Timeout Register Low
1642  ******************************************************************************/
1643
1644 /*!
1645  * @brief HW_I2C_SLTL - I2C SCL Low Timeout Register Low (RW)
1646  *
1647  * Reset value: 0x00U
1648  */
1649 typedef union _hw_i2c_sltl
1650 {
1651     uint8_t U;
1652     struct _hw_i2c_sltl_bitfields
1653     {
1654         uint8_t SSLT : 8;              /*!< [7:0]  */
1655     } B;
1656 } hw_i2c_sltl_t;
1657
1658 /*!
1659  * @name Constants and macros for entire I2C_SLTL register
1660  */
1661 /*@{*/
1662 #define HW_I2C_SLTL_ADDR(x)      ((x) + 0xBU)
1663
1664 #define HW_I2C_SLTL(x)           (*(__IO hw_i2c_sltl_t *) HW_I2C_SLTL_ADDR(x))
1665 #define HW_I2C_SLTL_RD(x)        (HW_I2C_SLTL(x).U)
1666 #define HW_I2C_SLTL_WR(x, v)     (HW_I2C_SLTL(x).U = (v))
1667 #define HW_I2C_SLTL_SET(x, v)    (HW_I2C_SLTL_WR(x, HW_I2C_SLTL_RD(x) |  (v)))
1668 #define HW_I2C_SLTL_CLR(x, v)    (HW_I2C_SLTL_WR(x, HW_I2C_SLTL_RD(x) & ~(v)))
1669 #define HW_I2C_SLTL_TOG(x, v)    (HW_I2C_SLTL_WR(x, HW_I2C_SLTL_RD(x) ^  (v)))
1670 /*@}*/
1671
1672 /*
1673  * Constants & macros for individual I2C_SLTL bitfields
1674  */
1675
1676 /*!
1677  * @name Register I2C_SLTL, field SSLT[7:0] (RW)
1678  *
1679  * Least significant byte of SCL low timeout value that determines the timeout
1680  * period of SCL low.
1681  */
1682 /*@{*/
1683 #define BP_I2C_SLTL_SSLT     (0U)          /*!< Bit position for I2C_SLTL_SSLT. */
1684 #define BM_I2C_SLTL_SSLT     (0xFFU)       /*!< Bit mask for I2C_SLTL_SSLT. */
1685 #define BS_I2C_SLTL_SSLT     (8U)          /*!< Bit field size in bits for I2C_SLTL_SSLT. */
1686
1687 /*! @brief Read current value of the I2C_SLTL_SSLT field. */
1688 #define BR_I2C_SLTL_SSLT(x)  (HW_I2C_SLTL(x).U)
1689
1690 /*! @brief Format value for bitfield I2C_SLTL_SSLT. */
1691 #define BF_I2C_SLTL_SSLT(v)  ((uint8_t)((uint8_t)(v) << BP_I2C_SLTL_SSLT) & BM_I2C_SLTL_SSLT)
1692
1693 /*! @brief Set the SSLT field to a new value. */
1694 #define BW_I2C_SLTL_SSLT(x, v) (HW_I2C_SLTL_WR(x, v))
1695 /*@}*/
1696
1697 /*******************************************************************************
1698  * hw_i2c_t - module struct
1699  ******************************************************************************/
1700 /*!
1701  * @brief All I2C module registers.
1702  */
1703 #pragma pack(1)
1704 typedef struct _hw_i2c
1705 {
1706     __IO hw_i2c_a1_t A1;                   /*!< [0x0] I2C Address Register 1 */
1707     __IO hw_i2c_f_t F;                     /*!< [0x1] I2C Frequency Divider register */
1708     __IO hw_i2c_c1_t C1;                   /*!< [0x2] I2C Control Register 1 */
1709     __IO hw_i2c_s_t S;                     /*!< [0x3] I2C Status register */
1710     __IO hw_i2c_d_t D;                     /*!< [0x4] I2C Data I/O register */
1711     __IO hw_i2c_c2_t C2;                   /*!< [0x5] I2C Control Register 2 */
1712     __IO hw_i2c_flt_t FLT;                 /*!< [0x6] I2C Programmable Input Glitch Filter register */
1713     __IO hw_i2c_ra_t RA;                   /*!< [0x7] I2C Range Address register */
1714     __IO hw_i2c_smb_t SMB;                 /*!< [0x8] I2C SMBus Control and Status register */
1715     __IO hw_i2c_a2_t A2;                   /*!< [0x9] I2C Address Register 2 */
1716     __IO hw_i2c_slth_t SLTH;               /*!< [0xA] I2C SCL Low Timeout Register High */
1717     __IO hw_i2c_sltl_t SLTL;               /*!< [0xB] I2C SCL Low Timeout Register Low */
1718 } hw_i2c_t;
1719 #pragma pack()
1720
1721 /*! @brief Macro to access all I2C registers. */
1722 /*! @param x I2C module instance base address. */
1723 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
1724  *     use the '&' operator, like <code>&HW_I2C(I2C0_BASE)</code>. */
1725 #define HW_I2C(x)      (*(hw_i2c_t *)(x))
1726
1727 #endif /* __HW_I2C_REGISTERS_H__ */
1728 /* EOF */