2 ** ###################################################################
3 ** Compilers: Keil ARM C/C++ Compiler
4 ** Freescale C/C++ for Embedded ARM
6 ** IAR ANSI C/C++ Compiler for ARM
8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
9 ** Version: rev. 2.5, 2014-02-10
13 ** Extension to the CMSIS register access layer header.
15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
16 ** All rights reserved.
18 ** Redistribution and use in source and binary forms, with or without modification,
19 ** are permitted provided that the following conditions are met:
21 ** o Redistributions of source code must retain the above copyright notice, this list
22 ** of conditions and the following disclaimer.
24 ** o Redistributions in binary form must reproduce the above copyright notice, this
25 ** list of conditions and the following disclaimer in the documentation and/or
26 ** other materials provided with the distribution.
28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
29 ** contributors may be used to endorse or promote products derived from this
30 ** software without specific prior written permission.
32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 ** http: www.freescale.com
44 ** mail: support@freescale.com
47 ** - rev. 1.0 (2013-08-12)
49 ** - rev. 2.0 (2013-10-29)
50 ** Register accessor macros added to the memory map.
51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
52 ** Startup file for gcc has been updated according to CMSIS 3.2.
53 ** System initialization updated.
54 ** MCG - registers updated.
55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
56 ** - rev. 2.1 (2013-10-30)
57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
58 ** - rev. 2.2 (2013-12-09)
59 ** DMA - EARS register removed.
60 ** AIPS0, AIPS1 - MPRA register updated.
61 ** - rev. 2.3 (2014-01-24)
62 ** Update according to reference manual rev. 2
63 ** ENET, MCG, MCM, SIM, USB - registers updated
64 ** - rev. 2.4 (2014-02-10)
65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
67 ** - rev. 2.5 (2014-02-10)
68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
72 ** ###################################################################
76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
78 * This file was generated automatically and any changes may be lost.
80 #ifndef __HW_LLWU_REGISTERS_H__
81 #define __HW_LLWU_REGISTERS_H__
84 #include "fsl_bitaccess.h"
89 * Low leakage wakeup unit
91 * Registers defined in this header file:
92 * - HW_LLWU_PE1 - LLWU Pin Enable 1 register
93 * - HW_LLWU_PE2 - LLWU Pin Enable 2 register
94 * - HW_LLWU_PE3 - LLWU Pin Enable 3 register
95 * - HW_LLWU_PE4 - LLWU Pin Enable 4 register
96 * - HW_LLWU_ME - LLWU Module Enable register
97 * - HW_LLWU_F1 - LLWU Flag 1 register
98 * - HW_LLWU_F2 - LLWU Flag 2 register
99 * - HW_LLWU_F3 - LLWU Flag 3 register
100 * - HW_LLWU_FILT1 - LLWU Pin Filter 1 register
101 * - HW_LLWU_FILT2 - LLWU Pin Filter 2 register
102 * - HW_LLWU_RST - LLWU Reset Enable register
104 * - hw_llwu_t - Struct containing all module registers.
107 #define HW_LLWU_INSTANCE_COUNT (1U) /*!< Number of instances of the LLWU module. */
109 /*******************************************************************************
110 * HW_LLWU_PE1 - LLWU Pin Enable 1 register
111 ******************************************************************************/
114 * @brief HW_LLWU_PE1 - LLWU Pin Enable 1 register (RW)
118 * LLWU_PE1 contains the field to enable and select the edge detect type for the
119 * external wakeup input pins LLWU_P3-LLWU_P0. This register is reset on Chip
120 * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
121 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
122 * IntroductionInformation found here describes the registers of the Reset Control Module
123 * (RCM). The RCM implements many of the reset functions for the chip. See the
124 * chip's reset chapter for more information. details for more information.
126 typedef union _hw_llwu_pe1
129 struct _hw_llwu_pe1_bitfields
131 uint8_t WUPE0
: 2; /*!< [1:0] Wakeup Pin Enable For LLWU_P0 */
132 uint8_t WUPE1
: 2; /*!< [3:2] Wakeup Pin Enable For LLWU_P1 */
133 uint8_t WUPE2
: 2; /*!< [5:4] Wakeup Pin Enable For LLWU_P2 */
134 uint8_t WUPE3
: 2; /*!< [7:6] Wakeup Pin Enable For LLWU_P3 */
139 * @name Constants and macros for entire LLWU_PE1 register
142 #define HW_LLWU_PE1_ADDR(x) ((x) + 0x0U)
144 #define HW_LLWU_PE1(x) (*(__IO hw_llwu_pe1_t *) HW_LLWU_PE1_ADDR(x))
145 #define HW_LLWU_PE1_RD(x) (HW_LLWU_PE1(x).U)
146 #define HW_LLWU_PE1_WR(x, v) (HW_LLWU_PE1(x).U = (v))
147 #define HW_LLWU_PE1_SET(x, v) (HW_LLWU_PE1_WR(x, HW_LLWU_PE1_RD(x) | (v)))
148 #define HW_LLWU_PE1_CLR(x, v) (HW_LLWU_PE1_WR(x, HW_LLWU_PE1_RD(x) & ~(v)))
149 #define HW_LLWU_PE1_TOG(x, v) (HW_LLWU_PE1_WR(x, HW_LLWU_PE1_RD(x) ^ (v)))
153 * Constants & macros for individual LLWU_PE1 bitfields
157 * @name Register LLWU_PE1, field WUPE0[1:0] (RW)
159 * Enables and configures the edge detection for the wakeup pin.
162 * - 00 - External input pin disabled as wakeup input
163 * - 01 - External input pin enabled with rising edge detection
164 * - 10 - External input pin enabled with falling edge detection
165 * - 11 - External input pin enabled with any change detection
168 #define BP_LLWU_PE1_WUPE0 (0U) /*!< Bit position for LLWU_PE1_WUPE0. */
169 #define BM_LLWU_PE1_WUPE0 (0x03U) /*!< Bit mask for LLWU_PE1_WUPE0. */
170 #define BS_LLWU_PE1_WUPE0 (2U) /*!< Bit field size in bits for LLWU_PE1_WUPE0. */
172 /*! @brief Read current value of the LLWU_PE1_WUPE0 field. */
173 #define BR_LLWU_PE1_WUPE0(x) (HW_LLWU_PE1(x).B.WUPE0)
175 /*! @brief Format value for bitfield LLWU_PE1_WUPE0. */
176 #define BF_LLWU_PE1_WUPE0(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE1_WUPE0) & BM_LLWU_PE1_WUPE0)
178 /*! @brief Set the WUPE0 field to a new value. */
179 #define BW_LLWU_PE1_WUPE0(x, v) (HW_LLWU_PE1_WR(x, (HW_LLWU_PE1_RD(x) & ~BM_LLWU_PE1_WUPE0) | BF_LLWU_PE1_WUPE0(v)))
183 * @name Register LLWU_PE1, field WUPE1[3:2] (RW)
185 * Enables and configures the edge detection for the wakeup pin.
188 * - 00 - External input pin disabled as wakeup input
189 * - 01 - External input pin enabled with rising edge detection
190 * - 10 - External input pin enabled with falling edge detection
191 * - 11 - External input pin enabled with any change detection
194 #define BP_LLWU_PE1_WUPE1 (2U) /*!< Bit position for LLWU_PE1_WUPE1. */
195 #define BM_LLWU_PE1_WUPE1 (0x0CU) /*!< Bit mask for LLWU_PE1_WUPE1. */
196 #define BS_LLWU_PE1_WUPE1 (2U) /*!< Bit field size in bits for LLWU_PE1_WUPE1. */
198 /*! @brief Read current value of the LLWU_PE1_WUPE1 field. */
199 #define BR_LLWU_PE1_WUPE1(x) (HW_LLWU_PE1(x).B.WUPE1)
201 /*! @brief Format value for bitfield LLWU_PE1_WUPE1. */
202 #define BF_LLWU_PE1_WUPE1(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE1_WUPE1) & BM_LLWU_PE1_WUPE1)
204 /*! @brief Set the WUPE1 field to a new value. */
205 #define BW_LLWU_PE1_WUPE1(x, v) (HW_LLWU_PE1_WR(x, (HW_LLWU_PE1_RD(x) & ~BM_LLWU_PE1_WUPE1) | BF_LLWU_PE1_WUPE1(v)))
209 * @name Register LLWU_PE1, field WUPE2[5:4] (RW)
211 * Enables and configures the edge detection for the wakeup pin.
214 * - 00 - External input pin disabled as wakeup input
215 * - 01 - External input pin enabled with rising edge detection
216 * - 10 - External input pin enabled with falling edge detection
217 * - 11 - External input pin enabled with any change detection
220 #define BP_LLWU_PE1_WUPE2 (4U) /*!< Bit position for LLWU_PE1_WUPE2. */
221 #define BM_LLWU_PE1_WUPE2 (0x30U) /*!< Bit mask for LLWU_PE1_WUPE2. */
222 #define BS_LLWU_PE1_WUPE2 (2U) /*!< Bit field size in bits for LLWU_PE1_WUPE2. */
224 /*! @brief Read current value of the LLWU_PE1_WUPE2 field. */
225 #define BR_LLWU_PE1_WUPE2(x) (HW_LLWU_PE1(x).B.WUPE2)
227 /*! @brief Format value for bitfield LLWU_PE1_WUPE2. */
228 #define BF_LLWU_PE1_WUPE2(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE1_WUPE2) & BM_LLWU_PE1_WUPE2)
230 /*! @brief Set the WUPE2 field to a new value. */
231 #define BW_LLWU_PE1_WUPE2(x, v) (HW_LLWU_PE1_WR(x, (HW_LLWU_PE1_RD(x) & ~BM_LLWU_PE1_WUPE2) | BF_LLWU_PE1_WUPE2(v)))
235 * @name Register LLWU_PE1, field WUPE3[7:6] (RW)
237 * Enables and configures the edge detection for the wakeup pin.
240 * - 00 - External input pin disabled as wakeup input
241 * - 01 - External input pin enabled with rising edge detection
242 * - 10 - External input pin enabled with falling edge detection
243 * - 11 - External input pin enabled with any change detection
246 #define BP_LLWU_PE1_WUPE3 (6U) /*!< Bit position for LLWU_PE1_WUPE3. */
247 #define BM_LLWU_PE1_WUPE3 (0xC0U) /*!< Bit mask for LLWU_PE1_WUPE3. */
248 #define BS_LLWU_PE1_WUPE3 (2U) /*!< Bit field size in bits for LLWU_PE1_WUPE3. */
250 /*! @brief Read current value of the LLWU_PE1_WUPE3 field. */
251 #define BR_LLWU_PE1_WUPE3(x) (HW_LLWU_PE1(x).B.WUPE3)
253 /*! @brief Format value for bitfield LLWU_PE1_WUPE3. */
254 #define BF_LLWU_PE1_WUPE3(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE1_WUPE3) & BM_LLWU_PE1_WUPE3)
256 /*! @brief Set the WUPE3 field to a new value. */
257 #define BW_LLWU_PE1_WUPE3(x, v) (HW_LLWU_PE1_WR(x, (HW_LLWU_PE1_RD(x) & ~BM_LLWU_PE1_WUPE3) | BF_LLWU_PE1_WUPE3(v)))
260 /*******************************************************************************
261 * HW_LLWU_PE2 - LLWU Pin Enable 2 register
262 ******************************************************************************/
265 * @brief HW_LLWU_PE2 - LLWU Pin Enable 2 register (RW)
269 * LLWU_PE2 contains the field to enable and select the edge detect type for the
270 * external wakeup input pins LLWU_P7-LLWU_P4. This register is reset on Chip
271 * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
272 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
273 * IntroductionInformation found here describes the registers of the Reset Control Module
274 * (RCM). The RCM implements many of the reset functions for the chip. See the
275 * chip's reset chapter for more information. details for more information.
277 typedef union _hw_llwu_pe2
280 struct _hw_llwu_pe2_bitfields
282 uint8_t WUPE4
: 2; /*!< [1:0] Wakeup Pin Enable For LLWU_P4 */
283 uint8_t WUPE5
: 2; /*!< [3:2] Wakeup Pin Enable For LLWU_P5 */
284 uint8_t WUPE6
: 2; /*!< [5:4] Wakeup Pin Enable For LLWU_P6 */
285 uint8_t WUPE7
: 2; /*!< [7:6] Wakeup Pin Enable For LLWU_P7 */
290 * @name Constants and macros for entire LLWU_PE2 register
293 #define HW_LLWU_PE2_ADDR(x) ((x) + 0x1U)
295 #define HW_LLWU_PE2(x) (*(__IO hw_llwu_pe2_t *) HW_LLWU_PE2_ADDR(x))
296 #define HW_LLWU_PE2_RD(x) (HW_LLWU_PE2(x).U)
297 #define HW_LLWU_PE2_WR(x, v) (HW_LLWU_PE2(x).U = (v))
298 #define HW_LLWU_PE2_SET(x, v) (HW_LLWU_PE2_WR(x, HW_LLWU_PE2_RD(x) | (v)))
299 #define HW_LLWU_PE2_CLR(x, v) (HW_LLWU_PE2_WR(x, HW_LLWU_PE2_RD(x) & ~(v)))
300 #define HW_LLWU_PE2_TOG(x, v) (HW_LLWU_PE2_WR(x, HW_LLWU_PE2_RD(x) ^ (v)))
304 * Constants & macros for individual LLWU_PE2 bitfields
308 * @name Register LLWU_PE2, field WUPE4[1:0] (RW)
310 * Enables and configures the edge detection for the wakeup pin.
313 * - 00 - External input pin disabled as wakeup input
314 * - 01 - External input pin enabled with rising edge detection
315 * - 10 - External input pin enabled with falling edge detection
316 * - 11 - External input pin enabled with any change detection
319 #define BP_LLWU_PE2_WUPE4 (0U) /*!< Bit position for LLWU_PE2_WUPE4. */
320 #define BM_LLWU_PE2_WUPE4 (0x03U) /*!< Bit mask for LLWU_PE2_WUPE4. */
321 #define BS_LLWU_PE2_WUPE4 (2U) /*!< Bit field size in bits for LLWU_PE2_WUPE4. */
323 /*! @brief Read current value of the LLWU_PE2_WUPE4 field. */
324 #define BR_LLWU_PE2_WUPE4(x) (HW_LLWU_PE2(x).B.WUPE4)
326 /*! @brief Format value for bitfield LLWU_PE2_WUPE4. */
327 #define BF_LLWU_PE2_WUPE4(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE2_WUPE4) & BM_LLWU_PE2_WUPE4)
329 /*! @brief Set the WUPE4 field to a new value. */
330 #define BW_LLWU_PE2_WUPE4(x, v) (HW_LLWU_PE2_WR(x, (HW_LLWU_PE2_RD(x) & ~BM_LLWU_PE2_WUPE4) | BF_LLWU_PE2_WUPE4(v)))
334 * @name Register LLWU_PE2, field WUPE5[3:2] (RW)
336 * Enables and configures the edge detection for the wakeup pin.
339 * - 00 - External input pin disabled as wakeup input
340 * - 01 - External input pin enabled with rising edge detection
341 * - 10 - External input pin enabled with falling edge detection
342 * - 11 - External input pin enabled with any change detection
345 #define BP_LLWU_PE2_WUPE5 (2U) /*!< Bit position for LLWU_PE2_WUPE5. */
346 #define BM_LLWU_PE2_WUPE5 (0x0CU) /*!< Bit mask for LLWU_PE2_WUPE5. */
347 #define BS_LLWU_PE2_WUPE5 (2U) /*!< Bit field size in bits for LLWU_PE2_WUPE5. */
349 /*! @brief Read current value of the LLWU_PE2_WUPE5 field. */
350 #define BR_LLWU_PE2_WUPE5(x) (HW_LLWU_PE2(x).B.WUPE5)
352 /*! @brief Format value for bitfield LLWU_PE2_WUPE5. */
353 #define BF_LLWU_PE2_WUPE5(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE2_WUPE5) & BM_LLWU_PE2_WUPE5)
355 /*! @brief Set the WUPE5 field to a new value. */
356 #define BW_LLWU_PE2_WUPE5(x, v) (HW_LLWU_PE2_WR(x, (HW_LLWU_PE2_RD(x) & ~BM_LLWU_PE2_WUPE5) | BF_LLWU_PE2_WUPE5(v)))
360 * @name Register LLWU_PE2, field WUPE6[5:4] (RW)
362 * Enables and configures the edge detection for the wakeup pin.
365 * - 00 - External input pin disabled as wakeup input
366 * - 01 - External input pin enabled with rising edge detection
367 * - 10 - External input pin enabled with falling edge detection
368 * - 11 - External input pin enabled with any change detection
371 #define BP_LLWU_PE2_WUPE6 (4U) /*!< Bit position for LLWU_PE2_WUPE6. */
372 #define BM_LLWU_PE2_WUPE6 (0x30U) /*!< Bit mask for LLWU_PE2_WUPE6. */
373 #define BS_LLWU_PE2_WUPE6 (2U) /*!< Bit field size in bits for LLWU_PE2_WUPE6. */
375 /*! @brief Read current value of the LLWU_PE2_WUPE6 field. */
376 #define BR_LLWU_PE2_WUPE6(x) (HW_LLWU_PE2(x).B.WUPE6)
378 /*! @brief Format value for bitfield LLWU_PE2_WUPE6. */
379 #define BF_LLWU_PE2_WUPE6(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE2_WUPE6) & BM_LLWU_PE2_WUPE6)
381 /*! @brief Set the WUPE6 field to a new value. */
382 #define BW_LLWU_PE2_WUPE6(x, v) (HW_LLWU_PE2_WR(x, (HW_LLWU_PE2_RD(x) & ~BM_LLWU_PE2_WUPE6) | BF_LLWU_PE2_WUPE6(v)))
386 * @name Register LLWU_PE2, field WUPE7[7:6] (RW)
388 * Enables and configures the edge detection for the wakeup pin.
391 * - 00 - External input pin disabled as wakeup input
392 * - 01 - External input pin enabled with rising edge detection
393 * - 10 - External input pin enabled with falling edge detection
394 * - 11 - External input pin enabled with any change detection
397 #define BP_LLWU_PE2_WUPE7 (6U) /*!< Bit position for LLWU_PE2_WUPE7. */
398 #define BM_LLWU_PE2_WUPE7 (0xC0U) /*!< Bit mask for LLWU_PE2_WUPE7. */
399 #define BS_LLWU_PE2_WUPE7 (2U) /*!< Bit field size in bits for LLWU_PE2_WUPE7. */
401 /*! @brief Read current value of the LLWU_PE2_WUPE7 field. */
402 #define BR_LLWU_PE2_WUPE7(x) (HW_LLWU_PE2(x).B.WUPE7)
404 /*! @brief Format value for bitfield LLWU_PE2_WUPE7. */
405 #define BF_LLWU_PE2_WUPE7(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE2_WUPE7) & BM_LLWU_PE2_WUPE7)
407 /*! @brief Set the WUPE7 field to a new value. */
408 #define BW_LLWU_PE2_WUPE7(x, v) (HW_LLWU_PE2_WR(x, (HW_LLWU_PE2_RD(x) & ~BM_LLWU_PE2_WUPE7) | BF_LLWU_PE2_WUPE7(v)))
411 /*******************************************************************************
412 * HW_LLWU_PE3 - LLWU Pin Enable 3 register
413 ******************************************************************************/
416 * @brief HW_LLWU_PE3 - LLWU Pin Enable 3 register (RW)
420 * LLWU_PE3 contains the field to enable and select the edge detect type for the
421 * external wakeup input pins LLWU_P11-LLWU_P8. This register is reset on Chip
422 * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
423 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
424 * IntroductionInformation found here describes the registers of the Reset Control Module
425 * (RCM). The RCM implements many of the reset functions for the chip. See the
426 * chip's reset chapter for more information. details for more information.
428 typedef union _hw_llwu_pe3
431 struct _hw_llwu_pe3_bitfields
433 uint8_t WUPE8
: 2; /*!< [1:0] Wakeup Pin Enable For LLWU_P8 */
434 uint8_t WUPE9
: 2; /*!< [3:2] Wakeup Pin Enable For LLWU_P9 */
435 uint8_t WUPE10
: 2; /*!< [5:4] Wakeup Pin Enable For LLWU_P10 */
436 uint8_t WUPE11
: 2; /*!< [7:6] Wakeup Pin Enable For LLWU_P11 */
441 * @name Constants and macros for entire LLWU_PE3 register
444 #define HW_LLWU_PE3_ADDR(x) ((x) + 0x2U)
446 #define HW_LLWU_PE3(x) (*(__IO hw_llwu_pe3_t *) HW_LLWU_PE3_ADDR(x))
447 #define HW_LLWU_PE3_RD(x) (HW_LLWU_PE3(x).U)
448 #define HW_LLWU_PE3_WR(x, v) (HW_LLWU_PE3(x).U = (v))
449 #define HW_LLWU_PE3_SET(x, v) (HW_LLWU_PE3_WR(x, HW_LLWU_PE3_RD(x) | (v)))
450 #define HW_LLWU_PE3_CLR(x, v) (HW_LLWU_PE3_WR(x, HW_LLWU_PE3_RD(x) & ~(v)))
451 #define HW_LLWU_PE3_TOG(x, v) (HW_LLWU_PE3_WR(x, HW_LLWU_PE3_RD(x) ^ (v)))
455 * Constants & macros for individual LLWU_PE3 bitfields
459 * @name Register LLWU_PE3, field WUPE8[1:0] (RW)
461 * Enables and configures the edge detection for the wakeup pin.
464 * - 00 - External input pin disabled as wakeup input
465 * - 01 - External input pin enabled with rising edge detection
466 * - 10 - External input pin enabled with falling edge detection
467 * - 11 - External input pin enabled with any change detection
470 #define BP_LLWU_PE3_WUPE8 (0U) /*!< Bit position for LLWU_PE3_WUPE8. */
471 #define BM_LLWU_PE3_WUPE8 (0x03U) /*!< Bit mask for LLWU_PE3_WUPE8. */
472 #define BS_LLWU_PE3_WUPE8 (2U) /*!< Bit field size in bits for LLWU_PE3_WUPE8. */
474 /*! @brief Read current value of the LLWU_PE3_WUPE8 field. */
475 #define BR_LLWU_PE3_WUPE8(x) (HW_LLWU_PE3(x).B.WUPE8)
477 /*! @brief Format value for bitfield LLWU_PE3_WUPE8. */
478 #define BF_LLWU_PE3_WUPE8(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE3_WUPE8) & BM_LLWU_PE3_WUPE8)
480 /*! @brief Set the WUPE8 field to a new value. */
481 #define BW_LLWU_PE3_WUPE8(x, v) (HW_LLWU_PE3_WR(x, (HW_LLWU_PE3_RD(x) & ~BM_LLWU_PE3_WUPE8) | BF_LLWU_PE3_WUPE8(v)))
485 * @name Register LLWU_PE3, field WUPE9[3:2] (RW)
487 * Enables and configures the edge detection for the wakeup pin.
490 * - 00 - External input pin disabled as wakeup input
491 * - 01 - External input pin enabled with rising edge detection
492 * - 10 - External input pin enabled with falling edge detection
493 * - 11 - External input pin enabled with any change detection
496 #define BP_LLWU_PE3_WUPE9 (2U) /*!< Bit position for LLWU_PE3_WUPE9. */
497 #define BM_LLWU_PE3_WUPE9 (0x0CU) /*!< Bit mask for LLWU_PE3_WUPE9. */
498 #define BS_LLWU_PE3_WUPE9 (2U) /*!< Bit field size in bits for LLWU_PE3_WUPE9. */
500 /*! @brief Read current value of the LLWU_PE3_WUPE9 field. */
501 #define BR_LLWU_PE3_WUPE9(x) (HW_LLWU_PE3(x).B.WUPE9)
503 /*! @brief Format value for bitfield LLWU_PE3_WUPE9. */
504 #define BF_LLWU_PE3_WUPE9(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE3_WUPE9) & BM_LLWU_PE3_WUPE9)
506 /*! @brief Set the WUPE9 field to a new value. */
507 #define BW_LLWU_PE3_WUPE9(x, v) (HW_LLWU_PE3_WR(x, (HW_LLWU_PE3_RD(x) & ~BM_LLWU_PE3_WUPE9) | BF_LLWU_PE3_WUPE9(v)))
511 * @name Register LLWU_PE3, field WUPE10[5:4] (RW)
513 * Enables and configures the edge detection for the wakeup pin.
516 * - 00 - External input pin disabled as wakeup input
517 * - 01 - External input pin enabled with rising edge detection
518 * - 10 - External input pin enabled with falling edge detection
519 * - 11 - External input pin enabled with any change detection
522 #define BP_LLWU_PE3_WUPE10 (4U) /*!< Bit position for LLWU_PE3_WUPE10. */
523 #define BM_LLWU_PE3_WUPE10 (0x30U) /*!< Bit mask for LLWU_PE3_WUPE10. */
524 #define BS_LLWU_PE3_WUPE10 (2U) /*!< Bit field size in bits for LLWU_PE3_WUPE10. */
526 /*! @brief Read current value of the LLWU_PE3_WUPE10 field. */
527 #define BR_LLWU_PE3_WUPE10(x) (HW_LLWU_PE3(x).B.WUPE10)
529 /*! @brief Format value for bitfield LLWU_PE3_WUPE10. */
530 #define BF_LLWU_PE3_WUPE10(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE3_WUPE10) & BM_LLWU_PE3_WUPE10)
532 /*! @brief Set the WUPE10 field to a new value. */
533 #define BW_LLWU_PE3_WUPE10(x, v) (HW_LLWU_PE3_WR(x, (HW_LLWU_PE3_RD(x) & ~BM_LLWU_PE3_WUPE10) | BF_LLWU_PE3_WUPE10(v)))
537 * @name Register LLWU_PE3, field WUPE11[7:6] (RW)
539 * Enables and configures the edge detection for the wakeup pin.
542 * - 00 - External input pin disabled as wakeup input
543 * - 01 - External input pin enabled with rising edge detection
544 * - 10 - External input pin enabled with falling edge detection
545 * - 11 - External input pin enabled with any change detection
548 #define BP_LLWU_PE3_WUPE11 (6U) /*!< Bit position for LLWU_PE3_WUPE11. */
549 #define BM_LLWU_PE3_WUPE11 (0xC0U) /*!< Bit mask for LLWU_PE3_WUPE11. */
550 #define BS_LLWU_PE3_WUPE11 (2U) /*!< Bit field size in bits for LLWU_PE3_WUPE11. */
552 /*! @brief Read current value of the LLWU_PE3_WUPE11 field. */
553 #define BR_LLWU_PE3_WUPE11(x) (HW_LLWU_PE3(x).B.WUPE11)
555 /*! @brief Format value for bitfield LLWU_PE3_WUPE11. */
556 #define BF_LLWU_PE3_WUPE11(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE3_WUPE11) & BM_LLWU_PE3_WUPE11)
558 /*! @brief Set the WUPE11 field to a new value. */
559 #define BW_LLWU_PE3_WUPE11(x, v) (HW_LLWU_PE3_WR(x, (HW_LLWU_PE3_RD(x) & ~BM_LLWU_PE3_WUPE11) | BF_LLWU_PE3_WUPE11(v)))
562 /*******************************************************************************
563 * HW_LLWU_PE4 - LLWU Pin Enable 4 register
564 ******************************************************************************/
567 * @brief HW_LLWU_PE4 - LLWU Pin Enable 4 register (RW)
571 * LLWU_PE4 contains the field to enable and select the edge detect type for the
572 * external wakeup input pins LLWU_P15-LLWU_P12. This register is reset on Chip
573 * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
574 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
575 * IntroductionInformation found here describes the registers of the Reset Control
576 * Module (RCM). The RCM implements many of the reset functions for the chip. See the
577 * chip's reset chapter for more information. details for more information.
579 typedef union _hw_llwu_pe4
582 struct _hw_llwu_pe4_bitfields
584 uint8_t WUPE12
: 2; /*!< [1:0] Wakeup Pin Enable For LLWU_P12 */
585 uint8_t WUPE13
: 2; /*!< [3:2] Wakeup Pin Enable For LLWU_P13 */
586 uint8_t WUPE14
: 2; /*!< [5:4] Wakeup Pin Enable For LLWU_P14 */
587 uint8_t WUPE15
: 2; /*!< [7:6] Wakeup Pin Enable For LLWU_P15 */
592 * @name Constants and macros for entire LLWU_PE4 register
595 #define HW_LLWU_PE4_ADDR(x) ((x) + 0x3U)
597 #define HW_LLWU_PE4(x) (*(__IO hw_llwu_pe4_t *) HW_LLWU_PE4_ADDR(x))
598 #define HW_LLWU_PE4_RD(x) (HW_LLWU_PE4(x).U)
599 #define HW_LLWU_PE4_WR(x, v) (HW_LLWU_PE4(x).U = (v))
600 #define HW_LLWU_PE4_SET(x, v) (HW_LLWU_PE4_WR(x, HW_LLWU_PE4_RD(x) | (v)))
601 #define HW_LLWU_PE4_CLR(x, v) (HW_LLWU_PE4_WR(x, HW_LLWU_PE4_RD(x) & ~(v)))
602 #define HW_LLWU_PE4_TOG(x, v) (HW_LLWU_PE4_WR(x, HW_LLWU_PE4_RD(x) ^ (v)))
606 * Constants & macros for individual LLWU_PE4 bitfields
610 * @name Register LLWU_PE4, field WUPE12[1:0] (RW)
612 * Enables and configures the edge detection for the wakeup pin.
615 * - 00 - External input pin disabled as wakeup input
616 * - 01 - External input pin enabled with rising edge detection
617 * - 10 - External input pin enabled with falling edge detection
618 * - 11 - External input pin enabled with any change detection
621 #define BP_LLWU_PE4_WUPE12 (0U) /*!< Bit position for LLWU_PE4_WUPE12. */
622 #define BM_LLWU_PE4_WUPE12 (0x03U) /*!< Bit mask for LLWU_PE4_WUPE12. */
623 #define BS_LLWU_PE4_WUPE12 (2U) /*!< Bit field size in bits for LLWU_PE4_WUPE12. */
625 /*! @brief Read current value of the LLWU_PE4_WUPE12 field. */
626 #define BR_LLWU_PE4_WUPE12(x) (HW_LLWU_PE4(x).B.WUPE12)
628 /*! @brief Format value for bitfield LLWU_PE4_WUPE12. */
629 #define BF_LLWU_PE4_WUPE12(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE4_WUPE12) & BM_LLWU_PE4_WUPE12)
631 /*! @brief Set the WUPE12 field to a new value. */
632 #define BW_LLWU_PE4_WUPE12(x, v) (HW_LLWU_PE4_WR(x, (HW_LLWU_PE4_RD(x) & ~BM_LLWU_PE4_WUPE12) | BF_LLWU_PE4_WUPE12(v)))
636 * @name Register LLWU_PE4, field WUPE13[3:2] (RW)
638 * Enables and configures the edge detection for the wakeup pin.
641 * - 00 - External input pin disabled as wakeup input
642 * - 01 - External input pin enabled with rising edge detection
643 * - 10 - External input pin enabled with falling edge detection
644 * - 11 - External input pin enabled with any change detection
647 #define BP_LLWU_PE4_WUPE13 (2U) /*!< Bit position for LLWU_PE4_WUPE13. */
648 #define BM_LLWU_PE4_WUPE13 (0x0CU) /*!< Bit mask for LLWU_PE4_WUPE13. */
649 #define BS_LLWU_PE4_WUPE13 (2U) /*!< Bit field size in bits for LLWU_PE4_WUPE13. */
651 /*! @brief Read current value of the LLWU_PE4_WUPE13 field. */
652 #define BR_LLWU_PE4_WUPE13(x) (HW_LLWU_PE4(x).B.WUPE13)
654 /*! @brief Format value for bitfield LLWU_PE4_WUPE13. */
655 #define BF_LLWU_PE4_WUPE13(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE4_WUPE13) & BM_LLWU_PE4_WUPE13)
657 /*! @brief Set the WUPE13 field to a new value. */
658 #define BW_LLWU_PE4_WUPE13(x, v) (HW_LLWU_PE4_WR(x, (HW_LLWU_PE4_RD(x) & ~BM_LLWU_PE4_WUPE13) | BF_LLWU_PE4_WUPE13(v)))
662 * @name Register LLWU_PE4, field WUPE14[5:4] (RW)
664 * Enables and configures the edge detection for the wakeup pin.
667 * - 00 - External input pin disabled as wakeup input
668 * - 01 - External input pin enabled with rising edge detection
669 * - 10 - External input pin enabled with falling edge detection
670 * - 11 - External input pin enabled with any change detection
673 #define BP_LLWU_PE4_WUPE14 (4U) /*!< Bit position for LLWU_PE4_WUPE14. */
674 #define BM_LLWU_PE4_WUPE14 (0x30U) /*!< Bit mask for LLWU_PE4_WUPE14. */
675 #define BS_LLWU_PE4_WUPE14 (2U) /*!< Bit field size in bits for LLWU_PE4_WUPE14. */
677 /*! @brief Read current value of the LLWU_PE4_WUPE14 field. */
678 #define BR_LLWU_PE4_WUPE14(x) (HW_LLWU_PE4(x).B.WUPE14)
680 /*! @brief Format value for bitfield LLWU_PE4_WUPE14. */
681 #define BF_LLWU_PE4_WUPE14(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE4_WUPE14) & BM_LLWU_PE4_WUPE14)
683 /*! @brief Set the WUPE14 field to a new value. */
684 #define BW_LLWU_PE4_WUPE14(x, v) (HW_LLWU_PE4_WR(x, (HW_LLWU_PE4_RD(x) & ~BM_LLWU_PE4_WUPE14) | BF_LLWU_PE4_WUPE14(v)))
688 * @name Register LLWU_PE4, field WUPE15[7:6] (RW)
690 * Enables and configures the edge detection for the wakeup pin.
693 * - 00 - External input pin disabled as wakeup input
694 * - 01 - External input pin enabled with rising edge detection
695 * - 10 - External input pin enabled with falling edge detection
696 * - 11 - External input pin enabled with any change detection
699 #define BP_LLWU_PE4_WUPE15 (6U) /*!< Bit position for LLWU_PE4_WUPE15. */
700 #define BM_LLWU_PE4_WUPE15 (0xC0U) /*!< Bit mask for LLWU_PE4_WUPE15. */
701 #define BS_LLWU_PE4_WUPE15 (2U) /*!< Bit field size in bits for LLWU_PE4_WUPE15. */
703 /*! @brief Read current value of the LLWU_PE4_WUPE15 field. */
704 #define BR_LLWU_PE4_WUPE15(x) (HW_LLWU_PE4(x).B.WUPE15)
706 /*! @brief Format value for bitfield LLWU_PE4_WUPE15. */
707 #define BF_LLWU_PE4_WUPE15(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE4_WUPE15) & BM_LLWU_PE4_WUPE15)
709 /*! @brief Set the WUPE15 field to a new value. */
710 #define BW_LLWU_PE4_WUPE15(x, v) (HW_LLWU_PE4_WR(x, (HW_LLWU_PE4_RD(x) & ~BM_LLWU_PE4_WUPE15) | BF_LLWU_PE4_WUPE15(v)))
713 /*******************************************************************************
714 * HW_LLWU_ME - LLWU Module Enable register
715 ******************************************************************************/
718 * @brief HW_LLWU_ME - LLWU Module Enable register (RW)
722 * LLWU_ME contains the bits to enable the internal module flag as a wakeup
723 * input source for inputs MWUF7-MWUF0. This register is reset on Chip Reset not VLLS
724 * and by reset types that trigger Chip Reset not VLLS. It is unaffected by
725 * reset types that do not trigger Chip Reset not VLLS. See the
726 * IntroductionInformation found here describes the registers of the Reset Control Module (RCM). The
727 * RCM implements many of the reset functions for the chip. See the chip's reset
728 * chapter for more information. details for more information.
730 typedef union _hw_llwu_me
733 struct _hw_llwu_me_bitfields
735 uint8_t WUME0
: 1; /*!< [0] Wakeup Module Enable For Module 0 */
736 uint8_t WUME1
: 1; /*!< [1] Wakeup Module Enable for Module 1 */
737 uint8_t WUME2
: 1; /*!< [2] Wakeup Module Enable For Module 2 */
738 uint8_t WUME3
: 1; /*!< [3] Wakeup Module Enable For Module 3 */
739 uint8_t WUME4
: 1; /*!< [4] Wakeup Module Enable For Module 4 */
740 uint8_t WUME5
: 1; /*!< [5] Wakeup Module Enable For Module 5 */
741 uint8_t WUME6
: 1; /*!< [6] Wakeup Module Enable For Module 6 */
742 uint8_t WUME7
: 1; /*!< [7] Wakeup Module Enable For Module 7 */
747 * @name Constants and macros for entire LLWU_ME register
750 #define HW_LLWU_ME_ADDR(x) ((x) + 0x4U)
752 #define HW_LLWU_ME(x) (*(__IO hw_llwu_me_t *) HW_LLWU_ME_ADDR(x))
753 #define HW_LLWU_ME_RD(x) (HW_LLWU_ME(x).U)
754 #define HW_LLWU_ME_WR(x, v) (HW_LLWU_ME(x).U = (v))
755 #define HW_LLWU_ME_SET(x, v) (HW_LLWU_ME_WR(x, HW_LLWU_ME_RD(x) | (v)))
756 #define HW_LLWU_ME_CLR(x, v) (HW_LLWU_ME_WR(x, HW_LLWU_ME_RD(x) & ~(v)))
757 #define HW_LLWU_ME_TOG(x, v) (HW_LLWU_ME_WR(x, HW_LLWU_ME_RD(x) ^ (v)))
761 * Constants & macros for individual LLWU_ME bitfields
765 * @name Register LLWU_ME, field WUME0[0] (RW)
767 * Enables an internal module as a wakeup source input.
770 * - 0 - Internal module flag not used as wakeup source
771 * - 1 - Internal module flag used as wakeup source
774 #define BP_LLWU_ME_WUME0 (0U) /*!< Bit position for LLWU_ME_WUME0. */
775 #define BM_LLWU_ME_WUME0 (0x01U) /*!< Bit mask for LLWU_ME_WUME0. */
776 #define BS_LLWU_ME_WUME0 (1U) /*!< Bit field size in bits for LLWU_ME_WUME0. */
778 /*! @brief Read current value of the LLWU_ME_WUME0 field. */
779 #define BR_LLWU_ME_WUME0(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME0))
781 /*! @brief Format value for bitfield LLWU_ME_WUME0. */
782 #define BF_LLWU_ME_WUME0(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME0) & BM_LLWU_ME_WUME0)
784 /*! @brief Set the WUME0 field to a new value. */
785 #define BW_LLWU_ME_WUME0(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME0) = (v))
789 * @name Register LLWU_ME, field WUME1[1] (RW)
791 * Enables an internal module as a wakeup source input.
794 * - 0 - Internal module flag not used as wakeup source
795 * - 1 - Internal module flag used as wakeup source
798 #define BP_LLWU_ME_WUME1 (1U) /*!< Bit position for LLWU_ME_WUME1. */
799 #define BM_LLWU_ME_WUME1 (0x02U) /*!< Bit mask for LLWU_ME_WUME1. */
800 #define BS_LLWU_ME_WUME1 (1U) /*!< Bit field size in bits for LLWU_ME_WUME1. */
802 /*! @brief Read current value of the LLWU_ME_WUME1 field. */
803 #define BR_LLWU_ME_WUME1(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME1))
805 /*! @brief Format value for bitfield LLWU_ME_WUME1. */
806 #define BF_LLWU_ME_WUME1(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME1) & BM_LLWU_ME_WUME1)
808 /*! @brief Set the WUME1 field to a new value. */
809 #define BW_LLWU_ME_WUME1(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME1) = (v))
813 * @name Register LLWU_ME, field WUME2[2] (RW)
815 * Enables an internal module as a wakeup source input.
818 * - 0 - Internal module flag not used as wakeup source
819 * - 1 - Internal module flag used as wakeup source
822 #define BP_LLWU_ME_WUME2 (2U) /*!< Bit position for LLWU_ME_WUME2. */
823 #define BM_LLWU_ME_WUME2 (0x04U) /*!< Bit mask for LLWU_ME_WUME2. */
824 #define BS_LLWU_ME_WUME2 (1U) /*!< Bit field size in bits for LLWU_ME_WUME2. */
826 /*! @brief Read current value of the LLWU_ME_WUME2 field. */
827 #define BR_LLWU_ME_WUME2(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME2))
829 /*! @brief Format value for bitfield LLWU_ME_WUME2. */
830 #define BF_LLWU_ME_WUME2(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME2) & BM_LLWU_ME_WUME2)
832 /*! @brief Set the WUME2 field to a new value. */
833 #define BW_LLWU_ME_WUME2(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME2) = (v))
837 * @name Register LLWU_ME, field WUME3[3] (RW)
839 * Enables an internal module as a wakeup source input.
842 * - 0 - Internal module flag not used as wakeup source
843 * - 1 - Internal module flag used as wakeup source
846 #define BP_LLWU_ME_WUME3 (3U) /*!< Bit position for LLWU_ME_WUME3. */
847 #define BM_LLWU_ME_WUME3 (0x08U) /*!< Bit mask for LLWU_ME_WUME3. */
848 #define BS_LLWU_ME_WUME3 (1U) /*!< Bit field size in bits for LLWU_ME_WUME3. */
850 /*! @brief Read current value of the LLWU_ME_WUME3 field. */
851 #define BR_LLWU_ME_WUME3(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME3))
853 /*! @brief Format value for bitfield LLWU_ME_WUME3. */
854 #define BF_LLWU_ME_WUME3(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME3) & BM_LLWU_ME_WUME3)
856 /*! @brief Set the WUME3 field to a new value. */
857 #define BW_LLWU_ME_WUME3(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME3) = (v))
861 * @name Register LLWU_ME, field WUME4[4] (RW)
863 * Enables an internal module as a wakeup source input.
866 * - 0 - Internal module flag not used as wakeup source
867 * - 1 - Internal module flag used as wakeup source
870 #define BP_LLWU_ME_WUME4 (4U) /*!< Bit position for LLWU_ME_WUME4. */
871 #define BM_LLWU_ME_WUME4 (0x10U) /*!< Bit mask for LLWU_ME_WUME4. */
872 #define BS_LLWU_ME_WUME4 (1U) /*!< Bit field size in bits for LLWU_ME_WUME4. */
874 /*! @brief Read current value of the LLWU_ME_WUME4 field. */
875 #define BR_LLWU_ME_WUME4(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME4))
877 /*! @brief Format value for bitfield LLWU_ME_WUME4. */
878 #define BF_LLWU_ME_WUME4(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME4) & BM_LLWU_ME_WUME4)
880 /*! @brief Set the WUME4 field to a new value. */
881 #define BW_LLWU_ME_WUME4(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME4) = (v))
885 * @name Register LLWU_ME, field WUME5[5] (RW)
887 * Enables an internal module as a wakeup source input.
890 * - 0 - Internal module flag not used as wakeup source
891 * - 1 - Internal module flag used as wakeup source
894 #define BP_LLWU_ME_WUME5 (5U) /*!< Bit position for LLWU_ME_WUME5. */
895 #define BM_LLWU_ME_WUME5 (0x20U) /*!< Bit mask for LLWU_ME_WUME5. */
896 #define BS_LLWU_ME_WUME5 (1U) /*!< Bit field size in bits for LLWU_ME_WUME5. */
898 /*! @brief Read current value of the LLWU_ME_WUME5 field. */
899 #define BR_LLWU_ME_WUME5(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME5))
901 /*! @brief Format value for bitfield LLWU_ME_WUME5. */
902 #define BF_LLWU_ME_WUME5(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME5) & BM_LLWU_ME_WUME5)
904 /*! @brief Set the WUME5 field to a new value. */
905 #define BW_LLWU_ME_WUME5(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME5) = (v))
909 * @name Register LLWU_ME, field WUME6[6] (RW)
911 * Enables an internal module as a wakeup source input.
914 * - 0 - Internal module flag not used as wakeup source
915 * - 1 - Internal module flag used as wakeup source
918 #define BP_LLWU_ME_WUME6 (6U) /*!< Bit position for LLWU_ME_WUME6. */
919 #define BM_LLWU_ME_WUME6 (0x40U) /*!< Bit mask for LLWU_ME_WUME6. */
920 #define BS_LLWU_ME_WUME6 (1U) /*!< Bit field size in bits for LLWU_ME_WUME6. */
922 /*! @brief Read current value of the LLWU_ME_WUME6 field. */
923 #define BR_LLWU_ME_WUME6(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME6))
925 /*! @brief Format value for bitfield LLWU_ME_WUME6. */
926 #define BF_LLWU_ME_WUME6(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME6) & BM_LLWU_ME_WUME6)
928 /*! @brief Set the WUME6 field to a new value. */
929 #define BW_LLWU_ME_WUME6(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME6) = (v))
933 * @name Register LLWU_ME, field WUME7[7] (RW)
935 * Enables an internal module as a wakeup source input.
938 * - 0 - Internal module flag not used as wakeup source
939 * - 1 - Internal module flag used as wakeup source
942 #define BP_LLWU_ME_WUME7 (7U) /*!< Bit position for LLWU_ME_WUME7. */
943 #define BM_LLWU_ME_WUME7 (0x80U) /*!< Bit mask for LLWU_ME_WUME7. */
944 #define BS_LLWU_ME_WUME7 (1U) /*!< Bit field size in bits for LLWU_ME_WUME7. */
946 /*! @brief Read current value of the LLWU_ME_WUME7 field. */
947 #define BR_LLWU_ME_WUME7(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME7))
949 /*! @brief Format value for bitfield LLWU_ME_WUME7. */
950 #define BF_LLWU_ME_WUME7(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME7) & BM_LLWU_ME_WUME7)
952 /*! @brief Set the WUME7 field to a new value. */
953 #define BW_LLWU_ME_WUME7(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME7) = (v))
956 /*******************************************************************************
957 * HW_LLWU_F1 - LLWU Flag 1 register
958 ******************************************************************************/
961 * @brief HW_LLWU_F1 - LLWU Flag 1 register (W1C)
965 * LLWU_F1 contains the wakeup flags indicating which wakeup source caused the
966 * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
967 * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
968 * external wakeup flags are read-only and clearing a flag is accomplished by a write
969 * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
970 * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
971 * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
972 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
973 * IntroductionInformation found here describes the registers of the Reset Control
974 * Module (RCM). The RCM implements many of the reset functions for the chip. See the
975 * chip's reset chapter for more information. details for more information.
977 typedef union _hw_llwu_f1
980 struct _hw_llwu_f1_bitfields
982 uint8_t WUF0
: 1; /*!< [0] Wakeup Flag For LLWU_P0 */
983 uint8_t WUF1
: 1; /*!< [1] Wakeup Flag For LLWU_P1 */
984 uint8_t WUF2
: 1; /*!< [2] Wakeup Flag For LLWU_P2 */
985 uint8_t WUF3
: 1; /*!< [3] Wakeup Flag For LLWU_P3 */
986 uint8_t WUF4
: 1; /*!< [4] Wakeup Flag For LLWU_P4 */
987 uint8_t WUF5
: 1; /*!< [5] Wakeup Flag For LLWU_P5 */
988 uint8_t WUF6
: 1; /*!< [6] Wakeup Flag For LLWU_P6 */
989 uint8_t WUF7
: 1; /*!< [7] Wakeup Flag For LLWU_P7 */
994 * @name Constants and macros for entire LLWU_F1 register
997 #define HW_LLWU_F1_ADDR(x) ((x) + 0x5U)
999 #define HW_LLWU_F1(x) (*(__IO hw_llwu_f1_t *) HW_LLWU_F1_ADDR(x))
1000 #define HW_LLWU_F1_RD(x) (HW_LLWU_F1(x).U)
1001 #define HW_LLWU_F1_WR(x, v) (HW_LLWU_F1(x).U = (v))
1002 #define HW_LLWU_F1_SET(x, v) (HW_LLWU_F1_WR(x, HW_LLWU_F1_RD(x) | (v)))
1003 #define HW_LLWU_F1_CLR(x, v) (HW_LLWU_F1_WR(x, HW_LLWU_F1_RD(x) & ~(v)))
1004 #define HW_LLWU_F1_TOG(x, v) (HW_LLWU_F1_WR(x, HW_LLWU_F1_RD(x) ^ (v)))
1008 * Constants & macros for individual LLWU_F1 bitfields
1012 * @name Register LLWU_F1, field WUF0[0] (W1C)
1014 * Indicates that an enabled external wake-up pin was a source of exiting a
1015 * low-leakage power mode. To clear the flag, write a 1 to WUF0.
1018 * - 0 - LLWU_P0 input was not a wakeup source
1019 * - 1 - LLWU_P0 input was a wakeup source
1022 #define BP_LLWU_F1_WUF0 (0U) /*!< Bit position for LLWU_F1_WUF0. */
1023 #define BM_LLWU_F1_WUF0 (0x01U) /*!< Bit mask for LLWU_F1_WUF0. */
1024 #define BS_LLWU_F1_WUF0 (1U) /*!< Bit field size in bits for LLWU_F1_WUF0. */
1026 /*! @brief Read current value of the LLWU_F1_WUF0 field. */
1027 #define BR_LLWU_F1_WUF0(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF0))
1029 /*! @brief Format value for bitfield LLWU_F1_WUF0. */
1030 #define BF_LLWU_F1_WUF0(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF0) & BM_LLWU_F1_WUF0)
1032 /*! @brief Set the WUF0 field to a new value. */
1033 #define BW_LLWU_F1_WUF0(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF0) = (v))
1037 * @name Register LLWU_F1, field WUF1[1] (W1C)
1039 * Indicates that an enabled external wakeup pin was a source of exiting a
1040 * low-leakage power mode. To clear the flag, write a 1 to WUF1.
1043 * - 0 - LLWU_P1 input was not a wakeup source
1044 * - 1 - LLWU_P1 input was a wakeup source
1047 #define BP_LLWU_F1_WUF1 (1U) /*!< Bit position for LLWU_F1_WUF1. */
1048 #define BM_LLWU_F1_WUF1 (0x02U) /*!< Bit mask for LLWU_F1_WUF1. */
1049 #define BS_LLWU_F1_WUF1 (1U) /*!< Bit field size in bits for LLWU_F1_WUF1. */
1051 /*! @brief Read current value of the LLWU_F1_WUF1 field. */
1052 #define BR_LLWU_F1_WUF1(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF1))
1054 /*! @brief Format value for bitfield LLWU_F1_WUF1. */
1055 #define BF_LLWU_F1_WUF1(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF1) & BM_LLWU_F1_WUF1)
1057 /*! @brief Set the WUF1 field to a new value. */
1058 #define BW_LLWU_F1_WUF1(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF1) = (v))
1062 * @name Register LLWU_F1, field WUF2[2] (W1C)
1064 * Indicates that an enabled external wakeup pin was a source of exiting a
1065 * low-leakage power mode. To clear the flag, write a 1 to WUF2.
1068 * - 0 - LLWU_P2 input was not a wakeup source
1069 * - 1 - LLWU_P2 input was a wakeup source
1072 #define BP_LLWU_F1_WUF2 (2U) /*!< Bit position for LLWU_F1_WUF2. */
1073 #define BM_LLWU_F1_WUF2 (0x04U) /*!< Bit mask for LLWU_F1_WUF2. */
1074 #define BS_LLWU_F1_WUF2 (1U) /*!< Bit field size in bits for LLWU_F1_WUF2. */
1076 /*! @brief Read current value of the LLWU_F1_WUF2 field. */
1077 #define BR_LLWU_F1_WUF2(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF2))
1079 /*! @brief Format value for bitfield LLWU_F1_WUF2. */
1080 #define BF_LLWU_F1_WUF2(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF2) & BM_LLWU_F1_WUF2)
1082 /*! @brief Set the WUF2 field to a new value. */
1083 #define BW_LLWU_F1_WUF2(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF2) = (v))
1087 * @name Register LLWU_F1, field WUF3[3] (W1C)
1089 * Indicates that an enabled external wakeup pin was a source of exiting a
1090 * low-leakage power mode. To clear the flag, write a 1 to WUF3.
1093 * - 0 - LLWU_P3 input was not a wake-up source
1094 * - 1 - LLWU_P3 input was a wake-up source
1097 #define BP_LLWU_F1_WUF3 (3U) /*!< Bit position for LLWU_F1_WUF3. */
1098 #define BM_LLWU_F1_WUF3 (0x08U) /*!< Bit mask for LLWU_F1_WUF3. */
1099 #define BS_LLWU_F1_WUF3 (1U) /*!< Bit field size in bits for LLWU_F1_WUF3. */
1101 /*! @brief Read current value of the LLWU_F1_WUF3 field. */
1102 #define BR_LLWU_F1_WUF3(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF3))
1104 /*! @brief Format value for bitfield LLWU_F1_WUF3. */
1105 #define BF_LLWU_F1_WUF3(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF3) & BM_LLWU_F1_WUF3)
1107 /*! @brief Set the WUF3 field to a new value. */
1108 #define BW_LLWU_F1_WUF3(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF3) = (v))
1112 * @name Register LLWU_F1, field WUF4[4] (W1C)
1114 * Indicates that an enabled external wake-up pin was a source of exiting a
1115 * low-leakage power mode. To clear the flag, write a 1 to WUF4.
1118 * - 0 - LLWU_P4 input was not a wakeup source
1119 * - 1 - LLWU_P4 input was a wakeup source
1122 #define BP_LLWU_F1_WUF4 (4U) /*!< Bit position for LLWU_F1_WUF4. */
1123 #define BM_LLWU_F1_WUF4 (0x10U) /*!< Bit mask for LLWU_F1_WUF4. */
1124 #define BS_LLWU_F1_WUF4 (1U) /*!< Bit field size in bits for LLWU_F1_WUF4. */
1126 /*! @brief Read current value of the LLWU_F1_WUF4 field. */
1127 #define BR_LLWU_F1_WUF4(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF4))
1129 /*! @brief Format value for bitfield LLWU_F1_WUF4. */
1130 #define BF_LLWU_F1_WUF4(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF4) & BM_LLWU_F1_WUF4)
1132 /*! @brief Set the WUF4 field to a new value. */
1133 #define BW_LLWU_F1_WUF4(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF4) = (v))
1137 * @name Register LLWU_F1, field WUF5[5] (W1C)
1139 * Indicates that an enabled external wakeup pin was a source of exiting a
1140 * low-leakage power mode. To clear the flag, write a 1 to WUF5.
1143 * - 0 - LLWU_P5 input was not a wakeup source
1144 * - 1 - LLWU_P5 input was a wakeup source
1147 #define BP_LLWU_F1_WUF5 (5U) /*!< Bit position for LLWU_F1_WUF5. */
1148 #define BM_LLWU_F1_WUF5 (0x20U) /*!< Bit mask for LLWU_F1_WUF5. */
1149 #define BS_LLWU_F1_WUF5 (1U) /*!< Bit field size in bits for LLWU_F1_WUF5. */
1151 /*! @brief Read current value of the LLWU_F1_WUF5 field. */
1152 #define BR_LLWU_F1_WUF5(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF5))
1154 /*! @brief Format value for bitfield LLWU_F1_WUF5. */
1155 #define BF_LLWU_F1_WUF5(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF5) & BM_LLWU_F1_WUF5)
1157 /*! @brief Set the WUF5 field to a new value. */
1158 #define BW_LLWU_F1_WUF5(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF5) = (v))
1162 * @name Register LLWU_F1, field WUF6[6] (W1C)
1164 * Indicates that an enabled external wakeup pin was a source of exiting a
1165 * low-leakage power mode. To clear the flag, write a 1 to WUF6.
1168 * - 0 - LLWU_P6 input was not a wakeup source
1169 * - 1 - LLWU_P6 input was a wakeup source
1172 #define BP_LLWU_F1_WUF6 (6U) /*!< Bit position for LLWU_F1_WUF6. */
1173 #define BM_LLWU_F1_WUF6 (0x40U) /*!< Bit mask for LLWU_F1_WUF6. */
1174 #define BS_LLWU_F1_WUF6 (1U) /*!< Bit field size in bits for LLWU_F1_WUF6. */
1176 /*! @brief Read current value of the LLWU_F1_WUF6 field. */
1177 #define BR_LLWU_F1_WUF6(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF6))
1179 /*! @brief Format value for bitfield LLWU_F1_WUF6. */
1180 #define BF_LLWU_F1_WUF6(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF6) & BM_LLWU_F1_WUF6)
1182 /*! @brief Set the WUF6 field to a new value. */
1183 #define BW_LLWU_F1_WUF6(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF6) = (v))
1187 * @name Register LLWU_F1, field WUF7[7] (W1C)
1189 * Indicates that an enabled external wakeup pin was a source of exiting a
1190 * low-leakage power mode. To clear the flag, write a 1 to WUF7.
1193 * - 0 - LLWU_P7 input was not a wakeup source
1194 * - 1 - LLWU_P7 input was a wakeup source
1197 #define BP_LLWU_F1_WUF7 (7U) /*!< Bit position for LLWU_F1_WUF7. */
1198 #define BM_LLWU_F1_WUF7 (0x80U) /*!< Bit mask for LLWU_F1_WUF7. */
1199 #define BS_LLWU_F1_WUF7 (1U) /*!< Bit field size in bits for LLWU_F1_WUF7. */
1201 /*! @brief Read current value of the LLWU_F1_WUF7 field. */
1202 #define BR_LLWU_F1_WUF7(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF7))
1204 /*! @brief Format value for bitfield LLWU_F1_WUF7. */
1205 #define BF_LLWU_F1_WUF7(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF7) & BM_LLWU_F1_WUF7)
1207 /*! @brief Set the WUF7 field to a new value. */
1208 #define BW_LLWU_F1_WUF7(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF7) = (v))
1211 /*******************************************************************************
1212 * HW_LLWU_F2 - LLWU Flag 2 register
1213 ******************************************************************************/
1216 * @brief HW_LLWU_F2 - LLWU Flag 2 register (W1C)
1218 * Reset value: 0x00U
1220 * LLWU_F2 contains the wakeup flags indicating which wakeup source caused the
1221 * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
1222 * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
1223 * external wakeup flags are read-only and clearing a flag is accomplished by a write
1224 * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
1225 * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
1226 * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
1227 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
1228 * IntroductionInformation found here describes the registers of the Reset Control
1229 * Module (RCM). The RCM implements many of the reset functions for the chip. See the
1230 * chip's reset chapter for more information. details for more information.
1232 typedef union _hw_llwu_f2
1235 struct _hw_llwu_f2_bitfields
1237 uint8_t WUF8
: 1; /*!< [0] Wakeup Flag For LLWU_P8 */
1238 uint8_t WUF9
: 1; /*!< [1] Wakeup Flag For LLWU_P9 */
1239 uint8_t WUF10
: 1; /*!< [2] Wakeup Flag For LLWU_P10 */
1240 uint8_t WUF11
: 1; /*!< [3] Wakeup Flag For LLWU_P11 */
1241 uint8_t WUF12
: 1; /*!< [4] Wakeup Flag For LLWU_P12 */
1242 uint8_t WUF13
: 1; /*!< [5] Wakeup Flag For LLWU_P13 */
1243 uint8_t WUF14
: 1; /*!< [6] Wakeup Flag For LLWU_P14 */
1244 uint8_t WUF15
: 1; /*!< [7] Wakeup Flag For LLWU_P15 */
1249 * @name Constants and macros for entire LLWU_F2 register
1252 #define HW_LLWU_F2_ADDR(x) ((x) + 0x6U)
1254 #define HW_LLWU_F2(x) (*(__IO hw_llwu_f2_t *) HW_LLWU_F2_ADDR(x))
1255 #define HW_LLWU_F2_RD(x) (HW_LLWU_F2(x).U)
1256 #define HW_LLWU_F2_WR(x, v) (HW_LLWU_F2(x).U = (v))
1257 #define HW_LLWU_F2_SET(x, v) (HW_LLWU_F2_WR(x, HW_LLWU_F2_RD(x) | (v)))
1258 #define HW_LLWU_F2_CLR(x, v) (HW_LLWU_F2_WR(x, HW_LLWU_F2_RD(x) & ~(v)))
1259 #define HW_LLWU_F2_TOG(x, v) (HW_LLWU_F2_WR(x, HW_LLWU_F2_RD(x) ^ (v)))
1263 * Constants & macros for individual LLWU_F2 bitfields
1267 * @name Register LLWU_F2, field WUF8[0] (W1C)
1269 * Indicates that an enabled external wakeup pin was a source of exiting a
1270 * low-leakage power mode. To clear the flag, write a 1 to WUF8.
1273 * - 0 - LLWU_P8 input was not a wakeup source
1274 * - 1 - LLWU_P8 input was a wakeup source
1277 #define BP_LLWU_F2_WUF8 (0U) /*!< Bit position for LLWU_F2_WUF8. */
1278 #define BM_LLWU_F2_WUF8 (0x01U) /*!< Bit mask for LLWU_F2_WUF8. */
1279 #define BS_LLWU_F2_WUF8 (1U) /*!< Bit field size in bits for LLWU_F2_WUF8. */
1281 /*! @brief Read current value of the LLWU_F2_WUF8 field. */
1282 #define BR_LLWU_F2_WUF8(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF8))
1284 /*! @brief Format value for bitfield LLWU_F2_WUF8. */
1285 #define BF_LLWU_F2_WUF8(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF8) & BM_LLWU_F2_WUF8)
1287 /*! @brief Set the WUF8 field to a new value. */
1288 #define BW_LLWU_F2_WUF8(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF8) = (v))
1292 * @name Register LLWU_F2, field WUF9[1] (W1C)
1294 * Indicates that an enabled external wakeup pin was a source of exiting a
1295 * low-leakage power mode. To clear the flag, write a 1 to WUF9.
1298 * - 0 - LLWU_P9 input was not a wakeup source
1299 * - 1 - LLWU_P9 input was a wakeup source
1302 #define BP_LLWU_F2_WUF9 (1U) /*!< Bit position for LLWU_F2_WUF9. */
1303 #define BM_LLWU_F2_WUF9 (0x02U) /*!< Bit mask for LLWU_F2_WUF9. */
1304 #define BS_LLWU_F2_WUF9 (1U) /*!< Bit field size in bits for LLWU_F2_WUF9. */
1306 /*! @brief Read current value of the LLWU_F2_WUF9 field. */
1307 #define BR_LLWU_F2_WUF9(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF9))
1309 /*! @brief Format value for bitfield LLWU_F2_WUF9. */
1310 #define BF_LLWU_F2_WUF9(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF9) & BM_LLWU_F2_WUF9)
1312 /*! @brief Set the WUF9 field to a new value. */
1313 #define BW_LLWU_F2_WUF9(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF9) = (v))
1317 * @name Register LLWU_F2, field WUF10[2] (W1C)
1319 * Indicates that an enabled external wakeup pin was a source of exiting a
1320 * low-leakage power mode. To clear the flag, write a 1 to WUF10.
1323 * - 0 - LLWU_P10 input was not a wakeup source
1324 * - 1 - LLWU_P10 input was a wakeup source
1327 #define BP_LLWU_F2_WUF10 (2U) /*!< Bit position for LLWU_F2_WUF10. */
1328 #define BM_LLWU_F2_WUF10 (0x04U) /*!< Bit mask for LLWU_F2_WUF10. */
1329 #define BS_LLWU_F2_WUF10 (1U) /*!< Bit field size in bits for LLWU_F2_WUF10. */
1331 /*! @brief Read current value of the LLWU_F2_WUF10 field. */
1332 #define BR_LLWU_F2_WUF10(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF10))
1334 /*! @brief Format value for bitfield LLWU_F2_WUF10. */
1335 #define BF_LLWU_F2_WUF10(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF10) & BM_LLWU_F2_WUF10)
1337 /*! @brief Set the WUF10 field to a new value. */
1338 #define BW_LLWU_F2_WUF10(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF10) = (v))
1342 * @name Register LLWU_F2, field WUF11[3] (W1C)
1344 * Indicates that an enabled external wakeup pin was a source of exiting a
1345 * low-leakage power mode. To clear the flag, write a 1 to WUF11.
1348 * - 0 - LLWU_P11 input was not a wakeup source
1349 * - 1 - LLWU_P11 input was a wakeup source
1352 #define BP_LLWU_F2_WUF11 (3U) /*!< Bit position for LLWU_F2_WUF11. */
1353 #define BM_LLWU_F2_WUF11 (0x08U) /*!< Bit mask for LLWU_F2_WUF11. */
1354 #define BS_LLWU_F2_WUF11 (1U) /*!< Bit field size in bits for LLWU_F2_WUF11. */
1356 /*! @brief Read current value of the LLWU_F2_WUF11 field. */
1357 #define BR_LLWU_F2_WUF11(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF11))
1359 /*! @brief Format value for bitfield LLWU_F2_WUF11. */
1360 #define BF_LLWU_F2_WUF11(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF11) & BM_LLWU_F2_WUF11)
1362 /*! @brief Set the WUF11 field to a new value. */
1363 #define BW_LLWU_F2_WUF11(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF11) = (v))
1367 * @name Register LLWU_F2, field WUF12[4] (W1C)
1369 * Indicates that an enabled external wakeup pin was a source of exiting a
1370 * low-leakage power mode. To clear the flag, write a 1 to WUF12.
1373 * - 0 - LLWU_P12 input was not a wakeup source
1374 * - 1 - LLWU_P12 input was a wakeup source
1377 #define BP_LLWU_F2_WUF12 (4U) /*!< Bit position for LLWU_F2_WUF12. */
1378 #define BM_LLWU_F2_WUF12 (0x10U) /*!< Bit mask for LLWU_F2_WUF12. */
1379 #define BS_LLWU_F2_WUF12 (1U) /*!< Bit field size in bits for LLWU_F2_WUF12. */
1381 /*! @brief Read current value of the LLWU_F2_WUF12 field. */
1382 #define BR_LLWU_F2_WUF12(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF12))
1384 /*! @brief Format value for bitfield LLWU_F2_WUF12. */
1385 #define BF_LLWU_F2_WUF12(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF12) & BM_LLWU_F2_WUF12)
1387 /*! @brief Set the WUF12 field to a new value. */
1388 #define BW_LLWU_F2_WUF12(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF12) = (v))
1392 * @name Register LLWU_F2, field WUF13[5] (W1C)
1394 * Indicates that an enabled external wakeup pin was a source of exiting a
1395 * low-leakage power mode. To clear the flag, write a 1 to WUF13.
1398 * - 0 - LLWU_P13 input was not a wakeup source
1399 * - 1 - LLWU_P13 input was a wakeup source
1402 #define BP_LLWU_F2_WUF13 (5U) /*!< Bit position for LLWU_F2_WUF13. */
1403 #define BM_LLWU_F2_WUF13 (0x20U) /*!< Bit mask for LLWU_F2_WUF13. */
1404 #define BS_LLWU_F2_WUF13 (1U) /*!< Bit field size in bits for LLWU_F2_WUF13. */
1406 /*! @brief Read current value of the LLWU_F2_WUF13 field. */
1407 #define BR_LLWU_F2_WUF13(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF13))
1409 /*! @brief Format value for bitfield LLWU_F2_WUF13. */
1410 #define BF_LLWU_F2_WUF13(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF13) & BM_LLWU_F2_WUF13)
1412 /*! @brief Set the WUF13 field to a new value. */
1413 #define BW_LLWU_F2_WUF13(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF13) = (v))
1417 * @name Register LLWU_F2, field WUF14[6] (W1C)
1419 * Indicates that an enabled external wakeup pin was a source of exiting a
1420 * low-leakage power mode. To clear the flag, write a 1 to WUF14.
1423 * - 0 - LLWU_P14 input was not a wakeup source
1424 * - 1 - LLWU_P14 input was a wakeup source
1427 #define BP_LLWU_F2_WUF14 (6U) /*!< Bit position for LLWU_F2_WUF14. */
1428 #define BM_LLWU_F2_WUF14 (0x40U) /*!< Bit mask for LLWU_F2_WUF14. */
1429 #define BS_LLWU_F2_WUF14 (1U) /*!< Bit field size in bits for LLWU_F2_WUF14. */
1431 /*! @brief Read current value of the LLWU_F2_WUF14 field. */
1432 #define BR_LLWU_F2_WUF14(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF14))
1434 /*! @brief Format value for bitfield LLWU_F2_WUF14. */
1435 #define BF_LLWU_F2_WUF14(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF14) & BM_LLWU_F2_WUF14)
1437 /*! @brief Set the WUF14 field to a new value. */
1438 #define BW_LLWU_F2_WUF14(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF14) = (v))
1442 * @name Register LLWU_F2, field WUF15[7] (W1C)
1444 * Indicates that an enabled external wakeup pin was a source of exiting a
1445 * low-leakage power mode. To clear the flag, write a 1 to WUF15.
1448 * - 0 - LLWU_P15 input was not a wakeup source
1449 * - 1 - LLWU_P15 input was a wakeup source
1452 #define BP_LLWU_F2_WUF15 (7U) /*!< Bit position for LLWU_F2_WUF15. */
1453 #define BM_LLWU_F2_WUF15 (0x80U) /*!< Bit mask for LLWU_F2_WUF15. */
1454 #define BS_LLWU_F2_WUF15 (1U) /*!< Bit field size in bits for LLWU_F2_WUF15. */
1456 /*! @brief Read current value of the LLWU_F2_WUF15 field. */
1457 #define BR_LLWU_F2_WUF15(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF15))
1459 /*! @brief Format value for bitfield LLWU_F2_WUF15. */
1460 #define BF_LLWU_F2_WUF15(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF15) & BM_LLWU_F2_WUF15)
1462 /*! @brief Set the WUF15 field to a new value. */
1463 #define BW_LLWU_F2_WUF15(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF15) = (v))
1466 /*******************************************************************************
1467 * HW_LLWU_F3 - LLWU Flag 3 register
1468 ******************************************************************************/
1471 * @brief HW_LLWU_F3 - LLWU Flag 3 register (RO)
1473 * Reset value: 0x00U
1475 * LLWU_F3 contains the wakeup flags indicating which internal wakeup source
1476 * caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the
1477 * CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow.
1478 * For internal peripherals that are capable of running in a low-leakage power
1479 * mode, such as a real time clock module or CMP module, the flag from the
1480 * associated peripheral is accessible as the MWUFx bit. The flag will need to be cleared
1481 * in the peripheral instead of writing a 1 to the MWUFx bit. This register is
1482 * reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not
1483 * VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See
1484 * the IntroductionInformation found here describes the registers of the Reset
1485 * Control Module (RCM). The RCM implements many of the reset functions for the
1486 * chip. See the chip's reset chapter for more information. details for more
1489 typedef union _hw_llwu_f3
1492 struct _hw_llwu_f3_bitfields
1494 uint8_t MWUF0
: 1; /*!< [0] Wakeup flag For module 0 */
1495 uint8_t MWUF1
: 1; /*!< [1] Wakeup flag For module 1 */
1496 uint8_t MWUF2
: 1; /*!< [2] Wakeup flag For module 2 */
1497 uint8_t MWUF3
: 1; /*!< [3] Wakeup flag For module 3 */
1498 uint8_t MWUF4
: 1; /*!< [4] Wakeup flag For module 4 */
1499 uint8_t MWUF5
: 1; /*!< [5] Wakeup flag For module 5 */
1500 uint8_t MWUF6
: 1; /*!< [6] Wakeup flag For module 6 */
1501 uint8_t MWUF7
: 1; /*!< [7] Wakeup flag For module 7 */
1506 * @name Constants and macros for entire LLWU_F3 register
1509 #define HW_LLWU_F3_ADDR(x) ((x) + 0x7U)
1511 #define HW_LLWU_F3(x) (*(__I hw_llwu_f3_t *) HW_LLWU_F3_ADDR(x))
1512 #define HW_LLWU_F3_RD(x) (HW_LLWU_F3(x).U)
1516 * Constants & macros for individual LLWU_F3 bitfields
1520 * @name Register LLWU_F3, field MWUF0[0] (RO)
1522 * Indicates that an enabled internal peripheral was a source of exiting a
1523 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
1524 * clearing mechanism.
1527 * - 0 - Module 0 input was not a wakeup source
1528 * - 1 - Module 0 input was a wakeup source
1531 #define BP_LLWU_F3_MWUF0 (0U) /*!< Bit position for LLWU_F3_MWUF0. */
1532 #define BM_LLWU_F3_MWUF0 (0x01U) /*!< Bit mask for LLWU_F3_MWUF0. */
1533 #define BS_LLWU_F3_MWUF0 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF0. */
1535 /*! @brief Read current value of the LLWU_F3_MWUF0 field. */
1536 #define BR_LLWU_F3_MWUF0(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF0))
1540 * @name Register LLWU_F3, field MWUF1[1] (RO)
1542 * Indicates that an enabled internal peripheral was a source of exiting a
1543 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
1544 * clearing mechanism.
1547 * - 0 - Module 1 input was not a wakeup source
1548 * - 1 - Module 1 input was a wakeup source
1551 #define BP_LLWU_F3_MWUF1 (1U) /*!< Bit position for LLWU_F3_MWUF1. */
1552 #define BM_LLWU_F3_MWUF1 (0x02U) /*!< Bit mask for LLWU_F3_MWUF1. */
1553 #define BS_LLWU_F3_MWUF1 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF1. */
1555 /*! @brief Read current value of the LLWU_F3_MWUF1 field. */
1556 #define BR_LLWU_F3_MWUF1(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF1))
1560 * @name Register LLWU_F3, field MWUF2[2] (RO)
1562 * Indicates that an enabled internal peripheral was a source of exiting a
1563 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
1564 * clearing mechanism.
1567 * - 0 - Module 2 input was not a wakeup source
1568 * - 1 - Module 2 input was a wakeup source
1571 #define BP_LLWU_F3_MWUF2 (2U) /*!< Bit position for LLWU_F3_MWUF2. */
1572 #define BM_LLWU_F3_MWUF2 (0x04U) /*!< Bit mask for LLWU_F3_MWUF2. */
1573 #define BS_LLWU_F3_MWUF2 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF2. */
1575 /*! @brief Read current value of the LLWU_F3_MWUF2 field. */
1576 #define BR_LLWU_F3_MWUF2(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF2))
1580 * @name Register LLWU_F3, field MWUF3[3] (RO)
1582 * Indicates that an enabled internal peripheral was a source of exiting a
1583 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
1584 * clearing mechanism.
1587 * - 0 - Module 3 input was not a wakeup source
1588 * - 1 - Module 3 input was a wakeup source
1591 #define BP_LLWU_F3_MWUF3 (3U) /*!< Bit position for LLWU_F3_MWUF3. */
1592 #define BM_LLWU_F3_MWUF3 (0x08U) /*!< Bit mask for LLWU_F3_MWUF3. */
1593 #define BS_LLWU_F3_MWUF3 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF3. */
1595 /*! @brief Read current value of the LLWU_F3_MWUF3 field. */
1596 #define BR_LLWU_F3_MWUF3(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF3))
1600 * @name Register LLWU_F3, field MWUF4[4] (RO)
1602 * Indicates that an enabled internal peripheral was a source of exiting a
1603 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
1604 * clearing mechanism.
1607 * - 0 - Module 4 input was not a wakeup source
1608 * - 1 - Module 4 input was a wakeup source
1611 #define BP_LLWU_F3_MWUF4 (4U) /*!< Bit position for LLWU_F3_MWUF4. */
1612 #define BM_LLWU_F3_MWUF4 (0x10U) /*!< Bit mask for LLWU_F3_MWUF4. */
1613 #define BS_LLWU_F3_MWUF4 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF4. */
1615 /*! @brief Read current value of the LLWU_F3_MWUF4 field. */
1616 #define BR_LLWU_F3_MWUF4(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF4))
1620 * @name Register LLWU_F3, field MWUF5[5] (RO)
1622 * Indicates that an enabled internal peripheral was a source of exiting a
1623 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
1624 * clearing mechanism.
1627 * - 0 - Module 5 input was not a wakeup source
1628 * - 1 - Module 5 input was a wakeup source
1631 #define BP_LLWU_F3_MWUF5 (5U) /*!< Bit position for LLWU_F3_MWUF5. */
1632 #define BM_LLWU_F3_MWUF5 (0x20U) /*!< Bit mask for LLWU_F3_MWUF5. */
1633 #define BS_LLWU_F3_MWUF5 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF5. */
1635 /*! @brief Read current value of the LLWU_F3_MWUF5 field. */
1636 #define BR_LLWU_F3_MWUF5(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF5))
1640 * @name Register LLWU_F3, field MWUF6[6] (RO)
1642 * Indicates that an enabled internal peripheral was a source of exiting a
1643 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
1644 * clearing mechanism.
1647 * - 0 - Module 6 input was not a wakeup source
1648 * - 1 - Module 6 input was a wakeup source
1651 #define BP_LLWU_F3_MWUF6 (6U) /*!< Bit position for LLWU_F3_MWUF6. */
1652 #define BM_LLWU_F3_MWUF6 (0x40U) /*!< Bit mask for LLWU_F3_MWUF6. */
1653 #define BS_LLWU_F3_MWUF6 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF6. */
1655 /*! @brief Read current value of the LLWU_F3_MWUF6 field. */
1656 #define BR_LLWU_F3_MWUF6(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF6))
1660 * @name Register LLWU_F3, field MWUF7[7] (RO)
1662 * Indicates that an enabled internal peripheral was a source of exiting a
1663 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
1664 * clearing mechanism.
1667 * - 0 - Module 7 input was not a wakeup source
1668 * - 1 - Module 7 input was a wakeup source
1671 #define BP_LLWU_F3_MWUF7 (7U) /*!< Bit position for LLWU_F3_MWUF7. */
1672 #define BM_LLWU_F3_MWUF7 (0x80U) /*!< Bit mask for LLWU_F3_MWUF7. */
1673 #define BS_LLWU_F3_MWUF7 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF7. */
1675 /*! @brief Read current value of the LLWU_F3_MWUF7 field. */
1676 #define BR_LLWU_F3_MWUF7(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF7))
1679 /*******************************************************************************
1680 * HW_LLWU_FILT1 - LLWU Pin Filter 1 register
1681 ******************************************************************************/
1684 * @brief HW_LLWU_FILT1 - LLWU Pin Filter 1 register (RW)
1686 * Reset value: 0x00U
1688 * LLWU_FILT1 is a control and status register that is used to enable/disable
1689 * the digital filter 1 features for an external pin. This register is reset on
1690 * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
1691 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
1692 * IntroductionInformation found here describes the registers of the Reset Control
1693 * Module (RCM). The RCM implements many of the reset functions for the chip. See
1694 * the chip's reset chapter for more information. details for more information.
1696 typedef union _hw_llwu_filt1
1699 struct _hw_llwu_filt1_bitfields
1701 uint8_t FILTSEL
: 4; /*!< [3:0] Filter Pin Select */
1702 uint8_t RESERVED0
: 1; /*!< [4] */
1703 uint8_t FILTE
: 2; /*!< [6:5] Digital Filter On External Pin */
1704 uint8_t FILTF
: 1; /*!< [7] Filter Detect Flag */
1709 * @name Constants and macros for entire LLWU_FILT1 register
1712 #define HW_LLWU_FILT1_ADDR(x) ((x) + 0x8U)
1714 #define HW_LLWU_FILT1(x) (*(__IO hw_llwu_filt1_t *) HW_LLWU_FILT1_ADDR(x))
1715 #define HW_LLWU_FILT1_RD(x) (HW_LLWU_FILT1(x).U)
1716 #define HW_LLWU_FILT1_WR(x, v) (HW_LLWU_FILT1(x).U = (v))
1717 #define HW_LLWU_FILT1_SET(x, v) (HW_LLWU_FILT1_WR(x, HW_LLWU_FILT1_RD(x) | (v)))
1718 #define HW_LLWU_FILT1_CLR(x, v) (HW_LLWU_FILT1_WR(x, HW_LLWU_FILT1_RD(x) & ~(v)))
1719 #define HW_LLWU_FILT1_TOG(x, v) (HW_LLWU_FILT1_WR(x, HW_LLWU_FILT1_RD(x) ^ (v)))
1723 * Constants & macros for individual LLWU_FILT1 bitfields
1727 * @name Register LLWU_FILT1, field FILTSEL[3:0] (RW)
1729 * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
1732 * - 0000 - Select LLWU_P0 for filter
1733 * - 1111 - Select LLWU_P15 for filter
1736 #define BP_LLWU_FILT1_FILTSEL (0U) /*!< Bit position for LLWU_FILT1_FILTSEL. */
1737 #define BM_LLWU_FILT1_FILTSEL (0x0FU) /*!< Bit mask for LLWU_FILT1_FILTSEL. */
1738 #define BS_LLWU_FILT1_FILTSEL (4U) /*!< Bit field size in bits for LLWU_FILT1_FILTSEL. */
1740 /*! @brief Read current value of the LLWU_FILT1_FILTSEL field. */
1741 #define BR_LLWU_FILT1_FILTSEL(x) (HW_LLWU_FILT1(x).B.FILTSEL)
1743 /*! @brief Format value for bitfield LLWU_FILT1_FILTSEL. */
1744 #define BF_LLWU_FILT1_FILTSEL(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT1_FILTSEL) & BM_LLWU_FILT1_FILTSEL)
1746 /*! @brief Set the FILTSEL field to a new value. */
1747 #define BW_LLWU_FILT1_FILTSEL(x, v) (HW_LLWU_FILT1_WR(x, (HW_LLWU_FILT1_RD(x) & ~BM_LLWU_FILT1_FILTSEL) | BF_LLWU_FILT1_FILTSEL(v)))
1751 * @name Register LLWU_FILT1, field FILTE[6:5] (RW)
1753 * Controls the digital filter options for the external pin detect.
1756 * - 00 - Filter disabled
1757 * - 01 - Filter posedge detect enabled
1758 * - 10 - Filter negedge detect enabled
1759 * - 11 - Filter any edge detect enabled
1762 #define BP_LLWU_FILT1_FILTE (5U) /*!< Bit position for LLWU_FILT1_FILTE. */
1763 #define BM_LLWU_FILT1_FILTE (0x60U) /*!< Bit mask for LLWU_FILT1_FILTE. */
1764 #define BS_LLWU_FILT1_FILTE (2U) /*!< Bit field size in bits for LLWU_FILT1_FILTE. */
1766 /*! @brief Read current value of the LLWU_FILT1_FILTE field. */
1767 #define BR_LLWU_FILT1_FILTE(x) (HW_LLWU_FILT1(x).B.FILTE)
1769 /*! @brief Format value for bitfield LLWU_FILT1_FILTE. */
1770 #define BF_LLWU_FILT1_FILTE(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT1_FILTE) & BM_LLWU_FILT1_FILTE)
1772 /*! @brief Set the FILTE field to a new value. */
1773 #define BW_LLWU_FILT1_FILTE(x, v) (HW_LLWU_FILT1_WR(x, (HW_LLWU_FILT1_RD(x) & ~BM_LLWU_FILT1_FILTE) | BF_LLWU_FILT1_FILTE(v)))
1777 * @name Register LLWU_FILT1, field FILTF[7] (W1C)
1779 * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
1780 * source of exiting a low-leakage power mode. To clear the flag write a one to
1784 * - 0 - Pin Filter 1 was not a wakeup source
1785 * - 1 - Pin Filter 1 was a wakeup source
1788 #define BP_LLWU_FILT1_FILTF (7U) /*!< Bit position for LLWU_FILT1_FILTF. */
1789 #define BM_LLWU_FILT1_FILTF (0x80U) /*!< Bit mask for LLWU_FILT1_FILTF. */
1790 #define BS_LLWU_FILT1_FILTF (1U) /*!< Bit field size in bits for LLWU_FILT1_FILTF. */
1792 /*! @brief Read current value of the LLWU_FILT1_FILTF field. */
1793 #define BR_LLWU_FILT1_FILTF(x) (BITBAND_ACCESS8(HW_LLWU_FILT1_ADDR(x), BP_LLWU_FILT1_FILTF))
1795 /*! @brief Format value for bitfield LLWU_FILT1_FILTF. */
1796 #define BF_LLWU_FILT1_FILTF(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT1_FILTF) & BM_LLWU_FILT1_FILTF)
1798 /*! @brief Set the FILTF field to a new value. */
1799 #define BW_LLWU_FILT1_FILTF(x, v) (BITBAND_ACCESS8(HW_LLWU_FILT1_ADDR(x), BP_LLWU_FILT1_FILTF) = (v))
1802 /*******************************************************************************
1803 * HW_LLWU_FILT2 - LLWU Pin Filter 2 register
1804 ******************************************************************************/
1807 * @brief HW_LLWU_FILT2 - LLWU Pin Filter 2 register (RW)
1809 * Reset value: 0x00U
1811 * LLWU_FILT2 is a control and status register that is used to enable/disable
1812 * the digital filter 2 features for an external pin. This register is reset on
1813 * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
1814 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
1815 * IntroductionInformation found here describes the registers of the Reset Control
1816 * Module (RCM). The RCM implements many of the reset functions for the chip. See
1817 * the chip's reset chapter for more information. details for more information.
1819 typedef union _hw_llwu_filt2
1822 struct _hw_llwu_filt2_bitfields
1824 uint8_t FILTSEL
: 4; /*!< [3:0] Filter Pin Select */
1825 uint8_t RESERVED0
: 1; /*!< [4] */
1826 uint8_t FILTE
: 2; /*!< [6:5] Digital Filter On External Pin */
1827 uint8_t FILTF
: 1; /*!< [7] Filter Detect Flag */
1832 * @name Constants and macros for entire LLWU_FILT2 register
1835 #define HW_LLWU_FILT2_ADDR(x) ((x) + 0x9U)
1837 #define HW_LLWU_FILT2(x) (*(__IO hw_llwu_filt2_t *) HW_LLWU_FILT2_ADDR(x))
1838 #define HW_LLWU_FILT2_RD(x) (HW_LLWU_FILT2(x).U)
1839 #define HW_LLWU_FILT2_WR(x, v) (HW_LLWU_FILT2(x).U = (v))
1840 #define HW_LLWU_FILT2_SET(x, v) (HW_LLWU_FILT2_WR(x, HW_LLWU_FILT2_RD(x) | (v)))
1841 #define HW_LLWU_FILT2_CLR(x, v) (HW_LLWU_FILT2_WR(x, HW_LLWU_FILT2_RD(x) & ~(v)))
1842 #define HW_LLWU_FILT2_TOG(x, v) (HW_LLWU_FILT2_WR(x, HW_LLWU_FILT2_RD(x) ^ (v)))
1846 * Constants & macros for individual LLWU_FILT2 bitfields
1850 * @name Register LLWU_FILT2, field FILTSEL[3:0] (RW)
1852 * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
1855 * - 0000 - Select LLWU_P0 for filter
1856 * - 1111 - Select LLWU_P15 for filter
1859 #define BP_LLWU_FILT2_FILTSEL (0U) /*!< Bit position for LLWU_FILT2_FILTSEL. */
1860 #define BM_LLWU_FILT2_FILTSEL (0x0FU) /*!< Bit mask for LLWU_FILT2_FILTSEL. */
1861 #define BS_LLWU_FILT2_FILTSEL (4U) /*!< Bit field size in bits for LLWU_FILT2_FILTSEL. */
1863 /*! @brief Read current value of the LLWU_FILT2_FILTSEL field. */
1864 #define BR_LLWU_FILT2_FILTSEL(x) (HW_LLWU_FILT2(x).B.FILTSEL)
1866 /*! @brief Format value for bitfield LLWU_FILT2_FILTSEL. */
1867 #define BF_LLWU_FILT2_FILTSEL(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT2_FILTSEL) & BM_LLWU_FILT2_FILTSEL)
1869 /*! @brief Set the FILTSEL field to a new value. */
1870 #define BW_LLWU_FILT2_FILTSEL(x, v) (HW_LLWU_FILT2_WR(x, (HW_LLWU_FILT2_RD(x) & ~BM_LLWU_FILT2_FILTSEL) | BF_LLWU_FILT2_FILTSEL(v)))
1874 * @name Register LLWU_FILT2, field FILTE[6:5] (RW)
1876 * Controls the digital filter options for the external pin detect.
1879 * - 00 - Filter disabled
1880 * - 01 - Filter posedge detect enabled
1881 * - 10 - Filter negedge detect enabled
1882 * - 11 - Filter any edge detect enabled
1885 #define BP_LLWU_FILT2_FILTE (5U) /*!< Bit position for LLWU_FILT2_FILTE. */
1886 #define BM_LLWU_FILT2_FILTE (0x60U) /*!< Bit mask for LLWU_FILT2_FILTE. */
1887 #define BS_LLWU_FILT2_FILTE (2U) /*!< Bit field size in bits for LLWU_FILT2_FILTE. */
1889 /*! @brief Read current value of the LLWU_FILT2_FILTE field. */
1890 #define BR_LLWU_FILT2_FILTE(x) (HW_LLWU_FILT2(x).B.FILTE)
1892 /*! @brief Format value for bitfield LLWU_FILT2_FILTE. */
1893 #define BF_LLWU_FILT2_FILTE(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT2_FILTE) & BM_LLWU_FILT2_FILTE)
1895 /*! @brief Set the FILTE field to a new value. */
1896 #define BW_LLWU_FILT2_FILTE(x, v) (HW_LLWU_FILT2_WR(x, (HW_LLWU_FILT2_RD(x) & ~BM_LLWU_FILT2_FILTE) | BF_LLWU_FILT2_FILTE(v)))
1900 * @name Register LLWU_FILT2, field FILTF[7] (W1C)
1902 * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
1903 * source of exiting a low-leakage power mode. To clear the flag write a one to
1907 * - 0 - Pin Filter 2 was not a wakeup source
1908 * - 1 - Pin Filter 2 was a wakeup source
1911 #define BP_LLWU_FILT2_FILTF (7U) /*!< Bit position for LLWU_FILT2_FILTF. */
1912 #define BM_LLWU_FILT2_FILTF (0x80U) /*!< Bit mask for LLWU_FILT2_FILTF. */
1913 #define BS_LLWU_FILT2_FILTF (1U) /*!< Bit field size in bits for LLWU_FILT2_FILTF. */
1915 /*! @brief Read current value of the LLWU_FILT2_FILTF field. */
1916 #define BR_LLWU_FILT2_FILTF(x) (BITBAND_ACCESS8(HW_LLWU_FILT2_ADDR(x), BP_LLWU_FILT2_FILTF))
1918 /*! @brief Format value for bitfield LLWU_FILT2_FILTF. */
1919 #define BF_LLWU_FILT2_FILTF(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT2_FILTF) & BM_LLWU_FILT2_FILTF)
1921 /*! @brief Set the FILTF field to a new value. */
1922 #define BW_LLWU_FILT2_FILTF(x, v) (BITBAND_ACCESS8(HW_LLWU_FILT2_ADDR(x), BP_LLWU_FILT2_FILTF) = (v))
1925 /*******************************************************************************
1926 * HW_LLWU_RST - LLWU Reset Enable register
1927 ******************************************************************************/
1930 * @brief HW_LLWU_RST - LLWU Reset Enable register (RW)
1932 * Reset value: 0x02U
1934 * LLWU_RST is a control register that is used to enable/disable the digital
1935 * filter for the external pin detect and RESET pin. This register is reset on Chip
1936 * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
1937 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
1938 * IntroductionInformation found here describes the registers of the Reset Control
1939 * Module (RCM). The RCM implements many of the reset functions for the chip. See the
1940 * chip's reset chapter for more information. details for more information.
1942 typedef union _hw_llwu_rst
1945 struct _hw_llwu_rst_bitfields
1947 uint8_t RSTFILT
: 1; /*!< [0] Digital Filter On RESET Pin */
1948 uint8_t LLRSTE
: 1; /*!< [1] Low-Leakage Mode RESET Enable */
1949 uint8_t RESERVED0
: 6; /*!< [7:2] */
1954 * @name Constants and macros for entire LLWU_RST register
1957 #define HW_LLWU_RST_ADDR(x) ((x) + 0xAU)
1959 #define HW_LLWU_RST(x) (*(__IO hw_llwu_rst_t *) HW_LLWU_RST_ADDR(x))
1960 #define HW_LLWU_RST_RD(x) (HW_LLWU_RST(x).U)
1961 #define HW_LLWU_RST_WR(x, v) (HW_LLWU_RST(x).U = (v))
1962 #define HW_LLWU_RST_SET(x, v) (HW_LLWU_RST_WR(x, HW_LLWU_RST_RD(x) | (v)))
1963 #define HW_LLWU_RST_CLR(x, v) (HW_LLWU_RST_WR(x, HW_LLWU_RST_RD(x) & ~(v)))
1964 #define HW_LLWU_RST_TOG(x, v) (HW_LLWU_RST_WR(x, HW_LLWU_RST_RD(x) ^ (v)))
1968 * Constants & macros for individual LLWU_RST bitfields
1972 * @name Register LLWU_RST, field RSTFILT[0] (RW)
1974 * Enables the digital filter for the RESET pin during LLS, VLLS3, VLLS2, or
1978 * - 0 - Filter not enabled
1979 * - 1 - Filter enabled
1982 #define BP_LLWU_RST_RSTFILT (0U) /*!< Bit position for LLWU_RST_RSTFILT. */
1983 #define BM_LLWU_RST_RSTFILT (0x01U) /*!< Bit mask for LLWU_RST_RSTFILT. */
1984 #define BS_LLWU_RST_RSTFILT (1U) /*!< Bit field size in bits for LLWU_RST_RSTFILT. */
1986 /*! @brief Read current value of the LLWU_RST_RSTFILT field. */
1987 #define BR_LLWU_RST_RSTFILT(x) (BITBAND_ACCESS8(HW_LLWU_RST_ADDR(x), BP_LLWU_RST_RSTFILT))
1989 /*! @brief Format value for bitfield LLWU_RST_RSTFILT. */
1990 #define BF_LLWU_RST_RSTFILT(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_RST_RSTFILT) & BM_LLWU_RST_RSTFILT)
1992 /*! @brief Set the RSTFILT field to a new value. */
1993 #define BW_LLWU_RST_RSTFILT(x, v) (BITBAND_ACCESS8(HW_LLWU_RST_ADDR(x), BP_LLWU_RST_RSTFILT) = (v))
1997 * @name Register LLWU_RST, field LLRSTE[1] (RW)
1999 * This bit must be set to allow the device to be reset while in a low-leakage
2000 * power mode. On devices where Reset is not a dedicated pin, the RESET pin must
2001 * also be enabled in the explicit port mux control.
2004 * - 0 - RESET pin not enabled as a leakage mode exit source
2005 * - 1 - RESET pin enabled as a low leakage mode exit source
2008 #define BP_LLWU_RST_LLRSTE (1U) /*!< Bit position for LLWU_RST_LLRSTE. */
2009 #define BM_LLWU_RST_LLRSTE (0x02U) /*!< Bit mask for LLWU_RST_LLRSTE. */
2010 #define BS_LLWU_RST_LLRSTE (1U) /*!< Bit field size in bits for LLWU_RST_LLRSTE. */
2012 /*! @brief Read current value of the LLWU_RST_LLRSTE field. */
2013 #define BR_LLWU_RST_LLRSTE(x) (BITBAND_ACCESS8(HW_LLWU_RST_ADDR(x), BP_LLWU_RST_LLRSTE))
2015 /*! @brief Format value for bitfield LLWU_RST_LLRSTE. */
2016 #define BF_LLWU_RST_LLRSTE(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_RST_LLRSTE) & BM_LLWU_RST_LLRSTE)
2018 /*! @brief Set the LLRSTE field to a new value. */
2019 #define BW_LLWU_RST_LLRSTE(x, v) (BITBAND_ACCESS8(HW_LLWU_RST_ADDR(x), BP_LLWU_RST_LLRSTE) = (v))
2022 /*******************************************************************************
2023 * hw_llwu_t - module struct
2024 ******************************************************************************/
2026 * @brief All LLWU module registers.
2029 typedef struct _hw_llwu
2031 __IO hw_llwu_pe1_t PE1
; /*!< [0x0] LLWU Pin Enable 1 register */
2032 __IO hw_llwu_pe2_t PE2
; /*!< [0x1] LLWU Pin Enable 2 register */
2033 __IO hw_llwu_pe3_t PE3
; /*!< [0x2] LLWU Pin Enable 3 register */
2034 __IO hw_llwu_pe4_t PE4
; /*!< [0x3] LLWU Pin Enable 4 register */
2035 __IO hw_llwu_me_t ME
; /*!< [0x4] LLWU Module Enable register */
2036 __IO hw_llwu_f1_t F1
; /*!< [0x5] LLWU Flag 1 register */
2037 __IO hw_llwu_f2_t F2
; /*!< [0x6] LLWU Flag 2 register */
2038 __I hw_llwu_f3_t F3
; /*!< [0x7] LLWU Flag 3 register */
2039 __IO hw_llwu_filt1_t FILT1
; /*!< [0x8] LLWU Pin Filter 1 register */
2040 __IO hw_llwu_filt2_t FILT2
; /*!< [0x9] LLWU Pin Filter 2 register */
2041 __IO hw_llwu_rst_t RST
; /*!< [0xA] LLWU Reset Enable register */
2045 /*! @brief Macro to access all LLWU registers. */
2046 /*! @param x LLWU module instance base address. */
2047 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
2048 * use the '&' operator, like <code>&HW_LLWU(LLWU_BASE)</code>. */
2049 #define HW_LLWU(x) (*(hw_llwu_t *)(x))
2051 #endif /* __HW_LLWU_REGISTERS_H__ */