tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_lptmr.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
   9 **     Version:             rev. 2.5, 2014-02-10
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-08-12)
  48 **         Initial version.
  49 **     - rev. 2.0 (2013-10-29)
  50 **         Register accessor macros added to the memory map.
  51 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  52 **         Startup file for gcc has been updated according to CMSIS 3.2.
  53 **         System initialization updated.
  54 **         MCG - registers updated.
  55 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-09)
  59 **         DMA - EARS register removed.
  60 **         AIPS0, AIPS1 - MPRA register updated.
  61 **     - rev. 2.3 (2014-01-24)
  62 **         Update according to reference manual rev. 2
  63 **         ENET, MCG, MCM, SIM, USB - registers updated
  64 **     - rev. 2.4 (2014-02-10)
  65 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  66 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  67 **     - rev. 2.5 (2014-02-10)
  68 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  69 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  70 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  71 **
  72 ** ###################################################################
  73 */
  74
  75 /*
  76  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  77  *
  78  * This file was generated automatically and any changes may be lost.
  79  */
  80 #ifndef __HW_LPTMR_REGISTERS_H__
  81 #define __HW_LPTMR_REGISTERS_H__
  82
  83 #include "MK64F12.h"
  84 #include "fsl_bitaccess.h"
  85
  86 /*
  87  * MK64F12 LPTMR
  88  *
  89  * Low Power Timer
  90  *
  91  * Registers defined in this header file:
  92  * - HW_LPTMR_CSR - Low Power Timer Control Status Register
  93  * - HW_LPTMR_PSR - Low Power Timer Prescale Register
  94  * - HW_LPTMR_CMR - Low Power Timer Compare Register
  95  * - HW_LPTMR_CNR - Low Power Timer Counter Register
  96  *
  97  * - hw_lptmr_t - Struct containing all module registers.
  98  */
  99
 100 #define HW_LPTMR_INSTANCE_COUNT (1U) /*!< Number of instances of the LPTMR module. */
 101
 102 /*******************************************************************************
 103  * HW_LPTMR_CSR - Low Power Timer Control Status Register
 104  ******************************************************************************/
 105
 106 /*!
 107  * @brief HW_LPTMR_CSR - Low Power Timer Control Status Register (RW)
 108  *
 109  * Reset value: 0x00000000U
 110  */
 111 typedef union _hw_lptmr_csr
 112 {
 113     uint32_t U;
 114     struct _hw_lptmr_csr_bitfields
 115     {
 116         uint32_t TEN : 1;              /*!< [0] Timer Enable */
 117         uint32_t TMS : 1;              /*!< [1] Timer Mode Select */
 118         uint32_t TFC : 1;              /*!< [2] Timer Free-Running Counter */
 119         uint32_t TPP : 1;              /*!< [3] Timer Pin Polarity */
 120         uint32_t TPS : 2;              /*!< [5:4] Timer Pin Select */
 121         uint32_t TIE : 1;              /*!< [6] Timer Interrupt Enable */
 122         uint32_t TCF : 1;              /*!< [7] Timer Compare Flag */
 123         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
 124     } B;
 125 } hw_lptmr_csr_t;
 126
 127 /*!
 128  * @name Constants and macros for entire LPTMR_CSR register
 129  */
 130 /*@{*/
 131 #define HW_LPTMR_CSR_ADDR(x)     ((x) + 0x0U)
 132
 133 #define HW_LPTMR_CSR(x)          (*(__IO hw_lptmr_csr_t *) HW_LPTMR_CSR_ADDR(x))
 134 #define HW_LPTMR_CSR_RD(x)       (HW_LPTMR_CSR(x).U)
 135 #define HW_LPTMR_CSR_WR(x, v)    (HW_LPTMR_CSR(x).U = (v))
 136 #define HW_LPTMR_CSR_SET(x, v)   (HW_LPTMR_CSR_WR(x, HW_LPTMR_CSR_RD(x) |  (v)))
 137 #define HW_LPTMR_CSR_CLR(x, v)   (HW_LPTMR_CSR_WR(x, HW_LPTMR_CSR_RD(x) & ~(v)))
 138 #define HW_LPTMR_CSR_TOG(x, v)   (HW_LPTMR_CSR_WR(x, HW_LPTMR_CSR_RD(x) ^  (v)))
 139 /*@}*/
 140
 141 /*
 142  * Constants & macros for individual LPTMR_CSR bitfields
 143  */
 144
 145 /*!
 146  * @name Register LPTMR_CSR, field TEN[0] (RW)
 147  *
 148  * When TEN is clear, it resets the LPTMR internal logic, including the CNR and
 149  * TCF. When TEN is set, the LPTMR is enabled. While writing 1 to this field,
 150  * CSR[5:1] must not be altered.
 151  *
 152  * Values:
 153  * - 0 - LPTMR is disabled and internal logic is reset.
 154  * - 1 - LPTMR is enabled.
 155  */
 156 /*@{*/
 157 #define BP_LPTMR_CSR_TEN     (0U)          /*!< Bit position for LPTMR_CSR_TEN. */
 158 #define BM_LPTMR_CSR_TEN     (0x00000001U) /*!< Bit mask for LPTMR_CSR_TEN. */
 159 #define BS_LPTMR_CSR_TEN     (1U)          /*!< Bit field size in bits for LPTMR_CSR_TEN. */
 160
 161 /*! @brief Read current value of the LPTMR_CSR_TEN field. */
 162 #define BR_LPTMR_CSR_TEN(x)  (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TEN))
 163
 164 /*! @brief Format value for bitfield LPTMR_CSR_TEN. */
 165 #define BF_LPTMR_CSR_TEN(v)  ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TEN) & BM_LPTMR_CSR_TEN)
 166
 167 /*! @brief Set the TEN field to a new value. */
 168 #define BW_LPTMR_CSR_TEN(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TEN) = (v))
 169 /*@}*/
 170
 171 /*!
 172  * @name Register LPTMR_CSR, field TMS[1] (RW)
 173  *
 174  * Configures the mode of the LPTMR. TMS must be altered only when the LPTMR is
 175  * disabled.
 176  *
 177  * Values:
 178  * - 0 - Time Counter mode.
 179  * - 1 - Pulse Counter mode.
 180  */
 181 /*@{*/
 182 #define BP_LPTMR_CSR_TMS     (1U)          /*!< Bit position for LPTMR_CSR_TMS. */
 183 #define BM_LPTMR_CSR_TMS     (0x00000002U) /*!< Bit mask for LPTMR_CSR_TMS. */
 184 #define BS_LPTMR_CSR_TMS     (1U)          /*!< Bit field size in bits for LPTMR_CSR_TMS. */
 185
 186 /*! @brief Read current value of the LPTMR_CSR_TMS field. */
 187 #define BR_LPTMR_CSR_TMS(x)  (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TMS))
 188
 189 /*! @brief Format value for bitfield LPTMR_CSR_TMS. */
 190 #define BF_LPTMR_CSR_TMS(v)  ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TMS) & BM_LPTMR_CSR_TMS)
 191
 192 /*! @brief Set the TMS field to a new value. */
 193 #define BW_LPTMR_CSR_TMS(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TMS) = (v))
 194 /*@}*/
 195
 196 /*!
 197  * @name Register LPTMR_CSR, field TFC[2] (RW)
 198  *
 199  * When clear, TFC configures the CNR to reset whenever TCF is set. When set,
 200  * TFC configures the CNR to reset on overflow. TFC must be altered only when the
 201  * LPTMR is disabled.
 202  *
 203  * Values:
 204  * - 0 - CNR is reset whenever TCF is set.
 205  * - 1 - CNR is reset on overflow.
 206  */
 207 /*@{*/
 208 #define BP_LPTMR_CSR_TFC     (2U)          /*!< Bit position for LPTMR_CSR_TFC. */
 209 #define BM_LPTMR_CSR_TFC     (0x00000004U) /*!< Bit mask for LPTMR_CSR_TFC. */
 210 #define BS_LPTMR_CSR_TFC     (1U)          /*!< Bit field size in bits for LPTMR_CSR_TFC. */
 211
 212 /*! @brief Read current value of the LPTMR_CSR_TFC field. */
 213 #define BR_LPTMR_CSR_TFC(x)  (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TFC))
 214
 215 /*! @brief Format value for bitfield LPTMR_CSR_TFC. */
 216 #define BF_LPTMR_CSR_TFC(v)  ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TFC) & BM_LPTMR_CSR_TFC)
 217
 218 /*! @brief Set the TFC field to a new value. */
 219 #define BW_LPTMR_CSR_TFC(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TFC) = (v))
 220 /*@}*/
 221
 222 /*!
 223  * @name Register LPTMR_CSR, field TPP[3] (RW)
 224  *
 225  * Configures the polarity of the input source in Pulse Counter mode. TPP must
 226  * be changed only when the LPTMR is disabled.
 227  *
 228  * Values:
 229  * - 0 - Pulse Counter input source is active-high, and the CNR will increment
 230  *     on the rising-edge.
 231  * - 1 - Pulse Counter input source is active-low, and the CNR will increment on
 232  *     the falling-edge.
 233  */
 234 /*@{*/
 235 #define BP_LPTMR_CSR_TPP     (3U)          /*!< Bit position for LPTMR_CSR_TPP. */
 236 #define BM_LPTMR_CSR_TPP     (0x00000008U) /*!< Bit mask for LPTMR_CSR_TPP. */
 237 #define BS_LPTMR_CSR_TPP     (1U)          /*!< Bit field size in bits for LPTMR_CSR_TPP. */
 238
 239 /*! @brief Read current value of the LPTMR_CSR_TPP field. */
 240 #define BR_LPTMR_CSR_TPP(x)  (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TPP))
 241
 242 /*! @brief Format value for bitfield LPTMR_CSR_TPP. */
 243 #define BF_LPTMR_CSR_TPP(v)  ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TPP) & BM_LPTMR_CSR_TPP)
 244
 245 /*! @brief Set the TPP field to a new value. */
 246 #define BW_LPTMR_CSR_TPP(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TPP) = (v))
 247 /*@}*/
 248
 249 /*!
 250  * @name Register LPTMR_CSR, field TPS[5:4] (RW)
 251  *
 252  * Configures the input source to be used in Pulse Counter mode. TPS must be
 253  * altered only when the LPTMR is disabled. The input connections vary by device.
 254  * See the chip configuration details for information on the connections to these
 255  * inputs.
 256  *
 257  * Values:
 258  * - 00 - Pulse counter input 0 is selected.
 259  * - 01 - Pulse counter input 1 is selected.
 260  * - 10 - Pulse counter input 2 is selected.
 261  * - 11 - Pulse counter input 3 is selected.
 262  */
 263 /*@{*/
 264 #define BP_LPTMR_CSR_TPS     (4U)          /*!< Bit position for LPTMR_CSR_TPS. */
 265 #define BM_LPTMR_CSR_TPS     (0x00000030U) /*!< Bit mask for LPTMR_CSR_TPS. */
 266 #define BS_LPTMR_CSR_TPS     (2U)          /*!< Bit field size in bits for LPTMR_CSR_TPS. */
 267
 268 /*! @brief Read current value of the LPTMR_CSR_TPS field. */
 269 #define BR_LPTMR_CSR_TPS(x)  (HW_LPTMR_CSR(x).B.TPS)
 270
 271 /*! @brief Format value for bitfield LPTMR_CSR_TPS. */
 272 #define BF_LPTMR_CSR_TPS(v)  ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TPS) & BM_LPTMR_CSR_TPS)
 273
 274 /*! @brief Set the TPS field to a new value. */
 275 #define BW_LPTMR_CSR_TPS(x, v) (HW_LPTMR_CSR_WR(x, (HW_LPTMR_CSR_RD(x) & ~BM_LPTMR_CSR_TPS) | BF_LPTMR_CSR_TPS(v)))
 276 /*@}*/
 277
 278 /*!
 279  * @name Register LPTMR_CSR, field TIE[6] (RW)
 280  *
 281  * When TIE is set, the LPTMR Interrupt is generated whenever TCF is also set.
 282  *
 283  * Values:
 284  * - 0 - Timer interrupt disabled.
 285  * - 1 - Timer interrupt enabled.
 286  */
 287 /*@{*/
 288 #define BP_LPTMR_CSR_TIE     (6U)          /*!< Bit position for LPTMR_CSR_TIE. */
 289 #define BM_LPTMR_CSR_TIE     (0x00000040U) /*!< Bit mask for LPTMR_CSR_TIE. */
 290 #define BS_LPTMR_CSR_TIE     (1U)          /*!< Bit field size in bits for LPTMR_CSR_TIE. */
 291
 292 /*! @brief Read current value of the LPTMR_CSR_TIE field. */
 293 #define BR_LPTMR_CSR_TIE(x)  (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TIE))
 294
 295 /*! @brief Format value for bitfield LPTMR_CSR_TIE. */
 296 #define BF_LPTMR_CSR_TIE(v)  ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TIE) & BM_LPTMR_CSR_TIE)
 297
 298 /*! @brief Set the TIE field to a new value. */
 299 #define BW_LPTMR_CSR_TIE(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TIE) = (v))
 300 /*@}*/
 301
 302 /*!
 303  * @name Register LPTMR_CSR, field TCF[7] (W1C)
 304  *
 305  * TCF is set when the LPTMR is enabled and the CNR equals the CMR and
 306  * increments. TCF is cleared when the LPTMR is disabled or a logic 1 is written to it.
 307  *
 308  * Values:
 309  * - 0 - The value of CNR is not equal to CMR and increments.
 310  * - 1 - The value of CNR is equal to CMR and increments.
 311  */
 312 /*@{*/
 313 #define BP_LPTMR_CSR_TCF     (7U)          /*!< Bit position for LPTMR_CSR_TCF. */
 314 #define BM_LPTMR_CSR_TCF     (0x00000080U) /*!< Bit mask for LPTMR_CSR_TCF. */
 315 #define BS_LPTMR_CSR_TCF     (1U)          /*!< Bit field size in bits for LPTMR_CSR_TCF. */
 316
 317 /*! @brief Read current value of the LPTMR_CSR_TCF field. */
 318 #define BR_LPTMR_CSR_TCF(x)  (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TCF))
 319
 320 /*! @brief Format value for bitfield LPTMR_CSR_TCF. */
 321 #define BF_LPTMR_CSR_TCF(v)  ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TCF) & BM_LPTMR_CSR_TCF)
 322
 323 /*! @brief Set the TCF field to a new value. */
 324 #define BW_LPTMR_CSR_TCF(x, v) (BITBAND_ACCESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TCF) = (v))
 325 /*@}*/
 326
 327 /*******************************************************************************
 328  * HW_LPTMR_PSR - Low Power Timer Prescale Register
 329  ******************************************************************************/
 330
 331 /*!
 332  * @brief HW_LPTMR_PSR - Low Power Timer Prescale Register (RW)
 333  *
 334  * Reset value: 0x00000000U
 335  */
 336 typedef union _hw_lptmr_psr
 337 {
 338     uint32_t U;
 339     struct _hw_lptmr_psr_bitfields
 340     {
 341         uint32_t PCS : 2;              /*!< [1:0] Prescaler Clock Select */
 342         uint32_t PBYP : 1;             /*!< [2] Prescaler Bypass */
 343         uint32_t PRESCALE : 4;         /*!< [6:3] Prescale Value */
 344         uint32_t RESERVED0 : 25;       /*!< [31:7]  */
 345     } B;
 346 } hw_lptmr_psr_t;
 347
 348 /*!
 349  * @name Constants and macros for entire LPTMR_PSR register
 350  */
 351 /*@{*/
 352 #define HW_LPTMR_PSR_ADDR(x)     ((x) + 0x4U)
 353
 354 #define HW_LPTMR_PSR(x)          (*(__IO hw_lptmr_psr_t *) HW_LPTMR_PSR_ADDR(x))
 355 #define HW_LPTMR_PSR_RD(x)       (HW_LPTMR_PSR(x).U)
 356 #define HW_LPTMR_PSR_WR(x, v)    (HW_LPTMR_PSR(x).U = (v))
 357 #define HW_LPTMR_PSR_SET(x, v)   (HW_LPTMR_PSR_WR(x, HW_LPTMR_PSR_RD(x) |  (v)))
 358 #define HW_LPTMR_PSR_CLR(x, v)   (HW_LPTMR_PSR_WR(x, HW_LPTMR_PSR_RD(x) & ~(v)))
 359 #define HW_LPTMR_PSR_TOG(x, v)   (HW_LPTMR_PSR_WR(x, HW_LPTMR_PSR_RD(x) ^  (v)))
 360 /*@}*/
 361
 362 /*
 363  * Constants & macros for individual LPTMR_PSR bitfields
 364  */
 365
 366 /*!
 367  * @name Register LPTMR_PSR, field PCS[1:0] (RW)
 368  *
 369  * Selects the clock to be used by the LPTMR prescaler/glitch filter. PCS must
 370  * be altered only when the LPTMR is disabled. The clock connections vary by
 371  * device. See the chip configuration details for information on the connections to
 372  * these inputs.
 373  *
 374  * Values:
 375  * - 00 - Prescaler/glitch filter clock 0 selected.
 376  * - 01 - Prescaler/glitch filter clock 1 selected.
 377  * - 10 - Prescaler/glitch filter clock 2 selected.
 378  * - 11 - Prescaler/glitch filter clock 3 selected.
 379  */
 380 /*@{*/
 381 #define BP_LPTMR_PSR_PCS     (0U)          /*!< Bit position for LPTMR_PSR_PCS. */
 382 #define BM_LPTMR_PSR_PCS     (0x00000003U) /*!< Bit mask for LPTMR_PSR_PCS. */
 383 #define BS_LPTMR_PSR_PCS     (2U)          /*!< Bit field size in bits for LPTMR_PSR_PCS. */
 384
 385 /*! @brief Read current value of the LPTMR_PSR_PCS field. */
 386 #define BR_LPTMR_PSR_PCS(x)  (HW_LPTMR_PSR(x).B.PCS)
 387
 388 /*! @brief Format value for bitfield LPTMR_PSR_PCS. */
 389 #define BF_LPTMR_PSR_PCS(v)  ((uint32_t)((uint32_t)(v) << BP_LPTMR_PSR_PCS) & BM_LPTMR_PSR_PCS)
 390
 391 /*! @brief Set the PCS field to a new value. */
 392 #define BW_LPTMR_PSR_PCS(x, v) (HW_LPTMR_PSR_WR(x, (HW_LPTMR_PSR_RD(x) & ~BM_LPTMR_PSR_PCS) | BF_LPTMR_PSR_PCS(v)))
 393 /*@}*/
 394
 395 /*!
 396  * @name Register LPTMR_PSR, field PBYP[2] (RW)
 397  *
 398  * When PBYP is set, the selected prescaler clock in Time Counter mode or
 399  * selected input source in Pulse Counter mode directly clocks the CNR. When PBYP is
 400  * clear, the CNR is clocked by the output of the prescaler/glitch filter. PBYP
 401  * must be altered only when the LPTMR is disabled.
 402  *
 403  * Values:
 404  * - 0 - Prescaler/glitch filter is enabled.
 405  * - 1 - Prescaler/glitch filter is bypassed.
 406  */
 407 /*@{*/
 408 #define BP_LPTMR_PSR_PBYP    (2U)          /*!< Bit position for LPTMR_PSR_PBYP. */
 409 #define BM_LPTMR_PSR_PBYP    (0x00000004U) /*!< Bit mask for LPTMR_PSR_PBYP. */
 410 #define BS_LPTMR_PSR_PBYP    (1U)          /*!< Bit field size in bits for LPTMR_PSR_PBYP. */
 411
 412 /*! @brief Read current value of the LPTMR_PSR_PBYP field. */
 413 #define BR_LPTMR_PSR_PBYP(x) (BITBAND_ACCESS32(HW_LPTMR_PSR_ADDR(x), BP_LPTMR_PSR_PBYP))
 414
 415 /*! @brief Format value for bitfield LPTMR_PSR_PBYP. */
 416 #define BF_LPTMR_PSR_PBYP(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_PSR_PBYP) & BM_LPTMR_PSR_PBYP)
 417
 418 /*! @brief Set the PBYP field to a new value. */
 419 #define BW_LPTMR_PSR_PBYP(x, v) (BITBAND_ACCESS32(HW_LPTMR_PSR_ADDR(x), BP_LPTMR_PSR_PBYP) = (v))
 420 /*@}*/
 421
 422 /*!
 423  * @name Register LPTMR_PSR, field PRESCALE[6:3] (RW)
 424  *
 425  * Configures the size of the Prescaler in Time Counter mode or width of the
 426  * glitch filter in Pulse Counter mode. PRESCALE must be altered only when the LPTMR
 427  * is disabled.
 428  *
 429  * Values:
 430  * - 0000 - Prescaler divides the prescaler clock by 2; glitch filter does not
 431  *     support this configuration.
 432  * - 0001 - Prescaler divides the prescaler clock by 4; glitch filter recognizes
 433  *     change on input pin after 2 rising clock edges.
 434  * - 0010 - Prescaler divides the prescaler clock by 8; glitch filter recognizes
 435  *     change on input pin after 4 rising clock edges.
 436  * - 0011 - Prescaler divides the prescaler clock by 16; glitch filter
 437  *     recognizes change on input pin after 8 rising clock edges.
 438  * - 0100 - Prescaler divides the prescaler clock by 32; glitch filter
 439  *     recognizes change on input pin after 16 rising clock edges.
 440  * - 0101 - Prescaler divides the prescaler clock by 64; glitch filter
 441  *     recognizes change on input pin after 32 rising clock edges.
 442  * - 0110 - Prescaler divides the prescaler clock by 128; glitch filter
 443  *     recognizes change on input pin after 64 rising clock edges.
 444  * - 0111 - Prescaler divides the prescaler clock by 256; glitch filter
 445  *     recognizes change on input pin after 128 rising clock edges.
 446  * - 1000 - Prescaler divides the prescaler clock by 512; glitch filter
 447  *     recognizes change on input pin after 256 rising clock edges.
 448  * - 1001 - Prescaler divides the prescaler clock by 1024; glitch filter
 449  *     recognizes change on input pin after 512 rising clock edges.
 450  * - 1010 - Prescaler divides the prescaler clock by 2048; glitch filter
 451  *     recognizes change on input pin after 1024 rising clock edges.
 452  * - 1011 - Prescaler divides the prescaler clock by 4096; glitch filter
 453  *     recognizes change on input pin after 2048 rising clock edges.
 454  * - 1100 - Prescaler divides the prescaler clock by 8192; glitch filter
 455  *     recognizes change on input pin after 4096 rising clock edges.
 456  * - 1101 - Prescaler divides the prescaler clock by 16,384; glitch filter
 457  *     recognizes change on input pin after 8192 rising clock edges.
 458  * - 1110 - Prescaler divides the prescaler clock by 32,768; glitch filter
 459  *     recognizes change on input pin after 16,384 rising clock edges.
 460  * - 1111 - Prescaler divides the prescaler clock by 65,536; glitch filter
 461  *     recognizes change on input pin after 32,768 rising clock edges.
 462  */
 463 /*@{*/
 464 #define BP_LPTMR_PSR_PRESCALE (3U)         /*!< Bit position for LPTMR_PSR_PRESCALE. */
 465 #define BM_LPTMR_PSR_PRESCALE (0x00000078U) /*!< Bit mask for LPTMR_PSR_PRESCALE. */
 466 #define BS_LPTMR_PSR_PRESCALE (4U)         /*!< Bit field size in bits for LPTMR_PSR_PRESCALE. */
 467
 468 /*! @brief Read current value of the LPTMR_PSR_PRESCALE field. */
 469 #define BR_LPTMR_PSR_PRESCALE(x) (HW_LPTMR_PSR(x).B.PRESCALE)
 470
 471 /*! @brief Format value for bitfield LPTMR_PSR_PRESCALE. */
 472 #define BF_LPTMR_PSR_PRESCALE(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_PSR_PRESCALE) & BM_LPTMR_PSR_PRESCALE)
 473
 474 /*! @brief Set the PRESCALE field to a new value. */
 475 #define BW_LPTMR_PSR_PRESCALE(x, v) (HW_LPTMR_PSR_WR(x, (HW_LPTMR_PSR_RD(x) & ~BM_LPTMR_PSR_PRESCALE) | BF_LPTMR_PSR_PRESCALE(v)))
 476 /*@}*/
 477
 478 /*******************************************************************************
 479  * HW_LPTMR_CMR - Low Power Timer Compare Register
 480  ******************************************************************************/
 481
 482 /*!
 483  * @brief HW_LPTMR_CMR - Low Power Timer Compare Register (RW)
 484  *
 485  * Reset value: 0x00000000U
 486  */
 487 typedef union _hw_lptmr_cmr
 488 {
 489     uint32_t U;
 490     struct _hw_lptmr_cmr_bitfields
 491     {
 492         uint32_t COMPARE : 16;         /*!< [15:0] Compare Value */
 493         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
 494     } B;
 495 } hw_lptmr_cmr_t;
 496
 497 /*!
 498  * @name Constants and macros for entire LPTMR_CMR register
 499  */
 500 /*@{*/
 501 #define HW_LPTMR_CMR_ADDR(x)     ((x) + 0x8U)
 502
 503 #define HW_LPTMR_CMR(x)          (*(__IO hw_lptmr_cmr_t *) HW_LPTMR_CMR_ADDR(x))
 504 #define HW_LPTMR_CMR_RD(x)       (HW_LPTMR_CMR(x).U)
 505 #define HW_LPTMR_CMR_WR(x, v)    (HW_LPTMR_CMR(x).U = (v))
 506 #define HW_LPTMR_CMR_SET(x, v)   (HW_LPTMR_CMR_WR(x, HW_LPTMR_CMR_RD(x) |  (v)))
 507 #define HW_LPTMR_CMR_CLR(x, v)   (HW_LPTMR_CMR_WR(x, HW_LPTMR_CMR_RD(x) & ~(v)))
 508 #define HW_LPTMR_CMR_TOG(x, v)   (HW_LPTMR_CMR_WR(x, HW_LPTMR_CMR_RD(x) ^  (v)))
 509 /*@}*/
 510
 511 /*
 512  * Constants & macros for individual LPTMR_CMR bitfields
 513  */
 514
 515 /*!
 516  * @name Register LPTMR_CMR, field COMPARE[15:0] (RW)
 517  *
 518  * When the LPTMR is enabled and the CNR equals the value in the CMR and
 519  * increments, TCF is set and the hardware trigger asserts until the next time the CNR
 520  * increments. If the CMR is 0, the hardware trigger will remain asserted until
 521  * the LPTMR is disabled. If the LPTMR is enabled, the CMR must be altered only
 522  * when TCF is set.
 523  */
 524 /*@{*/
 525 #define BP_LPTMR_CMR_COMPARE (0U)          /*!< Bit position for LPTMR_CMR_COMPARE. */
 526 #define BM_LPTMR_CMR_COMPARE (0x0000FFFFU) /*!< Bit mask for LPTMR_CMR_COMPARE. */
 527 #define BS_LPTMR_CMR_COMPARE (16U)         /*!< Bit field size in bits for LPTMR_CMR_COMPARE. */
 528
 529 /*! @brief Read current value of the LPTMR_CMR_COMPARE field. */
 530 #define BR_LPTMR_CMR_COMPARE(x) (HW_LPTMR_CMR(x).B.COMPARE)
 531
 532 /*! @brief Format value for bitfield LPTMR_CMR_COMPARE. */
 533 #define BF_LPTMR_CMR_COMPARE(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CMR_COMPARE) & BM_LPTMR_CMR_COMPARE)
 534
 535 /*! @brief Set the COMPARE field to a new value. */
 536 #define BW_LPTMR_CMR_COMPARE(x, v) (HW_LPTMR_CMR_WR(x, (HW_LPTMR_CMR_RD(x) & ~BM_LPTMR_CMR_COMPARE) | BF_LPTMR_CMR_COMPARE(v)))
 537 /*@}*/
 538
 539 /*******************************************************************************
 540  * HW_LPTMR_CNR - Low Power Timer Counter Register
 541  ******************************************************************************/
 542
 543 /*!
 544  * @brief HW_LPTMR_CNR - Low Power Timer Counter Register (RW)
 545  *
 546  * Reset value: 0x00000000U
 547  */
 548 typedef union _hw_lptmr_cnr
 549 {
 550     uint32_t U;
 551     struct _hw_lptmr_cnr_bitfields
 552     {
 553         uint32_t COUNTER : 16;         /*!< [15:0] Counter Value */
 554         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
 555     } B;
 556 } hw_lptmr_cnr_t;
 557
 558 /*!
 559  * @name Constants and macros for entire LPTMR_CNR register
 560  */
 561 /*@{*/
 562 #define HW_LPTMR_CNR_ADDR(x)     ((x) + 0xCU)
 563
 564 #define HW_LPTMR_CNR(x)          (*(__IO hw_lptmr_cnr_t *) HW_LPTMR_CNR_ADDR(x))
 565 #define HW_LPTMR_CNR_RD(x)       (HW_LPTMR_CNR(x).U)
 566 #define HW_LPTMR_CNR_WR(x, v)    (HW_LPTMR_CNR(x).U = (v))
 567 #define HW_LPTMR_CNR_SET(x, v)   (HW_LPTMR_CNR_WR(x, HW_LPTMR_CNR_RD(x) |  (v)))
 568 #define HW_LPTMR_CNR_CLR(x, v)   (HW_LPTMR_CNR_WR(x, HW_LPTMR_CNR_RD(x) & ~(v)))
 569 #define HW_LPTMR_CNR_TOG(x, v)   (HW_LPTMR_CNR_WR(x, HW_LPTMR_CNR_RD(x) ^  (v)))
 570 /*@}*/
 571
 572 /*
 573  * Constants & macros for individual LPTMR_CNR bitfields
 574  */
 575
 576 /*!
 577  * @name Register LPTMR_CNR, field COUNTER[15:0] (RW)
 578  */
 579 /*@{*/
 580 #define BP_LPTMR_CNR_COUNTER (0U)          /*!< Bit position for LPTMR_CNR_COUNTER. */
 581 #define BM_LPTMR_CNR_COUNTER (0x0000FFFFU) /*!< Bit mask for LPTMR_CNR_COUNTER. */
 582 #define BS_LPTMR_CNR_COUNTER (16U)         /*!< Bit field size in bits for LPTMR_CNR_COUNTER. */
 583
 584 /*! @brief Read current value of the LPTMR_CNR_COUNTER field. */
 585 #define BR_LPTMR_CNR_COUNTER(x) (HW_LPTMR_CNR(x).B.COUNTER)
 586
 587 /*! @brief Format value for bitfield LPTMR_CNR_COUNTER. */
 588 #define BF_LPTMR_CNR_COUNTER(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CNR_COUNTER) & BM_LPTMR_CNR_COUNTER)
 589
 590 /*! @brief Set the COUNTER field to a new value. */
 591 #define BW_LPTMR_CNR_COUNTER(x, v) (HW_LPTMR_CNR_WR(x, (HW_LPTMR_CNR_RD(x) & ~BM_LPTMR_CNR_COUNTER) | BF_LPTMR_CNR_COUNTER(v)))
 592 /*@}*/
 593
 594 /*******************************************************************************
 595  * hw_lptmr_t - module struct
 596  ******************************************************************************/
 597 /*!
 598  * @brief All LPTMR module registers.
 599  */
 600 #pragma pack(1)
 601 typedef struct _hw_lptmr
 602 {
 603     __IO hw_lptmr_csr_t CSR;               /*!< [0x0] Low Power Timer Control Status Register */
 604     __IO hw_lptmr_psr_t PSR;               /*!< [0x4] Low Power Timer Prescale Register */
 605     __IO hw_lptmr_cmr_t CMR;               /*!< [0x8] Low Power Timer Compare Register */
 606     __IO hw_lptmr_cnr_t CNR;               /*!< [0xC] Low Power Timer Counter Register */
 607 } hw_lptmr_t;
 608 #pragma pack()
 609
 610 /*! @brief Macro to access all LPTMR registers. */
 611 /*! @param x LPTMR module instance base address. */
 612 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
 613  *     use the '&' operator, like <code>&HW_LPTMR(LPTMR0_BASE)</code>. */
 614 #define HW_LPTMR(x)    (*(hw_lptmr_t *)(x))
 615
 616 #endif /* __HW_LPTMR_REGISTERS_H__ */
 617 /* EOF */