tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_mcg.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
   9 **     Version:             rev. 2.5, 2014-02-10
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-08-12)
  48 **         Initial version.
  49 **     - rev. 2.0 (2013-10-29)
  50 **         Register accessor macros added to the memory map.
  51 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  52 **         Startup file for gcc has been updated according to CMSIS 3.2.
  53 **         System initialization updated.
  54 **         MCG - registers updated.
  55 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-09)
  59 **         DMA - EARS register removed.
  60 **         AIPS0, AIPS1 - MPRA register updated.
  61 **     - rev. 2.3 (2014-01-24)
  62 **         Update according to reference manual rev. 2
  63 **         ENET, MCG, MCM, SIM, USB - registers updated
  64 **     - rev. 2.4 (2014-02-10)
  65 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  66 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  67 **     - rev. 2.5 (2014-02-10)
  68 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  69 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  70 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  71 **
  72 ** ###################################################################
  73 */
  74
  75 /*
  76  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  77  *
  78  * This file was generated automatically and any changes may be lost.
  79  */
  80 #ifndef __HW_MCG_REGISTERS_H__
  81 #define __HW_MCG_REGISTERS_H__
  82
  83 #include "MK64F12.h"
  84 #include "fsl_bitaccess.h"
  85
  86 /*
  87  * MK64F12 MCG
  88  *
  89  * Multipurpose Clock Generator module
  90  *
  91  * Registers defined in this header file:
  92  * - HW_MCG_C1 - MCG Control 1 Register
  93  * - HW_MCG_C2 - MCG Control 2 Register
  94  * - HW_MCG_C3 - MCG Control 3 Register
  95  * - HW_MCG_C4 - MCG Control 4 Register
  96  * - HW_MCG_C5 - MCG Control 5 Register
  97  * - HW_MCG_C6 - MCG Control 6 Register
  98  * - HW_MCG_S - MCG Status Register
  99  * - HW_MCG_SC - MCG Status and Control Register
 100  * - HW_MCG_ATCVH - MCG Auto Trim Compare Value High Register
 101  * - HW_MCG_ATCVL - MCG Auto Trim Compare Value Low Register
 102  * - HW_MCG_C7 - MCG Control 7 Register
 103  * - HW_MCG_C8 - MCG Control 8 Register
 104  *
 105  * - hw_mcg_t - Struct containing all module registers.
 106  */
 107
 108 #define HW_MCG_INSTANCE_COUNT (1U) /*!< Number of instances of the MCG module. */
 109
 110 /*******************************************************************************
 111  * HW_MCG_C1 - MCG Control 1 Register
 112  ******************************************************************************/
 113
 114 /*!
 115  * @brief HW_MCG_C1 - MCG Control 1 Register (RW)
 116  *
 117  * Reset value: 0x04U
 118  */
 119 typedef union _hw_mcg_c1
 120 {
 121     uint8_t U;
 122     struct _hw_mcg_c1_bitfields
 123     {
 124         uint8_t IREFSTEN : 1;          /*!< [0] Internal Reference Stop Enable */
 125         uint8_t IRCLKEN : 1;           /*!< [1] Internal Reference Clock Enable */
 126         uint8_t IREFS : 1;             /*!< [2] Internal Reference Select */
 127         uint8_t FRDIV : 3;             /*!< [5:3] FLL External Reference Divider */
 128         uint8_t CLKS : 2;              /*!< [7:6] Clock Source Select */
 129     } B;
 130 } hw_mcg_c1_t;
 131
 132 /*!
 133  * @name Constants and macros for entire MCG_C1 register
 134  */
 135 /*@{*/
 136 #define HW_MCG_C1_ADDR(x)        ((x) + 0x0U)
 137
 138 #define HW_MCG_C1(x)             (*(__IO hw_mcg_c1_t *) HW_MCG_C1_ADDR(x))
 139 #define HW_MCG_C1_RD(x)          (HW_MCG_C1(x).U)
 140 #define HW_MCG_C1_WR(x, v)       (HW_MCG_C1(x).U = (v))
 141 #define HW_MCG_C1_SET(x, v)      (HW_MCG_C1_WR(x, HW_MCG_C1_RD(x) |  (v)))
 142 #define HW_MCG_C1_CLR(x, v)      (HW_MCG_C1_WR(x, HW_MCG_C1_RD(x) & ~(v)))
 143 #define HW_MCG_C1_TOG(x, v)      (HW_MCG_C1_WR(x, HW_MCG_C1_RD(x) ^  (v)))
 144 /*@}*/
 145
 146 /*
 147  * Constants & macros for individual MCG_C1 bitfields
 148  */
 149
 150 /*!
 151  * @name Register MCG_C1, field IREFSTEN[0] (RW)
 152  *
 153  * Controls whether or not the internal reference clock remains enabled when the
 154  * MCG enters Stop mode.
 155  *
 156  * Values:
 157  * - 0 - Internal reference clock is disabled in Stop mode.
 158  * - 1 - Internal reference clock is enabled in Stop mode if IRCLKEN is set or
 159  *     if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
 160  */
 161 /*@{*/
 162 #define BP_MCG_C1_IREFSTEN   (0U)          /*!< Bit position for MCG_C1_IREFSTEN. */
 163 #define BM_MCG_C1_IREFSTEN   (0x01U)       /*!< Bit mask for MCG_C1_IREFSTEN. */
 164 #define BS_MCG_C1_IREFSTEN   (1U)          /*!< Bit field size in bits for MCG_C1_IREFSTEN. */
 165
 166 /*! @brief Read current value of the MCG_C1_IREFSTEN field. */
 167 #define BR_MCG_C1_IREFSTEN(x) (BITBAND_ACCESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IREFSTEN))
 168
 169 /*! @brief Format value for bitfield MCG_C1_IREFSTEN. */
 170 #define BF_MCG_C1_IREFSTEN(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C1_IREFSTEN) & BM_MCG_C1_IREFSTEN)
 171
 172 /*! @brief Set the IREFSTEN field to a new value. */
 173 #define BW_MCG_C1_IREFSTEN(x, v) (BITBAND_ACCESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IREFSTEN) = (v))
 174 /*@}*/
 175
 176 /*!
 177  * @name Register MCG_C1, field IRCLKEN[1] (RW)
 178  *
 179  * Enables the internal reference clock for use as MCGIRCLK.
 180  *
 181  * Values:
 182  * - 0 - MCGIRCLK inactive.
 183  * - 1 - MCGIRCLK active.
 184  */
 185 /*@{*/
 186 #define BP_MCG_C1_IRCLKEN    (1U)          /*!< Bit position for MCG_C1_IRCLKEN. */
 187 #define BM_MCG_C1_IRCLKEN    (0x02U)       /*!< Bit mask for MCG_C1_IRCLKEN. */
 188 #define BS_MCG_C1_IRCLKEN    (1U)          /*!< Bit field size in bits for MCG_C1_IRCLKEN. */
 189
 190 /*! @brief Read current value of the MCG_C1_IRCLKEN field. */
 191 #define BR_MCG_C1_IRCLKEN(x) (BITBAND_ACCESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IRCLKEN))
 192
 193 /*! @brief Format value for bitfield MCG_C1_IRCLKEN. */
 194 #define BF_MCG_C1_IRCLKEN(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C1_IRCLKEN) & BM_MCG_C1_IRCLKEN)
 195
 196 /*! @brief Set the IRCLKEN field to a new value. */
 197 #define BW_MCG_C1_IRCLKEN(x, v) (BITBAND_ACCESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IRCLKEN) = (v))
 198 /*@}*/
 199
 200 /*!
 201  * @name Register MCG_C1, field IREFS[2] (RW)
 202  *
 203  * Selects the reference clock source for the FLL.
 204  *
 205  * Values:
 206  * - 0 - External reference clock is selected.
 207  * - 1 - The slow internal reference clock is selected.
 208  */
 209 /*@{*/
 210 #define BP_MCG_C1_IREFS      (2U)          /*!< Bit position for MCG_C1_IREFS. */
 211 #define BM_MCG_C1_IREFS      (0x04U)       /*!< Bit mask for MCG_C1_IREFS. */
 212 #define BS_MCG_C1_IREFS      (1U)          /*!< Bit field size in bits for MCG_C1_IREFS. */
 213
 214 /*! @brief Read current value of the MCG_C1_IREFS field. */
 215 #define BR_MCG_C1_IREFS(x)   (BITBAND_ACCESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IREFS))
 216
 217 /*! @brief Format value for bitfield MCG_C1_IREFS. */
 218 #define BF_MCG_C1_IREFS(v)   ((uint8_t)((uint8_t)(v) << BP_MCG_C1_IREFS) & BM_MCG_C1_IREFS)
 219
 220 /*! @brief Set the IREFS field to a new value. */
 221 #define BW_MCG_C1_IREFS(x, v) (BITBAND_ACCESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IREFS) = (v))
 222 /*@}*/
 223
 224 /*!
 225  * @name Register MCG_C1, field FRDIV[5:3] (RW)
 226  *
 227  * Selects the amount to divide down the external reference clock for the FLL.
 228  * The resulting frequency must be in the range 31.25 kHz to 39.0625 kHz (This is
 229  * required when FLL/DCO is the clock source for MCGOUTCLK . In FBE mode, it is
 230  * not required to meet this range, but it is recommended in the cases when trying
 231  * to enter a FLL mode from FBE).
 232  *
 233  * Values:
 234  * - 000 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE
 235  *     values, Divide Factor is 32.
 236  * - 001 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE
 237  *     values, Divide Factor is 64.
 238  * - 010 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE
 239  *     values, Divide Factor is 128.
 240  * - 011 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE
 241  *     values, Divide Factor is 256.
 242  * - 100 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE
 243  *     values, Divide Factor is 512.
 244  * - 101 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE
 245  *     values, Divide Factor is 1024.
 246  * - 110 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE
 247  *     values, Divide Factor is 1280 .
 248  * - 111 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE
 249  *     values, Divide Factor is 1536 .
 250  */
 251 /*@{*/
 252 #define BP_MCG_C1_FRDIV      (3U)          /*!< Bit position for MCG_C1_FRDIV. */
 253 #define BM_MCG_C1_FRDIV      (0x38U)       /*!< Bit mask for MCG_C1_FRDIV. */
 254 #define BS_MCG_C1_FRDIV      (3U)          /*!< Bit field size in bits for MCG_C1_FRDIV. */
 255
 256 /*! @brief Read current value of the MCG_C1_FRDIV field. */
 257 #define BR_MCG_C1_FRDIV(x)   (HW_MCG_C1(x).B.FRDIV)
 258
 259 /*! @brief Format value for bitfield MCG_C1_FRDIV. */
 260 #define BF_MCG_C1_FRDIV(v)   ((uint8_t)((uint8_t)(v) << BP_MCG_C1_FRDIV) & BM_MCG_C1_FRDIV)
 261
 262 /*! @brief Set the FRDIV field to a new value. */
 263 #define BW_MCG_C1_FRDIV(x, v) (HW_MCG_C1_WR(x, (HW_MCG_C1_RD(x) & ~BM_MCG_C1_FRDIV) | BF_MCG_C1_FRDIV(v)))
 264 /*@}*/
 265
 266 /*!
 267  * @name Register MCG_C1, field CLKS[7:6] (RW)
 268  *
 269  * Selects the clock source for MCGOUTCLK .
 270  *
 271  * Values:
 272  * - 00 - Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control
 273  *     bit).
 274  * - 01 - Encoding 1 - Internal reference clock is selected.
 275  * - 10 - Encoding 2 - External reference clock is selected.
 276  * - 11 - Encoding 3 - Reserved.
 277  */
 278 /*@{*/
 279 #define BP_MCG_C1_CLKS       (6U)          /*!< Bit position for MCG_C1_CLKS. */
 280 #define BM_MCG_C1_CLKS       (0xC0U)       /*!< Bit mask for MCG_C1_CLKS. */
 281 #define BS_MCG_C1_CLKS       (2U)          /*!< Bit field size in bits for MCG_C1_CLKS. */
 282
 283 /*! @brief Read current value of the MCG_C1_CLKS field. */
 284 #define BR_MCG_C1_CLKS(x)    (HW_MCG_C1(x).B.CLKS)
 285
 286 /*! @brief Format value for bitfield MCG_C1_CLKS. */
 287 #define BF_MCG_C1_CLKS(v)    ((uint8_t)((uint8_t)(v) << BP_MCG_C1_CLKS) & BM_MCG_C1_CLKS)
 288
 289 /*! @brief Set the CLKS field to a new value. */
 290 #define BW_MCG_C1_CLKS(x, v) (HW_MCG_C1_WR(x, (HW_MCG_C1_RD(x) & ~BM_MCG_C1_CLKS) | BF_MCG_C1_CLKS(v)))
 291 /*@}*/
 292
 293 /*******************************************************************************
 294  * HW_MCG_C2 - MCG Control 2 Register
 295  ******************************************************************************/
 296
 297 /*!
 298  * @brief HW_MCG_C2 - MCG Control 2 Register (RW)
 299  *
 300  * Reset value: 0x80U
 301  */
 302 typedef union _hw_mcg_c2
 303 {
 304     uint8_t U;
 305     struct _hw_mcg_c2_bitfields
 306     {
 307         uint8_t IRCS : 1;              /*!< [0] Internal Reference Clock Select */
 308         uint8_t LP : 1;                /*!< [1] Low Power Select */
 309         uint8_t EREFS : 1;             /*!< [2] External Reference Select */
 310         uint8_t HGO : 1;               /*!< [3] High Gain Oscillator Select */
 311         uint8_t RANGE : 2;             /*!< [5:4] Frequency Range Select */
 312         uint8_t FCFTRIM : 1;           /*!< [6] Fast Internal Reference Clock Fine Trim
 313                                         * */
 314         uint8_t LOCRE0 : 1;            /*!< [7] Loss of Clock Reset Enable */
 315     } B;
 316 } hw_mcg_c2_t;
 317
 318 /*!
 319  * @name Constants and macros for entire MCG_C2 register
 320  */
 321 /*@{*/
 322 #define HW_MCG_C2_ADDR(x)        ((x) + 0x1U)
 323
 324 #define HW_MCG_C2(x)             (*(__IO hw_mcg_c2_t *) HW_MCG_C2_ADDR(x))
 325 #define HW_MCG_C2_RD(x)          (HW_MCG_C2(x).U)
 326 #define HW_MCG_C2_WR(x, v)       (HW_MCG_C2(x).U = (v))
 327 #define HW_MCG_C2_SET(x, v)      (HW_MCG_C2_WR(x, HW_MCG_C2_RD(x) |  (v)))
 328 #define HW_MCG_C2_CLR(x, v)      (HW_MCG_C2_WR(x, HW_MCG_C2_RD(x) & ~(v)))
 329 #define HW_MCG_C2_TOG(x, v)      (HW_MCG_C2_WR(x, HW_MCG_C2_RD(x) ^  (v)))
 330 /*@}*/
 331
 332 /*
 333  * Constants & macros for individual MCG_C2 bitfields
 334  */
 335
 336 /*!
 337  * @name Register MCG_C2, field IRCS[0] (RW)
 338  *
 339  * Selects between the fast or slow internal reference clock source.
 340  *
 341  * Values:
 342  * - 0 - Slow internal reference clock selected.
 343  * - 1 - Fast internal reference clock selected.
 344  */
 345 /*@{*/
 346 #define BP_MCG_C2_IRCS       (0U)          /*!< Bit position for MCG_C2_IRCS. */
 347 #define BM_MCG_C2_IRCS       (0x01U)       /*!< Bit mask for MCG_C2_IRCS. */
 348 #define BS_MCG_C2_IRCS       (1U)          /*!< Bit field size in bits for MCG_C2_IRCS. */
 349
 350 /*! @brief Read current value of the MCG_C2_IRCS field. */
 351 #define BR_MCG_C2_IRCS(x)    (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_IRCS))
 352
 353 /*! @brief Format value for bitfield MCG_C2_IRCS. */
 354 #define BF_MCG_C2_IRCS(v)    ((uint8_t)((uint8_t)(v) << BP_MCG_C2_IRCS) & BM_MCG_C2_IRCS)
 355
 356 /*! @brief Set the IRCS field to a new value. */
 357 #define BW_MCG_C2_IRCS(x, v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_IRCS) = (v))
 358 /*@}*/
 359
 360 /*!
 361  * @name Register MCG_C2, field LP[1] (RW)
 362  *
 363  * Controls whether the FLL or PLL is disabled in BLPI and BLPE modes. In FBE or
 364  * PBE modes, setting this bit to 1 will transition the MCG into BLPE mode; in
 365  * FBI mode, setting this bit to 1 will transition the MCG into BLPI mode. In any
 366  * other MCG mode, LP bit has no affect.
 367  *
 368  * Values:
 369  * - 0 - FLL or PLL is not disabled in bypass modes.
 370  * - 1 - FLL or PLL is disabled in bypass modes (lower power)
 371  */
 372 /*@{*/
 373 #define BP_MCG_C2_LP         (1U)          /*!< Bit position for MCG_C2_LP. */
 374 #define BM_MCG_C2_LP         (0x02U)       /*!< Bit mask for MCG_C2_LP. */
 375 #define BS_MCG_C2_LP         (1U)          /*!< Bit field size in bits for MCG_C2_LP. */
 376
 377 /*! @brief Read current value of the MCG_C2_LP field. */
 378 #define BR_MCG_C2_LP(x)      (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_LP))
 379
 380 /*! @brief Format value for bitfield MCG_C2_LP. */
 381 #define BF_MCG_C2_LP(v)      ((uint8_t)((uint8_t)(v) << BP_MCG_C2_LP) & BM_MCG_C2_LP)
 382
 383 /*! @brief Set the LP field to a new value. */
 384 #define BW_MCG_C2_LP(x, v)   (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_LP) = (v))
 385 /*@}*/
 386
 387 /*!
 388  * @name Register MCG_C2, field EREFS[2] (RW)
 389  *
 390  * Selects the source for the external reference clock. See the Oscillator (OSC)
 391  * chapter for more details.
 392  *
 393  * Values:
 394  * - 0 - External reference clock requested.
 395  * - 1 - Oscillator requested.
 396  */
 397 /*@{*/
 398 #define BP_MCG_C2_EREFS      (2U)          /*!< Bit position for MCG_C2_EREFS. */
 399 #define BM_MCG_C2_EREFS      (0x04U)       /*!< Bit mask for MCG_C2_EREFS. */
 400 #define BS_MCG_C2_EREFS      (1U)          /*!< Bit field size in bits for MCG_C2_EREFS. */
 401
 402 /*! @brief Read current value of the MCG_C2_EREFS field. */
 403 #define BR_MCG_C2_EREFS(x)   (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_EREFS))
 404
 405 /*! @brief Format value for bitfield MCG_C2_EREFS. */
 406 #define BF_MCG_C2_EREFS(v)   ((uint8_t)((uint8_t)(v) << BP_MCG_C2_EREFS) & BM_MCG_C2_EREFS)
 407
 408 /*! @brief Set the EREFS field to a new value. */
 409 #define BW_MCG_C2_EREFS(x, v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_EREFS) = (v))
 410 /*@}*/
 411
 412 /*!
 413  * @name Register MCG_C2, field HGO[3] (RW)
 414  *
 415  * Controls the crystal oscillator mode of operation. See the Oscillator (OSC)
 416  * chapter for more details.
 417  *
 418  * Values:
 419  * - 0 - Configure crystal oscillator for low-power operation.
 420  * - 1 - Configure crystal oscillator for high-gain operation.
 421  */
 422 /*@{*/
 423 #define BP_MCG_C2_HGO        (3U)          /*!< Bit position for MCG_C2_HGO. */
 424 #define BM_MCG_C2_HGO        (0x08U)       /*!< Bit mask for MCG_C2_HGO. */
 425 #define BS_MCG_C2_HGO        (1U)          /*!< Bit field size in bits for MCG_C2_HGO. */
 426
 427 /*! @brief Read current value of the MCG_C2_HGO field. */
 428 #define BR_MCG_C2_HGO(x)     (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_HGO))
 429
 430 /*! @brief Format value for bitfield MCG_C2_HGO. */
 431 #define BF_MCG_C2_HGO(v)     ((uint8_t)((uint8_t)(v) << BP_MCG_C2_HGO) & BM_MCG_C2_HGO)
 432
 433 /*! @brief Set the HGO field to a new value. */
 434 #define BW_MCG_C2_HGO(x, v)  (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_HGO) = (v))
 435 /*@}*/
 436
 437 /*!
 438  * @name Register MCG_C2, field RANGE[5:4] (RW)
 439  *
 440  * Selects the frequency range for the crystal oscillator or external clock
 441  * source. See the Oscillator (OSC) chapter for more details and the device data
 442  * sheet for the frequency ranges used.
 443  *
 444  * Values:
 445  * - 00 - Encoding 0 - Low frequency range selected for the crystal oscillator .
 446  * - 01 - Encoding 1 - High frequency range selected for the crystal oscillator .
 447  */
 448 /*@{*/
 449 #define BP_MCG_C2_RANGE      (4U)          /*!< Bit position for MCG_C2_RANGE. */
 450 #define BM_MCG_C2_RANGE      (0x30U)       /*!< Bit mask for MCG_C2_RANGE. */
 451 #define BS_MCG_C2_RANGE      (2U)          /*!< Bit field size in bits for MCG_C2_RANGE. */
 452
 453 /*! @brief Read current value of the MCG_C2_RANGE field. */
 454 #define BR_MCG_C2_RANGE(x)   (HW_MCG_C2(x).B.RANGE)
 455
 456 /*! @brief Format value for bitfield MCG_C2_RANGE. */
 457 #define BF_MCG_C2_RANGE(v)   ((uint8_t)((uint8_t)(v) << BP_MCG_C2_RANGE) & BM_MCG_C2_RANGE)
 458
 459 /*! @brief Set the RANGE field to a new value. */
 460 #define BW_MCG_C2_RANGE(x, v) (HW_MCG_C2_WR(x, (HW_MCG_C2_RD(x) & ~BM_MCG_C2_RANGE) | BF_MCG_C2_RANGE(v)))
 461 /*@}*/
 462
 463 /*!
 464  * @name Register MCG_C2, field FCFTRIM[6] (RW)
 465  *
 466  * FCFTRIM controls the smallest adjustment of the fast internal reference clock
 467  * frequency. Setting FCFTRIM increases the period and clearing FCFTRIM
 468  * decreases the period by the smallest amount possible. If an FCFTRIM value stored in
 469  * nonvolatile memory is to be used, it is your responsibility to copy that value
 470  * from the nonvolatile memory location to this bit.
 471  */
 472 /*@{*/
 473 #define BP_MCG_C2_FCFTRIM    (6U)          /*!< Bit position for MCG_C2_FCFTRIM. */
 474 #define BM_MCG_C2_FCFTRIM    (0x40U)       /*!< Bit mask for MCG_C2_FCFTRIM. */
 475 #define BS_MCG_C2_FCFTRIM    (1U)          /*!< Bit field size in bits for MCG_C2_FCFTRIM. */
 476
 477 /*! @brief Read current value of the MCG_C2_FCFTRIM field. */
 478 #define BR_MCG_C2_FCFTRIM(x) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_FCFTRIM))
 479
 480 /*! @brief Format value for bitfield MCG_C2_FCFTRIM. */
 481 #define BF_MCG_C2_FCFTRIM(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C2_FCFTRIM) & BM_MCG_C2_FCFTRIM)
 482
 483 /*! @brief Set the FCFTRIM field to a new value. */
 484 #define BW_MCG_C2_FCFTRIM(x, v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_FCFTRIM) = (v))
 485 /*@}*/
 486
 487 /*!
 488  * @name Register MCG_C2, field LOCRE0[7] (RW)
 489  *
 490  * Determines whether an interrupt or a reset request is made following a loss
 491  * of OSC0 external reference clock. The LOCRE0 only has an affect when CME0 is
 492  * set.
 493  *
 494  * Values:
 495  * - 0 - Interrupt request is generated on a loss of OSC0 external reference
 496  *     clock.
 497  * - 1 - Generate a reset request on a loss of OSC0 external reference clock.
 498  */
 499 /*@{*/
 500 #define BP_MCG_C2_LOCRE0     (7U)          /*!< Bit position for MCG_C2_LOCRE0. */
 501 #define BM_MCG_C2_LOCRE0     (0x80U)       /*!< Bit mask for MCG_C2_LOCRE0. */
 502 #define BS_MCG_C2_LOCRE0     (1U)          /*!< Bit field size in bits for MCG_C2_LOCRE0. */
 503
 504 /*! @brief Read current value of the MCG_C2_LOCRE0 field. */
 505 #define BR_MCG_C2_LOCRE0(x)  (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_LOCRE0))
 506
 507 /*! @brief Format value for bitfield MCG_C2_LOCRE0. */
 508 #define BF_MCG_C2_LOCRE0(v)  ((uint8_t)((uint8_t)(v) << BP_MCG_C2_LOCRE0) & BM_MCG_C2_LOCRE0)
 509
 510 /*! @brief Set the LOCRE0 field to a new value. */
 511 #define BW_MCG_C2_LOCRE0(x, v) (BITBAND_ACCESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_LOCRE0) = (v))
 512 /*@}*/
 513
 514 /*******************************************************************************
 515  * HW_MCG_C3 - MCG Control 3 Register
 516  ******************************************************************************/
 517
 518 /*!
 519  * @brief HW_MCG_C3 - MCG Control 3 Register (RW)
 520  *
 521  * Reset value: 0x00U
 522  */
 523 typedef union _hw_mcg_c3
 524 {
 525     uint8_t U;
 526     struct _hw_mcg_c3_bitfields
 527     {
 528         uint8_t SCTRIM : 8;            /*!< [7:0] Slow Internal Reference Clock Trim
 529                                         * Setting */
 530     } B;
 531 } hw_mcg_c3_t;
 532
 533 /*!
 534  * @name Constants and macros for entire MCG_C3 register
 535  */
 536 /*@{*/
 537 #define HW_MCG_C3_ADDR(x)        ((x) + 0x2U)
 538
 539 #define HW_MCG_C3(x)             (*(__IO hw_mcg_c3_t *) HW_MCG_C3_ADDR(x))
 540 #define HW_MCG_C3_RD(x)          (HW_MCG_C3(x).U)
 541 #define HW_MCG_C3_WR(x, v)       (HW_MCG_C3(x).U = (v))
 542 #define HW_MCG_C3_SET(x, v)      (HW_MCG_C3_WR(x, HW_MCG_C3_RD(x) |  (v)))
 543 #define HW_MCG_C3_CLR(x, v)      (HW_MCG_C3_WR(x, HW_MCG_C3_RD(x) & ~(v)))
 544 #define HW_MCG_C3_TOG(x, v)      (HW_MCG_C3_WR(x, HW_MCG_C3_RD(x) ^  (v)))
 545 /*@}*/
 546
 547 /*
 548  * Constants & macros for individual MCG_C3 bitfields
 549  */
 550
 551 /*!
 552  * @name Register MCG_C3, field SCTRIM[7:0] (RW)
 553  *
 554  * SCTRIM A value for SCTRIM is loaded during reset from a factory programmed
 555  * location. controls the slow internal reference clock frequency by controlling
 556  * the slow internal reference clock period. The SCTRIM bits are binary weighted,
 557  * that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value
 558  * increases the period, and decreasing the value decreases the period. An additional
 559  * fine trim bit is available in C4 register as the SCFTRIM bit. Upon reset,
 560  * this value is loaded with a factory trim value. If an SCTRIM value stored in
 561  * nonvolatile memory is to be used, it is your responsibility to copy that value
 562  * from the nonvolatile memory location to this register.
 563  */
 564 /*@{*/
 565 #define BP_MCG_C3_SCTRIM     (0U)          /*!< Bit position for MCG_C3_SCTRIM. */
 566 #define BM_MCG_C3_SCTRIM     (0xFFU)       /*!< Bit mask for MCG_C3_SCTRIM. */
 567 #define BS_MCG_C3_SCTRIM     (8U)          /*!< Bit field size in bits for MCG_C3_SCTRIM. */
 568
 569 /*! @brief Read current value of the MCG_C3_SCTRIM field. */
 570 #define BR_MCG_C3_SCTRIM(x)  (HW_MCG_C3(x).U)
 571
 572 /*! @brief Format value for bitfield MCG_C3_SCTRIM. */
 573 #define BF_MCG_C3_SCTRIM(v)  ((uint8_t)((uint8_t)(v) << BP_MCG_C3_SCTRIM) & BM_MCG_C3_SCTRIM)
 574
 575 /*! @brief Set the SCTRIM field to a new value. */
 576 #define BW_MCG_C3_SCTRIM(x, v) (HW_MCG_C3_WR(x, v))
 577 /*@}*/
 578
 579 /*******************************************************************************
 580  * HW_MCG_C4 - MCG Control 4 Register
 581  ******************************************************************************/
 582
 583 /*!
 584  * @brief HW_MCG_C4 - MCG Control 4 Register (RW)
 585  *
 586  * Reset value: 0x00U
 587  *
 588  * Reset values for DRST and DMX32 bits are 0.
 589  */
 590 typedef union _hw_mcg_c4
 591 {
 592     uint8_t U;
 593     struct _hw_mcg_c4_bitfields
 594     {
 595         uint8_t SCFTRIM : 1;           /*!< [0] Slow Internal Reference Clock Fine Trim
 596                                         * */
 597         uint8_t FCTRIM : 4;            /*!< [4:1] Fast Internal Reference Clock Trim
 598                                         * Setting */
 599         uint8_t DRST_DRS : 2;          /*!< [6:5] DCO Range Select */
 600         uint8_t DMX32 : 1;             /*!< [7] DCO Maximum Frequency with 32.768 kHz
 601                                         * Reference */
 602     } B;
 603 } hw_mcg_c4_t;
 604
 605 /*!
 606  * @name Constants and macros for entire MCG_C4 register
 607  */
 608 /*@{*/
 609 #define HW_MCG_C4_ADDR(x)        ((x) + 0x3U)
 610
 611 #define HW_MCG_C4(x)             (*(__IO hw_mcg_c4_t *) HW_MCG_C4_ADDR(x))
 612 #define HW_MCG_C4_RD(x)          (HW_MCG_C4(x).U)
 613 #define HW_MCG_C4_WR(x, v)       (HW_MCG_C4(x).U = (v))
 614 #define HW_MCG_C4_SET(x, v)      (HW_MCG_C4_WR(x, HW_MCG_C4_RD(x) |  (v)))
 615 #define HW_MCG_C4_CLR(x, v)      (HW_MCG_C4_WR(x, HW_MCG_C4_RD(x) & ~(v)))
 616 #define HW_MCG_C4_TOG(x, v)      (HW_MCG_C4_WR(x, HW_MCG_C4_RD(x) ^  (v)))
 617 /*@}*/
 618
 619 /*
 620  * Constants & macros for individual MCG_C4 bitfields
 621  */
 622
 623 /*!
 624  * @name Register MCG_C4, field SCFTRIM[0] (RW)
 625  *
 626  * SCFTRIM A value for SCFTRIM is loaded during reset from a factory programmed
 627  * location . controls the smallest adjustment of the slow internal reference
 628  * clock frequency. Setting SCFTRIM increases the period and clearing SCFTRIM
 629  * decreases the period by the smallest amount possible. If an SCFTRIM value stored in
 630  * nonvolatile memory is to be used, it is your responsibility to copy that value
 631  * from the nonvolatile memory location to this bit.
 632  */
 633 /*@{*/
 634 #define BP_MCG_C4_SCFTRIM    (0U)          /*!< Bit position for MCG_C4_SCFTRIM. */
 635 #define BM_MCG_C4_SCFTRIM    (0x01U)       /*!< Bit mask for MCG_C4_SCFTRIM. */
 636 #define BS_MCG_C4_SCFTRIM    (1U)          /*!< Bit field size in bits for MCG_C4_SCFTRIM. */
 637
 638 /*! @brief Read current value of the MCG_C4_SCFTRIM field. */
 639 #define BR_MCG_C4_SCFTRIM(x) (BITBAND_ACCESS8(HW_MCG_C4_ADDR(x), BP_MCG_C4_SCFTRIM))
 640
 641 /*! @brief Format value for bitfield MCG_C4_SCFTRIM. */
 642 #define BF_MCG_C4_SCFTRIM(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C4_SCFTRIM) & BM_MCG_C4_SCFTRIM)
 643
 644 /*! @brief Set the SCFTRIM field to a new value. */
 645 #define BW_MCG_C4_SCFTRIM(x, v) (BITBAND_ACCESS8(HW_MCG_C4_ADDR(x), BP_MCG_C4_SCFTRIM) = (v))
 646 /*@}*/
 647
 648 /*!
 649  * @name Register MCG_C4, field FCTRIM[4:1] (RW)
 650  *
 651  * FCTRIM A value for FCTRIM is loaded during reset from a factory programmed
 652  * location. controls the fast internal reference clock frequency by controlling
 653  * the fast internal reference clock period. The FCTRIM bits are binary weighted,
 654  * that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value
 655  * increases the period, and decreasing the value decreases the period. If an
 656  * FCTRIM[3:0] value stored in nonvolatile memory is to be used, it is your
 657  * responsibility to copy that value from the nonvolatile memory location to this register.
 658  */
 659 /*@{*/
 660 #define BP_MCG_C4_FCTRIM     (1U)          /*!< Bit position for MCG_C4_FCTRIM. */
 661 #define BM_MCG_C4_FCTRIM     (0x1EU)       /*!< Bit mask for MCG_C4_FCTRIM. */
 662 #define BS_MCG_C4_FCTRIM     (4U)          /*!< Bit field size in bits for MCG_C4_FCTRIM. */
 663
 664 /*! @brief Read current value of the MCG_C4_FCTRIM field. */
 665 #define BR_MCG_C4_FCTRIM(x)  (HW_MCG_C4(x).B.FCTRIM)
 666
 667 /*! @brief Format value for bitfield MCG_C4_FCTRIM. */
 668 #define BF_MCG_C4_FCTRIM(v)  ((uint8_t)((uint8_t)(v) << BP_MCG_C4_FCTRIM) & BM_MCG_C4_FCTRIM)
 669
 670 /*! @brief Set the FCTRIM field to a new value. */
 671 #define BW_MCG_C4_FCTRIM(x, v) (HW_MCG_C4_WR(x, (HW_MCG_C4_RD(x) & ~BM_MCG_C4_FCTRIM) | BF_MCG_C4_FCTRIM(v)))
 672 /*@}*/
 673
 674 /*!
 675  * @name Register MCG_C4, field DRST_DRS[6:5] (RW)
 676  *
 677  * The DRS bits select the frequency range for the FLL output, DCOOUT. When the
 678  * LP bit is set, writes to the DRS bits are ignored. The DRST read field
 679  * indicates the current frequency range for DCOOUT. The DRST field does not update
 680  * immediately after a write to the DRS field due to internal synchronization between
 681  * clock domains. See the DCO Frequency Range table for more details.
 682  *
 683  * Values:
 684  * - 00 - Encoding 0 - Low range (reset default).
 685  * - 01 - Encoding 1 - Mid range.
 686  * - 10 - Encoding 2 - Mid-high range.
 687  * - 11 - Encoding 3 - High range.
 688  */
 689 /*@{*/
 690 #define BP_MCG_C4_DRST_DRS   (5U)          /*!< Bit position for MCG_C4_DRST_DRS. */
 691 #define BM_MCG_C4_DRST_DRS   (0x60U)       /*!< Bit mask for MCG_C4_DRST_DRS. */
 692 #define BS_MCG_C4_DRST_DRS   (2U)          /*!< Bit field size in bits for MCG_C4_DRST_DRS. */
 693
 694 /*! @brief Read current value of the MCG_C4_DRST_DRS field. */
 695 #define BR_MCG_C4_DRST_DRS(x) (HW_MCG_C4(x).B.DRST_DRS)
 696
 697 /*! @brief Format value for bitfield MCG_C4_DRST_DRS. */
 698 #define BF_MCG_C4_DRST_DRS(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C4_DRST_DRS) & BM_MCG_C4_DRST_DRS)
 699
 700 /*! @brief Set the DRST_DRS field to a new value. */
 701 #define BW_MCG_C4_DRST_DRS(x, v) (HW_MCG_C4_WR(x, (HW_MCG_C4_RD(x) & ~BM_MCG_C4_DRST_DRS) | BF_MCG_C4_DRST_DRS(v)))
 702 /*@}*/
 703
 704 /*!
 705  * @name Register MCG_C4, field DMX32[7] (RW)
 706  *
 707  * The DMX32 bit controls whether the DCO frequency range is narrowed to its
 708  * maximum frequency with a 32.768 kHz reference. The following table identifies
 709  * settings for the DCO frequency range. The system clocks derived from this source
 710  * should not exceed their specified maximums. DRST_DRS DMX32 Reference Range FLL
 711  * Factor DCO Range 00 0 31.25-39.0625 kHz 640 20-25 MHz 1 32.768 kHz 732 24 MHz
 712  * 01 0 31.25-39.0625 kHz 1280 40-50 MHz 1 32.768 kHz 1464 48 MHz 10 0
 713  * 31.25-39.0625 kHz 1920 60-75 MHz 1 32.768 kHz 2197 72 MHz 11 0 31.25-39.0625 kHz 2560
 714  * 80-100 MHz 1 32.768 kHz 2929 96 MHz
 715  *
 716  * Values:
 717  * - 0 - DCO has a default range of 25%.
 718  * - 1 - DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
 719  */
 720 /*@{*/
 721 #define BP_MCG_C4_DMX32      (7U)          /*!< Bit position for MCG_C4_DMX32. */
 722 #define BM_MCG_C4_DMX32      (0x80U)       /*!< Bit mask for MCG_C4_DMX32. */
 723 #define BS_MCG_C4_DMX32      (1U)          /*!< Bit field size in bits for MCG_C4_DMX32. */
 724
 725 /*! @brief Read current value of the MCG_C4_DMX32 field. */
 726 #define BR_MCG_C4_DMX32(x)   (BITBAND_ACCESS8(HW_MCG_C4_ADDR(x), BP_MCG_C4_DMX32))
 727
 728 /*! @brief Format value for bitfield MCG_C4_DMX32. */
 729 #define BF_MCG_C4_DMX32(v)   ((uint8_t)((uint8_t)(v) << BP_MCG_C4_DMX32) & BM_MCG_C4_DMX32)
 730
 731 /*! @brief Set the DMX32 field to a new value. */
 732 #define BW_MCG_C4_DMX32(x, v) (BITBAND_ACCESS8(HW_MCG_C4_ADDR(x), BP_MCG_C4_DMX32) = (v))
 733 /*@}*/
 734
 735 /*******************************************************************************
 736  * HW_MCG_C5 - MCG Control 5 Register
 737  ******************************************************************************/
 738
 739 /*!
 740  * @brief HW_MCG_C5 - MCG Control 5 Register (RW)
 741  *
 742  * Reset value: 0x00U
 743  */
 744 typedef union _hw_mcg_c5
 745 {
 746     uint8_t U;
 747     struct _hw_mcg_c5_bitfields
 748     {
 749         uint8_t PRDIV0 : 5;            /*!< [4:0] PLL External Reference Divider */
 750         uint8_t PLLSTEN0 : 1;          /*!< [5] PLL Stop Enable */
 751         uint8_t PLLCLKEN0 : 1;         /*!< [6] PLL Clock Enable */
 752         uint8_t RESERVED0 : 1;         /*!< [7]  */
 753     } B;
 754 } hw_mcg_c5_t;
 755
 756 /*!
 757  * @name Constants and macros for entire MCG_C5 register
 758  */
 759 /*@{*/
 760 #define HW_MCG_C5_ADDR(x)        ((x) + 0x4U)
 761
 762 #define HW_MCG_C5(x)             (*(__IO hw_mcg_c5_t *) HW_MCG_C5_ADDR(x))
 763 #define HW_MCG_C5_RD(x)          (HW_MCG_C5(x).U)
 764 #define HW_MCG_C5_WR(x, v)       (HW_MCG_C5(x).U = (v))
 765 #define HW_MCG_C5_SET(x, v)      (HW_MCG_C5_WR(x, HW_MCG_C5_RD(x) |  (v)))
 766 #define HW_MCG_C5_CLR(x, v)      (HW_MCG_C5_WR(x, HW_MCG_C5_RD(x) & ~(v)))
 767 #define HW_MCG_C5_TOG(x, v)      (HW_MCG_C5_WR(x, HW_MCG_C5_RD(x) ^  (v)))
 768 /*@}*/
 769
 770 /*
 771  * Constants & macros for individual MCG_C5 bitfields
 772  */
 773
 774 /*!
 775  * @name Register MCG_C5, field PRDIV0[4:0] (RW)
 776  *
 777  * Selects the amount to divide down the external reference clock for the PLL.
 778  * The resulting frequency must be in the range of 2 MHz to 4 MHz. After the PLL
 779  * is enabled (by setting either PLLCLKEN 0 or PLLS), the PRDIV 0 value must not
 780  * be changed when LOCK0 is zero. PLL External Reference Divide Factor PRDIV 0
 781  * Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor
 782  * 00000 1 01000 9 10000 17 11000 25 00001 2 01001 10 10001 18 11001 Reserved
 783  * 00010 3 01010 11 10010 19 11010 Reserved 00011 4 01011 12 10011 20 11011 Reserved
 784  * 00100 5 01100 13 10100 21 11100 Reserved 00101 6 01101 14 10101 22 11101
 785  * Reserved 00110 7 01110 15 10110 23 11110 Reserved 00111 8 01111 16 10111 24 11111
 786  * Reserved
 787  */
 788 /*@{*/
 789 #define BP_MCG_C5_PRDIV0     (0U)          /*!< Bit position for MCG_C5_PRDIV0. */
 790 #define BM_MCG_C5_PRDIV0     (0x1FU)       /*!< Bit mask for MCG_C5_PRDIV0. */
 791 #define BS_MCG_C5_PRDIV0     (5U)          /*!< Bit field size in bits for MCG_C5_PRDIV0. */
 792
 793 /*! @brief Read current value of the MCG_C5_PRDIV0 field. */
 794 #define BR_MCG_C5_PRDIV0(x)  (HW_MCG_C5(x).B.PRDIV0)
 795
 796 /*! @brief Format value for bitfield MCG_C5_PRDIV0. */
 797 #define BF_MCG_C5_PRDIV0(v)  ((uint8_t)((uint8_t)(v) << BP_MCG_C5_PRDIV0) & BM_MCG_C5_PRDIV0)
 798
 799 /*! @brief Set the PRDIV0 field to a new value. */
 800 #define BW_MCG_C5_PRDIV0(x, v) (HW_MCG_C5_WR(x, (HW_MCG_C5_RD(x) & ~BM_MCG_C5_PRDIV0) | BF_MCG_C5_PRDIV0(v)))
 801 /*@}*/
 802
 803 /*!
 804  * @name Register MCG_C5, field PLLSTEN0[5] (RW)
 805  *
 806  * Enables the PLL Clock during Normal Stop. In Low Power Stop mode, the PLL
 807  * clock gets disabled even if PLLSTEN 0 =1. All other power modes, PLLSTEN 0 bit
 808  * has no affect and does not enable the PLL Clock to run if it is written to 1.
 809  *
 810  * Values:
 811  * - 0 - MCGPLLCLK is disabled in any of the Stop modes.
 812  * - 1 - MCGPLLCLK is enabled if system is in Normal Stop mode.
 813  */
 814 /*@{*/
 815 #define BP_MCG_C5_PLLSTEN0   (5U)          /*!< Bit position for MCG_C5_PLLSTEN0. */
 816 #define BM_MCG_C5_PLLSTEN0   (0x20U)       /*!< Bit mask for MCG_C5_PLLSTEN0. */
 817 #define BS_MCG_C5_PLLSTEN0   (1U)          /*!< Bit field size in bits for MCG_C5_PLLSTEN0. */
 818
 819 /*! @brief Read current value of the MCG_C5_PLLSTEN0 field. */
 820 #define BR_MCG_C5_PLLSTEN0(x) (BITBAND_ACCESS8(HW_MCG_C5_ADDR(x), BP_MCG_C5_PLLSTEN0))
 821
 822 /*! @brief Format value for bitfield MCG_C5_PLLSTEN0. */
 823 #define BF_MCG_C5_PLLSTEN0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C5_PLLSTEN0) & BM_MCG_C5_PLLSTEN0)
 824
 825 /*! @brief Set the PLLSTEN0 field to a new value. */
 826 #define BW_MCG_C5_PLLSTEN0(x, v) (BITBAND_ACCESS8(HW_MCG_C5_ADDR(x), BP_MCG_C5_PLLSTEN0) = (v))
 827 /*@}*/
 828
 829 /*!
 830  * @name Register MCG_C5, field PLLCLKEN0[6] (RW)
 831  *
 832  * Enables the PLL independent of PLLS and enables the PLL clock for use as
 833  * MCGPLLCLK. (PRDIV 0 needs to be programmed to the correct divider to generate a
 834  * PLL reference clock in the range of 2 - 4 MHz range prior to setting the
 835  * PLLCLKEN 0 bit). Setting PLLCLKEN 0 will enable the external oscillator if not
 836  * already enabled. Whenever the PLL is being enabled by means of the PLLCLKEN 0 bit,
 837  * and the external oscillator is being used as the reference clock, the OSCINIT 0
 838  * bit should be checked to make sure it is set.
 839  *
 840  * Values:
 841  * - 0 - MCGPLLCLK is inactive.
 842  * - 1 - MCGPLLCLK is active.
 843  */
 844 /*@{*/
 845 #define BP_MCG_C5_PLLCLKEN0  (6U)          /*!< Bit position for MCG_C5_PLLCLKEN0. */
 846 #define BM_MCG_C5_PLLCLKEN0  (0x40U)       /*!< Bit mask for MCG_C5_PLLCLKEN0. */
 847 #define BS_MCG_C5_PLLCLKEN0  (1U)          /*!< Bit field size in bits for MCG_C5_PLLCLKEN0. */
 848
 849 /*! @brief Read current value of the MCG_C5_PLLCLKEN0 field. */
 850 #define BR_MCG_C5_PLLCLKEN0(x) (BITBAND_ACCESS8(HW_MCG_C5_ADDR(x), BP_MCG_C5_PLLCLKEN0))
 851
 852 /*! @brief Format value for bitfield MCG_C5_PLLCLKEN0. */
 853 #define BF_MCG_C5_PLLCLKEN0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C5_PLLCLKEN0) & BM_MCG_C5_PLLCLKEN0)
 854
 855 /*! @brief Set the PLLCLKEN0 field to a new value. */
 856 #define BW_MCG_C5_PLLCLKEN0(x, v) (BITBAND_ACCESS8(HW_MCG_C5_ADDR(x), BP_MCG_C5_PLLCLKEN0) = (v))
 857 /*@}*/
 858
 859 /*******************************************************************************
 860  * HW_MCG_C6 - MCG Control 6 Register
 861  ******************************************************************************/
 862
 863 /*!
 864  * @brief HW_MCG_C6 - MCG Control 6 Register (RW)
 865  *
 866  * Reset value: 0x00U
 867  */
 868 typedef union _hw_mcg_c6
 869 {
 870     uint8_t U;
 871     struct _hw_mcg_c6_bitfields
 872     {
 873         uint8_t VDIV0 : 5;             /*!< [4:0] VCO 0 Divider */
 874         uint8_t CME0 : 1;              /*!< [5] Clock Monitor Enable */
 875         uint8_t PLLS : 1;              /*!< [6] PLL Select */
 876         uint8_t LOLIE0 : 1;            /*!< [7] Loss of Lock Interrrupt Enable */
 877     } B;
 878 } hw_mcg_c6_t;
 879
 880 /*!
 881  * @name Constants and macros for entire MCG_C6 register
 882  */
 883 /*@{*/
 884 #define HW_MCG_C6_ADDR(x)        ((x) + 0x5U)
 885
 886 #define HW_MCG_C6(x)             (*(__IO hw_mcg_c6_t *) HW_MCG_C6_ADDR(x))
 887 #define HW_MCG_C6_RD(x)          (HW_MCG_C6(x).U)
 888 #define HW_MCG_C6_WR(x, v)       (HW_MCG_C6(x).U = (v))
 889 #define HW_MCG_C6_SET(x, v)      (HW_MCG_C6_WR(x, HW_MCG_C6_RD(x) |  (v)))
 890 #define HW_MCG_C6_CLR(x, v)      (HW_MCG_C6_WR(x, HW_MCG_C6_RD(x) & ~(v)))
 891 #define HW_MCG_C6_TOG(x, v)      (HW_MCG_C6_WR(x, HW_MCG_C6_RD(x) ^  (v)))
 892 /*@}*/
 893
 894 /*
 895  * Constants & macros for individual MCG_C6 bitfields
 896  */
 897
 898 /*!
 899  * @name Register MCG_C6, field VDIV0[4:0] (RW)
 900  *
 901  * Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits
 902  * establish the multiplication factor (M) applied to the reference clock frequency.
 903  * After the PLL is enabled (by setting either PLLCLKEN 0 or PLLS), the VDIV 0
 904  * value must not be changed when LOCK 0 is zero. PLL VCO Divide Factor VDIV 0
 905  * Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply
 906  * Factor 00000 24 01000 32 10000 40 11000 48 00001 25 01001 33 10001 41 11001 49
 907  * 00010 26 01010 34 10010 42 11010 50 00011 27 01011 35 10011 43 11011 51 00100 28
 908  * 01100 36 10100 44 11100 52 00101 29 01101 37 10101 45 11101 53 00110 30 01110
 909  * 38 10110 46 11110 54 00111 31 01111 39 10111 47 11111 55
 910  */
 911 /*@{*/
 912 #define BP_MCG_C6_VDIV0      (0U)          /*!< Bit position for MCG_C6_VDIV0. */
 913 #define BM_MCG_C6_VDIV0      (0x1FU)       /*!< Bit mask for MCG_C6_VDIV0. */
 914 #define BS_MCG_C6_VDIV0      (5U)          /*!< Bit field size in bits for MCG_C6_VDIV0. */
 915
 916 /*! @brief Read current value of the MCG_C6_VDIV0 field. */
 917 #define BR_MCG_C6_VDIV0(x)   (HW_MCG_C6(x).B.VDIV0)
 918
 919 /*! @brief Format value for bitfield MCG_C6_VDIV0. */
 920 #define BF_MCG_C6_VDIV0(v)   ((uint8_t)((uint8_t)(v) << BP_MCG_C6_VDIV0) & BM_MCG_C6_VDIV0)
 921
 922 /*! @brief Set the VDIV0 field to a new value. */
 923 #define BW_MCG_C6_VDIV0(x, v) (HW_MCG_C6_WR(x, (HW_MCG_C6_RD(x) & ~BM_MCG_C6_VDIV0) | BF_MCG_C6_VDIV0(v)))
 924 /*@}*/
 925
 926 /*!
 927  * @name Register MCG_C6, field CME0[5] (RW)
 928  *
 929  * Enables the loss of clock monitoring circuit for the OSC0 external reference
 930  * mux select. The LOCRE0 bit will determine if a interrupt or a reset request is
 931  * generated following a loss of OSC0 indication. The CME0 bit must only be set
 932  * to a logic 1 when the MCG is in an operational mode that uses the external
 933  * clock (FEE, FBE, PEE, PBE, or BLPE) . Whenever the CME0 bit is set to a logic 1,
 934  * the value of the RANGE0 bits in the C2 register should not be changed. CME0
 935  * bit should be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a
 936  * reset request may occur while in Stop mode. CME0 should also be set to a
 937  * logic 0 before entering VLPR or VLPW power modes if the MCG is in BLPE mode.
 938  *
 939  * Values:
 940  * - 0 - External clock monitor is disabled for OSC0.
 941  * - 1 - External clock monitor is enabled for OSC0.
 942  */
 943 /*@{*/
 944 #define BP_MCG_C6_CME0       (5U)          /*!< Bit position for MCG_C6_CME0. */
 945 #define BM_MCG_C6_CME0       (0x20U)       /*!< Bit mask for MCG_C6_CME0. */
 946 #define BS_MCG_C6_CME0       (1U)          /*!< Bit field size in bits for MCG_C6_CME0. */
 947
 948 /*! @brief Read current value of the MCG_C6_CME0 field. */
 949 #define BR_MCG_C6_CME0(x)    (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_CME0))
 950
 951 /*! @brief Format value for bitfield MCG_C6_CME0. */
 952 #define BF_MCG_C6_CME0(v)    ((uint8_t)((uint8_t)(v) << BP_MCG_C6_CME0) & BM_MCG_C6_CME0)
 953
 954 /*! @brief Set the CME0 field to a new value. */
 955 #define BW_MCG_C6_CME0(x, v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_CME0) = (v))
 956 /*@}*/
 957
 958 /*!
 959  * @name Register MCG_C6, field PLLS[6] (RW)
 960  *
 961  * Controls whether the PLL or FLL output is selected as the MCG source when
 962  * CLKS[1:0]=00. If the PLLS bit is cleared and PLLCLKEN 0 is not set, the PLL is
 963  * disabled in all modes. If the PLLS is set, the FLL is disabled in all modes.
 964  *
 965  * Values:
 966  * - 0 - FLL is selected.
 967  * - 1 - PLL is selected (PRDIV 0 need to be programmed to the correct divider
 968  *     to generate a PLL reference clock in the range of 2-4 MHz prior to setting
 969  *     the PLLS bit).
 970  */
 971 /*@{*/
 972 #define BP_MCG_C6_PLLS       (6U)          /*!< Bit position for MCG_C6_PLLS. */
 973 #define BM_MCG_C6_PLLS       (0x40U)       /*!< Bit mask for MCG_C6_PLLS. */
 974 #define BS_MCG_C6_PLLS       (1U)          /*!< Bit field size in bits for MCG_C6_PLLS. */
 975
 976 /*! @brief Read current value of the MCG_C6_PLLS field. */
 977 #define BR_MCG_C6_PLLS(x)    (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_PLLS))
 978
 979 /*! @brief Format value for bitfield MCG_C6_PLLS. */
 980 #define BF_MCG_C6_PLLS(v)    ((uint8_t)((uint8_t)(v) << BP_MCG_C6_PLLS) & BM_MCG_C6_PLLS)
 981
 982 /*! @brief Set the PLLS field to a new value. */
 983 #define BW_MCG_C6_PLLS(x, v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_PLLS) = (v))
 984 /*@}*/
 985
 986 /*!
 987  * @name Register MCG_C6, field LOLIE0[7] (RW)
 988  *
 989  * Determines if an interrupt request is made following a loss of lock
 990  * indication. This bit only has an effect when LOLS 0 is set.
 991  *
 992  * Values:
 993  * - 0 - No interrupt request is generated on loss of lock.
 994  * - 1 - Generate an interrupt request on loss of lock.
 995  */
 996 /*@{*/
 997 #define BP_MCG_C6_LOLIE0     (7U)          /*!< Bit position for MCG_C6_LOLIE0. */
 998 #define BM_MCG_C6_LOLIE0     (0x80U)       /*!< Bit mask for MCG_C6_LOLIE0. */
 999 #define BS_MCG_C6_LOLIE0     (1U)          /*!< Bit field size in bits for MCG_C6_LOLIE0. */
1000
1001 /*! @brief Read current value of the MCG_C6_LOLIE0 field. */
1002 #define BR_MCG_C6_LOLIE0(x)  (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_LOLIE0))
1003
1004 /*! @brief Format value for bitfield MCG_C6_LOLIE0. */
1005 #define BF_MCG_C6_LOLIE0(v)  ((uint8_t)((uint8_t)(v) << BP_MCG_C6_LOLIE0) & BM_MCG_C6_LOLIE0)
1006
1007 /*! @brief Set the LOLIE0 field to a new value. */
1008 #define BW_MCG_C6_LOLIE0(x, v) (BITBAND_ACCESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_LOLIE0) = (v))
1009 /*@}*/
1010
1011 /*******************************************************************************
1012  * HW_MCG_S - MCG Status Register
1013  ******************************************************************************/
1014
1015 /*!
1016  * @brief HW_MCG_S - MCG Status Register (RW)
1017  *
1018  * Reset value: 0x10U
1019  */
1020 typedef union _hw_mcg_s
1021 {
1022     uint8_t U;
1023     struct _hw_mcg_s_bitfields
1024     {
1025         uint8_t IRCST : 1;             /*!< [0] Internal Reference Clock Status */
1026         uint8_t OSCINIT0 : 1;          /*!< [1] OSC Initialization */
1027         uint8_t CLKST : 2;             /*!< [3:2] Clock Mode Status */
1028         uint8_t IREFST : 1;            /*!< [4] Internal Reference Status */
1029         uint8_t PLLST : 1;             /*!< [5] PLL Select Status */
1030         uint8_t LOCK0 : 1;             /*!< [6] Lock Status */
1031         uint8_t LOLS0 : 1;             /*!< [7] Loss of Lock Status */
1032     } B;
1033 } hw_mcg_s_t;
1034
1035 /*!
1036  * @name Constants and macros for entire MCG_S register
1037  */
1038 /*@{*/
1039 #define HW_MCG_S_ADDR(x)         ((x) + 0x6U)
1040
1041 #define HW_MCG_S(x)              (*(__IO hw_mcg_s_t *) HW_MCG_S_ADDR(x))
1042 #define HW_MCG_S_RD(x)           (HW_MCG_S(x).U)
1043 #define HW_MCG_S_WR(x, v)        (HW_MCG_S(x).U = (v))
1044 #define HW_MCG_S_SET(x, v)       (HW_MCG_S_WR(x, HW_MCG_S_RD(x) |  (v)))
1045 #define HW_MCG_S_CLR(x, v)       (HW_MCG_S_WR(x, HW_MCG_S_RD(x) & ~(v)))
1046 #define HW_MCG_S_TOG(x, v)       (HW_MCG_S_WR(x, HW_MCG_S_RD(x) ^  (v)))
1047 /*@}*/
1048
1049 /*
1050  * Constants & macros for individual MCG_S bitfields
1051  */
1052
1053 /*!
1054  * @name Register MCG_S, field IRCST[0] (RO)
1055  *
1056  * The IRCST bit indicates the current source for the internal reference clock
1057  * select clock (IRCSCLK). The IRCST bit does not update immediately after a write
1058  * to the IRCS bit due to internal synchronization between clock domains. The
1059  * IRCST bit will only be updated if the internal reference clock is enabled,
1060  * either by the MCG being in a mode that uses the IRC or by setting the C1[IRCLKEN]
1061  * bit .
1062  *
1063  * Values:
1064  * - 0 - Source of internal reference clock is the slow clock (32 kHz IRC).
1065  * - 1 - Source of internal reference clock is the fast clock (4 MHz IRC).
1066  */
1067 /*@{*/
1068 #define BP_MCG_S_IRCST       (0U)          /*!< Bit position for MCG_S_IRCST. */
1069 #define BM_MCG_S_IRCST       (0x01U)       /*!< Bit mask for MCG_S_IRCST. */
1070 #define BS_MCG_S_IRCST       (1U)          /*!< Bit field size in bits for MCG_S_IRCST. */
1071
1072 /*! @brief Read current value of the MCG_S_IRCST field. */
1073 #define BR_MCG_S_IRCST(x)    (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_IRCST))
1074 /*@}*/
1075
1076 /*!
1077  * @name Register MCG_S, field OSCINIT0[1] (RO)
1078  *
1079  * This bit, which resets to 0, is set to 1 after the initialization cycles of
1080  * the crystal oscillator clock have completed. After being set, the bit is
1081  * cleared to 0 if the OSC is subsequently disabled. See the OSC module's detailed
1082  * description for more information.
1083  */
1084 /*@{*/
1085 #define BP_MCG_S_OSCINIT0    (1U)          /*!< Bit position for MCG_S_OSCINIT0. */
1086 #define BM_MCG_S_OSCINIT0    (0x02U)       /*!< Bit mask for MCG_S_OSCINIT0. */
1087 #define BS_MCG_S_OSCINIT0    (1U)          /*!< Bit field size in bits for MCG_S_OSCINIT0. */
1088
1089 /*! @brief Read current value of the MCG_S_OSCINIT0 field. */
1090 #define BR_MCG_S_OSCINIT0(x) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_OSCINIT0))
1091 /*@}*/
1092
1093 /*!
1094  * @name Register MCG_S, field CLKST[3:2] (RO)
1095  *
1096  * These bits indicate the current clock mode. The CLKST bits do not update
1097  * immediately after a write to the CLKS bits due to internal synchronization between
1098  * clock domains.
1099  *
1100  * Values:
1101  * - 00 - Encoding 0 - Output of the FLL is selected (reset default).
1102  * - 01 - Encoding 1 - Internal reference clock is selected.
1103  * - 10 - Encoding 2 - External reference clock is selected.
1104  * - 11 - Encoding 3 - Output of the PLL is selected.
1105  */
1106 /*@{*/
1107 #define BP_MCG_S_CLKST       (2U)          /*!< Bit position for MCG_S_CLKST. */
1108 #define BM_MCG_S_CLKST       (0x0CU)       /*!< Bit mask for MCG_S_CLKST. */
1109 #define BS_MCG_S_CLKST       (2U)          /*!< Bit field size in bits for MCG_S_CLKST. */
1110
1111 /*! @brief Read current value of the MCG_S_CLKST field. */
1112 #define BR_MCG_S_CLKST(x)    (HW_MCG_S(x).B.CLKST)
1113 /*@}*/
1114
1115 /*!
1116  * @name Register MCG_S, field IREFST[4] (RO)
1117  *
1118  * This bit indicates the current source for the FLL reference clock. The IREFST
1119  * bit does not update immediately after a write to the IREFS bit due to
1120  * internal synchronization between clock domains.
1121  *
1122  * Values:
1123  * - 0 - Source of FLL reference clock is the external reference clock.
1124  * - 1 - Source of FLL reference clock is the internal reference clock.
1125  */
1126 /*@{*/
1127 #define BP_MCG_S_IREFST      (4U)          /*!< Bit position for MCG_S_IREFST. */
1128 #define BM_MCG_S_IREFST      (0x10U)       /*!< Bit mask for MCG_S_IREFST. */
1129 #define BS_MCG_S_IREFST      (1U)          /*!< Bit field size in bits for MCG_S_IREFST. */
1130
1131 /*! @brief Read current value of the MCG_S_IREFST field. */
1132 #define BR_MCG_S_IREFST(x)   (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_IREFST))
1133 /*@}*/
1134
1135 /*!
1136  * @name Register MCG_S, field PLLST[5] (RO)
1137  *
1138  * This bit indicates the clock source selected by PLLS . The PLLST bit does not
1139  * update immediately after a write to the PLLS bit due to internal
1140  * synchronization between clock domains.
1141  *
1142  * Values:
1143  * - 0 - Source of PLLS clock is FLL clock.
1144  * - 1 - Source of PLLS clock is PLL output clock.
1145  */
1146 /*@{*/
1147 #define BP_MCG_S_PLLST       (5U)          /*!< Bit position for MCG_S_PLLST. */
1148 #define BM_MCG_S_PLLST       (0x20U)       /*!< Bit mask for MCG_S_PLLST. */
1149 #define BS_MCG_S_PLLST       (1U)          /*!< Bit field size in bits for MCG_S_PLLST. */
1150
1151 /*! @brief Read current value of the MCG_S_PLLST field. */
1152 #define BR_MCG_S_PLLST(x)    (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_PLLST))
1153 /*@}*/
1154
1155 /*!
1156  * @name Register MCG_S, field LOCK0[6] (RO)
1157  *
1158  * This bit indicates whether the PLL has acquired lock. Lock detection is only
1159  * enabled when the PLL is enabled (either through clock mode selection or
1160  * PLLCLKEN0=1 setting). While the PLL clock is locking to the desired frequency, the
1161  * MCG PLL clock (MCGPLLCLK) will be gated off until the LOCK bit gets asserted.
1162  * If the lock status bit is set, changing the value of the PRDIV0 [4:0] bits in
1163  * the C5 register or the VDIV0[4:0] bits in the C6 register causes the lock
1164  * status bit to clear and stay cleared until the PLL has reacquired lock. Loss of PLL
1165  * reference clock will also cause the LOCK0 bit to clear until the PLL has
1166  * reacquired lock. Entry into LLS, VLPS, or regular Stop with PLLSTEN=0 also causes
1167  * the lock status bit to clear and stay cleared until the Stop mode is exited
1168  * and the PLL has reacquired lock. Any time the PLL is enabled and the LOCK0 bit
1169  * is cleared, the MCGPLLCLK will be gated off until the LOCK0 bit is asserted
1170  * again.
1171  *
1172  * Values:
1173  * - 0 - PLL is currently unlocked.
1174  * - 1 - PLL is currently locked.
1175  */
1176 /*@{*/
1177 #define BP_MCG_S_LOCK0       (6U)          /*!< Bit position for MCG_S_LOCK0. */
1178 #define BM_MCG_S_LOCK0       (0x40U)       /*!< Bit mask for MCG_S_LOCK0. */
1179 #define BS_MCG_S_LOCK0       (1U)          /*!< Bit field size in bits for MCG_S_LOCK0. */
1180
1181 /*! @brief Read current value of the MCG_S_LOCK0 field. */
1182 #define BR_MCG_S_LOCK0(x)    (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_LOCK0))
1183 /*@}*/
1184
1185 /*!
1186  * @name Register MCG_S, field LOLS0[7] (W1C)
1187  *
1188  * This bit is a sticky bit indicating the lock status for the PLL. LOLS is set
1189  * if after acquiring lock, the PLL output frequency has fallen outside the lock
1190  * exit frequency tolerance, D unl . LOLIE determines whether an interrupt
1191  * request is made when LOLS is set. LOLRE determines whether a reset request is made
1192  * when LOLS is set. This bit is cleared by reset or by writing a logic 1 to it
1193  * when set. Writing a logic 0 to this bit has no effect.
1194  *
1195  * Values:
1196  * - 0 - PLL has not lost lock since LOLS 0 was last cleared.
1197  * - 1 - PLL has lost lock since LOLS 0 was last cleared.
1198  */
1199 /*@{*/
1200 #define BP_MCG_S_LOLS0       (7U)          /*!< Bit position for MCG_S_LOLS0. */
1201 #define BM_MCG_S_LOLS0       (0x80U)       /*!< Bit mask for MCG_S_LOLS0. */
1202 #define BS_MCG_S_LOLS0       (1U)          /*!< Bit field size in bits for MCG_S_LOLS0. */
1203
1204 /*! @brief Read current value of the MCG_S_LOLS0 field. */
1205 #define BR_MCG_S_LOLS0(x)    (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_LOLS0))
1206
1207 /*! @brief Format value for bitfield MCG_S_LOLS0. */
1208 #define BF_MCG_S_LOLS0(v)    ((uint8_t)((uint8_t)(v) << BP_MCG_S_LOLS0) & BM_MCG_S_LOLS0)
1209
1210 /*! @brief Set the LOLS0 field to a new value. */
1211 #define BW_MCG_S_LOLS0(x, v) (BITBAND_ACCESS8(HW_MCG_S_ADDR(x), BP_MCG_S_LOLS0) = (v))
1212 /*@}*/
1213
1214 /*******************************************************************************
1215  * HW_MCG_SC - MCG Status and Control Register
1216  ******************************************************************************/
1217
1218 /*!
1219  * @brief HW_MCG_SC - MCG Status and Control Register (RW)
1220  *
1221  * Reset value: 0x02U
1222  */
1223 typedef union _hw_mcg_sc
1224 {
1225     uint8_t U;
1226     struct _hw_mcg_sc_bitfields
1227     {
1228         uint8_t LOCS0 : 1;             /*!< [0] OSC0 Loss of Clock Status */
1229         uint8_t FCRDIV : 3;            /*!< [3:1] Fast Clock Internal Reference Divider
1230                                         * */
1231         uint8_t FLTPRSRV : 1;          /*!< [4] FLL Filter Preserve Enable */
1232         uint8_t ATMF : 1;              /*!< [5] Automatic Trim Machine Fail Flag */
1233         uint8_t ATMS : 1;              /*!< [6] Automatic Trim Machine Select */
1234         uint8_t ATME : 1;              /*!< [7] Automatic Trim Machine Enable */
1235     } B;
1236 } hw_mcg_sc_t;
1237
1238 /*!
1239  * @name Constants and macros for entire MCG_SC register
1240  */
1241 /*@{*/
1242 #define HW_MCG_SC_ADDR(x)        ((x) + 0x8U)
1243
1244 #define HW_MCG_SC(x)             (*(__IO hw_mcg_sc_t *) HW_MCG_SC_ADDR(x))
1245 #define HW_MCG_SC_RD(x)          (HW_MCG_SC(x).U)
1246 #define HW_MCG_SC_WR(x, v)       (HW_MCG_SC(x).U = (v))
1247 #define HW_MCG_SC_SET(x, v)      (HW_MCG_SC_WR(x, HW_MCG_SC_RD(x) |  (v)))
1248 #define HW_MCG_SC_CLR(x, v)      (HW_MCG_SC_WR(x, HW_MCG_SC_RD(x) & ~(v)))
1249 #define HW_MCG_SC_TOG(x, v)      (HW_MCG_SC_WR(x, HW_MCG_SC_RD(x) ^  (v)))
1250 /*@}*/
1251
1252 /*
1253  * Constants & macros for individual MCG_SC bitfields
1254  */
1255
1256 /*!
1257  * @name Register MCG_SC, field LOCS0[0] (W1C)
1258  *
1259  * The LOCS0 indicates when a loss of OSC0 reference clock has occurred. The
1260  * LOCS0 bit only has an effect when CME0 is set. This bit is cleared by writing a
1261  * logic 1 to it when set.
1262  *
1263  * Values:
1264  * - 0 - Loss of OSC0 has not occurred.
1265  * - 1 - Loss of OSC0 has occurred.
1266  */
1267 /*@{*/
1268 #define BP_MCG_SC_LOCS0      (0U)          /*!< Bit position for MCG_SC_LOCS0. */
1269 #define BM_MCG_SC_LOCS0      (0x01U)       /*!< Bit mask for MCG_SC_LOCS0. */
1270 #define BS_MCG_SC_LOCS0      (1U)          /*!< Bit field size in bits for MCG_SC_LOCS0. */
1271
1272 /*! @brief Read current value of the MCG_SC_LOCS0 field. */
1273 #define BR_MCG_SC_LOCS0(x)   (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_LOCS0))
1274
1275 /*! @brief Format value for bitfield MCG_SC_LOCS0. */
1276 #define BF_MCG_SC_LOCS0(v)   ((uint8_t)((uint8_t)(v) << BP_MCG_SC_LOCS0) & BM_MCG_SC_LOCS0)
1277
1278 /*! @brief Set the LOCS0 field to a new value. */
1279 #define BW_MCG_SC_LOCS0(x, v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_LOCS0) = (v))
1280 /*@}*/
1281
1282 /*!
1283  * @name Register MCG_SC, field FCRDIV[3:1] (RW)
1284  *
1285  * Selects the amount to divide down the fast internal reference clock. The
1286  * resulting frequency will be in the range 31.25 kHz to 4 MHz (Note: Changing the
1287  * divider when the Fast IRC is enabled is not supported).
1288  *
1289  * Values:
1290  * - 000 - Divide Factor is 1
1291  * - 001 - Divide Factor is 2.
1292  * - 010 - Divide Factor is 4.
1293  * - 011 - Divide Factor is 8.
1294  * - 100 - Divide Factor is 16
1295  * - 101 - Divide Factor is 32
1296  * - 110 - Divide Factor is 64
1297  * - 111 - Divide Factor is 128.
1298  */
1299 /*@{*/
1300 #define BP_MCG_SC_FCRDIV     (1U)          /*!< Bit position for MCG_SC_FCRDIV. */
1301 #define BM_MCG_SC_FCRDIV     (0x0EU)       /*!< Bit mask for MCG_SC_FCRDIV. */
1302 #define BS_MCG_SC_FCRDIV     (3U)          /*!< Bit field size in bits for MCG_SC_FCRDIV. */
1303
1304 /*! @brief Read current value of the MCG_SC_FCRDIV field. */
1305 #define BR_MCG_SC_FCRDIV(x)  (HW_MCG_SC(x).B.FCRDIV)
1306
1307 /*! @brief Format value for bitfield MCG_SC_FCRDIV. */
1308 #define BF_MCG_SC_FCRDIV(v)  ((uint8_t)((uint8_t)(v) << BP_MCG_SC_FCRDIV) & BM_MCG_SC_FCRDIV)
1309
1310 /*! @brief Set the FCRDIV field to a new value. */
1311 #define BW_MCG_SC_FCRDIV(x, v) (HW_MCG_SC_WR(x, (HW_MCG_SC_RD(x) & ~BM_MCG_SC_FCRDIV) | BF_MCG_SC_FCRDIV(v)))
1312 /*@}*/
1313
1314 /*!
1315  * @name Register MCG_SC, field FLTPRSRV[4] (RW)
1316  *
1317  * This bit will prevent the FLL filter values from resetting allowing the FLL
1318  * output frequency to remain the same during clock mode changes where the FLL/DCO
1319  * output is still valid. (Note: This requires that the FLL reference frequency
1320  * to remain the same as what it was prior to the new clock mode switch.
1321  * Otherwise FLL filter and frequency values will change.)
1322  *
1323  * Values:
1324  * - 0 - FLL filter and FLL frequency will reset on changes to currect clock
1325  *     mode.
1326  * - 1 - Fll filter and FLL frequency retain their previous values during new
1327  *     clock mode change.
1328  */
1329 /*@{*/
1330 #define BP_MCG_SC_FLTPRSRV   (4U)          /*!< Bit position for MCG_SC_FLTPRSRV. */
1331 #define BM_MCG_SC_FLTPRSRV   (0x10U)       /*!< Bit mask for MCG_SC_FLTPRSRV. */
1332 #define BS_MCG_SC_FLTPRSRV   (1U)          /*!< Bit field size in bits for MCG_SC_FLTPRSRV. */
1333
1334 /*! @brief Read current value of the MCG_SC_FLTPRSRV field. */
1335 #define BR_MCG_SC_FLTPRSRV(x) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_FLTPRSRV))
1336
1337 /*! @brief Format value for bitfield MCG_SC_FLTPRSRV. */
1338 #define BF_MCG_SC_FLTPRSRV(v) ((uint8_t)((uint8_t)(v) << BP_MCG_SC_FLTPRSRV) & BM_MCG_SC_FLTPRSRV)
1339
1340 /*! @brief Set the FLTPRSRV field to a new value. */
1341 #define BW_MCG_SC_FLTPRSRV(x, v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_FLTPRSRV) = (v))
1342 /*@}*/
1343
1344 /*!
1345  * @name Register MCG_SC, field ATMF[5] (RW)
1346  *
1347  * Fail flag for the Automatic Trim Machine (ATM). This bit asserts when the
1348  * Automatic Trim Machine is enabled, ATME=1, and a write to the C1, C3, C4, and SC
1349  * registers is detected or the MCG enters into any Stop mode. A write to ATMF
1350  * clears the flag.
1351  *
1352  * Values:
1353  * - 0 - Automatic Trim Machine completed normally.
1354  * - 1 - Automatic Trim Machine failed.
1355  */
1356 /*@{*/
1357 #define BP_MCG_SC_ATMF       (5U)          /*!< Bit position for MCG_SC_ATMF. */
1358 #define BM_MCG_SC_ATMF       (0x20U)       /*!< Bit mask for MCG_SC_ATMF. */
1359 #define BS_MCG_SC_ATMF       (1U)          /*!< Bit field size in bits for MCG_SC_ATMF. */
1360
1361 /*! @brief Read current value of the MCG_SC_ATMF field. */
1362 #define BR_MCG_SC_ATMF(x)    (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATMF))
1363
1364 /*! @brief Format value for bitfield MCG_SC_ATMF. */
1365 #define BF_MCG_SC_ATMF(v)    ((uint8_t)((uint8_t)(v) << BP_MCG_SC_ATMF) & BM_MCG_SC_ATMF)
1366
1367 /*! @brief Set the ATMF field to a new value. */
1368 #define BW_MCG_SC_ATMF(x, v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATMF) = (v))
1369 /*@}*/
1370
1371 /*!
1372  * @name Register MCG_SC, field ATMS[6] (RW)
1373  *
1374  * Selects the IRCS clock for Auto Trim Test.
1375  *
1376  * Values:
1377  * - 0 - 32 kHz Internal Reference Clock selected.
1378  * - 1 - 4 MHz Internal Reference Clock selected.
1379  */
1380 /*@{*/
1381 #define BP_MCG_SC_ATMS       (6U)          /*!< Bit position for MCG_SC_ATMS. */
1382 #define BM_MCG_SC_ATMS       (0x40U)       /*!< Bit mask for MCG_SC_ATMS. */
1383 #define BS_MCG_SC_ATMS       (1U)          /*!< Bit field size in bits for MCG_SC_ATMS. */
1384
1385 /*! @brief Read current value of the MCG_SC_ATMS field. */
1386 #define BR_MCG_SC_ATMS(x)    (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATMS))
1387
1388 /*! @brief Format value for bitfield MCG_SC_ATMS. */
1389 #define BF_MCG_SC_ATMS(v)    ((uint8_t)((uint8_t)(v) << BP_MCG_SC_ATMS) & BM_MCG_SC_ATMS)
1390
1391 /*! @brief Set the ATMS field to a new value. */
1392 #define BW_MCG_SC_ATMS(x, v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATMS) = (v))
1393 /*@}*/
1394
1395 /*!
1396  * @name Register MCG_SC, field ATME[7] (RW)
1397  *
1398  * Enables the Auto Trim Machine to start automatically trimming the selected
1399  * Internal Reference Clock. ATME deasserts after the Auto Trim Machine has
1400  * completed trimming all trim bits of the IRCS clock selected by the ATMS bit. Writing
1401  * to C1, C3, C4, and SC registers or entering Stop mode aborts the auto trim
1402  * operation and clears this bit.
1403  *
1404  * Values:
1405  * - 0 - Auto Trim Machine disabled.
1406  * - 1 - Auto Trim Machine enabled.
1407  */
1408 /*@{*/
1409 #define BP_MCG_SC_ATME       (7U)          /*!< Bit position for MCG_SC_ATME. */
1410 #define BM_MCG_SC_ATME       (0x80U)       /*!< Bit mask for MCG_SC_ATME. */
1411 #define BS_MCG_SC_ATME       (1U)          /*!< Bit field size in bits for MCG_SC_ATME. */
1412
1413 /*! @brief Read current value of the MCG_SC_ATME field. */
1414 #define BR_MCG_SC_ATME(x)    (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATME))
1415
1416 /*! @brief Format value for bitfield MCG_SC_ATME. */
1417 #define BF_MCG_SC_ATME(v)    ((uint8_t)((uint8_t)(v) << BP_MCG_SC_ATME) & BM_MCG_SC_ATME)
1418
1419 /*! @brief Set the ATME field to a new value. */
1420 #define BW_MCG_SC_ATME(x, v) (BITBAND_ACCESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATME) = (v))
1421 /*@}*/
1422
1423 /*******************************************************************************
1424  * HW_MCG_ATCVH - MCG Auto Trim Compare Value High Register
1425  ******************************************************************************/
1426
1427 /*!
1428  * @brief HW_MCG_ATCVH - MCG Auto Trim Compare Value High Register (RW)
1429  *
1430  * Reset value: 0x00U
1431  */
1432 typedef union _hw_mcg_atcvh
1433 {
1434     uint8_t U;
1435     struct _hw_mcg_atcvh_bitfields
1436     {
1437         uint8_t ATCVH : 8;             /*!< [7:0] ATM Compare Value High */
1438     } B;
1439 } hw_mcg_atcvh_t;
1440
1441 /*!
1442  * @name Constants and macros for entire MCG_ATCVH register
1443  */
1444 /*@{*/
1445 #define HW_MCG_ATCVH_ADDR(x)     ((x) + 0xAU)
1446
1447 #define HW_MCG_ATCVH(x)          (*(__IO hw_mcg_atcvh_t *) HW_MCG_ATCVH_ADDR(x))
1448 #define HW_MCG_ATCVH_RD(x)       (HW_MCG_ATCVH(x).U)
1449 #define HW_MCG_ATCVH_WR(x, v)    (HW_MCG_ATCVH(x).U = (v))
1450 #define HW_MCG_ATCVH_SET(x, v)   (HW_MCG_ATCVH_WR(x, HW_MCG_ATCVH_RD(x) |  (v)))
1451 #define HW_MCG_ATCVH_CLR(x, v)   (HW_MCG_ATCVH_WR(x, HW_MCG_ATCVH_RD(x) & ~(v)))
1452 #define HW_MCG_ATCVH_TOG(x, v)   (HW_MCG_ATCVH_WR(x, HW_MCG_ATCVH_RD(x) ^  (v)))
1453 /*@}*/
1454
1455 /*
1456  * Constants & macros for individual MCG_ATCVH bitfields
1457  */
1458
1459 /*!
1460  * @name Register MCG_ATCVH, field ATCVH[7:0] (RW)
1461  *
1462  * Values are used by Auto Trim Machine to compare and adjust Internal Reference
1463  * trim values during ATM SAR conversion.
1464  */
1465 /*@{*/
1466 #define BP_MCG_ATCVH_ATCVH   (0U)          /*!< Bit position for MCG_ATCVH_ATCVH. */
1467 #define BM_MCG_ATCVH_ATCVH   (0xFFU)       /*!< Bit mask for MCG_ATCVH_ATCVH. */
1468 #define BS_MCG_ATCVH_ATCVH   (8U)          /*!< Bit field size in bits for MCG_ATCVH_ATCVH. */
1469
1470 /*! @brief Read current value of the MCG_ATCVH_ATCVH field. */
1471 #define BR_MCG_ATCVH_ATCVH(x) (HW_MCG_ATCVH(x).U)
1472
1473 /*! @brief Format value for bitfield MCG_ATCVH_ATCVH. */
1474 #define BF_MCG_ATCVH_ATCVH(v) ((uint8_t)((uint8_t)(v) << BP_MCG_ATCVH_ATCVH) & BM_MCG_ATCVH_ATCVH)
1475
1476 /*! @brief Set the ATCVH field to a new value. */
1477 #define BW_MCG_ATCVH_ATCVH(x, v) (HW_MCG_ATCVH_WR(x, v))
1478 /*@}*/
1479
1480 /*******************************************************************************
1481  * HW_MCG_ATCVL - MCG Auto Trim Compare Value Low Register
1482  ******************************************************************************/
1483
1484 /*!
1485  * @brief HW_MCG_ATCVL - MCG Auto Trim Compare Value Low Register (RW)
1486  *
1487  * Reset value: 0x00U
1488  */
1489 typedef union _hw_mcg_atcvl
1490 {
1491     uint8_t U;
1492     struct _hw_mcg_atcvl_bitfields
1493     {
1494         uint8_t ATCVL : 8;             /*!< [7:0] ATM Compare Value Low */
1495     } B;
1496 } hw_mcg_atcvl_t;
1497
1498 /*!
1499  * @name Constants and macros for entire MCG_ATCVL register
1500  */
1501 /*@{*/
1502 #define HW_MCG_ATCVL_ADDR(x)     ((x) + 0xBU)
1503
1504 #define HW_MCG_ATCVL(x)          (*(__IO hw_mcg_atcvl_t *) HW_MCG_ATCVL_ADDR(x))
1505 #define HW_MCG_ATCVL_RD(x)       (HW_MCG_ATCVL(x).U)
1506 #define HW_MCG_ATCVL_WR(x, v)    (HW_MCG_ATCVL(x).U = (v))
1507 #define HW_MCG_ATCVL_SET(x, v)   (HW_MCG_ATCVL_WR(x, HW_MCG_ATCVL_RD(x) |  (v)))
1508 #define HW_MCG_ATCVL_CLR(x, v)   (HW_MCG_ATCVL_WR(x, HW_MCG_ATCVL_RD(x) & ~(v)))
1509 #define HW_MCG_ATCVL_TOG(x, v)   (HW_MCG_ATCVL_WR(x, HW_MCG_ATCVL_RD(x) ^  (v)))
1510 /*@}*/
1511
1512 /*
1513  * Constants & macros for individual MCG_ATCVL bitfields
1514  */
1515
1516 /*!
1517  * @name Register MCG_ATCVL, field ATCVL[7:0] (RW)
1518  *
1519  * Values are used by Auto Trim Machine to compare and adjust Internal Reference
1520  * trim values during ATM SAR conversion.
1521  */
1522 /*@{*/
1523 #define BP_MCG_ATCVL_ATCVL   (0U)          /*!< Bit position for MCG_ATCVL_ATCVL. */
1524 #define BM_MCG_ATCVL_ATCVL   (0xFFU)       /*!< Bit mask for MCG_ATCVL_ATCVL. */
1525 #define BS_MCG_ATCVL_ATCVL   (8U)          /*!< Bit field size in bits for MCG_ATCVL_ATCVL. */
1526
1527 /*! @brief Read current value of the MCG_ATCVL_ATCVL field. */
1528 #define BR_MCG_ATCVL_ATCVL(x) (HW_MCG_ATCVL(x).U)
1529
1530 /*! @brief Format value for bitfield MCG_ATCVL_ATCVL. */
1531 #define BF_MCG_ATCVL_ATCVL(v) ((uint8_t)((uint8_t)(v) << BP_MCG_ATCVL_ATCVL) & BM_MCG_ATCVL_ATCVL)
1532
1533 /*! @brief Set the ATCVL field to a new value. */
1534 #define BW_MCG_ATCVL_ATCVL(x, v) (HW_MCG_ATCVL_WR(x, v))
1535 /*@}*/
1536
1537 /*******************************************************************************
1538  * HW_MCG_C7 - MCG Control 7 Register
1539  ******************************************************************************/
1540
1541 /*!
1542  * @brief HW_MCG_C7 - MCG Control 7 Register (RW)
1543  *
1544  * Reset value: 0x00U
1545  */
1546 typedef union _hw_mcg_c7
1547 {
1548     uint8_t U;
1549     struct _hw_mcg_c7_bitfields
1550     {
1551         uint8_t OSCSEL : 2;            /*!< [1:0] MCG OSC Clock Select */
1552         uint8_t RESERVED0 : 6;         /*!< [7:2]  */
1553     } B;
1554 } hw_mcg_c7_t;
1555
1556 /*!
1557  * @name Constants and macros for entire MCG_C7 register
1558  */
1559 /*@{*/
1560 #define HW_MCG_C7_ADDR(x)        ((x) + 0xCU)
1561
1562 #define HW_MCG_C7(x)             (*(__IO hw_mcg_c7_t *) HW_MCG_C7_ADDR(x))
1563 #define HW_MCG_C7_RD(x)          (HW_MCG_C7(x).U)
1564 #define HW_MCG_C7_WR(x, v)       (HW_MCG_C7(x).U = (v))
1565 #define HW_MCG_C7_SET(x, v)      (HW_MCG_C7_WR(x, HW_MCG_C7_RD(x) |  (v)))
1566 #define HW_MCG_C7_CLR(x, v)      (HW_MCG_C7_WR(x, HW_MCG_C7_RD(x) & ~(v)))
1567 #define HW_MCG_C7_TOG(x, v)      (HW_MCG_C7_WR(x, HW_MCG_C7_RD(x) ^  (v)))
1568 /*@}*/
1569
1570 /*
1571  * Constants & macros for individual MCG_C7 bitfields
1572  */
1573
1574 /*!
1575  * @name Register MCG_C7, field OSCSEL[1:0] (RW)
1576  *
1577  * Selects the MCG FLL external reference clock
1578  *
1579  * Values:
1580  * - 00 - Selects Oscillator (OSCCLK0).
1581  * - 01 - Selects 32 kHz RTC Oscillator.
1582  * - 10 - Selects Oscillator (OSCCLK1).
1583  * - 11 - RESERVED
1584  */
1585 /*@{*/
1586 #define BP_MCG_C7_OSCSEL     (0U)          /*!< Bit position for MCG_C7_OSCSEL. */
1587 #define BM_MCG_C7_OSCSEL     (0x03U)       /*!< Bit mask for MCG_C7_OSCSEL. */
1588 #define BS_MCG_C7_OSCSEL     (2U)          /*!< Bit field size in bits for MCG_C7_OSCSEL. */
1589
1590 /*! @brief Read current value of the MCG_C7_OSCSEL field. */
1591 #define BR_MCG_C7_OSCSEL(x)  (HW_MCG_C7(x).B.OSCSEL)
1592
1593 /*! @brief Format value for bitfield MCG_C7_OSCSEL. */
1594 #define BF_MCG_C7_OSCSEL(v)  ((uint8_t)((uint8_t)(v) << BP_MCG_C7_OSCSEL) & BM_MCG_C7_OSCSEL)
1595
1596 /*! @brief Set the OSCSEL field to a new value. */
1597 #define BW_MCG_C7_OSCSEL(x, v) (HW_MCG_C7_WR(x, (HW_MCG_C7_RD(x) & ~BM_MCG_C7_OSCSEL) | BF_MCG_C7_OSCSEL(v)))
1598 /*@}*/
1599
1600 /*******************************************************************************
1601  * HW_MCG_C8 - MCG Control 8 Register
1602  ******************************************************************************/
1603
1604 /*!
1605  * @brief HW_MCG_C8 - MCG Control 8 Register (RW)
1606  *
1607  * Reset value: 0x80U
1608  */
1609 typedef union _hw_mcg_c8
1610 {
1611     uint8_t U;
1612     struct _hw_mcg_c8_bitfields
1613     {
1614         uint8_t LOCS1 : 1;             /*!< [0] RTC Loss of Clock Status */
1615         uint8_t RESERVED0 : 4;         /*!< [4:1]  */
1616         uint8_t CME1 : 1;              /*!< [5] Clock Monitor Enable1 */
1617         uint8_t LOLRE : 1;             /*!< [6] PLL Loss of Lock Reset Enable */
1618         uint8_t LOCRE1 : 1;            /*!< [7] Loss of Clock Reset Enable */
1619     } B;
1620 } hw_mcg_c8_t;
1621
1622 /*!
1623  * @name Constants and macros for entire MCG_C8 register
1624  */
1625 /*@{*/
1626 #define HW_MCG_C8_ADDR(x)        ((x) + 0xDU)
1627
1628 #define HW_MCG_C8(x)             (*(__IO hw_mcg_c8_t *) HW_MCG_C8_ADDR(x))
1629 #define HW_MCG_C8_RD(x)          (HW_MCG_C8(x).U)
1630 #define HW_MCG_C8_WR(x, v)       (HW_MCG_C8(x).U = (v))
1631 #define HW_MCG_C8_SET(x, v)      (HW_MCG_C8_WR(x, HW_MCG_C8_RD(x) |  (v)))
1632 #define HW_MCG_C8_CLR(x, v)      (HW_MCG_C8_WR(x, HW_MCG_C8_RD(x) & ~(v)))
1633 #define HW_MCG_C8_TOG(x, v)      (HW_MCG_C8_WR(x, HW_MCG_C8_RD(x) ^  (v)))
1634 /*@}*/
1635
1636 /*
1637  * Constants & macros for individual MCG_C8 bitfields
1638  */
1639
1640 /*!
1641  * @name Register MCG_C8, field LOCS1[0] (W1C)
1642  *
1643  * This bit indicates when a loss of clock has occurred. This bit is cleared by
1644  * writing a logic 1 to it when set.
1645  *
1646  * Values:
1647  * - 0 - Loss of RTC has not occur.
1648  * - 1 - Loss of RTC has occur
1649  */
1650 /*@{*/
1651 #define BP_MCG_C8_LOCS1      (0U)          /*!< Bit position for MCG_C8_LOCS1. */
1652 #define BM_MCG_C8_LOCS1      (0x01U)       /*!< Bit mask for MCG_C8_LOCS1. */
1653 #define BS_MCG_C8_LOCS1      (1U)          /*!< Bit field size in bits for MCG_C8_LOCS1. */
1654
1655 /*! @brief Read current value of the MCG_C8_LOCS1 field. */
1656 #define BR_MCG_C8_LOCS1(x)   (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOCS1))
1657
1658 /*! @brief Format value for bitfield MCG_C8_LOCS1. */
1659 #define BF_MCG_C8_LOCS1(v)   ((uint8_t)((uint8_t)(v) << BP_MCG_C8_LOCS1) & BM_MCG_C8_LOCS1)
1660
1661 /*! @brief Set the LOCS1 field to a new value. */
1662 #define BW_MCG_C8_LOCS1(x, v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOCS1) = (v))
1663 /*@}*/
1664
1665 /*!
1666  * @name Register MCG_C8, field CME1[5] (RW)
1667  *
1668  * Enables the loss of clock monitoring circuit for the output of the RTC
1669  * external reference clock. The LOCRE1 bit will determine whether an interrupt or a
1670  * reset request is generated following a loss of RTC clock indication. The CME1
1671  * bit should be set to a logic 1 when the MCG is in an operational mode that uses
1672  * the RTC as its external reference clock or if the RTC is operational. CME1 bit
1673  * must be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a
1674  * reset request may occur when in Stop mode. CME1 should also be set to a logic 0
1675  * before entering VLPR or VLPW power modes.
1676  *
1677  * Values:
1678  * - 0 - External clock monitor is disabled for RTC clock.
1679  * - 1 - External clock monitor is enabled for RTC clock.
1680  */
1681 /*@{*/
1682 #define BP_MCG_C8_CME1       (5U)          /*!< Bit position for MCG_C8_CME1. */
1683 #define BM_MCG_C8_CME1       (0x20U)       /*!< Bit mask for MCG_C8_CME1. */
1684 #define BS_MCG_C8_CME1       (1U)          /*!< Bit field size in bits for MCG_C8_CME1. */
1685
1686 /*! @brief Read current value of the MCG_C8_CME1 field. */
1687 #define BR_MCG_C8_CME1(x)    (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_CME1))
1688
1689 /*! @brief Format value for bitfield MCG_C8_CME1. */
1690 #define BF_MCG_C8_CME1(v)    ((uint8_t)((uint8_t)(v) << BP_MCG_C8_CME1) & BM_MCG_C8_CME1)
1691
1692 /*! @brief Set the CME1 field to a new value. */
1693 #define BW_MCG_C8_CME1(x, v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_CME1) = (v))
1694 /*@}*/
1695
1696 /*!
1697  * @name Register MCG_C8, field LOLRE[6] (RW)
1698  *
1699  * Determines if an interrupt or a reset request is made following a PLL loss of
1700  * lock.
1701  *
1702  * Values:
1703  * - 0 - Interrupt request is generated on a PLL loss of lock indication. The
1704  *     PLL loss of lock interrupt enable bit must also be set to generate the
1705  *     interrupt request.
1706  * - 1 - Generate a reset request on a PLL loss of lock indication.
1707  */
1708 /*@{*/
1709 #define BP_MCG_C8_LOLRE      (6U)          /*!< Bit position for MCG_C8_LOLRE. */
1710 #define BM_MCG_C8_LOLRE      (0x40U)       /*!< Bit mask for MCG_C8_LOLRE. */
1711 #define BS_MCG_C8_LOLRE      (1U)          /*!< Bit field size in bits for MCG_C8_LOLRE. */
1712
1713 /*! @brief Read current value of the MCG_C8_LOLRE field. */
1714 #define BR_MCG_C8_LOLRE(x)   (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOLRE))
1715
1716 /*! @brief Format value for bitfield MCG_C8_LOLRE. */
1717 #define BF_MCG_C8_LOLRE(v)   ((uint8_t)((uint8_t)(v) << BP_MCG_C8_LOLRE) & BM_MCG_C8_LOLRE)
1718
1719 /*! @brief Set the LOLRE field to a new value. */
1720 #define BW_MCG_C8_LOLRE(x, v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOLRE) = (v))
1721 /*@}*/
1722
1723 /*!
1724  * @name Register MCG_C8, field LOCRE1[7] (RW)
1725  *
1726  * Determines if a interrupt or a reset request is made following a loss of RTC
1727  * external reference clock. The LOCRE1 only has an affect when CME1 is set.
1728  *
1729  * Values:
1730  * - 0 - Interrupt request is generated on a loss of RTC external reference
1731  *     clock.
1732  * - 1 - Generate a reset request on a loss of RTC external reference clock
1733  */
1734 /*@{*/
1735 #define BP_MCG_C8_LOCRE1     (7U)          /*!< Bit position for MCG_C8_LOCRE1. */
1736 #define BM_MCG_C8_LOCRE1     (0x80U)       /*!< Bit mask for MCG_C8_LOCRE1. */
1737 #define BS_MCG_C8_LOCRE1     (1U)          /*!< Bit field size in bits for MCG_C8_LOCRE1. */
1738
1739 /*! @brief Read current value of the MCG_C8_LOCRE1 field. */
1740 #define BR_MCG_C8_LOCRE1(x)  (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOCRE1))
1741
1742 /*! @brief Format value for bitfield MCG_C8_LOCRE1. */
1743 #define BF_MCG_C8_LOCRE1(v)  ((uint8_t)((uint8_t)(v) << BP_MCG_C8_LOCRE1) & BM_MCG_C8_LOCRE1)
1744
1745 /*! @brief Set the LOCRE1 field to a new value. */
1746 #define BW_MCG_C8_LOCRE1(x, v) (BITBAND_ACCESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOCRE1) = (v))
1747 /*@}*/
1748
1749 /*******************************************************************************
1750  * hw_mcg_t - module struct
1751  ******************************************************************************/
1752 /*!
1753  * @brief All MCG module registers.
1754  */
1755 #pragma pack(1)
1756 typedef struct _hw_mcg
1757 {
1758     __IO hw_mcg_c1_t C1;                   /*!< [0x0] MCG Control 1 Register */
1759     __IO hw_mcg_c2_t C2;                   /*!< [0x1] MCG Control 2 Register */
1760     __IO hw_mcg_c3_t C3;                   /*!< [0x2] MCG Control 3 Register */
1761     __IO hw_mcg_c4_t C4;                   /*!< [0x3] MCG Control 4 Register */
1762     __IO hw_mcg_c5_t C5;                   /*!< [0x4] MCG Control 5 Register */
1763     __IO hw_mcg_c6_t C6;                   /*!< [0x5] MCG Control 6 Register */
1764     __IO hw_mcg_s_t S;                     /*!< [0x6] MCG Status Register */
1765     uint8_t _reserved0[1];
1766     __IO hw_mcg_sc_t SC;                   /*!< [0x8] MCG Status and Control Register */
1767     uint8_t _reserved1[1];
1768     __IO hw_mcg_atcvh_t ATCVH;             /*!< [0xA] MCG Auto Trim Compare Value High Register */
1769     __IO hw_mcg_atcvl_t ATCVL;             /*!< [0xB] MCG Auto Trim Compare Value Low Register */
1770     __IO hw_mcg_c7_t C7;                   /*!< [0xC] MCG Control 7 Register */
1771     __IO hw_mcg_c8_t C8;                   /*!< [0xD] MCG Control 8 Register */
1772 } hw_mcg_t;
1773 #pragma pack()
1774
1775 /*! @brief Macro to access all MCG registers. */
1776 /*! @param x MCG module instance base address. */
1777 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
1778  *     use the '&' operator, like <code>&HW_MCG(MCG_BASE)</code>. */
1779 #define HW_MCG(x)      (*(hw_mcg_t *)(x))
1780
1781 #endif /* __HW_MCG_REGISTERS_H__ */
1782 /* EOF */