tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_pdb.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
   9 **     Version:             rev. 2.5, 2014-02-10
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-08-12)
  48 **         Initial version.
  49 **     - rev. 2.0 (2013-10-29)
  50 **         Register accessor macros added to the memory map.
  51 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  52 **         Startup file for gcc has been updated according to CMSIS 3.2.
  53 **         System initialization updated.
  54 **         MCG - registers updated.
  55 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-09)
  59 **         DMA - EARS register removed.
  60 **         AIPS0, AIPS1 - MPRA register updated.
  61 **     - rev. 2.3 (2014-01-24)
  62 **         Update according to reference manual rev. 2
  63 **         ENET, MCG, MCM, SIM, USB - registers updated
  64 **     - rev. 2.4 (2014-02-10)
  65 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  66 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  67 **     - rev. 2.5 (2014-02-10)
  68 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  69 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  70 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  71 **
  72 ** ###################################################################
  73 */
  74
  75 /*
  76  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  77  *
  78  * This file was generated automatically and any changes may be lost.
  79  */
  80 #ifndef __HW_PDB_REGISTERS_H__
  81 #define __HW_PDB_REGISTERS_H__
  82
  83 #include "MK64F12.h"
  84 #include "fsl_bitaccess.h"
  85
  86 /*
  87  * MK64F12 PDB
  88  *
  89  * Programmable Delay Block
  90  *
  91  * Registers defined in this header file:
  92  * - HW_PDB_SC - Status and Control register
  93  * - HW_PDB_MOD - Modulus register
  94  * - HW_PDB_CNT - Counter register
  95  * - HW_PDB_IDLY - Interrupt Delay register
  96  * - HW_PDB_CHnC1 - Channel n Control register 1
  97  * - HW_PDB_CHnS - Channel n Status register
  98  * - HW_PDB_CHnDLY0 - Channel n Delay 0 register
  99  * - HW_PDB_CHnDLY1 - Channel n Delay 1 register
 100  * - HW_PDB_DACINTCn - DAC Interval Trigger n Control register
 101  * - HW_PDB_DACINTn - DAC Interval n register
 102  * - HW_PDB_POEN - Pulse-Out n Enable register
 103  * - HW_PDB_POnDLY - Pulse-Out n Delay register
 104  *
 105  * - hw_pdb_t - Struct containing all module registers.
 106  */
 107
 108 #define HW_PDB_INSTANCE_COUNT (1U) /*!< Number of instances of the PDB module. */
 109
 110 /*******************************************************************************
 111  * HW_PDB_SC - Status and Control register
 112  ******************************************************************************/
 113
 114 /*!
 115  * @brief HW_PDB_SC - Status and Control register (RW)
 116  *
 117  * Reset value: 0x00000000U
 118  */
 119 typedef union _hw_pdb_sc
 120 {
 121     uint32_t U;
 122     struct _hw_pdb_sc_bitfields
 123     {
 124         uint32_t LDOK : 1;             /*!< [0] Load OK */
 125         uint32_t CONT : 1;             /*!< [1] Continuous Mode Enable */
 126         uint32_t MULT : 2;             /*!< [3:2] Multiplication Factor Select for
 127                                         * Prescaler */
 128         uint32_t RESERVED0 : 1;        /*!< [4]  */
 129         uint32_t PDBIE : 1;            /*!< [5] PDB Interrupt Enable */
 130         uint32_t PDBIF : 1;            /*!< [6] PDB Interrupt Flag */
 131         uint32_t PDBEN : 1;            /*!< [7] PDB Enable */
 132         uint32_t TRGSEL : 4;           /*!< [11:8] Trigger Input Source Select */
 133         uint32_t PRESCALER : 3;        /*!< [14:12] Prescaler Divider Select */
 134         uint32_t DMAEN : 1;            /*!< [15] DMA Enable */
 135         uint32_t SWTRIG : 1;           /*!< [16] Software Trigger */
 136         uint32_t PDBEIE : 1;           /*!< [17] PDB Sequence Error Interrupt Enable */
 137         uint32_t LDMOD : 2;            /*!< [19:18] Load Mode Select */
 138         uint32_t RESERVED1 : 12;       /*!< [31:20]  */
 139     } B;
 140 } hw_pdb_sc_t;
 141
 142 /*!
 143  * @name Constants and macros for entire PDB_SC register
 144  */
 145 /*@{*/
 146 #define HW_PDB_SC_ADDR(x)        ((x) + 0x0U)
 147
 148 #define HW_PDB_SC(x)             (*(__IO hw_pdb_sc_t *) HW_PDB_SC_ADDR(x))
 149 #define HW_PDB_SC_RD(x)          (HW_PDB_SC(x).U)
 150 #define HW_PDB_SC_WR(x, v)       (HW_PDB_SC(x).U = (v))
 151 #define HW_PDB_SC_SET(x, v)      (HW_PDB_SC_WR(x, HW_PDB_SC_RD(x) |  (v)))
 152 #define HW_PDB_SC_CLR(x, v)      (HW_PDB_SC_WR(x, HW_PDB_SC_RD(x) & ~(v)))
 153 #define HW_PDB_SC_TOG(x, v)      (HW_PDB_SC_WR(x, HW_PDB_SC_RD(x) ^  (v)))
 154 /*@}*/
 155
 156 /*
 157  * Constants & macros for individual PDB_SC bitfields
 158  */
 159
 160 /*!
 161  * @name Register PDB_SC, field LDOK[0] (RW)
 162  *
 163  * Writing 1 to this bit updates the internal registers of MOD, IDLY, CHnDLYm,
 164  * DACINTx,and POyDLY with the values written to their buffers. The MOD, IDLY,
 165  * CHnDLYm, DACINTx, and POyDLY will take effect according to the LDMOD. After 1 is
 166  * written to the LDOK field, the values in the buffers of above registers are
 167  * not effective and the buffers cannot be written until the values in buffers are
 168  * loaded into their internal registers. LDOK can be written only when PDBEN is
 169  * set or it can be written at the same time with PDBEN being written to 1. It is
 170  * automatically cleared when the values in buffers are loaded into the internal
 171  * registers or the PDBEN is cleared. Writing 0 to it has no effect.
 172  */
 173 /*@{*/
 174 #define BP_PDB_SC_LDOK       (0U)          /*!< Bit position for PDB_SC_LDOK. */
 175 #define BM_PDB_SC_LDOK       (0x00000001U) /*!< Bit mask for PDB_SC_LDOK. */
 176 #define BS_PDB_SC_LDOK       (1U)          /*!< Bit field size in bits for PDB_SC_LDOK. */
 177
 178 /*! @brief Read current value of the PDB_SC_LDOK field. */
 179 #define BR_PDB_SC_LDOK(x)    (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_LDOK))
 180
 181 /*! @brief Format value for bitfield PDB_SC_LDOK. */
 182 #define BF_PDB_SC_LDOK(v)    ((uint32_t)((uint32_t)(v) << BP_PDB_SC_LDOK) & BM_PDB_SC_LDOK)
 183
 184 /*! @brief Set the LDOK field to a new value. */
 185 #define BW_PDB_SC_LDOK(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_LDOK) = (v))
 186 /*@}*/
 187
 188 /*!
 189  * @name Register PDB_SC, field CONT[1] (RW)
 190  *
 191  * Enables the PDB operation in Continuous mode.
 192  *
 193  * Values:
 194  * - 0 - PDB operation in One-Shot mode
 195  * - 1 - PDB operation in Continuous mode
 196  */
 197 /*@{*/
 198 #define BP_PDB_SC_CONT       (1U)          /*!< Bit position for PDB_SC_CONT. */
 199 #define BM_PDB_SC_CONT       (0x00000002U) /*!< Bit mask for PDB_SC_CONT. */
 200 #define BS_PDB_SC_CONT       (1U)          /*!< Bit field size in bits for PDB_SC_CONT. */
 201
 202 /*! @brief Read current value of the PDB_SC_CONT field. */
 203 #define BR_PDB_SC_CONT(x)    (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_CONT))
 204
 205 /*! @brief Format value for bitfield PDB_SC_CONT. */
 206 #define BF_PDB_SC_CONT(v)    ((uint32_t)((uint32_t)(v) << BP_PDB_SC_CONT) & BM_PDB_SC_CONT)
 207
 208 /*! @brief Set the CONT field to a new value. */
 209 #define BW_PDB_SC_CONT(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_CONT) = (v))
 210 /*@}*/
 211
 212 /*!
 213  * @name Register PDB_SC, field MULT[3:2] (RW)
 214  *
 215  * Selects the multiplication factor of the prescaler divider for the counter
 216  * clock.
 217  *
 218  * Values:
 219  * - 00 - Multiplication factor is 1.
 220  * - 01 - Multiplication factor is 10.
 221  * - 10 - Multiplication factor is 20.
 222  * - 11 - Multiplication factor is 40.
 223  */
 224 /*@{*/
 225 #define BP_PDB_SC_MULT       (2U)          /*!< Bit position for PDB_SC_MULT. */
 226 #define BM_PDB_SC_MULT       (0x0000000CU) /*!< Bit mask for PDB_SC_MULT. */
 227 #define BS_PDB_SC_MULT       (2U)          /*!< Bit field size in bits for PDB_SC_MULT. */
 228
 229 /*! @brief Read current value of the PDB_SC_MULT field. */
 230 #define BR_PDB_SC_MULT(x)    (HW_PDB_SC(x).B.MULT)
 231
 232 /*! @brief Format value for bitfield PDB_SC_MULT. */
 233 #define BF_PDB_SC_MULT(v)    ((uint32_t)((uint32_t)(v) << BP_PDB_SC_MULT) & BM_PDB_SC_MULT)
 234
 235 /*! @brief Set the MULT field to a new value. */
 236 #define BW_PDB_SC_MULT(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_MULT) | BF_PDB_SC_MULT(v)))
 237 /*@}*/
 238
 239 /*!
 240  * @name Register PDB_SC, field PDBIE[5] (RW)
 241  *
 242  * Enables the PDB interrupt. When this field is set and DMAEN is cleared, PDBIF
 243  * generates a PDB interrupt.
 244  *
 245  * Values:
 246  * - 0 - PDB interrupt disabled.
 247  * - 1 - PDB interrupt enabled.
 248  */
 249 /*@{*/
 250 #define BP_PDB_SC_PDBIE      (5U)          /*!< Bit position for PDB_SC_PDBIE. */
 251 #define BM_PDB_SC_PDBIE      (0x00000020U) /*!< Bit mask for PDB_SC_PDBIE. */
 252 #define BS_PDB_SC_PDBIE      (1U)          /*!< Bit field size in bits for PDB_SC_PDBIE. */
 253
 254 /*! @brief Read current value of the PDB_SC_PDBIE field. */
 255 #define BR_PDB_SC_PDBIE(x)   (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIE))
 256
 257 /*! @brief Format value for bitfield PDB_SC_PDBIE. */
 258 #define BF_PDB_SC_PDBIE(v)   ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBIE) & BM_PDB_SC_PDBIE)
 259
 260 /*! @brief Set the PDBIE field to a new value. */
 261 #define BW_PDB_SC_PDBIE(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIE) = (v))
 262 /*@}*/
 263
 264 /*!
 265  * @name Register PDB_SC, field PDBIF[6] (RW)
 266  *
 267  * This field is set when the counter value is equal to the IDLY register.
 268  * Writing zero clears this field.
 269  */
 270 /*@{*/
 271 #define BP_PDB_SC_PDBIF      (6U)          /*!< Bit position for PDB_SC_PDBIF. */
 272 #define BM_PDB_SC_PDBIF      (0x00000040U) /*!< Bit mask for PDB_SC_PDBIF. */
 273 #define BS_PDB_SC_PDBIF      (1U)          /*!< Bit field size in bits for PDB_SC_PDBIF. */
 274
 275 /*! @brief Read current value of the PDB_SC_PDBIF field. */
 276 #define BR_PDB_SC_PDBIF(x)   (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIF))
 277
 278 /*! @brief Format value for bitfield PDB_SC_PDBIF. */
 279 #define BF_PDB_SC_PDBIF(v)   ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBIF) & BM_PDB_SC_PDBIF)
 280
 281 /*! @brief Set the PDBIF field to a new value. */
 282 #define BW_PDB_SC_PDBIF(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIF) = (v))
 283 /*@}*/
 284
 285 /*!
 286  * @name Register PDB_SC, field PDBEN[7] (RW)
 287  *
 288  * Values:
 289  * - 0 - PDB disabled. Counter is off.
 290  * - 1 - PDB enabled.
 291  */
 292 /*@{*/
 293 #define BP_PDB_SC_PDBEN      (7U)          /*!< Bit position for PDB_SC_PDBEN. */
 294 #define BM_PDB_SC_PDBEN      (0x00000080U) /*!< Bit mask for PDB_SC_PDBEN. */
 295 #define BS_PDB_SC_PDBEN      (1U)          /*!< Bit field size in bits for PDB_SC_PDBEN. */
 296
 297 /*! @brief Read current value of the PDB_SC_PDBEN field. */
 298 #define BR_PDB_SC_PDBEN(x)   (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEN))
 299
 300 /*! @brief Format value for bitfield PDB_SC_PDBEN. */
 301 #define BF_PDB_SC_PDBEN(v)   ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBEN) & BM_PDB_SC_PDBEN)
 302
 303 /*! @brief Set the PDBEN field to a new value. */
 304 #define BW_PDB_SC_PDBEN(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEN) = (v))
 305 /*@}*/
 306
 307 /*!
 308  * @name Register PDB_SC, field TRGSEL[11:8] (RW)
 309  *
 310  * Selects the trigger input source for the PDB. The trigger input source can be
 311  * internal or external (EXTRG pin), or the software trigger. Refer to chip
 312  * configuration details for the actual PDB input trigger connections.
 313  *
 314  * Values:
 315  * - 0000 - Trigger-In 0 is selected.
 316  * - 0001 - Trigger-In 1 is selected.
 317  * - 0010 - Trigger-In 2 is selected.
 318  * - 0011 - Trigger-In 3 is selected.
 319  * - 0100 - Trigger-In 4 is selected.
 320  * - 0101 - Trigger-In 5 is selected.
 321  * - 0110 - Trigger-In 6 is selected.
 322  * - 0111 - Trigger-In 7 is selected.
 323  * - 1000 - Trigger-In 8 is selected.
 324  * - 1001 - Trigger-In 9 is selected.
 325  * - 1010 - Trigger-In 10 is selected.
 326  * - 1011 - Trigger-In 11 is selected.
 327  * - 1100 - Trigger-In 12 is selected.
 328  * - 1101 - Trigger-In 13 is selected.
 329  * - 1110 - Trigger-In 14 is selected.
 330  * - 1111 - Software trigger is selected.
 331  */
 332 /*@{*/
 333 #define BP_PDB_SC_TRGSEL     (8U)          /*!< Bit position for PDB_SC_TRGSEL. */
 334 #define BM_PDB_SC_TRGSEL     (0x00000F00U) /*!< Bit mask for PDB_SC_TRGSEL. */
 335 #define BS_PDB_SC_TRGSEL     (4U)          /*!< Bit field size in bits for PDB_SC_TRGSEL. */
 336
 337 /*! @brief Read current value of the PDB_SC_TRGSEL field. */
 338 #define BR_PDB_SC_TRGSEL(x)  (HW_PDB_SC(x).B.TRGSEL)
 339
 340 /*! @brief Format value for bitfield PDB_SC_TRGSEL. */
 341 #define BF_PDB_SC_TRGSEL(v)  ((uint32_t)((uint32_t)(v) << BP_PDB_SC_TRGSEL) & BM_PDB_SC_TRGSEL)
 342
 343 /*! @brief Set the TRGSEL field to a new value. */
 344 #define BW_PDB_SC_TRGSEL(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_TRGSEL) | BF_PDB_SC_TRGSEL(v)))
 345 /*@}*/
 346
 347 /*!
 348  * @name Register PDB_SC, field PRESCALER[14:12] (RW)
 349  *
 350  * Values:
 351  * - 000 - Counting uses the peripheral clock divided by multiplication factor
 352  *     selected by MULT.
 353  * - 001 - Counting uses the peripheral clock divided by twice of the
 354  *     multiplication factor selected by MULT.
 355  * - 010 - Counting uses the peripheral clock divided by four times of the
 356  *     multiplication factor selected by MULT.
 357  * - 011 - Counting uses the peripheral clock divided by eight times of the
 358  *     multiplication factor selected by MULT.
 359  * - 100 - Counting uses the peripheral clock divided by 16 times of the
 360  *     multiplication factor selected by MULT.
 361  * - 101 - Counting uses the peripheral clock divided by 32 times of the
 362  *     multiplication factor selected by MULT.
 363  * - 110 - Counting uses the peripheral clock divided by 64 times of the
 364  *     multiplication factor selected by MULT.
 365  * - 111 - Counting uses the peripheral clock divided by 128 times of the
 366  *     multiplication factor selected by MULT.
 367  */
 368 /*@{*/
 369 #define BP_PDB_SC_PRESCALER  (12U)         /*!< Bit position for PDB_SC_PRESCALER. */
 370 #define BM_PDB_SC_PRESCALER  (0x00007000U) /*!< Bit mask for PDB_SC_PRESCALER. */
 371 #define BS_PDB_SC_PRESCALER  (3U)          /*!< Bit field size in bits for PDB_SC_PRESCALER. */
 372
 373 /*! @brief Read current value of the PDB_SC_PRESCALER field. */
 374 #define BR_PDB_SC_PRESCALER(x) (HW_PDB_SC(x).B.PRESCALER)
 375
 376 /*! @brief Format value for bitfield PDB_SC_PRESCALER. */
 377 #define BF_PDB_SC_PRESCALER(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PRESCALER) & BM_PDB_SC_PRESCALER)
 378
 379 /*! @brief Set the PRESCALER field to a new value. */
 380 #define BW_PDB_SC_PRESCALER(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_PRESCALER) | BF_PDB_SC_PRESCALER(v)))
 381 /*@}*/
 382
 383 /*!
 384  * @name Register PDB_SC, field DMAEN[15] (RW)
 385  *
 386  * When DMA is enabled, the PDBIF flag generates a DMA request instead of an
 387  * interrupt.
 388  *
 389  * Values:
 390  * - 0 - DMA disabled.
 391  * - 1 - DMA enabled.
 392  */
 393 /*@{*/
 394 #define BP_PDB_SC_DMAEN      (15U)         /*!< Bit position for PDB_SC_DMAEN. */
 395 #define BM_PDB_SC_DMAEN      (0x00008000U) /*!< Bit mask for PDB_SC_DMAEN. */
 396 #define BS_PDB_SC_DMAEN      (1U)          /*!< Bit field size in bits for PDB_SC_DMAEN. */
 397
 398 /*! @brief Read current value of the PDB_SC_DMAEN field. */
 399 #define BR_PDB_SC_DMAEN(x)   (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_DMAEN))
 400
 401 /*! @brief Format value for bitfield PDB_SC_DMAEN. */
 402 #define BF_PDB_SC_DMAEN(v)   ((uint32_t)((uint32_t)(v) << BP_PDB_SC_DMAEN) & BM_PDB_SC_DMAEN)
 403
 404 /*! @brief Set the DMAEN field to a new value. */
 405 #define BW_PDB_SC_DMAEN(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_DMAEN) = (v))
 406 /*@}*/
 407
 408 /*!
 409  * @name Register PDB_SC, field SWTRIG[16] (WORZ)
 410  *
 411  * When PDB is enabled and the software trigger is selected as the trigger input
 412  * source, writing 1 to this field resets and restarts the counter. Writing 0 to
 413  * this field has no effect. Reading this field results 0.
 414  */
 415 /*@{*/
 416 #define BP_PDB_SC_SWTRIG     (16U)         /*!< Bit position for PDB_SC_SWTRIG. */
 417 #define BM_PDB_SC_SWTRIG     (0x00010000U) /*!< Bit mask for PDB_SC_SWTRIG. */
 418 #define BS_PDB_SC_SWTRIG     (1U)          /*!< Bit field size in bits for PDB_SC_SWTRIG. */
 419
 420 /*! @brief Format value for bitfield PDB_SC_SWTRIG. */
 421 #define BF_PDB_SC_SWTRIG(v)  ((uint32_t)((uint32_t)(v) << BP_PDB_SC_SWTRIG) & BM_PDB_SC_SWTRIG)
 422
 423 /*! @brief Set the SWTRIG field to a new value. */
 424 #define BW_PDB_SC_SWTRIG(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_SWTRIG) = (v))
 425 /*@}*/
 426
 427 /*!
 428  * @name Register PDB_SC, field PDBEIE[17] (RW)
 429  *
 430  * Enables the PDB sequence error interrupt. When this field is set, any of the
 431  * PDB channel sequence error flags generates a PDB sequence error interrupt.
 432  *
 433  * Values:
 434  * - 0 - PDB sequence error interrupt disabled.
 435  * - 1 - PDB sequence error interrupt enabled.
 436  */
 437 /*@{*/
 438 #define BP_PDB_SC_PDBEIE     (17U)         /*!< Bit position for PDB_SC_PDBEIE. */
 439 #define BM_PDB_SC_PDBEIE     (0x00020000U) /*!< Bit mask for PDB_SC_PDBEIE. */
 440 #define BS_PDB_SC_PDBEIE     (1U)          /*!< Bit field size in bits for PDB_SC_PDBEIE. */
 441
 442 /*! @brief Read current value of the PDB_SC_PDBEIE field. */
 443 #define BR_PDB_SC_PDBEIE(x)  (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEIE))
 444
 445 /*! @brief Format value for bitfield PDB_SC_PDBEIE. */
 446 #define BF_PDB_SC_PDBEIE(v)  ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBEIE) & BM_PDB_SC_PDBEIE)
 447
 448 /*! @brief Set the PDBEIE field to a new value. */
 449 #define BW_PDB_SC_PDBEIE(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEIE) = (v))
 450 /*@}*/
 451
 452 /*!
 453  * @name Register PDB_SC, field LDMOD[19:18] (RW)
 454  *
 455  * Selects the mode to load the MOD, IDLY, CHnDLYm, INTx, and POyDLY registers,
 456  * after 1 is written to LDOK.
 457  *
 458  * Values:
 459  * - 00 - The internal registers are loaded with the values from their buffers
 460  *     immediately after 1 is written to LDOK.
 461  * - 01 - The internal registers are loaded with the values from their buffers
 462  *     when the PDB counter reaches the MOD register value after 1 is written to
 463  *     LDOK.
 464  * - 10 - The internal registers are loaded with the values from their buffers
 465  *     when a trigger input event is detected after 1 is written to LDOK.
 466  * - 11 - The internal registers are loaded with the values from their buffers
 467  *     when either the PDB counter reaches the MOD register value or a trigger
 468  *     input event is detected, after 1 is written to LDOK.
 469  */
 470 /*@{*/
 471 #define BP_PDB_SC_LDMOD      (18U)         /*!< Bit position for PDB_SC_LDMOD. */
 472 #define BM_PDB_SC_LDMOD      (0x000C0000U) /*!< Bit mask for PDB_SC_LDMOD. */
 473 #define BS_PDB_SC_LDMOD      (2U)          /*!< Bit field size in bits for PDB_SC_LDMOD. */
 474
 475 /*! @brief Read current value of the PDB_SC_LDMOD field. */
 476 #define BR_PDB_SC_LDMOD(x)   (HW_PDB_SC(x).B.LDMOD)
 477
 478 /*! @brief Format value for bitfield PDB_SC_LDMOD. */
 479 #define BF_PDB_SC_LDMOD(v)   ((uint32_t)((uint32_t)(v) << BP_PDB_SC_LDMOD) & BM_PDB_SC_LDMOD)
 480
 481 /*! @brief Set the LDMOD field to a new value. */
 482 #define BW_PDB_SC_LDMOD(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_LDMOD) | BF_PDB_SC_LDMOD(v)))
 483 /*@}*/
 484
 485 /*******************************************************************************
 486  * HW_PDB_MOD - Modulus register
 487  ******************************************************************************/
 488
 489 /*!
 490  * @brief HW_PDB_MOD - Modulus register (RW)
 491  *
 492  * Reset value: 0x0000FFFFU
 493  */
 494 typedef union _hw_pdb_mod
 495 {
 496     uint32_t U;
 497     struct _hw_pdb_mod_bitfields
 498     {
 499         uint32_t MOD : 16;             /*!< [15:0] PDB Modulus */
 500         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
 501     } B;
 502 } hw_pdb_mod_t;
 503
 504 /*!
 505  * @name Constants and macros for entire PDB_MOD register
 506  */
 507 /*@{*/
 508 #define HW_PDB_MOD_ADDR(x)       ((x) + 0x4U)
 509
 510 #define HW_PDB_MOD(x)            (*(__IO hw_pdb_mod_t *) HW_PDB_MOD_ADDR(x))
 511 #define HW_PDB_MOD_RD(x)         (HW_PDB_MOD(x).U)
 512 #define HW_PDB_MOD_WR(x, v)      (HW_PDB_MOD(x).U = (v))
 513 #define HW_PDB_MOD_SET(x, v)     (HW_PDB_MOD_WR(x, HW_PDB_MOD_RD(x) |  (v)))
 514 #define HW_PDB_MOD_CLR(x, v)     (HW_PDB_MOD_WR(x, HW_PDB_MOD_RD(x) & ~(v)))
 515 #define HW_PDB_MOD_TOG(x, v)     (HW_PDB_MOD_WR(x, HW_PDB_MOD_RD(x) ^  (v)))
 516 /*@}*/
 517
 518 /*
 519  * Constants & macros for individual PDB_MOD bitfields
 520  */
 521
 522 /*!
 523  * @name Register PDB_MOD, field MOD[15:0] (RW)
 524  *
 525  * Specifies the period of the counter. When the counter reaches this value, it
 526  * will be reset back to zero. If the PDB is in Continuous mode, the count begins
 527  * anew. Reading this field returns the value of the internal register that is
 528  * effective for the current cycle of PDB.
 529  */
 530 /*@{*/
 531 #define BP_PDB_MOD_MOD       (0U)          /*!< Bit position for PDB_MOD_MOD. */
 532 #define BM_PDB_MOD_MOD       (0x0000FFFFU) /*!< Bit mask for PDB_MOD_MOD. */
 533 #define BS_PDB_MOD_MOD       (16U)         /*!< Bit field size in bits for PDB_MOD_MOD. */
 534
 535 /*! @brief Read current value of the PDB_MOD_MOD field. */
 536 #define BR_PDB_MOD_MOD(x)    (HW_PDB_MOD(x).B.MOD)
 537
 538 /*! @brief Format value for bitfield PDB_MOD_MOD. */
 539 #define BF_PDB_MOD_MOD(v)    ((uint32_t)((uint32_t)(v) << BP_PDB_MOD_MOD) & BM_PDB_MOD_MOD)
 540
 541 /*! @brief Set the MOD field to a new value. */
 542 #define BW_PDB_MOD_MOD(x, v) (HW_PDB_MOD_WR(x, (HW_PDB_MOD_RD(x) & ~BM_PDB_MOD_MOD) | BF_PDB_MOD_MOD(v)))
 543 /*@}*/
 544
 545 /*******************************************************************************
 546  * HW_PDB_CNT - Counter register
 547  ******************************************************************************/
 548
 549 /*!
 550  * @brief HW_PDB_CNT - Counter register (RO)
 551  *
 552  * Reset value: 0x00000000U
 553  */
 554 typedef union _hw_pdb_cnt
 555 {
 556     uint32_t U;
 557     struct _hw_pdb_cnt_bitfields
 558     {
 559         uint32_t CNT : 16;             /*!< [15:0] PDB Counter */
 560         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
 561     } B;
 562 } hw_pdb_cnt_t;
 563
 564 /*!
 565  * @name Constants and macros for entire PDB_CNT register
 566  */
 567 /*@{*/
 568 #define HW_PDB_CNT_ADDR(x)       ((x) + 0x8U)
 569
 570 #define HW_PDB_CNT(x)            (*(__I hw_pdb_cnt_t *) HW_PDB_CNT_ADDR(x))
 571 #define HW_PDB_CNT_RD(x)         (HW_PDB_CNT(x).U)
 572 /*@}*/
 573
 574 /*
 575  * Constants & macros for individual PDB_CNT bitfields
 576  */
 577
 578 /*!
 579  * @name Register PDB_CNT, field CNT[15:0] (RO)
 580  *
 581  * Contains the current value of the counter.
 582  */
 583 /*@{*/
 584 #define BP_PDB_CNT_CNT       (0U)          /*!< Bit position for PDB_CNT_CNT. */
 585 #define BM_PDB_CNT_CNT       (0x0000FFFFU) /*!< Bit mask for PDB_CNT_CNT. */
 586 #define BS_PDB_CNT_CNT       (16U)         /*!< Bit field size in bits for PDB_CNT_CNT. */
 587
 588 /*! @brief Read current value of the PDB_CNT_CNT field. */
 589 #define BR_PDB_CNT_CNT(x)    (HW_PDB_CNT(x).B.CNT)
 590 /*@}*/
 591
 592 /*******************************************************************************
 593  * HW_PDB_IDLY - Interrupt Delay register
 594  ******************************************************************************/
 595
 596 /*!
 597  * @brief HW_PDB_IDLY - Interrupt Delay register (RW)
 598  *
 599  * Reset value: 0x0000FFFFU
 600  */
 601 typedef union _hw_pdb_idly
 602 {
 603     uint32_t U;
 604     struct _hw_pdb_idly_bitfields
 605     {
 606         uint32_t IDLY : 16;            /*!< [15:0] PDB Interrupt Delay */
 607         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
 608     } B;
 609 } hw_pdb_idly_t;
 610
 611 /*!
 612  * @name Constants and macros for entire PDB_IDLY register
 613  */
 614 /*@{*/
 615 #define HW_PDB_IDLY_ADDR(x)      ((x) + 0xCU)
 616
 617 #define HW_PDB_IDLY(x)           (*(__IO hw_pdb_idly_t *) HW_PDB_IDLY_ADDR(x))
 618 #define HW_PDB_IDLY_RD(x)        (HW_PDB_IDLY(x).U)
 619 #define HW_PDB_IDLY_WR(x, v)     (HW_PDB_IDLY(x).U = (v))
 620 #define HW_PDB_IDLY_SET(x, v)    (HW_PDB_IDLY_WR(x, HW_PDB_IDLY_RD(x) |  (v)))
 621 #define HW_PDB_IDLY_CLR(x, v)    (HW_PDB_IDLY_WR(x, HW_PDB_IDLY_RD(x) & ~(v)))
 622 #define HW_PDB_IDLY_TOG(x, v)    (HW_PDB_IDLY_WR(x, HW_PDB_IDLY_RD(x) ^  (v)))
 623 /*@}*/
 624
 625 /*
 626  * Constants & macros for individual PDB_IDLY bitfields
 627  */
 628
 629 /*!
 630  * @name Register PDB_IDLY, field IDLY[15:0] (RW)
 631  *
 632  * Specifies the delay value to schedule the PDB interrupt. It can be used to
 633  * schedule an independent interrupt at some point in the PDB cycle. If enabled, a
 634  * PDB interrupt is generated, when the counter is equal to the IDLY. Reading
 635  * this field returns the value of internal register that is effective for the
 636  * current cycle of the PDB.
 637  */
 638 /*@{*/
 639 #define BP_PDB_IDLY_IDLY     (0U)          /*!< Bit position for PDB_IDLY_IDLY. */
 640 #define BM_PDB_IDLY_IDLY     (0x0000FFFFU) /*!< Bit mask for PDB_IDLY_IDLY. */
 641 #define BS_PDB_IDLY_IDLY     (16U)         /*!< Bit field size in bits for PDB_IDLY_IDLY. */
 642
 643 /*! @brief Read current value of the PDB_IDLY_IDLY field. */
 644 #define BR_PDB_IDLY_IDLY(x)  (HW_PDB_IDLY(x).B.IDLY)
 645
 646 /*! @brief Format value for bitfield PDB_IDLY_IDLY. */
 647 #define BF_PDB_IDLY_IDLY(v)  ((uint32_t)((uint32_t)(v) << BP_PDB_IDLY_IDLY) & BM_PDB_IDLY_IDLY)
 648
 649 /*! @brief Set the IDLY field to a new value. */
 650 #define BW_PDB_IDLY_IDLY(x, v) (HW_PDB_IDLY_WR(x, (HW_PDB_IDLY_RD(x) & ~BM_PDB_IDLY_IDLY) | BF_PDB_IDLY_IDLY(v)))
 651 /*@}*/
 652
 653 /*******************************************************************************
 654  * HW_PDB_CHnC1 - Channel n Control register 1
 655  ******************************************************************************/
 656
 657 /*!
 658  * @brief HW_PDB_CHnC1 - Channel n Control register 1 (RW)
 659  *
 660  * Reset value: 0x00000000U
 661  *
 662  * Each PDB channel has one control register, CHnC1. The bits in this register
 663  * control the functionality of each PDB channel operation.
 664  */
 665 typedef union _hw_pdb_chnc1
 666 {
 667     uint32_t U;
 668     struct _hw_pdb_chnc1_bitfields
 669     {
 670         uint32_t EN : 8;               /*!< [7:0] PDB Channel Pre-Trigger Enable */
 671         uint32_t TOS : 8;              /*!< [15:8] PDB Channel Pre-Trigger Output Select */
 672         uint32_t BB : 8;               /*!< [23:16] PDB Channel Pre-Trigger Back-to-Back
 673                                         * Operation Enable */
 674         uint32_t RESERVED0 : 8;        /*!< [31:24]  */
 675     } B;
 676 } hw_pdb_chnc1_t;
 677
 678 /*!
 679  * @name Constants and macros for entire PDB_CHnC1 register
 680  */
 681 /*@{*/
 682 #define HW_PDB_CHnC1_COUNT (2U)
 683
 684 #define HW_PDB_CHnC1_ADDR(x, n)  ((x) + 0x10U + (0x28U * (n)))
 685
 686 #define HW_PDB_CHnC1(x, n)       (*(__IO hw_pdb_chnc1_t *) HW_PDB_CHnC1_ADDR(x, n))
 687 #define HW_PDB_CHnC1_RD(x, n)    (HW_PDB_CHnC1(x, n).U)
 688 #define HW_PDB_CHnC1_WR(x, n, v) (HW_PDB_CHnC1(x, n).U = (v))
 689 #define HW_PDB_CHnC1_SET(x, n, v) (HW_PDB_CHnC1_WR(x, n, HW_PDB_CHnC1_RD(x, n) |  (v)))
 690 #define HW_PDB_CHnC1_CLR(x, n, v) (HW_PDB_CHnC1_WR(x, n, HW_PDB_CHnC1_RD(x, n) & ~(v)))
 691 #define HW_PDB_CHnC1_TOG(x, n, v) (HW_PDB_CHnC1_WR(x, n, HW_PDB_CHnC1_RD(x, n) ^  (v)))
 692 /*@}*/
 693
 694 /*
 695  * Constants & macros for individual PDB_CHnC1 bitfields
 696  */
 697
 698 /*!
 699  * @name Register PDB_CHnC1, field EN[7:0] (RW)
 700  *
 701  * These bits enable the PDB ADC pre-trigger outputs. Only lower M pre-trigger
 702  * bits are implemented in this MCU.
 703  *
 704  * Values:
 705  * - 0 - PDB channel's corresponding pre-trigger disabled.
 706  * - 1 - PDB channel's corresponding pre-trigger enabled.
 707  */
 708 /*@{*/
 709 #define BP_PDB_CHnC1_EN      (0U)          /*!< Bit position for PDB_CHnC1_EN. */
 710 #define BM_PDB_CHnC1_EN      (0x000000FFU) /*!< Bit mask for PDB_CHnC1_EN. */
 711 #define BS_PDB_CHnC1_EN      (8U)          /*!< Bit field size in bits for PDB_CHnC1_EN. */
 712
 713 /*! @brief Read current value of the PDB_CHnC1_EN field. */
 714 #define BR_PDB_CHnC1_EN(x, n) (HW_PDB_CHnC1(x, n).B.EN)
 715
 716 /*! @brief Format value for bitfield PDB_CHnC1_EN. */
 717 #define BF_PDB_CHnC1_EN(v)   ((uint32_t)((uint32_t)(v) << BP_PDB_CHnC1_EN) & BM_PDB_CHnC1_EN)
 718
 719 /*! @brief Set the EN field to a new value. */
 720 #define BW_PDB_CHnC1_EN(x, n, v) (HW_PDB_CHnC1_WR(x, n, (HW_PDB_CHnC1_RD(x, n) & ~BM_PDB_CHnC1_EN) | BF_PDB_CHnC1_EN(v)))
 721 /*@}*/
 722
 723 /*!
 724  * @name Register PDB_CHnC1, field TOS[15:8] (RW)
 725  *
 726  * Selects the PDB ADC pre-trigger outputs. Only lower M pre-trigger fields are
 727  * implemented in this MCU.
 728  *
 729  * Values:
 730  * - 0 - PDB channel's corresponding pre-trigger is in bypassed mode. The
 731  *     pre-trigger asserts one peripheral clock cycle after a rising edge is detected
 732  *     on selected trigger input source or software trigger is selected and SWTRIG
 733  *     is written with 1.
 734  * - 1 - PDB channel's corresponding pre-trigger asserts when the counter
 735  *     reaches the channel delay register and one peripheral clock cycle after a rising
 736  *     edge is detected on selected trigger input source or software trigger is
 737  *     selected and SETRIG is written with 1.
 738  */
 739 /*@{*/
 740 #define BP_PDB_CHnC1_TOS     (8U)          /*!< Bit position for PDB_CHnC1_TOS. */
 741 #define BM_PDB_CHnC1_TOS     (0x0000FF00U) /*!< Bit mask for PDB_CHnC1_TOS. */
 742 #define BS_PDB_CHnC1_TOS     (8U)          /*!< Bit field size in bits for PDB_CHnC1_TOS. */
 743
 744 /*! @brief Read current value of the PDB_CHnC1_TOS field. */
 745 #define BR_PDB_CHnC1_TOS(x, n) (HW_PDB_CHnC1(x, n).B.TOS)
 746
 747 /*! @brief Format value for bitfield PDB_CHnC1_TOS. */
 748 #define BF_PDB_CHnC1_TOS(v)  ((uint32_t)((uint32_t)(v) << BP_PDB_CHnC1_TOS) & BM_PDB_CHnC1_TOS)
 749
 750 /*! @brief Set the TOS field to a new value. */
 751 #define BW_PDB_CHnC1_TOS(x, n, v) (HW_PDB_CHnC1_WR(x, n, (HW_PDB_CHnC1_RD(x, n) & ~BM_PDB_CHnC1_TOS) | BF_PDB_CHnC1_TOS(v)))
 752 /*@}*/
 753
 754 /*!
 755  * @name Register PDB_CHnC1, field BB[23:16] (RW)
 756  *
 757  * These bits enable the PDB ADC pre-trigger operation as back-to-back mode.
 758  * Only lower M pre-trigger bits are implemented in this MCU. Back-to-back operation
 759  * enables the ADC conversions complete to trigger the next PDB channel
 760  * pre-trigger and trigger output, so that the ADC conversions can be triggered on next
 761  * set of configuration and results registers. Application code must only enable
 762  * the back-to-back operation of the PDB pre-triggers at the leading of the
 763  * back-to-back connection chain.
 764  *
 765  * Values:
 766  * - 0 - PDB channel's corresponding pre-trigger back-to-back operation disabled.
 767  * - 1 - PDB channel's corresponding pre-trigger back-to-back operation enabled.
 768  */
 769 /*@{*/
 770 #define BP_PDB_CHnC1_BB      (16U)         /*!< Bit position for PDB_CHnC1_BB. */
 771 #define BM_PDB_CHnC1_BB      (0x00FF0000U) /*!< Bit mask for PDB_CHnC1_BB. */
 772 #define BS_PDB_CHnC1_BB      (8U)          /*!< Bit field size in bits for PDB_CHnC1_BB. */
 773
 774 /*! @brief Read current value of the PDB_CHnC1_BB field. */
 775 #define BR_PDB_CHnC1_BB(x, n) (HW_PDB_CHnC1(x, n).B.BB)
 776
 777 /*! @brief Format value for bitfield PDB_CHnC1_BB. */
 778 #define BF_PDB_CHnC1_BB(v)   ((uint32_t)((uint32_t)(v) << BP_PDB_CHnC1_BB) & BM_PDB_CHnC1_BB)
 779
 780 /*! @brief Set the BB field to a new value. */
 781 #define BW_PDB_CHnC1_BB(x, n, v) (HW_PDB_CHnC1_WR(x, n, (HW_PDB_CHnC1_RD(x, n) & ~BM_PDB_CHnC1_BB) | BF_PDB_CHnC1_BB(v)))
 782 /*@}*/
 783 /*******************************************************************************
 784  * HW_PDB_CHnS - Channel n Status register
 785  ******************************************************************************/
 786
 787 /*!
 788  * @brief HW_PDB_CHnS - Channel n Status register (RW)
 789  *
 790  * Reset value: 0x00000000U
 791  */
 792 typedef union _hw_pdb_chns
 793 {
 794     uint32_t U;
 795     struct _hw_pdb_chns_bitfields
 796     {
 797         uint32_t ERR : 8;              /*!< [7:0] PDB Channel Sequence Error Flags */
 798         uint32_t RESERVED0 : 8;        /*!< [15:8]  */
 799         uint32_t CF : 8;               /*!< [23:16] PDB Channel Flags */
 800         uint32_t RESERVED1 : 8;        /*!< [31:24]  */
 801     } B;
 802 } hw_pdb_chns_t;
 803
 804 /*!
 805  * @name Constants and macros for entire PDB_CHnS register
 806  */
 807 /*@{*/
 808 #define HW_PDB_CHnS_COUNT (2U)
 809
 810 #define HW_PDB_CHnS_ADDR(x, n)   ((x) + 0x14U + (0x28U * (n)))
 811
 812 #define HW_PDB_CHnS(x, n)        (*(__IO hw_pdb_chns_t *) HW_PDB_CHnS_ADDR(x, n))
 813 #define HW_PDB_CHnS_RD(x, n)     (HW_PDB_CHnS(x, n).U)
 814 #define HW_PDB_CHnS_WR(x, n, v)  (HW_PDB_CHnS(x, n).U = (v))
 815 #define HW_PDB_CHnS_SET(x, n, v) (HW_PDB_CHnS_WR(x, n, HW_PDB_CHnS_RD(x, n) |  (v)))
 816 #define HW_PDB_CHnS_CLR(x, n, v) (HW_PDB_CHnS_WR(x, n, HW_PDB_CHnS_RD(x, n) & ~(v)))
 817 #define HW_PDB_CHnS_TOG(x, n, v) (HW_PDB_CHnS_WR(x, n, HW_PDB_CHnS_RD(x, n) ^  (v)))
 818 /*@}*/
 819
 820 /*
 821  * Constants & macros for individual PDB_CHnS bitfields
 822  */
 823
 824 /*!
 825  * @name Register PDB_CHnS, field ERR[7:0] (RW)
 826  *
 827  * Only the lower M bits are implemented in this MCU.
 828  *
 829  * Values:
 830  * - 0 - Sequence error not detected on PDB channel's corresponding pre-trigger.
 831  * - 1 - Sequence error detected on PDB channel's corresponding pre-trigger.
 832  *     ADCn block can be triggered for a conversion by one pre-trigger from PDB
 833  *     channel n. When one conversion, which is triggered by one of the pre-triggers
 834  *     from PDB channel n, is in progress, new trigger from PDB channel's
 835  *     corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set.
 836  *     Writing 0's to clear the sequence error flags.
 837  */
 838 /*@{*/
 839 #define BP_PDB_CHnS_ERR      (0U)          /*!< Bit position for PDB_CHnS_ERR. */
 840 #define BM_PDB_CHnS_ERR      (0x000000FFU) /*!< Bit mask for PDB_CHnS_ERR. */
 841 #define BS_PDB_CHnS_ERR      (8U)          /*!< Bit field size in bits for PDB_CHnS_ERR. */
 842
 843 /*! @brief Read current value of the PDB_CHnS_ERR field. */
 844 #define BR_PDB_CHnS_ERR(x, n) (HW_PDB_CHnS(x, n).B.ERR)
 845
 846 /*! @brief Format value for bitfield PDB_CHnS_ERR. */
 847 #define BF_PDB_CHnS_ERR(v)   ((uint32_t)((uint32_t)(v) << BP_PDB_CHnS_ERR) & BM_PDB_CHnS_ERR)
 848
 849 /*! @brief Set the ERR field to a new value. */
 850 #define BW_PDB_CHnS_ERR(x, n, v) (HW_PDB_CHnS_WR(x, n, (HW_PDB_CHnS_RD(x, n) & ~BM_PDB_CHnS_ERR) | BF_PDB_CHnS_ERR(v)))
 851 /*@}*/
 852
 853 /*!
 854  * @name Register PDB_CHnS, field CF[23:16] (RW)
 855  *
 856  * The CF[m] bit is set when the PDB counter matches the CHnDLYm. Write 0 to
 857  * clear these bits.
 858  */
 859 /*@{*/
 860 #define BP_PDB_CHnS_CF       (16U)         /*!< Bit position for PDB_CHnS_CF. */
 861 #define BM_PDB_CHnS_CF       (0x00FF0000U) /*!< Bit mask for PDB_CHnS_CF. */
 862 #define BS_PDB_CHnS_CF       (8U)          /*!< Bit field size in bits for PDB_CHnS_CF. */
 863
 864 /*! @brief Read current value of the PDB_CHnS_CF field. */
 865 #define BR_PDB_CHnS_CF(x, n) (HW_PDB_CHnS(x, n).B.CF)
 866
 867 /*! @brief Format value for bitfield PDB_CHnS_CF. */
 868 #define BF_PDB_CHnS_CF(v)    ((uint32_t)((uint32_t)(v) << BP_PDB_CHnS_CF) & BM_PDB_CHnS_CF)
 869
 870 /*! @brief Set the CF field to a new value. */
 871 #define BW_PDB_CHnS_CF(x, n, v) (HW_PDB_CHnS_WR(x, n, (HW_PDB_CHnS_RD(x, n) & ~BM_PDB_CHnS_CF) | BF_PDB_CHnS_CF(v)))
 872 /*@}*/
 873 /*******************************************************************************
 874  * HW_PDB_CHnDLY0 - Channel n Delay 0 register
 875  ******************************************************************************/
 876
 877 /*!
 878  * @brief HW_PDB_CHnDLY0 - Channel n Delay 0 register (RW)
 879  *
 880  * Reset value: 0x00000000U
 881  */
 882 typedef union _hw_pdb_chndly0
 883 {
 884     uint32_t U;
 885     struct _hw_pdb_chndly0_bitfields
 886     {
 887         uint32_t DLY : 16;             /*!< [15:0] PDB Channel Delay */
 888         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
 889     } B;
 890 } hw_pdb_chndly0_t;
 891
 892 /*!
 893  * @name Constants and macros for entire PDB_CHnDLY0 register
 894  */
 895 /*@{*/
 896 #define HW_PDB_CHnDLY0_COUNT (2U)
 897
 898 #define HW_PDB_CHnDLY0_ADDR(x, n) ((x) + 0x18U + (0x28U * (n)))
 899
 900 #define HW_PDB_CHnDLY0(x, n)     (*(__IO hw_pdb_chndly0_t *) HW_PDB_CHnDLY0_ADDR(x, n))
 901 #define HW_PDB_CHnDLY0_RD(x, n)  (HW_PDB_CHnDLY0(x, n).U)
 902 #define HW_PDB_CHnDLY0_WR(x, n, v) (HW_PDB_CHnDLY0(x, n).U = (v))
 903 #define HW_PDB_CHnDLY0_SET(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, HW_PDB_CHnDLY0_RD(x, n) |  (v)))
 904 #define HW_PDB_CHnDLY0_CLR(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, HW_PDB_CHnDLY0_RD(x, n) & ~(v)))
 905 #define HW_PDB_CHnDLY0_TOG(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, HW_PDB_CHnDLY0_RD(x, n) ^  (v)))
 906 /*@}*/
 907
 908 /*
 909  * Constants & macros for individual PDB_CHnDLY0 bitfields
 910  */
 911
 912 /*!
 913  * @name Register PDB_CHnDLY0, field DLY[15:0] (RW)
 914  *
 915  * Specifies the delay value for the channel's corresponding pre-trigger. The
 916  * pre-trigger asserts when the counter is equal to DLY. Reading this field returns
 917  * the value of internal register that is effective for the current PDB cycle.
 918  */
 919 /*@{*/
 920 #define BP_PDB_CHnDLY0_DLY   (0U)          /*!< Bit position for PDB_CHnDLY0_DLY. */
 921 #define BM_PDB_CHnDLY0_DLY   (0x0000FFFFU) /*!< Bit mask for PDB_CHnDLY0_DLY. */
 922 #define BS_PDB_CHnDLY0_DLY   (16U)         /*!< Bit field size in bits for PDB_CHnDLY0_DLY. */
 923
 924 /*! @brief Read current value of the PDB_CHnDLY0_DLY field. */
 925 #define BR_PDB_CHnDLY0_DLY(x, n) (HW_PDB_CHnDLY0(x, n).B.DLY)
 926
 927 /*! @brief Format value for bitfield PDB_CHnDLY0_DLY. */
 928 #define BF_PDB_CHnDLY0_DLY(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnDLY0_DLY) & BM_PDB_CHnDLY0_DLY)
 929
 930 /*! @brief Set the DLY field to a new value. */
 931 #define BW_PDB_CHnDLY0_DLY(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, (HW_PDB_CHnDLY0_RD(x, n) & ~BM_PDB_CHnDLY0_DLY) | BF_PDB_CHnDLY0_DLY(v)))
 932 /*@}*/
 933 /*******************************************************************************
 934  * HW_PDB_CHnDLY1 - Channel n Delay 1 register
 935  ******************************************************************************/
 936
 937 /*!
 938  * @brief HW_PDB_CHnDLY1 - Channel n Delay 1 register (RW)
 939  *
 940  * Reset value: 0x00000000U
 941  */
 942 typedef union _hw_pdb_chndly1
 943 {
 944     uint32_t U;
 945     struct _hw_pdb_chndly1_bitfields
 946     {
 947         uint32_t DLY : 16;             /*!< [15:0] PDB Channel Delay */
 948         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
 949     } B;
 950 } hw_pdb_chndly1_t;
 951
 952 /*!
 953  * @name Constants and macros for entire PDB_CHnDLY1 register
 954  */
 955 /*@{*/
 956 #define HW_PDB_CHnDLY1_COUNT (2U)
 957
 958 #define HW_PDB_CHnDLY1_ADDR(x, n) ((x) + 0x1CU + (0x28U * (n)))
 959
 960 #define HW_PDB_CHnDLY1(x, n)     (*(__IO hw_pdb_chndly1_t *) HW_PDB_CHnDLY1_ADDR(x, n))
 961 #define HW_PDB_CHnDLY1_RD(x, n)  (HW_PDB_CHnDLY1(x, n).U)
 962 #define HW_PDB_CHnDLY1_WR(x, n, v) (HW_PDB_CHnDLY1(x, n).U = (v))
 963 #define HW_PDB_CHnDLY1_SET(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, HW_PDB_CHnDLY1_RD(x, n) |  (v)))
 964 #define HW_PDB_CHnDLY1_CLR(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, HW_PDB_CHnDLY1_RD(x, n) & ~(v)))
 965 #define HW_PDB_CHnDLY1_TOG(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, HW_PDB_CHnDLY1_RD(x, n) ^  (v)))
 966 /*@}*/
 967
 968 /*
 969  * Constants & macros for individual PDB_CHnDLY1 bitfields
 970  */
 971
 972 /*!
 973  * @name Register PDB_CHnDLY1, field DLY[15:0] (RW)
 974  *
 975  * These bits specify the delay value for the channel's corresponding
 976  * pre-trigger. The pre-trigger asserts when the counter is equal to DLY. Reading these
 977  * bits returns the value of internal register that is effective for the current PDB
 978  * cycle.
 979  */
 980 /*@{*/
 981 #define BP_PDB_CHnDLY1_DLY   (0U)          /*!< Bit position for PDB_CHnDLY1_DLY. */
 982 #define BM_PDB_CHnDLY1_DLY   (0x0000FFFFU) /*!< Bit mask for PDB_CHnDLY1_DLY. */
 983 #define BS_PDB_CHnDLY1_DLY   (16U)         /*!< Bit field size in bits for PDB_CHnDLY1_DLY. */
 984
 985 /*! @brief Read current value of the PDB_CHnDLY1_DLY field. */
 986 #define BR_PDB_CHnDLY1_DLY(x, n) (HW_PDB_CHnDLY1(x, n).B.DLY)
 987
 988 /*! @brief Format value for bitfield PDB_CHnDLY1_DLY. */
 989 #define BF_PDB_CHnDLY1_DLY(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnDLY1_DLY) & BM_PDB_CHnDLY1_DLY)
 990
 991 /*! @brief Set the DLY field to a new value. */
 992 #define BW_PDB_CHnDLY1_DLY(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, (HW_PDB_CHnDLY1_RD(x, n) & ~BM_PDB_CHnDLY1_DLY) | BF_PDB_CHnDLY1_DLY(v)))
 993 /*@}*/
 994
 995 /*******************************************************************************
 996  * HW_PDB_DACINTCn - DAC Interval Trigger n Control register
 997  ******************************************************************************/
 998
 999 /*!
1000  * @brief HW_PDB_DACINTCn - DAC Interval Trigger n Control register (RW)
1001  *
1002  * Reset value: 0x00000000U
1003  */
1004 typedef union _hw_pdb_dacintcn
1005 {
1006     uint32_t U;
1007     struct _hw_pdb_dacintcn_bitfields
1008     {
1009         uint32_t TOE : 1;              /*!< [0] DAC Interval Trigger Enable */
1010         uint32_t EXT : 1;              /*!< [1] DAC External Trigger Input Enable */
1011         uint32_t RESERVED0 : 30;       /*!< [31:2]  */
1012     } B;
1013 } hw_pdb_dacintcn_t;
1014
1015 /*!
1016  * @name Constants and macros for entire PDB_DACINTCn register
1017  */
1018 /*@{*/
1019 #define HW_PDB_DACINTCn_COUNT (2U)
1020
1021 #define HW_PDB_DACINTCn_ADDR(x, n) ((x) + 0x150U + (0x8U * (n)))
1022
1023 #define HW_PDB_DACINTCn(x, n)    (*(__IO hw_pdb_dacintcn_t *) HW_PDB_DACINTCn_ADDR(x, n))
1024 #define HW_PDB_DACINTCn_RD(x, n) (HW_PDB_DACINTCn(x, n).U)
1025 #define HW_PDB_DACINTCn_WR(x, n, v) (HW_PDB_DACINTCn(x, n).U = (v))
1026 #define HW_PDB_DACINTCn_SET(x, n, v) (HW_PDB_DACINTCn_WR(x, n, HW_PDB_DACINTCn_RD(x, n) |  (v)))
1027 #define HW_PDB_DACINTCn_CLR(x, n, v) (HW_PDB_DACINTCn_WR(x, n, HW_PDB_DACINTCn_RD(x, n) & ~(v)))
1028 #define HW_PDB_DACINTCn_TOG(x, n, v) (HW_PDB_DACINTCn_WR(x, n, HW_PDB_DACINTCn_RD(x, n) ^  (v)))
1029 /*@}*/
1030
1031 /*
1032  * Constants & macros for individual PDB_DACINTCn bitfields
1033  */
1034
1035 /*!
1036  * @name Register PDB_DACINTCn, field TOE[0] (RW)
1037  *
1038  * This bit enables the DAC interval trigger.
1039  *
1040  * Values:
1041  * - 0 - DAC interval trigger disabled.
1042  * - 1 - DAC interval trigger enabled.
1043  */
1044 /*@{*/
1045 #define BP_PDB_DACINTCn_TOE  (0U)          /*!< Bit position for PDB_DACINTCn_TOE. */
1046 #define BM_PDB_DACINTCn_TOE  (0x00000001U) /*!< Bit mask for PDB_DACINTCn_TOE. */
1047 #define BS_PDB_DACINTCn_TOE  (1U)          /*!< Bit field size in bits for PDB_DACINTCn_TOE. */
1048
1049 /*! @brief Read current value of the PDB_DACINTCn_TOE field. */
1050 #define BR_PDB_DACINTCn_TOE(x, n) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_TOE))
1051
1052 /*! @brief Format value for bitfield PDB_DACINTCn_TOE. */
1053 #define BF_PDB_DACINTCn_TOE(v) ((uint32_t)((uint32_t)(v) << BP_PDB_DACINTCn_TOE) & BM_PDB_DACINTCn_TOE)
1054
1055 /*! @brief Set the TOE field to a new value. */
1056 #define BW_PDB_DACINTCn_TOE(x, n, v) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_TOE) = (v))
1057 /*@}*/
1058
1059 /*!
1060  * @name Register PDB_DACINTCn, field EXT[1] (RW)
1061  *
1062  * Enables the external trigger for DAC interval counter.
1063  *
1064  * Values:
1065  * - 0 - DAC external trigger input disabled. DAC interval counter is reset and
1066  *     counting starts when a rising edge is detected on selected trigger input
1067  *     source or software trigger is selected and SWTRIG is written with 1.
1068  * - 1 - DAC external trigger input enabled. DAC interval counter is bypassed
1069  *     and DAC external trigger input triggers the DAC interval trigger.
1070  */
1071 /*@{*/
1072 #define BP_PDB_DACINTCn_EXT  (1U)          /*!< Bit position for PDB_DACINTCn_EXT. */
1073 #define BM_PDB_DACINTCn_EXT  (0x00000002U) /*!< Bit mask for PDB_DACINTCn_EXT. */
1074 #define BS_PDB_DACINTCn_EXT  (1U)          /*!< Bit field size in bits for PDB_DACINTCn_EXT. */
1075
1076 /*! @brief Read current value of the PDB_DACINTCn_EXT field. */
1077 #define BR_PDB_DACINTCn_EXT(x, n) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_EXT))
1078
1079 /*! @brief Format value for bitfield PDB_DACINTCn_EXT. */
1080 #define BF_PDB_DACINTCn_EXT(v) ((uint32_t)((uint32_t)(v) << BP_PDB_DACINTCn_EXT) & BM_PDB_DACINTCn_EXT)
1081
1082 /*! @brief Set the EXT field to a new value. */
1083 #define BW_PDB_DACINTCn_EXT(x, n, v) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_EXT) = (v))
1084 /*@}*/
1085 /*******************************************************************************
1086  * HW_PDB_DACINTn - DAC Interval n register
1087  ******************************************************************************/
1088
1089 /*!
1090  * @brief HW_PDB_DACINTn - DAC Interval n register (RW)
1091  *
1092  * Reset value: 0x00000000U
1093  */
1094 typedef union _hw_pdb_dacintn
1095 {
1096     uint32_t U;
1097     struct _hw_pdb_dacintn_bitfields
1098     {
1099         uint32_t INT : 16;             /*!< [15:0] DAC Interval */
1100         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
1101     } B;
1102 } hw_pdb_dacintn_t;
1103
1104 /*!
1105  * @name Constants and macros for entire PDB_DACINTn register
1106  */
1107 /*@{*/
1108 #define HW_PDB_DACINTn_COUNT (2U)
1109
1110 #define HW_PDB_DACINTn_ADDR(x, n) ((x) + 0x154U + (0x8U * (n)))
1111
1112 #define HW_PDB_DACINTn(x, n)     (*(__IO hw_pdb_dacintn_t *) HW_PDB_DACINTn_ADDR(x, n))
1113 #define HW_PDB_DACINTn_RD(x, n)  (HW_PDB_DACINTn(x, n).U)
1114 #define HW_PDB_DACINTn_WR(x, n, v) (HW_PDB_DACINTn(x, n).U = (v))
1115 #define HW_PDB_DACINTn_SET(x, n, v) (HW_PDB_DACINTn_WR(x, n, HW_PDB_DACINTn_RD(x, n) |  (v)))
1116 #define HW_PDB_DACINTn_CLR(x, n, v) (HW_PDB_DACINTn_WR(x, n, HW_PDB_DACINTn_RD(x, n) & ~(v)))
1117 #define HW_PDB_DACINTn_TOG(x, n, v) (HW_PDB_DACINTn_WR(x, n, HW_PDB_DACINTn_RD(x, n) ^  (v)))
1118 /*@}*/
1119
1120 /*
1121  * Constants & macros for individual PDB_DACINTn bitfields
1122  */
1123
1124 /*!
1125  * @name Register PDB_DACINTn, field INT[15:0] (RW)
1126  *
1127  * Specifies the interval value for DAC interval trigger. DAC interval trigger
1128  * triggers DAC[1:0] update when the DAC interval counter is equal to the DACINT.
1129  * Reading this field returns the value of internal register that is effective
1130  * for the current PDB cycle.
1131  */
1132 /*@{*/
1133 #define BP_PDB_DACINTn_INT   (0U)          /*!< Bit position for PDB_DACINTn_INT. */
1134 #define BM_PDB_DACINTn_INT   (0x0000FFFFU) /*!< Bit mask for PDB_DACINTn_INT. */
1135 #define BS_PDB_DACINTn_INT   (16U)         /*!< Bit field size in bits for PDB_DACINTn_INT. */
1136
1137 /*! @brief Read current value of the PDB_DACINTn_INT field. */
1138 #define BR_PDB_DACINTn_INT(x, n) (HW_PDB_DACINTn(x, n).B.INT)
1139
1140 /*! @brief Format value for bitfield PDB_DACINTn_INT. */
1141 #define BF_PDB_DACINTn_INT(v) ((uint32_t)((uint32_t)(v) << BP_PDB_DACINTn_INT) & BM_PDB_DACINTn_INT)
1142
1143 /*! @brief Set the INT field to a new value. */
1144 #define BW_PDB_DACINTn_INT(x, n, v) (HW_PDB_DACINTn_WR(x, n, (HW_PDB_DACINTn_RD(x, n) & ~BM_PDB_DACINTn_INT) | BF_PDB_DACINTn_INT(v)))
1145 /*@}*/
1146
1147 /*******************************************************************************
1148  * HW_PDB_POEN - Pulse-Out n Enable register
1149  ******************************************************************************/
1150
1151 /*!
1152  * @brief HW_PDB_POEN - Pulse-Out n Enable register (RW)
1153  *
1154  * Reset value: 0x00000000U
1155  */
1156 typedef union _hw_pdb_poen
1157 {
1158     uint32_t U;
1159     struct _hw_pdb_poen_bitfields
1160     {
1161         uint32_t POEN : 8;             /*!< [7:0] PDB Pulse-Out Enable */
1162         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
1163     } B;
1164 } hw_pdb_poen_t;
1165
1166 /*!
1167  * @name Constants and macros for entire PDB_POEN register
1168  */
1169 /*@{*/
1170 #define HW_PDB_POEN_ADDR(x)      ((x) + 0x190U)
1171
1172 #define HW_PDB_POEN(x)           (*(__IO hw_pdb_poen_t *) HW_PDB_POEN_ADDR(x))
1173 #define HW_PDB_POEN_RD(x)        (HW_PDB_POEN(x).U)
1174 #define HW_PDB_POEN_WR(x, v)     (HW_PDB_POEN(x).U = (v))
1175 #define HW_PDB_POEN_SET(x, v)    (HW_PDB_POEN_WR(x, HW_PDB_POEN_RD(x) |  (v)))
1176 #define HW_PDB_POEN_CLR(x, v)    (HW_PDB_POEN_WR(x, HW_PDB_POEN_RD(x) & ~(v)))
1177 #define HW_PDB_POEN_TOG(x, v)    (HW_PDB_POEN_WR(x, HW_PDB_POEN_RD(x) ^  (v)))
1178 /*@}*/
1179
1180 /*
1181  * Constants & macros for individual PDB_POEN bitfields
1182  */
1183
1184 /*!
1185  * @name Register PDB_POEN, field POEN[7:0] (RW)
1186  *
1187  * Enables the pulse output. Only lower Y bits are implemented in this MCU.
1188  *
1189  * Values:
1190  * - 0 - PDB Pulse-Out disabled
1191  * - 1 - PDB Pulse-Out enabled
1192  */
1193 /*@{*/
1194 #define BP_PDB_POEN_POEN     (0U)          /*!< Bit position for PDB_POEN_POEN. */
1195 #define BM_PDB_POEN_POEN     (0x000000FFU) /*!< Bit mask for PDB_POEN_POEN. */
1196 #define BS_PDB_POEN_POEN     (8U)          /*!< Bit field size in bits for PDB_POEN_POEN. */
1197
1198 /*! @brief Read current value of the PDB_POEN_POEN field. */
1199 #define BR_PDB_POEN_POEN(x)  (HW_PDB_POEN(x).B.POEN)
1200
1201 /*! @brief Format value for bitfield PDB_POEN_POEN. */
1202 #define BF_PDB_POEN_POEN(v)  ((uint32_t)((uint32_t)(v) << BP_PDB_POEN_POEN) & BM_PDB_POEN_POEN)
1203
1204 /*! @brief Set the POEN field to a new value. */
1205 #define BW_PDB_POEN_POEN(x, v) (HW_PDB_POEN_WR(x, (HW_PDB_POEN_RD(x) & ~BM_PDB_POEN_POEN) | BF_PDB_POEN_POEN(v)))
1206 /*@}*/
1207
1208 /*******************************************************************************
1209  * HW_PDB_POnDLY - Pulse-Out n Delay register
1210  ******************************************************************************/
1211
1212 /*!
1213  * @brief HW_PDB_POnDLY - Pulse-Out n Delay register (RW)
1214  *
1215  * Reset value: 0x00000000U
1216  */
1217 typedef union _hw_pdb_pondly
1218 {
1219     uint32_t U;
1220     struct _hw_pdb_pondly_bitfields
1221     {
1222         uint32_t DLY2 : 16;            /*!< [15:0] PDB Pulse-Out Delay 2 */
1223         uint32_t DLY1 : 16;            /*!< [31:16] PDB Pulse-Out Delay 1 */
1224     } B;
1225 } hw_pdb_pondly_t;
1226
1227 /*!
1228  * @name Constants and macros for entire PDB_POnDLY register
1229  */
1230 /*@{*/
1231 #define HW_PDB_POnDLY_COUNT (3U)
1232
1233 #define HW_PDB_POnDLY_ADDR(x, n) ((x) + 0x194U + (0x4U * (n)))
1234
1235 #define HW_PDB_POnDLY(x, n)      (*(__IO hw_pdb_pondly_t *) HW_PDB_POnDLY_ADDR(x, n))
1236 #define HW_PDB_POnDLY_RD(x, n)   (HW_PDB_POnDLY(x, n).U)
1237 #define HW_PDB_POnDLY_WR(x, n, v) (HW_PDB_POnDLY(x, n).U = (v))
1238 #define HW_PDB_POnDLY_SET(x, n, v) (HW_PDB_POnDLY_WR(x, n, HW_PDB_POnDLY_RD(x, n) |  (v)))
1239 #define HW_PDB_POnDLY_CLR(x, n, v) (HW_PDB_POnDLY_WR(x, n, HW_PDB_POnDLY_RD(x, n) & ~(v)))
1240 #define HW_PDB_POnDLY_TOG(x, n, v) (HW_PDB_POnDLY_WR(x, n, HW_PDB_POnDLY_RD(x, n) ^  (v)))
1241 /*@}*/
1242
1243 /*
1244  * Constants & macros for individual PDB_POnDLY bitfields
1245  */
1246
1247 /*!
1248  * @name Register PDB_POnDLY, field DLY2[15:0] (RW)
1249  *
1250  * These bits specify the delay 2 value for the PDB Pulse-Out. Pulse-Out goes
1251  * low when the PDB counter is equal to the DLY2. Reading these bits returns the
1252  * value of internal register that is effective for the current PDB cycle.
1253  */
1254 /*@{*/
1255 #define BP_PDB_POnDLY_DLY2   (0U)          /*!< Bit position for PDB_POnDLY_DLY2. */
1256 #define BM_PDB_POnDLY_DLY2   (0x0000FFFFU) /*!< Bit mask for PDB_POnDLY_DLY2. */
1257 #define BS_PDB_POnDLY_DLY2   (16U)         /*!< Bit field size in bits for PDB_POnDLY_DLY2. */
1258
1259 /*! @brief Read current value of the PDB_POnDLY_DLY2 field. */
1260 #define BR_PDB_POnDLY_DLY2(x, n) (HW_PDB_POnDLY(x, n).B.DLY2)
1261
1262 /*! @brief Format value for bitfield PDB_POnDLY_DLY2. */
1263 #define BF_PDB_POnDLY_DLY2(v) ((uint32_t)((uint32_t)(v) << BP_PDB_POnDLY_DLY2) & BM_PDB_POnDLY_DLY2)
1264
1265 /*! @brief Set the DLY2 field to a new value. */
1266 #define BW_PDB_POnDLY_DLY2(x, n, v) (HW_PDB_POnDLY_WR(x, n, (HW_PDB_POnDLY_RD(x, n) & ~BM_PDB_POnDLY_DLY2) | BF_PDB_POnDLY_DLY2(v)))
1267 /*@}*/
1268
1269 /*!
1270  * @name Register PDB_POnDLY, field DLY1[31:16] (RW)
1271  *
1272  * These bits specify the delay 1 value for the PDB Pulse-Out. Pulse-Out goes
1273  * high when the PDB counter is equal to the DLY1. Reading these bits returns the
1274  * value of internal register that is effective for the current PDB cycle.
1275  */
1276 /*@{*/
1277 #define BP_PDB_POnDLY_DLY1   (16U)         /*!< Bit position for PDB_POnDLY_DLY1. */
1278 #define BM_PDB_POnDLY_DLY1   (0xFFFF0000U) /*!< Bit mask for PDB_POnDLY_DLY1. */
1279 #define BS_PDB_POnDLY_DLY1   (16U)         /*!< Bit field size in bits for PDB_POnDLY_DLY1. */
1280
1281 /*! @brief Read current value of the PDB_POnDLY_DLY1 field. */
1282 #define BR_PDB_POnDLY_DLY1(x, n) (HW_PDB_POnDLY(x, n).B.DLY1)
1283
1284 /*! @brief Format value for bitfield PDB_POnDLY_DLY1. */
1285 #define BF_PDB_POnDLY_DLY1(v) ((uint32_t)((uint32_t)(v) << BP_PDB_POnDLY_DLY1) & BM_PDB_POnDLY_DLY1)
1286
1287 /*! @brief Set the DLY1 field to a new value. */
1288 #define BW_PDB_POnDLY_DLY1(x, n, v) (HW_PDB_POnDLY_WR(x, n, (HW_PDB_POnDLY_RD(x, n) & ~BM_PDB_POnDLY_DLY1) | BF_PDB_POnDLY_DLY1(v)))
1289 /*@}*/
1290
1291 /*******************************************************************************
1292  * hw_pdb_t - module struct
1293  ******************************************************************************/
1294 /*!
1295  * @brief All PDB module registers.
1296  */
1297 #pragma pack(1)
1298 typedef struct _hw_pdb
1299 {
1300     __IO hw_pdb_sc_t SC;                   /*!< [0x0] Status and Control register */
1301     __IO hw_pdb_mod_t MOD;                 /*!< [0x4] Modulus register */
1302     __I hw_pdb_cnt_t CNT;                  /*!< [0x8] Counter register */
1303     __IO hw_pdb_idly_t IDLY;               /*!< [0xC] Interrupt Delay register */
1304     struct {
1305         __IO hw_pdb_chnc1_t CHnC1;         /*!< [0x10] Channel n Control register 1 */
1306         __IO hw_pdb_chns_t CHnS;           /*!< [0x14] Channel n Status register */
1307         __IO hw_pdb_chndly0_t CHnDLY0;     /*!< [0x18] Channel n Delay 0 register */
1308         __IO hw_pdb_chndly1_t CHnDLY1;     /*!< [0x1C] Channel n Delay 1 register */
1309         uint8_t _reserved0[24];
1310     } CH[2];
1311     uint8_t _reserved0[240];
1312     struct {
1313         __IO hw_pdb_dacintcn_t DACINTCn;   /*!< [0x150] DAC Interval Trigger n Control register */
1314         __IO hw_pdb_dacintn_t DACINTn;     /*!< [0x154] DAC Interval n register */
1315     } DAC[2];
1316     uint8_t _reserved1[48];
1317     __IO hw_pdb_poen_t POEN;               /*!< [0x190] Pulse-Out n Enable register */
1318     __IO hw_pdb_pondly_t POnDLY[3];        /*!< [0x194] Pulse-Out n Delay register */
1319 } hw_pdb_t;
1320 #pragma pack()
1321
1322 /*! @brief Macro to access all PDB registers. */
1323 /*! @param x PDB module instance base address. */
1324 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
1325  *     use the '&' operator, like <code>&HW_PDB(PDB0_BASE)</code>. */
1326 #define HW_PDB(x)      (*(hw_pdb_t *)(x))
1327
1328 #endif /* __HW_PDB_REGISTERS_H__ */
1329 /* EOF */