tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_pit.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
   9 **     Version:             rev. 2.5, 2014-02-10
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-08-12)
  48 **         Initial version.
  49 **     - rev. 2.0 (2013-10-29)
  50 **         Register accessor macros added to the memory map.
  51 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  52 **         Startup file for gcc has been updated according to CMSIS 3.2.
  53 **         System initialization updated.
  54 **         MCG - registers updated.
  55 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-09)
  59 **         DMA - EARS register removed.
  60 **         AIPS0, AIPS1 - MPRA register updated.
  61 **     - rev. 2.3 (2014-01-24)
  62 **         Update according to reference manual rev. 2
  63 **         ENET, MCG, MCM, SIM, USB - registers updated
  64 **     - rev. 2.4 (2014-02-10)
  65 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  66 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  67 **     - rev. 2.5 (2014-02-10)
  68 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  69 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  70 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  71 **
  72 ** ###################################################################
  73 */
  74
  75 /*
  76  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  77  *
  78  * This file was generated automatically and any changes may be lost.
  79  */
  80 #ifndef __HW_PIT_REGISTERS_H__
  81 #define __HW_PIT_REGISTERS_H__
  82
  83 #include "MK64F12.h"
  84 #include "fsl_bitaccess.h"
  85
  86 /*
  87  * MK64F12 PIT
  88  *
  89  * Periodic Interrupt Timer
  90  *
  91  * Registers defined in this header file:
  92  * - HW_PIT_MCR - PIT Module Control Register
  93  * - HW_PIT_LDVALn - Timer Load Value Register
  94  * - HW_PIT_CVALn - Current Timer Value Register
  95  * - HW_PIT_TCTRLn - Timer Control Register
  96  * - HW_PIT_TFLGn - Timer Flag Register
  97  *
  98  * - hw_pit_t - Struct containing all module registers.
  99  */
 100
 101 #define HW_PIT_INSTANCE_COUNT (1U) /*!< Number of instances of the PIT module. */
 102
 103 /*******************************************************************************
 104  * HW_PIT_MCR - PIT Module Control Register
 105  ******************************************************************************/
 106
 107 /*!
 108  * @brief HW_PIT_MCR - PIT Module Control Register (RW)
 109  *
 110  * Reset value: 0x00000006U
 111  *
 112  * This register enables or disables the PIT timer clocks and controls the
 113  * timers when the PIT enters the Debug mode.
 114  */
 115 typedef union _hw_pit_mcr
 116 {
 117     uint32_t U;
 118     struct _hw_pit_mcr_bitfields
 119     {
 120         uint32_t FRZ : 1;              /*!< [0] Freeze */
 121         uint32_t MDIS : 1;             /*!< [1] Module Disable - (PIT section) */
 122         uint32_t RESERVED0 : 30;       /*!< [31:2]  */
 123     } B;
 124 } hw_pit_mcr_t;
 125
 126 /*!
 127  * @name Constants and macros for entire PIT_MCR register
 128  */
 129 /*@{*/
 130 #define HW_PIT_MCR_ADDR(x)       ((x) + 0x0U)
 131
 132 #define HW_PIT_MCR(x)            (*(__IO hw_pit_mcr_t *) HW_PIT_MCR_ADDR(x))
 133 #define HW_PIT_MCR_RD(x)         (HW_PIT_MCR(x).U)
 134 #define HW_PIT_MCR_WR(x, v)      (HW_PIT_MCR(x).U = (v))
 135 #define HW_PIT_MCR_SET(x, v)     (HW_PIT_MCR_WR(x, HW_PIT_MCR_RD(x) |  (v)))
 136 #define HW_PIT_MCR_CLR(x, v)     (HW_PIT_MCR_WR(x, HW_PIT_MCR_RD(x) & ~(v)))
 137 #define HW_PIT_MCR_TOG(x, v)     (HW_PIT_MCR_WR(x, HW_PIT_MCR_RD(x) ^  (v)))
 138 /*@}*/
 139
 140 /*
 141  * Constants & macros for individual PIT_MCR bitfields
 142  */
 143
 144 /*!
 145  * @name Register PIT_MCR, field FRZ[0] (RW)
 146  *
 147  * Allows the timers to be stopped when the device enters the Debug mode.
 148  *
 149  * Values:
 150  * - 0 - Timers continue to run in Debug mode.
 151  * - 1 - Timers are stopped in Debug mode.
 152  */
 153 /*@{*/
 154 #define BP_PIT_MCR_FRZ       (0U)          /*!< Bit position for PIT_MCR_FRZ. */
 155 #define BM_PIT_MCR_FRZ       (0x00000001U) /*!< Bit mask for PIT_MCR_FRZ. */
 156 #define BS_PIT_MCR_FRZ       (1U)          /*!< Bit field size in bits for PIT_MCR_FRZ. */
 157
 158 /*! @brief Read current value of the PIT_MCR_FRZ field. */
 159 #define BR_PIT_MCR_FRZ(x)    (BITBAND_ACCESS32(HW_PIT_MCR_ADDR(x), BP_PIT_MCR_FRZ))
 160
 161 /*! @brief Format value for bitfield PIT_MCR_FRZ. */
 162 #define BF_PIT_MCR_FRZ(v)    ((uint32_t)((uint32_t)(v) << BP_PIT_MCR_FRZ) & BM_PIT_MCR_FRZ)
 163
 164 /*! @brief Set the FRZ field to a new value. */
 165 #define BW_PIT_MCR_FRZ(x, v) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR(x), BP_PIT_MCR_FRZ) = (v))
 166 /*@}*/
 167
 168 /*!
 169  * @name Register PIT_MCR, field MDIS[1] (RW)
 170  *
 171  * Disables the standard timers. This field must be enabled before any other
 172  * setup is done.
 173  *
 174  * Values:
 175  * - 0 - Clock for standard PIT timers is enabled.
 176  * - 1 - Clock for standard PIT timers is disabled.
 177  */
 178 /*@{*/
 179 #define BP_PIT_MCR_MDIS      (1U)          /*!< Bit position for PIT_MCR_MDIS. */
 180 #define BM_PIT_MCR_MDIS      (0x00000002U) /*!< Bit mask for PIT_MCR_MDIS. */
 181 #define BS_PIT_MCR_MDIS      (1U)          /*!< Bit field size in bits for PIT_MCR_MDIS. */
 182
 183 /*! @brief Read current value of the PIT_MCR_MDIS field. */
 184 #define BR_PIT_MCR_MDIS(x)   (BITBAND_ACCESS32(HW_PIT_MCR_ADDR(x), BP_PIT_MCR_MDIS))
 185
 186 /*! @brief Format value for bitfield PIT_MCR_MDIS. */
 187 #define BF_PIT_MCR_MDIS(v)   ((uint32_t)((uint32_t)(v) << BP_PIT_MCR_MDIS) & BM_PIT_MCR_MDIS)
 188
 189 /*! @brief Set the MDIS field to a new value. */
 190 #define BW_PIT_MCR_MDIS(x, v) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR(x), BP_PIT_MCR_MDIS) = (v))
 191 /*@}*/
 192
 193 /*******************************************************************************
 194  * HW_PIT_LDVALn - Timer Load Value Register
 195  ******************************************************************************/
 196
 197 /*!
 198  * @brief HW_PIT_LDVALn - Timer Load Value Register (RW)
 199  *
 200  * Reset value: 0x00000000U
 201  *
 202  * These registers select the timeout period for the timer interrupts.
 203  */
 204 typedef union _hw_pit_ldvaln
 205 {
 206     uint32_t U;
 207     struct _hw_pit_ldvaln_bitfields
 208     {
 209         uint32_t TSV : 32;             /*!< [31:0] Timer Start Value */
 210     } B;
 211 } hw_pit_ldvaln_t;
 212
 213 /*!
 214  * @name Constants and macros for entire PIT_LDVALn register
 215  */
 216 /*@{*/
 217 #define HW_PIT_LDVALn_COUNT (4U)
 218
 219 #define HW_PIT_LDVALn_ADDR(x, n) ((x) + 0x100U + (0x10U * (n)))
 220
 221 #define HW_PIT_LDVALn(x, n)      (*(__IO hw_pit_ldvaln_t *) HW_PIT_LDVALn_ADDR(x, n))
 222 #define HW_PIT_LDVALn_RD(x, n)   (HW_PIT_LDVALn(x, n).U)
 223 #define HW_PIT_LDVALn_WR(x, n, v) (HW_PIT_LDVALn(x, n).U = (v))
 224 #define HW_PIT_LDVALn_SET(x, n, v) (HW_PIT_LDVALn_WR(x, n, HW_PIT_LDVALn_RD(x, n) |  (v)))
 225 #define HW_PIT_LDVALn_CLR(x, n, v) (HW_PIT_LDVALn_WR(x, n, HW_PIT_LDVALn_RD(x, n) & ~(v)))
 226 #define HW_PIT_LDVALn_TOG(x, n, v) (HW_PIT_LDVALn_WR(x, n, HW_PIT_LDVALn_RD(x, n) ^  (v)))
 227 /*@}*/
 228
 229 /*
 230  * Constants & macros for individual PIT_LDVALn bitfields
 231  */
 232
 233 /*!
 234  * @name Register PIT_LDVALn, field TSV[31:0] (RW)
 235  *
 236  * Sets the timer start value. The timer will count down until it reaches 0,
 237  * then it will generate an interrupt and load this register value again. Writing a
 238  * new value to this register will not restart the timer; instead the value will
 239  * be loaded after the timer expires. To abort the current cycle and start a
 240  * timer period with the new value, the timer must be disabled and enabled again.
 241  */
 242 /*@{*/
 243 #define BP_PIT_LDVALn_TSV    (0U)          /*!< Bit position for PIT_LDVALn_TSV. */
 244 #define BM_PIT_LDVALn_TSV    (0xFFFFFFFFU) /*!< Bit mask for PIT_LDVALn_TSV. */
 245 #define BS_PIT_LDVALn_TSV    (32U)         /*!< Bit field size in bits for PIT_LDVALn_TSV. */
 246
 247 /*! @brief Read current value of the PIT_LDVALn_TSV field. */
 248 #define BR_PIT_LDVALn_TSV(x, n) (HW_PIT_LDVALn(x, n).U)
 249
 250 /*! @brief Format value for bitfield PIT_LDVALn_TSV. */
 251 #define BF_PIT_LDVALn_TSV(v) ((uint32_t)((uint32_t)(v) << BP_PIT_LDVALn_TSV) & BM_PIT_LDVALn_TSV)
 252
 253 /*! @brief Set the TSV field to a new value. */
 254 #define BW_PIT_LDVALn_TSV(x, n, v) (HW_PIT_LDVALn_WR(x, n, v))
 255 /*@}*/
 256 /*******************************************************************************
 257  * HW_PIT_CVALn - Current Timer Value Register
 258  ******************************************************************************/
 259
 260 /*!
 261  * @brief HW_PIT_CVALn - Current Timer Value Register (RO)
 262  *
 263  * Reset value: 0x00000000U
 264  *
 265  * These registers indicate the current timer position.
 266  */
 267 typedef union _hw_pit_cvaln
 268 {
 269     uint32_t U;
 270     struct _hw_pit_cvaln_bitfields
 271     {
 272         uint32_t TVL : 32;             /*!< [31:0] Current Timer Value */
 273     } B;
 274 } hw_pit_cvaln_t;
 275
 276 /*!
 277  * @name Constants and macros for entire PIT_CVALn register
 278  */
 279 /*@{*/
 280 #define HW_PIT_CVALn_COUNT (4U)
 281
 282 #define HW_PIT_CVALn_ADDR(x, n)  ((x) + 0x104U + (0x10U * (n)))
 283
 284 #define HW_PIT_CVALn(x, n)       (*(__I hw_pit_cvaln_t *) HW_PIT_CVALn_ADDR(x, n))
 285 #define HW_PIT_CVALn_RD(x, n)    (HW_PIT_CVALn(x, n).U)
 286 /*@}*/
 287
 288 /*
 289  * Constants & macros for individual PIT_CVALn bitfields
 290  */
 291
 292 /*!
 293  * @name Register PIT_CVALn, field TVL[31:0] (RO)
 294  *
 295  * Represents the current timer value, if the timer is enabled. If the timer is
 296  * disabled, do not use this field as its value is unreliable. The timer uses a
 297  * downcounter. The timer values are frozen in Debug mode if MCR[FRZ] is set.
 298  */
 299 /*@{*/
 300 #define BP_PIT_CVALn_TVL     (0U)          /*!< Bit position for PIT_CVALn_TVL. */
 301 #define BM_PIT_CVALn_TVL     (0xFFFFFFFFU) /*!< Bit mask for PIT_CVALn_TVL. */
 302 #define BS_PIT_CVALn_TVL     (32U)         /*!< Bit field size in bits for PIT_CVALn_TVL. */
 303
 304 /*! @brief Read current value of the PIT_CVALn_TVL field. */
 305 #define BR_PIT_CVALn_TVL(x, n) (HW_PIT_CVALn(x, n).U)
 306 /*@}*/
 307 /*******************************************************************************
 308  * HW_PIT_TCTRLn - Timer Control Register
 309  ******************************************************************************/
 310
 311 /*!
 312  * @brief HW_PIT_TCTRLn - Timer Control Register (RW)
 313  *
 314  * Reset value: 0x00000000U
 315  *
 316  * These registers contain the control bits for each timer.
 317  */
 318 typedef union _hw_pit_tctrln
 319 {
 320     uint32_t U;
 321     struct _hw_pit_tctrln_bitfields
 322     {
 323         uint32_t TEN : 1;              /*!< [0] Timer Enable */
 324         uint32_t TIE : 1;              /*!< [1] Timer Interrupt Enable */
 325         uint32_t CHN : 1;              /*!< [2] Chain Mode */
 326         uint32_t RESERVED0 : 29;       /*!< [31:3]  */
 327     } B;
 328 } hw_pit_tctrln_t;
 329
 330 /*!
 331  * @name Constants and macros for entire PIT_TCTRLn register
 332  */
 333 /*@{*/
 334 #define HW_PIT_TCTRLn_COUNT (4U)
 335
 336 #define HW_PIT_TCTRLn_ADDR(x, n) ((x) + 0x108U + (0x10U * (n)))
 337
 338 #define HW_PIT_TCTRLn(x, n)      (*(__IO hw_pit_tctrln_t *) HW_PIT_TCTRLn_ADDR(x, n))
 339 #define HW_PIT_TCTRLn_RD(x, n)   (HW_PIT_TCTRLn(x, n).U)
 340 #define HW_PIT_TCTRLn_WR(x, n, v) (HW_PIT_TCTRLn(x, n).U = (v))
 341 #define HW_PIT_TCTRLn_SET(x, n, v) (HW_PIT_TCTRLn_WR(x, n, HW_PIT_TCTRLn_RD(x, n) |  (v)))
 342 #define HW_PIT_TCTRLn_CLR(x, n, v) (HW_PIT_TCTRLn_WR(x, n, HW_PIT_TCTRLn_RD(x, n) & ~(v)))
 343 #define HW_PIT_TCTRLn_TOG(x, n, v) (HW_PIT_TCTRLn_WR(x, n, HW_PIT_TCTRLn_RD(x, n) ^  (v)))
 344 /*@}*/
 345
 346 /*
 347  * Constants & macros for individual PIT_TCTRLn bitfields
 348  */
 349
 350 /*!
 351  * @name Register PIT_TCTRLn, field TEN[0] (RW)
 352  *
 353  * Enables or disables the timer.
 354  *
 355  * Values:
 356  * - 0 - Timer n is disabled.
 357  * - 1 - Timer n is enabled.
 358  */
 359 /*@{*/
 360 #define BP_PIT_TCTRLn_TEN    (0U)          /*!< Bit position for PIT_TCTRLn_TEN. */
 361 #define BM_PIT_TCTRLn_TEN    (0x00000001U) /*!< Bit mask for PIT_TCTRLn_TEN. */
 362 #define BS_PIT_TCTRLn_TEN    (1U)          /*!< Bit field size in bits for PIT_TCTRLn_TEN. */
 363
 364 /*! @brief Read current value of the PIT_TCTRLn_TEN field. */
 365 #define BR_PIT_TCTRLn_TEN(x, n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_TEN))
 366
 367 /*! @brief Format value for bitfield PIT_TCTRLn_TEN. */
 368 #define BF_PIT_TCTRLn_TEN(v) ((uint32_t)((uint32_t)(v) << BP_PIT_TCTRLn_TEN) & BM_PIT_TCTRLn_TEN)
 369
 370 /*! @brief Set the TEN field to a new value. */
 371 #define BW_PIT_TCTRLn_TEN(x, n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_TEN) = (v))
 372 /*@}*/
 373
 374 /*!
 375  * @name Register PIT_TCTRLn, field TIE[1] (RW)
 376  *
 377  * When an interrupt is pending, or, TFLGn[TIF] is set, enabling the interrupt
 378  * will immediately cause an interrupt event. To avoid this, the associated
 379  * TFLGn[TIF] must be cleared first.
 380  *
 381  * Values:
 382  * - 0 - Interrupt requests from Timer n are disabled.
 383  * - 1 - Interrupt will be requested whenever TIF is set.
 384  */
 385 /*@{*/
 386 #define BP_PIT_TCTRLn_TIE    (1U)          /*!< Bit position for PIT_TCTRLn_TIE. */
 387 #define BM_PIT_TCTRLn_TIE    (0x00000002U) /*!< Bit mask for PIT_TCTRLn_TIE. */
 388 #define BS_PIT_TCTRLn_TIE    (1U)          /*!< Bit field size in bits for PIT_TCTRLn_TIE. */
 389
 390 /*! @brief Read current value of the PIT_TCTRLn_TIE field. */
 391 #define BR_PIT_TCTRLn_TIE(x, n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_TIE))
 392
 393 /*! @brief Format value for bitfield PIT_TCTRLn_TIE. */
 394 #define BF_PIT_TCTRLn_TIE(v) ((uint32_t)((uint32_t)(v) << BP_PIT_TCTRLn_TIE) & BM_PIT_TCTRLn_TIE)
 395
 396 /*! @brief Set the TIE field to a new value. */
 397 #define BW_PIT_TCTRLn_TIE(x, n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_TIE) = (v))
 398 /*@}*/
 399
 400 /*!
 401  * @name Register PIT_TCTRLn, field CHN[2] (RW)
 402  *
 403  * When activated, Timer n-1 needs to expire before timer n can decrement by 1.
 404  * Timer 0 cannot be chained.
 405  *
 406  * Values:
 407  * - 0 - Timer is not chained.
 408  * - 1 - Timer is chained to previous timer. For example, for Channel 2, if this
 409  *     field is set, Timer 2 is chained to Timer 1.
 410  */
 411 /*@{*/
 412 #define BP_PIT_TCTRLn_CHN    (2U)          /*!< Bit position for PIT_TCTRLn_CHN. */
 413 #define BM_PIT_TCTRLn_CHN    (0x00000004U) /*!< Bit mask for PIT_TCTRLn_CHN. */
 414 #define BS_PIT_TCTRLn_CHN    (1U)          /*!< Bit field size in bits for PIT_TCTRLn_CHN. */
 415
 416 /*! @brief Read current value of the PIT_TCTRLn_CHN field. */
 417 #define BR_PIT_TCTRLn_CHN(x, n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_CHN))
 418
 419 /*! @brief Format value for bitfield PIT_TCTRLn_CHN. */
 420 #define BF_PIT_TCTRLn_CHN(v) ((uint32_t)((uint32_t)(v) << BP_PIT_TCTRLn_CHN) & BM_PIT_TCTRLn_CHN)
 421
 422 /*! @brief Set the CHN field to a new value. */
 423 #define BW_PIT_TCTRLn_CHN(x, n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_CHN) = (v))
 424 /*@}*/
 425 /*******************************************************************************
 426  * HW_PIT_TFLGn - Timer Flag Register
 427  ******************************************************************************/
 428
 429 /*!
 430  * @brief HW_PIT_TFLGn - Timer Flag Register (RW)
 431  *
 432  * Reset value: 0x00000000U
 433  *
 434  * These registers hold the PIT interrupt flags.
 435  */
 436 typedef union _hw_pit_tflgn
 437 {
 438     uint32_t U;
 439     struct _hw_pit_tflgn_bitfields
 440     {
 441         uint32_t TIF : 1;              /*!< [0] Timer Interrupt Flag */
 442         uint32_t RESERVED0 : 31;       /*!< [31:1]  */
 443     } B;
 444 } hw_pit_tflgn_t;
 445
 446 /*!
 447  * @name Constants and macros for entire PIT_TFLGn register
 448  */
 449 /*@{*/
 450 #define HW_PIT_TFLGn_COUNT (4U)
 451
 452 #define HW_PIT_TFLGn_ADDR(x, n)  ((x) + 0x10CU + (0x10U * (n)))
 453
 454 #define HW_PIT_TFLGn(x, n)       (*(__IO hw_pit_tflgn_t *) HW_PIT_TFLGn_ADDR(x, n))
 455 #define HW_PIT_TFLGn_RD(x, n)    (HW_PIT_TFLGn(x, n).U)
 456 #define HW_PIT_TFLGn_WR(x, n, v) (HW_PIT_TFLGn(x, n).U = (v))
 457 #define HW_PIT_TFLGn_SET(x, n, v) (HW_PIT_TFLGn_WR(x, n, HW_PIT_TFLGn_RD(x, n) |  (v)))
 458 #define HW_PIT_TFLGn_CLR(x, n, v) (HW_PIT_TFLGn_WR(x, n, HW_PIT_TFLGn_RD(x, n) & ~(v)))
 459 #define HW_PIT_TFLGn_TOG(x, n, v) (HW_PIT_TFLGn_WR(x, n, HW_PIT_TFLGn_RD(x, n) ^  (v)))
 460 /*@}*/
 461
 462 /*
 463  * Constants & macros for individual PIT_TFLGn bitfields
 464  */
 465
 466 /*!
 467  * @name Register PIT_TFLGn, field TIF[0] (W1C)
 468  *
 469  * Sets to 1 at the end of the timer period. Writing 1 to this flag clears it.
 470  * Writing 0 has no effect. If enabled, or, when TCTRLn[TIE] = 1, TIF causes an
 471  * interrupt request.
 472  *
 473  * Values:
 474  * - 0 - Timeout has not yet occurred.
 475  * - 1 - Timeout has occurred.
 476  */
 477 /*@{*/
 478 #define BP_PIT_TFLGn_TIF     (0U)          /*!< Bit position for PIT_TFLGn_TIF. */
 479 #define BM_PIT_TFLGn_TIF     (0x00000001U) /*!< Bit mask for PIT_TFLGn_TIF. */
 480 #define BS_PIT_TFLGn_TIF     (1U)          /*!< Bit field size in bits for PIT_TFLGn_TIF. */
 481
 482 /*! @brief Read current value of the PIT_TFLGn_TIF field. */
 483 #define BR_PIT_TFLGn_TIF(x, n) (BITBAND_ACCESS32(HW_PIT_TFLGn_ADDR(x, n), BP_PIT_TFLGn_TIF))
 484
 485 /*! @brief Format value for bitfield PIT_TFLGn_TIF. */
 486 #define BF_PIT_TFLGn_TIF(v)  ((uint32_t)((uint32_t)(v) << BP_PIT_TFLGn_TIF) & BM_PIT_TFLGn_TIF)
 487
 488 /*! @brief Set the TIF field to a new value. */
 489 #define BW_PIT_TFLGn_TIF(x, n, v) (BITBAND_ACCESS32(HW_PIT_TFLGn_ADDR(x, n), BP_PIT_TFLGn_TIF) = (v))
 490 /*@}*/
 491
 492 /*******************************************************************************
 493  * hw_pit_t - module struct
 494  ******************************************************************************/
 495 /*!
 496  * @brief All PIT module registers.
 497  */
 498 #pragma pack(1)
 499 typedef struct _hw_pit
 500 {
 501     __IO hw_pit_mcr_t MCR;                 /*!< [0x0] PIT Module Control Register */
 502     uint8_t _reserved0[252];
 503     struct {
 504         __IO hw_pit_ldvaln_t LDVALn;       /*!< [0x100] Timer Load Value Register */
 505         __I hw_pit_cvaln_t CVALn;          /*!< [0x104] Current Timer Value Register */
 506         __IO hw_pit_tctrln_t TCTRLn;       /*!< [0x108] Timer Control Register */
 507         __IO hw_pit_tflgn_t TFLGn;         /*!< [0x10C] Timer Flag Register */
 508     } CHANNEL[4];
 509 } hw_pit_t;
 510 #pragma pack()
 511
 512 /*! @brief Macro to access all PIT registers. */
 513 /*! @param x PIT module instance base address. */
 514 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
 515  *     use the '&' operator, like <code>&HW_PIT(PIT_BASE)</code>. */
 516 #define HW_PIT(x)      (*(hw_pit_t *)(x))
 517
 518 #endif /* __HW_PIT_REGISTERS_H__ */
 519 /* EOF */