tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_pmc.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
   9 **     Version:             rev. 2.5, 2014-02-10
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-08-12)
  48 **         Initial version.
  49 **     - rev. 2.0 (2013-10-29)
  50 **         Register accessor macros added to the memory map.
  51 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  52 **         Startup file for gcc has been updated according to CMSIS 3.2.
  53 **         System initialization updated.
  54 **         MCG - registers updated.
  55 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-09)
  59 **         DMA - EARS register removed.
  60 **         AIPS0, AIPS1 - MPRA register updated.
  61 **     - rev. 2.3 (2014-01-24)
  62 **         Update according to reference manual rev. 2
  63 **         ENET, MCG, MCM, SIM, USB - registers updated
  64 **     - rev. 2.4 (2014-02-10)
  65 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  66 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  67 **     - rev. 2.5 (2014-02-10)
  68 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  69 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  70 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  71 **
  72 ** ###################################################################
  73 */
  74
  75 /*
  76  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  77  *
  78  * This file was generated automatically and any changes may be lost.
  79  */
  80 #ifndef __HW_PMC_REGISTERS_H__
  81 #define __HW_PMC_REGISTERS_H__
  82
  83 #include "MK64F12.h"
  84 #include "fsl_bitaccess.h"
  85
  86 /*
  87  * MK64F12 PMC
  88  *
  89  * Power Management Controller
  90  *
  91  * Registers defined in this header file:
  92  * - HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
  93  * - HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
  94  * - HW_PMC_REGSC - Regulator Status And Control register
  95  *
  96  * - hw_pmc_t - Struct containing all module registers.
  97  */
  98
  99 #define HW_PMC_INSTANCE_COUNT (1U) /*!< Number of instances of the PMC module. */
 100
 101 /*******************************************************************************
 102  * HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
 103  ******************************************************************************/
 104
 105 /*!
 106  * @brief HW_PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register (RW)
 107  *
 108  * Reset value: 0x10U
 109  *
 110  * This register contains status and control bits to support the low voltage
 111  * detect function. This register should be written during the reset initialization
 112  * program to set the desired controls even if the desired settings are the same
 113  * as the reset settings. While the device is in the very low power or low
 114  * leakage modes, the LVD system is disabled regardless of LVDSC1 settings. To protect
 115  * systems that must have LVD always on, configure the Power Mode Protection
 116  * (PMPROT) register of the SMC module (SMC_PMPROT) to disallow any very low power or
 117  * low leakage modes from being enabled. See the device's data sheet for the
 118  * exact LVD trip voltages. The LVDV bits are reset solely on a POR Only event. The
 119  * register's other bits are reset on Chip Reset Not VLLS. For more information
 120  * about these reset types, refer to the Reset section details.
 121  */
 122 typedef union _hw_pmc_lvdsc1
 123 {
 124     uint8_t U;
 125     struct _hw_pmc_lvdsc1_bitfields
 126     {
 127         uint8_t LVDV : 2;              /*!< [1:0] Low-Voltage Detect Voltage Select */
 128         uint8_t RESERVED0 : 2;         /*!< [3:2]  */
 129         uint8_t LVDRE : 1;             /*!< [4] Low-Voltage Detect Reset Enable */
 130         uint8_t LVDIE : 1;             /*!< [5] Low-Voltage Detect Interrupt Enable */
 131         uint8_t LVDACK : 1;            /*!< [6] Low-Voltage Detect Acknowledge */
 132         uint8_t LVDF : 1;              /*!< [7] Low-Voltage Detect Flag */
 133     } B;
 134 } hw_pmc_lvdsc1_t;
 135
 136 /*!
 137  * @name Constants and macros for entire PMC_LVDSC1 register
 138  */
 139 /*@{*/
 140 #define HW_PMC_LVDSC1_ADDR(x)    ((x) + 0x0U)
 141
 142 #define HW_PMC_LVDSC1(x)         (*(__IO hw_pmc_lvdsc1_t *) HW_PMC_LVDSC1_ADDR(x))
 143 #define HW_PMC_LVDSC1_RD(x)      (HW_PMC_LVDSC1(x).U)
 144 #define HW_PMC_LVDSC1_WR(x, v)   (HW_PMC_LVDSC1(x).U = (v))
 145 #define HW_PMC_LVDSC1_SET(x, v)  (HW_PMC_LVDSC1_WR(x, HW_PMC_LVDSC1_RD(x) |  (v)))
 146 #define HW_PMC_LVDSC1_CLR(x, v)  (HW_PMC_LVDSC1_WR(x, HW_PMC_LVDSC1_RD(x) & ~(v)))
 147 #define HW_PMC_LVDSC1_TOG(x, v)  (HW_PMC_LVDSC1_WR(x, HW_PMC_LVDSC1_RD(x) ^  (v)))
 148 /*@}*/
 149
 150 /*
 151  * Constants & macros for individual PMC_LVDSC1 bitfields
 152  */
 153
 154 /*!
 155  * @name Register PMC_LVDSC1, field LVDV[1:0] (RW)
 156  *
 157  * Selects the LVD trip point voltage (V LVD ).
 158  *
 159  * Values:
 160  * - 00 - Low trip point selected (V LVD = V LVDL )
 161  * - 01 - High trip point selected (V LVD = V LVDH )
 162  * - 10 - Reserved
 163  * - 11 - Reserved
 164  */
 165 /*@{*/
 166 #define BP_PMC_LVDSC1_LVDV   (0U)          /*!< Bit position for PMC_LVDSC1_LVDV. */
 167 #define BM_PMC_LVDSC1_LVDV   (0x03U)       /*!< Bit mask for PMC_LVDSC1_LVDV. */
 168 #define BS_PMC_LVDSC1_LVDV   (2U)          /*!< Bit field size in bits for PMC_LVDSC1_LVDV. */
 169
 170 /*! @brief Read current value of the PMC_LVDSC1_LVDV field. */
 171 #define BR_PMC_LVDSC1_LVDV(x) (HW_PMC_LVDSC1(x).B.LVDV)
 172
 173 /*! @brief Format value for bitfield PMC_LVDSC1_LVDV. */
 174 #define BF_PMC_LVDSC1_LVDV(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDV) & BM_PMC_LVDSC1_LVDV)
 175
 176 /*! @brief Set the LVDV field to a new value. */
 177 #define BW_PMC_LVDSC1_LVDV(x, v) (HW_PMC_LVDSC1_WR(x, (HW_PMC_LVDSC1_RD(x) & ~BM_PMC_LVDSC1_LVDV) | BF_PMC_LVDSC1_LVDV(v)))
 178 /*@}*/
 179
 180 /*!
 181  * @name Register PMC_LVDSC1, field LVDRE[4] (RW)
 182  *
 183  * This write-once bit enables LVDF events to generate a hardware reset.
 184  * Additional writes are ignored.
 185  *
 186  * Values:
 187  * - 0 - LVDF does not generate hardware resets
 188  * - 1 - Force an MCU reset when LVDF = 1
 189  */
 190 /*@{*/
 191 #define BP_PMC_LVDSC1_LVDRE  (4U)          /*!< Bit position for PMC_LVDSC1_LVDRE. */
 192 #define BM_PMC_LVDSC1_LVDRE  (0x10U)       /*!< Bit mask for PMC_LVDSC1_LVDRE. */
 193 #define BS_PMC_LVDSC1_LVDRE  (1U)          /*!< Bit field size in bits for PMC_LVDSC1_LVDRE. */
 194
 195 /*! @brief Read current value of the PMC_LVDSC1_LVDRE field. */
 196 #define BR_PMC_LVDSC1_LVDRE(x) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDRE))
 197
 198 /*! @brief Format value for bitfield PMC_LVDSC1_LVDRE. */
 199 #define BF_PMC_LVDSC1_LVDRE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDRE) & BM_PMC_LVDSC1_LVDRE)
 200
 201 /*! @brief Set the LVDRE field to a new value. */
 202 #define BW_PMC_LVDSC1_LVDRE(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDRE) = (v))
 203 /*@}*/
 204
 205 /*!
 206  * @name Register PMC_LVDSC1, field LVDIE[5] (RW)
 207  *
 208  * Enables hardware interrupt requests for LVDF.
 209  *
 210  * Values:
 211  * - 0 - Hardware interrupt disabled (use polling)
 212  * - 1 - Request a hardware interrupt when LVDF = 1
 213  */
 214 /*@{*/
 215 #define BP_PMC_LVDSC1_LVDIE  (5U)          /*!< Bit position for PMC_LVDSC1_LVDIE. */
 216 #define BM_PMC_LVDSC1_LVDIE  (0x20U)       /*!< Bit mask for PMC_LVDSC1_LVDIE. */
 217 #define BS_PMC_LVDSC1_LVDIE  (1U)          /*!< Bit field size in bits for PMC_LVDSC1_LVDIE. */
 218
 219 /*! @brief Read current value of the PMC_LVDSC1_LVDIE field. */
 220 #define BR_PMC_LVDSC1_LVDIE(x) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDIE))
 221
 222 /*! @brief Format value for bitfield PMC_LVDSC1_LVDIE. */
 223 #define BF_PMC_LVDSC1_LVDIE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDIE) & BM_PMC_LVDSC1_LVDIE)
 224
 225 /*! @brief Set the LVDIE field to a new value. */
 226 #define BW_PMC_LVDSC1_LVDIE(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDIE) = (v))
 227 /*@}*/
 228
 229 /*!
 230  * @name Register PMC_LVDSC1, field LVDACK[6] (WORZ)
 231  *
 232  * This write-only field is used to acknowledge low voltage detection errors.
 233  * Write 1 to clear LVDF. Reads always return 0.
 234  */
 235 /*@{*/
 236 #define BP_PMC_LVDSC1_LVDACK (6U)          /*!< Bit position for PMC_LVDSC1_LVDACK. */
 237 #define BM_PMC_LVDSC1_LVDACK (0x40U)       /*!< Bit mask for PMC_LVDSC1_LVDACK. */
 238 #define BS_PMC_LVDSC1_LVDACK (1U)          /*!< Bit field size in bits for PMC_LVDSC1_LVDACK. */
 239
 240 /*! @brief Format value for bitfield PMC_LVDSC1_LVDACK. */
 241 #define BF_PMC_LVDSC1_LVDACK(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC1_LVDACK) & BM_PMC_LVDSC1_LVDACK)
 242
 243 /*! @brief Set the LVDACK field to a new value. */
 244 #define BW_PMC_LVDSC1_LVDACK(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDACK) = (v))
 245 /*@}*/
 246
 247 /*!
 248  * @name Register PMC_LVDSC1, field LVDF[7] (RO)
 249  *
 250  * This read-only status field indicates a low-voltage detect event.
 251  *
 252  * Values:
 253  * - 0 - Low-voltage event not detected
 254  * - 1 - Low-voltage event detected
 255  */
 256 /*@{*/
 257 #define BP_PMC_LVDSC1_LVDF   (7U)          /*!< Bit position for PMC_LVDSC1_LVDF. */
 258 #define BM_PMC_LVDSC1_LVDF   (0x80U)       /*!< Bit mask for PMC_LVDSC1_LVDF. */
 259 #define BS_PMC_LVDSC1_LVDF   (1U)          /*!< Bit field size in bits for PMC_LVDSC1_LVDF. */
 260
 261 /*! @brief Read current value of the PMC_LVDSC1_LVDF field. */
 262 #define BR_PMC_LVDSC1_LVDF(x) (BITBAND_ACCESS8(HW_PMC_LVDSC1_ADDR(x), BP_PMC_LVDSC1_LVDF))
 263 /*@}*/
 264
 265 /*******************************************************************************
 266  * HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
 267  ******************************************************************************/
 268
 269 /*!
 270  * @brief HW_PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register (RW)
 271  *
 272  * Reset value: 0x00U
 273  *
 274  * This register contains status and control bits to support the low voltage
 275  * warning function. While the device is in the very low power or low leakage modes,
 276  * the LVD system is disabled regardless of LVDSC2 settings. See the device's
 277  * data sheet for the exact LVD trip voltages. The LVW trip voltages depend on LVWV
 278  * and LVDV. LVWV is reset solely on a POR Only event. The other fields of the
 279  * register are reset on Chip Reset Not VLLS. For more information about these
 280  * reset types, refer to the Reset section details.
 281  */
 282 typedef union _hw_pmc_lvdsc2
 283 {
 284     uint8_t U;
 285     struct _hw_pmc_lvdsc2_bitfields
 286     {
 287         uint8_t LVWV : 2;              /*!< [1:0] Low-Voltage Warning Voltage Select */
 288         uint8_t RESERVED0 : 3;         /*!< [4:2]  */
 289         uint8_t LVWIE : 1;             /*!< [5] Low-Voltage Warning Interrupt Enable */
 290         uint8_t LVWACK : 1;            /*!< [6] Low-Voltage Warning Acknowledge */
 291         uint8_t LVWF : 1;              /*!< [7] Low-Voltage Warning Flag */
 292     } B;
 293 } hw_pmc_lvdsc2_t;
 294
 295 /*!
 296  * @name Constants and macros for entire PMC_LVDSC2 register
 297  */
 298 /*@{*/
 299 #define HW_PMC_LVDSC2_ADDR(x)    ((x) + 0x1U)
 300
 301 #define HW_PMC_LVDSC2(x)         (*(__IO hw_pmc_lvdsc2_t *) HW_PMC_LVDSC2_ADDR(x))
 302 #define HW_PMC_LVDSC2_RD(x)      (HW_PMC_LVDSC2(x).U)
 303 #define HW_PMC_LVDSC2_WR(x, v)   (HW_PMC_LVDSC2(x).U = (v))
 304 #define HW_PMC_LVDSC2_SET(x, v)  (HW_PMC_LVDSC2_WR(x, HW_PMC_LVDSC2_RD(x) |  (v)))
 305 #define HW_PMC_LVDSC2_CLR(x, v)  (HW_PMC_LVDSC2_WR(x, HW_PMC_LVDSC2_RD(x) & ~(v)))
 306 #define HW_PMC_LVDSC2_TOG(x, v)  (HW_PMC_LVDSC2_WR(x, HW_PMC_LVDSC2_RD(x) ^  (v)))
 307 /*@}*/
 308
 309 /*
 310  * Constants & macros for individual PMC_LVDSC2 bitfields
 311  */
 312
 313 /*!
 314  * @name Register PMC_LVDSC2, field LVWV[1:0] (RW)
 315  *
 316  * Selects the LVW trip point voltage (VLVW). The actual voltage for the warning
 317  * depends on LVDSC1[LVDV].
 318  *
 319  * Values:
 320  * - 00 - Low trip point selected (VLVW = VLVW1)
 321  * - 01 - Mid 1 trip point selected (VLVW = VLVW2)
 322  * - 10 - Mid 2 trip point selected (VLVW = VLVW3)
 323  * - 11 - High trip point selected (VLVW = VLVW4)
 324  */
 325 /*@{*/
 326 #define BP_PMC_LVDSC2_LVWV   (0U)          /*!< Bit position for PMC_LVDSC2_LVWV. */
 327 #define BM_PMC_LVDSC2_LVWV   (0x03U)       /*!< Bit mask for PMC_LVDSC2_LVWV. */
 328 #define BS_PMC_LVDSC2_LVWV   (2U)          /*!< Bit field size in bits for PMC_LVDSC2_LVWV. */
 329
 330 /*! @brief Read current value of the PMC_LVDSC2_LVWV field. */
 331 #define BR_PMC_LVDSC2_LVWV(x) (HW_PMC_LVDSC2(x).B.LVWV)
 332
 333 /*! @brief Format value for bitfield PMC_LVDSC2_LVWV. */
 334 #define BF_PMC_LVDSC2_LVWV(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC2_LVWV) & BM_PMC_LVDSC2_LVWV)
 335
 336 /*! @brief Set the LVWV field to a new value. */
 337 #define BW_PMC_LVDSC2_LVWV(x, v) (HW_PMC_LVDSC2_WR(x, (HW_PMC_LVDSC2_RD(x) & ~BM_PMC_LVDSC2_LVWV) | BF_PMC_LVDSC2_LVWV(v)))
 338 /*@}*/
 339
 340 /*!
 341  * @name Register PMC_LVDSC2, field LVWIE[5] (RW)
 342  *
 343  * Enables hardware interrupt requests for LVWF.
 344  *
 345  * Values:
 346  * - 0 - Hardware interrupt disabled (use polling)
 347  * - 1 - Request a hardware interrupt when LVWF = 1
 348  */
 349 /*@{*/
 350 #define BP_PMC_LVDSC2_LVWIE  (5U)          /*!< Bit position for PMC_LVDSC2_LVWIE. */
 351 #define BM_PMC_LVDSC2_LVWIE  (0x20U)       /*!< Bit mask for PMC_LVDSC2_LVWIE. */
 352 #define BS_PMC_LVDSC2_LVWIE  (1U)          /*!< Bit field size in bits for PMC_LVDSC2_LVWIE. */
 353
 354 /*! @brief Read current value of the PMC_LVDSC2_LVWIE field. */
 355 #define BR_PMC_LVDSC2_LVWIE(x) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWIE))
 356
 357 /*! @brief Format value for bitfield PMC_LVDSC2_LVWIE. */
 358 #define BF_PMC_LVDSC2_LVWIE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC2_LVWIE) & BM_PMC_LVDSC2_LVWIE)
 359
 360 /*! @brief Set the LVWIE field to a new value. */
 361 #define BW_PMC_LVDSC2_LVWIE(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWIE) = (v))
 362 /*@}*/
 363
 364 /*!
 365  * @name Register PMC_LVDSC2, field LVWACK[6] (WORZ)
 366  *
 367  * This write-only field is used to acknowledge low voltage warning errors.
 368  * Write 1 to clear LVWF. Reads always return 0.
 369  */
 370 /*@{*/
 371 #define BP_PMC_LVDSC2_LVWACK (6U)          /*!< Bit position for PMC_LVDSC2_LVWACK. */
 372 #define BM_PMC_LVDSC2_LVWACK (0x40U)       /*!< Bit mask for PMC_LVDSC2_LVWACK. */
 373 #define BS_PMC_LVDSC2_LVWACK (1U)          /*!< Bit field size in bits for PMC_LVDSC2_LVWACK. */
 374
 375 /*! @brief Format value for bitfield PMC_LVDSC2_LVWACK. */
 376 #define BF_PMC_LVDSC2_LVWACK(v) ((uint8_t)((uint8_t)(v) << BP_PMC_LVDSC2_LVWACK) & BM_PMC_LVDSC2_LVWACK)
 377
 378 /*! @brief Set the LVWACK field to a new value. */
 379 #define BW_PMC_LVDSC2_LVWACK(x, v) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWACK) = (v))
 380 /*@}*/
 381
 382 /*!
 383  * @name Register PMC_LVDSC2, field LVWF[7] (RO)
 384  *
 385  * This read-only status field indicates a low-voltage warning event. LVWF is
 386  * set when VSupply transitions below the trip point, or after reset and VSupply is
 387  * already below VLVW. LVWF may be 1 after power-on reset, therefore, to use LVW
 388  * interrupt function, before enabling LVWIE, LVWF must be cleared by writing
 389  * LVWACK first.
 390  *
 391  * Values:
 392  * - 0 - Low-voltage warning event not detected
 393  * - 1 - Low-voltage warning event detected
 394  */
 395 /*@{*/
 396 #define BP_PMC_LVDSC2_LVWF   (7U)          /*!< Bit position for PMC_LVDSC2_LVWF. */
 397 #define BM_PMC_LVDSC2_LVWF   (0x80U)       /*!< Bit mask for PMC_LVDSC2_LVWF. */
 398 #define BS_PMC_LVDSC2_LVWF   (1U)          /*!< Bit field size in bits for PMC_LVDSC2_LVWF. */
 399
 400 /*! @brief Read current value of the PMC_LVDSC2_LVWF field. */
 401 #define BR_PMC_LVDSC2_LVWF(x) (BITBAND_ACCESS8(HW_PMC_LVDSC2_ADDR(x), BP_PMC_LVDSC2_LVWF))
 402 /*@}*/
 403
 404 /*******************************************************************************
 405  * HW_PMC_REGSC - Regulator Status And Control register
 406  ******************************************************************************/
 407
 408 /*!
 409  * @brief HW_PMC_REGSC - Regulator Status And Control register (RW)
 410  *
 411  * Reset value: 0x04U
 412  *
 413  * The PMC contains an internal voltage regulator. The voltage regulator design
 414  * uses a bandgap reference that is also available through a buffer as input to
 415  * certain internal peripherals, such as the CMP and ADC. The internal regulator
 416  * provides a status bit (REGONS) indicating the regulator is in run regulation.
 417  * This register is reset on Chip Reset Not VLLS and by reset types that trigger
 418  * Chip Reset not VLLS. See the Reset section details for more information.
 419  */
 420 typedef union _hw_pmc_regsc
 421 {
 422     uint8_t U;
 423     struct _hw_pmc_regsc_bitfields
 424     {
 425         uint8_t BGBE : 1;              /*!< [0] Bandgap Buffer Enable */
 426         uint8_t RESERVED0 : 1;         /*!< [1]  */
 427         uint8_t REGONS : 1;            /*!< [2] Regulator In Run Regulation Status */
 428         uint8_t ACKISO : 1;            /*!< [3] Acknowledge Isolation */
 429         uint8_t BGEN : 1;              /*!< [4] Bandgap Enable In VLPx Operation */
 430         uint8_t RESERVED1 : 3;         /*!< [7:5]  */
 431     } B;
 432 } hw_pmc_regsc_t;
 433
 434 /*!
 435  * @name Constants and macros for entire PMC_REGSC register
 436  */
 437 /*@{*/
 438 #define HW_PMC_REGSC_ADDR(x)     ((x) + 0x2U)
 439
 440 #define HW_PMC_REGSC(x)          (*(__IO hw_pmc_regsc_t *) HW_PMC_REGSC_ADDR(x))
 441 #define HW_PMC_REGSC_RD(x)       (HW_PMC_REGSC(x).U)
 442 #define HW_PMC_REGSC_WR(x, v)    (HW_PMC_REGSC(x).U = (v))
 443 #define HW_PMC_REGSC_SET(x, v)   (HW_PMC_REGSC_WR(x, HW_PMC_REGSC_RD(x) |  (v)))
 444 #define HW_PMC_REGSC_CLR(x, v)   (HW_PMC_REGSC_WR(x, HW_PMC_REGSC_RD(x) & ~(v)))
 445 #define HW_PMC_REGSC_TOG(x, v)   (HW_PMC_REGSC_WR(x, HW_PMC_REGSC_RD(x) ^  (v)))
 446 /*@}*/
 447
 448 /*
 449  * Constants & macros for individual PMC_REGSC bitfields
 450  */
 451
 452 /*!
 453  * @name Register PMC_REGSC, field BGBE[0] (RW)
 454  *
 455  * Enables the bandgap buffer.
 456  *
 457  * Values:
 458  * - 0 - Bandgap buffer not enabled
 459  * - 1 - Bandgap buffer enabled
 460  */
 461 /*@{*/
 462 #define BP_PMC_REGSC_BGBE    (0U)          /*!< Bit position for PMC_REGSC_BGBE. */
 463 #define BM_PMC_REGSC_BGBE    (0x01U)       /*!< Bit mask for PMC_REGSC_BGBE. */
 464 #define BS_PMC_REGSC_BGBE    (1U)          /*!< Bit field size in bits for PMC_REGSC_BGBE. */
 465
 466 /*! @brief Read current value of the PMC_REGSC_BGBE field. */
 467 #define BR_PMC_REGSC_BGBE(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGBE))
 468
 469 /*! @brief Format value for bitfield PMC_REGSC_BGBE. */
 470 #define BF_PMC_REGSC_BGBE(v) ((uint8_t)((uint8_t)(v) << BP_PMC_REGSC_BGBE) & BM_PMC_REGSC_BGBE)
 471
 472 /*! @brief Set the BGBE field to a new value. */
 473 #define BW_PMC_REGSC_BGBE(x, v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGBE) = (v))
 474 /*@}*/
 475
 476 /*!
 477  * @name Register PMC_REGSC, field REGONS[2] (RO)
 478  *
 479  * This read-only field provides the current status of the internal voltage
 480  * regulator.
 481  *
 482  * Values:
 483  * - 0 - Regulator is in stop regulation or in transition to/from it
 484  * - 1 - Regulator is in run regulation
 485  */
 486 /*@{*/
 487 #define BP_PMC_REGSC_REGONS  (2U)          /*!< Bit position for PMC_REGSC_REGONS. */
 488 #define BM_PMC_REGSC_REGONS  (0x04U)       /*!< Bit mask for PMC_REGSC_REGONS. */
 489 #define BS_PMC_REGSC_REGONS  (1U)          /*!< Bit field size in bits for PMC_REGSC_REGONS. */
 490
 491 /*! @brief Read current value of the PMC_REGSC_REGONS field. */
 492 #define BR_PMC_REGSC_REGONS(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_REGONS))
 493 /*@}*/
 494
 495 /*!
 496  * @name Register PMC_REGSC, field ACKISO[3] (W1C)
 497  *
 498  * Reading this field indicates whether certain peripherals and the I/O pads are
 499  * in a latched state as a result of having been in a VLLS mode. Writing 1 to
 500  * this field when it is set releases the I/O pads and certain peripherals to their
 501  * normal run mode state. After recovering from a VLLS mode, user should restore
 502  * chip configuration before clearing ACKISO. In particular, pin configuration
 503  * for enabled LLWU wakeup pins should be restored to avoid any LLWU flag from
 504  * being falsely set when ACKISO is cleared.
 505  *
 506  * Values:
 507  * - 0 - Peripherals and I/O pads are in normal run state.
 508  * - 1 - Certain peripherals and I/O pads are in an isolated and latched state.
 509  */
 510 /*@{*/
 511 #define BP_PMC_REGSC_ACKISO  (3U)          /*!< Bit position for PMC_REGSC_ACKISO. */
 512 #define BM_PMC_REGSC_ACKISO  (0x08U)       /*!< Bit mask for PMC_REGSC_ACKISO. */
 513 #define BS_PMC_REGSC_ACKISO  (1U)          /*!< Bit field size in bits for PMC_REGSC_ACKISO. */
 514
 515 /*! @brief Read current value of the PMC_REGSC_ACKISO field. */
 516 #define BR_PMC_REGSC_ACKISO(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_ACKISO))
 517
 518 /*! @brief Format value for bitfield PMC_REGSC_ACKISO. */
 519 #define BF_PMC_REGSC_ACKISO(v) ((uint8_t)((uint8_t)(v) << BP_PMC_REGSC_ACKISO) & BM_PMC_REGSC_ACKISO)
 520
 521 /*! @brief Set the ACKISO field to a new value. */
 522 #define BW_PMC_REGSC_ACKISO(x, v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_ACKISO) = (v))
 523 /*@}*/
 524
 525 /*!
 526  * @name Register PMC_REGSC, field BGEN[4] (RW)
 527  *
 528  * BGEN controls whether the bandgap is enabled in lower power modes of
 529  * operation (VLPx, LLS, and VLLSx). When on-chip peripherals require the bandgap voltage
 530  * reference in low power modes of operation, set BGEN to continue to enable the
 531  * bandgap operation. When the bandgap voltage reference is not needed in low
 532  * power modes, clear BGEN to avoid excess power consumption.
 533  *
 534  * Values:
 535  * - 0 - Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.
 536  * - 1 - Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.
 537  */
 538 /*@{*/
 539 #define BP_PMC_REGSC_BGEN    (4U)          /*!< Bit position for PMC_REGSC_BGEN. */
 540 #define BM_PMC_REGSC_BGEN    (0x10U)       /*!< Bit mask for PMC_REGSC_BGEN. */
 541 #define BS_PMC_REGSC_BGEN    (1U)          /*!< Bit field size in bits for PMC_REGSC_BGEN. */
 542
 543 /*! @brief Read current value of the PMC_REGSC_BGEN field. */
 544 #define BR_PMC_REGSC_BGEN(x) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGEN))
 545
 546 /*! @brief Format value for bitfield PMC_REGSC_BGEN. */
 547 #define BF_PMC_REGSC_BGEN(v) ((uint8_t)((uint8_t)(v) << BP_PMC_REGSC_BGEN) & BM_PMC_REGSC_BGEN)
 548
 549 /*! @brief Set the BGEN field to a new value. */
 550 #define BW_PMC_REGSC_BGEN(x, v) (BITBAND_ACCESS8(HW_PMC_REGSC_ADDR(x), BP_PMC_REGSC_BGEN) = (v))
 551 /*@}*/
 552
 553 /*******************************************************************************
 554  * hw_pmc_t - module struct
 555  ******************************************************************************/
 556 /*!
 557  * @brief All PMC module registers.
 558  */
 559 #pragma pack(1)
 560 typedef struct _hw_pmc
 561 {
 562     __IO hw_pmc_lvdsc1_t LVDSC1;           /*!< [0x0] Low Voltage Detect Status And Control 1 register */
 563     __IO hw_pmc_lvdsc2_t LVDSC2;           /*!< [0x1] Low Voltage Detect Status And Control 2 register */
 564     __IO hw_pmc_regsc_t REGSC;             /*!< [0x2] Regulator Status And Control register */
 565 } hw_pmc_t;
 566 #pragma pack()
 567
 568 /*! @brief Macro to access all PMC registers. */
 569 /*! @param x PMC module instance base address. */
 570 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
 571  *     use the '&' operator, like <code>&HW_PMC(PMC_BASE)</code>. */
 572 #define HW_PMC(x)      (*(hw_pmc_t *)(x))
 573
 574 #endif /* __HW_PMC_REGISTERS_H__ */
 575 /* EOF */