tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_rcm.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
   9 **     Version:             rev. 2.5, 2014-02-10
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-08-12)
  48 **         Initial version.
  49 **     - rev. 2.0 (2013-10-29)
  50 **         Register accessor macros added to the memory map.
  51 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  52 **         Startup file for gcc has been updated according to CMSIS 3.2.
  53 **         System initialization updated.
  54 **         MCG - registers updated.
  55 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-09)
  59 **         DMA - EARS register removed.
  60 **         AIPS0, AIPS1 - MPRA register updated.
  61 **     - rev. 2.3 (2014-01-24)
  62 **         Update according to reference manual rev. 2
  63 **         ENET, MCG, MCM, SIM, USB - registers updated
  64 **     - rev. 2.4 (2014-02-10)
  65 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  66 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  67 **     - rev. 2.5 (2014-02-10)
  68 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  69 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  70 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  71 **
  72 ** ###################################################################
  73 */
  74
  75 /*
  76  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  77  *
  78  * This file was generated automatically and any changes may be lost.
  79  */
  80 #ifndef __HW_RCM_REGISTERS_H__
  81 #define __HW_RCM_REGISTERS_H__
  82
  83 #include "MK64F12.h"
  84 #include "fsl_bitaccess.h"
  85
  86 /*
  87  * MK64F12 RCM
  88  *
  89  * Reset Control Module
  90  *
  91  * Registers defined in this header file:
  92  * - HW_RCM_SRS0 - System Reset Status Register 0
  93  * - HW_RCM_SRS1 - System Reset Status Register 1
  94  * - HW_RCM_RPFC - Reset Pin Filter Control register
  95  * - HW_RCM_RPFW - Reset Pin Filter Width register
  96  * - HW_RCM_MR - Mode Register
  97  *
  98  * - hw_rcm_t - Struct containing all module registers.
  99  */
 100
 101 #define HW_RCM_INSTANCE_COUNT (1U) /*!< Number of instances of the RCM module. */
 102
 103 /*******************************************************************************
 104  * HW_RCM_SRS0 - System Reset Status Register 0
 105  ******************************************************************************/
 106
 107 /*!
 108  * @brief HW_RCM_SRS0 - System Reset Status Register 0 (RO)
 109  *
 110  * Reset value: 0x82U
 111  *
 112  * This register includes read-only status flags to indicate the source of the
 113  * most recent reset. The reset state of these bits depends on what caused the MCU
 114  * to reset. The reset value of this register depends on the reset source: POR
 115  * (including LVD) - 0x82 LVD (without POR) - 0x02 VLLS mode wakeup due to RESET
 116  * pin assertion - 0x41 VLLS mode wakeup due to other wakeup sources - 0x01 Other
 117  * reset - a bit is set if its corresponding reset source caused the reset
 118  */
 119 typedef union _hw_rcm_srs0
 120 {
 121     uint8_t U;
 122     struct _hw_rcm_srs0_bitfields
 123     {
 124         uint8_t WAKEUP : 1;            /*!< [0] Low Leakage Wakeup Reset */
 125         uint8_t LVD : 1;               /*!< [1] Low-Voltage Detect Reset */
 126         uint8_t LOC : 1;               /*!< [2] Loss-of-Clock Reset */
 127         uint8_t LOL : 1;               /*!< [3] Loss-of-Lock Reset */
 128         uint8_t RESERVED0 : 1;         /*!< [4]  */
 129         uint8_t WDOGb : 1;             /*!< [5] Watchdog */
 130         uint8_t PIN : 1;               /*!< [6] External Reset Pin */
 131         uint8_t POR : 1;               /*!< [7] Power-On Reset */
 132     } B;
 133 } hw_rcm_srs0_t;
 134
 135 /*!
 136  * @name Constants and macros for entire RCM_SRS0 register
 137  */
 138 /*@{*/
 139 #define HW_RCM_SRS0_ADDR(x)      ((x) + 0x0U)
 140
 141 #define HW_RCM_SRS0(x)           (*(__I hw_rcm_srs0_t *) HW_RCM_SRS0_ADDR(x))
 142 #define HW_RCM_SRS0_RD(x)        (HW_RCM_SRS0(x).U)
 143 /*@}*/
 144
 145 /*
 146  * Constants & macros for individual RCM_SRS0 bitfields
 147  */
 148
 149 /*!
 150  * @name Register RCM_SRS0, field WAKEUP[0] (RO)
 151  *
 152  * Indicates a reset has been caused by an enabled LLWU module wakeup source
 153  * while the chip was in a low leakage mode. In LLS mode, the RESET pin is the only
 154  * wakeup source that can cause this reset. Any enabled wakeup source in a VLLSx
 155  * mode causes a reset. This bit is cleared by any reset except WAKEUP.
 156  *
 157  * Values:
 158  * - 0 - Reset not caused by LLWU module wakeup source
 159  * - 1 - Reset caused by LLWU module wakeup source
 160  */
 161 /*@{*/
 162 #define BP_RCM_SRS0_WAKEUP   (0U)          /*!< Bit position for RCM_SRS0_WAKEUP. */
 163 #define BM_RCM_SRS0_WAKEUP   (0x01U)       /*!< Bit mask for RCM_SRS0_WAKEUP. */
 164 #define BS_RCM_SRS0_WAKEUP   (1U)          /*!< Bit field size in bits for RCM_SRS0_WAKEUP. */
 165
 166 /*! @brief Read current value of the RCM_SRS0_WAKEUP field. */
 167 #define BR_RCM_SRS0_WAKEUP(x) (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_WAKEUP))
 168 /*@}*/
 169
 170 /*!
 171  * @name Register RCM_SRS0, field LVD[1] (RO)
 172  *
 173  * If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage,
 174  * an LVD reset occurs. This field is also set by POR.
 175  *
 176  * Values:
 177  * - 0 - Reset not caused by LVD trip or POR
 178  * - 1 - Reset caused by LVD trip or POR
 179  */
 180 /*@{*/
 181 #define BP_RCM_SRS0_LVD      (1U)          /*!< Bit position for RCM_SRS0_LVD. */
 182 #define BM_RCM_SRS0_LVD      (0x02U)       /*!< Bit mask for RCM_SRS0_LVD. */
 183 #define BS_RCM_SRS0_LVD      (1U)          /*!< Bit field size in bits for RCM_SRS0_LVD. */
 184
 185 /*! @brief Read current value of the RCM_SRS0_LVD field. */
 186 #define BR_RCM_SRS0_LVD(x)   (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_LVD))
 187 /*@}*/
 188
 189 /*!
 190  * @name Register RCM_SRS0, field LOC[2] (RO)
 191  *
 192  * Indicates a reset has been caused by a loss of external clock. The MCG clock
 193  * monitor must be enabled for a loss of clock to be detected. Refer to the
 194  * detailed MCG description for information on enabling the clock monitor.
 195  *
 196  * Values:
 197  * - 0 - Reset not caused by a loss of external clock.
 198  * - 1 - Reset caused by a loss of external clock.
 199  */
 200 /*@{*/
 201 #define BP_RCM_SRS0_LOC      (2U)          /*!< Bit position for RCM_SRS0_LOC. */
 202 #define BM_RCM_SRS0_LOC      (0x04U)       /*!< Bit mask for RCM_SRS0_LOC. */
 203 #define BS_RCM_SRS0_LOC      (1U)          /*!< Bit field size in bits for RCM_SRS0_LOC. */
 204
 205 /*! @brief Read current value of the RCM_SRS0_LOC field. */
 206 #define BR_RCM_SRS0_LOC(x)   (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_LOC))
 207 /*@}*/
 208
 209 /*!
 210  * @name Register RCM_SRS0, field LOL[3] (RO)
 211  *
 212  * Indicates a reset has been caused by a loss of lock in the MCG PLL. See the
 213  * MCG description for information on the loss-of-clock event.
 214  *
 215  * Values:
 216  * - 0 - Reset not caused by a loss of lock in the PLL
 217  * - 1 - Reset caused by a loss of lock in the PLL
 218  */
 219 /*@{*/
 220 #define BP_RCM_SRS0_LOL      (3U)          /*!< Bit position for RCM_SRS0_LOL. */
 221 #define BM_RCM_SRS0_LOL      (0x08U)       /*!< Bit mask for RCM_SRS0_LOL. */
 222 #define BS_RCM_SRS0_LOL      (1U)          /*!< Bit field size in bits for RCM_SRS0_LOL. */
 223
 224 /*! @brief Read current value of the RCM_SRS0_LOL field. */
 225 #define BR_RCM_SRS0_LOL(x)   (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_LOL))
 226 /*@}*/
 227
 228 /*!
 229  * @name Register RCM_SRS0, field WDOG[5] (RO)
 230  *
 231  * Indicates a reset has been caused by the watchdog timer Computer Operating
 232  * Properly (COP) timing out. This reset source can be blocked by disabling the COP
 233  * watchdog: write 00 to SIM_COPCTRL[COPT].
 234  *
 235  * Values:
 236  * - 0 - Reset not caused by watchdog timeout
 237  * - 1 - Reset caused by watchdog timeout
 238  */
 239 /*@{*/
 240 #define BP_RCM_SRS0_WDOG     (5U)          /*!< Bit position for RCM_SRS0_WDOG. */
 241 #define BM_RCM_SRS0_WDOG     (0x20U)       /*!< Bit mask for RCM_SRS0_WDOG. */
 242 #define BS_RCM_SRS0_WDOG     (1U)          /*!< Bit field size in bits for RCM_SRS0_WDOG. */
 243
 244 /*! @brief Read current value of the RCM_SRS0_WDOG field. */
 245 #define BR_RCM_SRS0_WDOG(x)  (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_WDOG))
 246 /*@}*/
 247
 248 /*!
 249  * @name Register RCM_SRS0, field PIN[6] (RO)
 250  *
 251  * Indicates a reset has been caused by an active-low level on the external
 252  * RESET pin.
 253  *
 254  * Values:
 255  * - 0 - Reset not caused by external reset pin
 256  * - 1 - Reset caused by external reset pin
 257  */
 258 /*@{*/
 259 #define BP_RCM_SRS0_PIN      (6U)          /*!< Bit position for RCM_SRS0_PIN. */
 260 #define BM_RCM_SRS0_PIN      (0x40U)       /*!< Bit mask for RCM_SRS0_PIN. */
 261 #define BS_RCM_SRS0_PIN      (1U)          /*!< Bit field size in bits for RCM_SRS0_PIN. */
 262
 263 /*! @brief Read current value of the RCM_SRS0_PIN field. */
 264 #define BR_RCM_SRS0_PIN(x)   (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_PIN))
 265 /*@}*/
 266
 267 /*!
 268  * @name Register RCM_SRS0, field POR[7] (RO)
 269  *
 270  * Indicates a reset has been caused by the power-on detection logic. Because
 271  * the internal supply voltage was ramping up at the time, the low-voltage reset
 272  * (LVD) status bit is also set to indicate that the reset occurred while the
 273  * internal supply was below the LVD threshold.
 274  *
 275  * Values:
 276  * - 0 - Reset not caused by POR
 277  * - 1 - Reset caused by POR
 278  */
 279 /*@{*/
 280 #define BP_RCM_SRS0_POR      (7U)          /*!< Bit position for RCM_SRS0_POR. */
 281 #define BM_RCM_SRS0_POR      (0x80U)       /*!< Bit mask for RCM_SRS0_POR. */
 282 #define BS_RCM_SRS0_POR      (1U)          /*!< Bit field size in bits for RCM_SRS0_POR. */
 283
 284 /*! @brief Read current value of the RCM_SRS0_POR field. */
 285 #define BR_RCM_SRS0_POR(x)   (BITBAND_ACCESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_POR))
 286 /*@}*/
 287
 288 /*******************************************************************************
 289  * HW_RCM_SRS1 - System Reset Status Register 1
 290  ******************************************************************************/
 291
 292 /*!
 293  * @brief HW_RCM_SRS1 - System Reset Status Register 1 (RO)
 294  *
 295  * Reset value: 0x00U
 296  *
 297  * This register includes read-only status flags to indicate the source of the
 298  * most recent reset. The reset state of these bits depends on what caused the MCU
 299  * to reset. The reset value of this register depends on the reset source: POR
 300  * (including LVD) - 0x00 LVD (without POR) - 0x00 VLLS mode wakeup - 0x00 Other
 301  * reset - a bit is set if its corresponding reset source caused the reset
 302  */
 303 typedef union _hw_rcm_srs1
 304 {
 305     uint8_t U;
 306     struct _hw_rcm_srs1_bitfields
 307     {
 308         uint8_t JTAG : 1;              /*!< [0] JTAG Generated Reset */
 309         uint8_t LOCKUP : 1;            /*!< [1] Core Lockup */
 310         uint8_t SW : 1;                /*!< [2] Software */
 311         uint8_t MDM_AP : 1;            /*!< [3] MDM-AP System Reset Request */
 312         uint8_t EZPT : 1;              /*!< [4] EzPort Reset */
 313         uint8_t SACKERR : 1;           /*!< [5] Stop Mode Acknowledge Error Reset */
 314         uint8_t RESERVED0 : 2;         /*!< [7:6]  */
 315     } B;
 316 } hw_rcm_srs1_t;
 317
 318 /*!
 319  * @name Constants and macros for entire RCM_SRS1 register
 320  */
 321 /*@{*/
 322 #define HW_RCM_SRS1_ADDR(x)      ((x) + 0x1U)
 323
 324 #define HW_RCM_SRS1(x)           (*(__I hw_rcm_srs1_t *) HW_RCM_SRS1_ADDR(x))
 325 #define HW_RCM_SRS1_RD(x)        (HW_RCM_SRS1(x).U)
 326 /*@}*/
 327
 328 /*
 329  * Constants & macros for individual RCM_SRS1 bitfields
 330  */
 331
 332 /*!
 333  * @name Register RCM_SRS1, field JTAG[0] (RO)
 334  *
 335  * Indicates a reset has been caused by JTAG selection of certain IR codes:
 336  * EZPORT, EXTEST, HIGHZ, and CLAMP.
 337  *
 338  * Values:
 339  * - 0 - Reset not caused by JTAG
 340  * - 1 - Reset caused by JTAG
 341  */
 342 /*@{*/
 343 #define BP_RCM_SRS1_JTAG     (0U)          /*!< Bit position for RCM_SRS1_JTAG. */
 344 #define BM_RCM_SRS1_JTAG     (0x01U)       /*!< Bit mask for RCM_SRS1_JTAG. */
 345 #define BS_RCM_SRS1_JTAG     (1U)          /*!< Bit field size in bits for RCM_SRS1_JTAG. */
 346
 347 /*! @brief Read current value of the RCM_SRS1_JTAG field. */
 348 #define BR_RCM_SRS1_JTAG(x)  (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_JTAG))
 349 /*@}*/
 350
 351 /*!
 352  * @name Register RCM_SRS1, field LOCKUP[1] (RO)
 353  *
 354  * Indicates a reset has been caused by the ARM core indication of a LOCKUP
 355  * event.
 356  *
 357  * Values:
 358  * - 0 - Reset not caused by core LOCKUP event
 359  * - 1 - Reset caused by core LOCKUP event
 360  */
 361 /*@{*/
 362 #define BP_RCM_SRS1_LOCKUP   (1U)          /*!< Bit position for RCM_SRS1_LOCKUP. */
 363 #define BM_RCM_SRS1_LOCKUP   (0x02U)       /*!< Bit mask for RCM_SRS1_LOCKUP. */
 364 #define BS_RCM_SRS1_LOCKUP   (1U)          /*!< Bit field size in bits for RCM_SRS1_LOCKUP. */
 365
 366 /*! @brief Read current value of the RCM_SRS1_LOCKUP field. */
 367 #define BR_RCM_SRS1_LOCKUP(x) (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_LOCKUP))
 368 /*@}*/
 369
 370 /*!
 371  * @name Register RCM_SRS1, field SW[2] (RO)
 372  *
 373  * Indicates a reset has been caused by software setting of SYSRESETREQ bit in
 374  * Application Interrupt and Reset Control Register in the ARM core.
 375  *
 376  * Values:
 377  * - 0 - Reset not caused by software setting of SYSRESETREQ bit
 378  * - 1 - Reset caused by software setting of SYSRESETREQ bit
 379  */
 380 /*@{*/
 381 #define BP_RCM_SRS1_SW       (2U)          /*!< Bit position for RCM_SRS1_SW. */
 382 #define BM_RCM_SRS1_SW       (0x04U)       /*!< Bit mask for RCM_SRS1_SW. */
 383 #define BS_RCM_SRS1_SW       (1U)          /*!< Bit field size in bits for RCM_SRS1_SW. */
 384
 385 /*! @brief Read current value of the RCM_SRS1_SW field. */
 386 #define BR_RCM_SRS1_SW(x)    (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_SW))
 387 /*@}*/
 388
 389 /*!
 390  * @name Register RCM_SRS1, field MDM_AP[3] (RO)
 391  *
 392  * Indicates a reset has been caused by the host debugger system setting of the
 393  * System Reset Request bit in the MDM-AP Control Register.
 394  *
 395  * Values:
 396  * - 0 - Reset not caused by host debugger system setting of the System Reset
 397  *     Request bit
 398  * - 1 - Reset caused by host debugger system setting of the System Reset
 399  *     Request bit
 400  */
 401 /*@{*/
 402 #define BP_RCM_SRS1_MDM_AP   (3U)          /*!< Bit position for RCM_SRS1_MDM_AP. */
 403 #define BM_RCM_SRS1_MDM_AP   (0x08U)       /*!< Bit mask for RCM_SRS1_MDM_AP. */
 404 #define BS_RCM_SRS1_MDM_AP   (1U)          /*!< Bit field size in bits for RCM_SRS1_MDM_AP. */
 405
 406 /*! @brief Read current value of the RCM_SRS1_MDM_AP field. */
 407 #define BR_RCM_SRS1_MDM_AP(x) (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_MDM_AP))
 408 /*@}*/
 409
 410 /*!
 411  * @name Register RCM_SRS1, field EZPT[4] (RO)
 412  *
 413  * Indicates a reset has been caused by EzPort receiving the RESET command while
 414  * the device is in EzPort mode.
 415  *
 416  * Values:
 417  * - 0 - Reset not caused by EzPort receiving the RESET command while the device
 418  *     is in EzPort mode
 419  * - 1 - Reset caused by EzPort receiving the RESET command while the device is
 420  *     in EzPort mode
 421  */
 422 /*@{*/
 423 #define BP_RCM_SRS1_EZPT     (4U)          /*!< Bit position for RCM_SRS1_EZPT. */
 424 #define BM_RCM_SRS1_EZPT     (0x10U)       /*!< Bit mask for RCM_SRS1_EZPT. */
 425 #define BS_RCM_SRS1_EZPT     (1U)          /*!< Bit field size in bits for RCM_SRS1_EZPT. */
 426
 427 /*! @brief Read current value of the RCM_SRS1_EZPT field. */
 428 #define BR_RCM_SRS1_EZPT(x)  (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_EZPT))
 429 /*@}*/
 430
 431 /*!
 432  * @name Register RCM_SRS1, field SACKERR[5] (RO)
 433  *
 434  * Indicates that after an attempt to enter Stop mode, a reset has been caused
 435  * by a failure of one or more peripherals to acknowledge within approximately one
 436  * second to enter stop mode.
 437  *
 438  * Values:
 439  * - 0 - Reset not caused by peripheral failure to acknowledge attempt to enter
 440  *     stop mode
 441  * - 1 - Reset caused by peripheral failure to acknowledge attempt to enter stop
 442  *     mode
 443  */
 444 /*@{*/
 445 #define BP_RCM_SRS1_SACKERR  (5U)          /*!< Bit position for RCM_SRS1_SACKERR. */
 446 #define BM_RCM_SRS1_SACKERR  (0x20U)       /*!< Bit mask for RCM_SRS1_SACKERR. */
 447 #define BS_RCM_SRS1_SACKERR  (1U)          /*!< Bit field size in bits for RCM_SRS1_SACKERR. */
 448
 449 /*! @brief Read current value of the RCM_SRS1_SACKERR field. */
 450 #define BR_RCM_SRS1_SACKERR(x) (BITBAND_ACCESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_SACKERR))
 451 /*@}*/
 452
 453 /*******************************************************************************
 454  * HW_RCM_RPFC - Reset Pin Filter Control register
 455  ******************************************************************************/
 456
 457 /*!
 458  * @brief HW_RCM_RPFC - Reset Pin Filter Control register (RW)
 459  *
 460  * Reset value: 0x00U
 461  *
 462  * The reset values of bits 2-0 are for Chip POR only. They are unaffected by
 463  * other reset types. The bus clock filter is reset when disabled or when entering
 464  * stop mode. The LPO filter is reset when disabled or when entering any low
 465  * leakage stop mode .
 466  */
 467 typedef union _hw_rcm_rpfc
 468 {
 469     uint8_t U;
 470     struct _hw_rcm_rpfc_bitfields
 471     {
 472         uint8_t RSTFLTSRW : 2;         /*!< [1:0] Reset Pin Filter Select in Run and
 473                                         * Wait Modes */
 474         uint8_t RSTFLTSS : 1;          /*!< [2] Reset Pin Filter Select in Stop Mode */
 475         uint8_t RESERVED0 : 5;         /*!< [7:3]  */
 476     } B;
 477 } hw_rcm_rpfc_t;
 478
 479 /*!
 480  * @name Constants and macros for entire RCM_RPFC register
 481  */
 482 /*@{*/
 483 #define HW_RCM_RPFC_ADDR(x)      ((x) + 0x4U)
 484
 485 #define HW_RCM_RPFC(x)           (*(__IO hw_rcm_rpfc_t *) HW_RCM_RPFC_ADDR(x))
 486 #define HW_RCM_RPFC_RD(x)        (HW_RCM_RPFC(x).U)
 487 #define HW_RCM_RPFC_WR(x, v)     (HW_RCM_RPFC(x).U = (v))
 488 #define HW_RCM_RPFC_SET(x, v)    (HW_RCM_RPFC_WR(x, HW_RCM_RPFC_RD(x) |  (v)))
 489 #define HW_RCM_RPFC_CLR(x, v)    (HW_RCM_RPFC_WR(x, HW_RCM_RPFC_RD(x) & ~(v)))
 490 #define HW_RCM_RPFC_TOG(x, v)    (HW_RCM_RPFC_WR(x, HW_RCM_RPFC_RD(x) ^  (v)))
 491 /*@}*/
 492
 493 /*
 494  * Constants & macros for individual RCM_RPFC bitfields
 495  */
 496
 497 /*!
 498  * @name Register RCM_RPFC, field RSTFLTSRW[1:0] (RW)
 499  *
 500  * Selects how the reset pin filter is enabled in run and wait modes.
 501  *
 502  * Values:
 503  * - 00 - All filtering disabled
 504  * - 01 - Bus clock filter enabled for normal operation
 505  * - 10 - LPO clock filter enabled for normal operation
 506  * - 11 - Reserved
 507  */
 508 /*@{*/
 509 #define BP_RCM_RPFC_RSTFLTSRW (0U)         /*!< Bit position for RCM_RPFC_RSTFLTSRW. */
 510 #define BM_RCM_RPFC_RSTFLTSRW (0x03U)      /*!< Bit mask for RCM_RPFC_RSTFLTSRW. */
 511 #define BS_RCM_RPFC_RSTFLTSRW (2U)         /*!< Bit field size in bits for RCM_RPFC_RSTFLTSRW. */
 512
 513 /*! @brief Read current value of the RCM_RPFC_RSTFLTSRW field. */
 514 #define BR_RCM_RPFC_RSTFLTSRW(x) (HW_RCM_RPFC(x).B.RSTFLTSRW)
 515
 516 /*! @brief Format value for bitfield RCM_RPFC_RSTFLTSRW. */
 517 #define BF_RCM_RPFC_RSTFLTSRW(v) ((uint8_t)((uint8_t)(v) << BP_RCM_RPFC_RSTFLTSRW) & BM_RCM_RPFC_RSTFLTSRW)
 518
 519 /*! @brief Set the RSTFLTSRW field to a new value. */
 520 #define BW_RCM_RPFC_RSTFLTSRW(x, v) (HW_RCM_RPFC_WR(x, (HW_RCM_RPFC_RD(x) & ~BM_RCM_RPFC_RSTFLTSRW) | BF_RCM_RPFC_RSTFLTSRW(v)))
 521 /*@}*/
 522
 523 /*!
 524  * @name Register RCM_RPFC, field RSTFLTSS[2] (RW)
 525  *
 526  * Selects how the reset pin filter is enabled in Stop and VLPS modes
 527  *
 528  * Values:
 529  * - 0 - All filtering disabled
 530  * - 1 - LPO clock filter enabled
 531  */
 532 /*@{*/
 533 #define BP_RCM_RPFC_RSTFLTSS (2U)          /*!< Bit position for RCM_RPFC_RSTFLTSS. */
 534 #define BM_RCM_RPFC_RSTFLTSS (0x04U)       /*!< Bit mask for RCM_RPFC_RSTFLTSS. */
 535 #define BS_RCM_RPFC_RSTFLTSS (1U)          /*!< Bit field size in bits for RCM_RPFC_RSTFLTSS. */
 536
 537 /*! @brief Read current value of the RCM_RPFC_RSTFLTSS field. */
 538 #define BR_RCM_RPFC_RSTFLTSS(x) (BITBAND_ACCESS8(HW_RCM_RPFC_ADDR(x), BP_RCM_RPFC_RSTFLTSS))
 539
 540 /*! @brief Format value for bitfield RCM_RPFC_RSTFLTSS. */
 541 #define BF_RCM_RPFC_RSTFLTSS(v) ((uint8_t)((uint8_t)(v) << BP_RCM_RPFC_RSTFLTSS) & BM_RCM_RPFC_RSTFLTSS)
 542
 543 /*! @brief Set the RSTFLTSS field to a new value. */
 544 #define BW_RCM_RPFC_RSTFLTSS(x, v) (BITBAND_ACCESS8(HW_RCM_RPFC_ADDR(x), BP_RCM_RPFC_RSTFLTSS) = (v))
 545 /*@}*/
 546
 547 /*******************************************************************************
 548  * HW_RCM_RPFW - Reset Pin Filter Width register
 549  ******************************************************************************/
 550
 551 /*!
 552  * @brief HW_RCM_RPFW - Reset Pin Filter Width register (RW)
 553  *
 554  * Reset value: 0x00U
 555  *
 556  * The reset values of the bits in the RSTFLTSEL field are for Chip POR only.
 557  * They are unaffected by other reset types.
 558  */
 559 typedef union _hw_rcm_rpfw
 560 {
 561     uint8_t U;
 562     struct _hw_rcm_rpfw_bitfields
 563     {
 564         uint8_t RSTFLTSEL : 5;         /*!< [4:0] Reset Pin Filter Bus Clock Select */
 565         uint8_t RESERVED0 : 3;         /*!< [7:5]  */
 566     } B;
 567 } hw_rcm_rpfw_t;
 568
 569 /*!
 570  * @name Constants and macros for entire RCM_RPFW register
 571  */
 572 /*@{*/
 573 #define HW_RCM_RPFW_ADDR(x)      ((x) + 0x5U)
 574
 575 #define HW_RCM_RPFW(x)           (*(__IO hw_rcm_rpfw_t *) HW_RCM_RPFW_ADDR(x))
 576 #define HW_RCM_RPFW_RD(x)        (HW_RCM_RPFW(x).U)
 577 #define HW_RCM_RPFW_WR(x, v)     (HW_RCM_RPFW(x).U = (v))
 578 #define HW_RCM_RPFW_SET(x, v)    (HW_RCM_RPFW_WR(x, HW_RCM_RPFW_RD(x) |  (v)))
 579 #define HW_RCM_RPFW_CLR(x, v)    (HW_RCM_RPFW_WR(x, HW_RCM_RPFW_RD(x) & ~(v)))
 580 #define HW_RCM_RPFW_TOG(x, v)    (HW_RCM_RPFW_WR(x, HW_RCM_RPFW_RD(x) ^  (v)))
 581 /*@}*/
 582
 583 /*
 584  * Constants & macros for individual RCM_RPFW bitfields
 585  */
 586
 587 /*!
 588  * @name Register RCM_RPFW, field RSTFLTSEL[4:0] (RW)
 589  *
 590  * Selects the reset pin bus clock filter width.
 591  *
 592  * Values:
 593  * - 00000 - Bus clock filter count is 1
 594  * - 00001 - Bus clock filter count is 2
 595  * - 00010 - Bus clock filter count is 3
 596  * - 00011 - Bus clock filter count is 4
 597  * - 00100 - Bus clock filter count is 5
 598  * - 00101 - Bus clock filter count is 6
 599  * - 00110 - Bus clock filter count is 7
 600  * - 00111 - Bus clock filter count is 8
 601  * - 01000 - Bus clock filter count is 9
 602  * - 01001 - Bus clock filter count is 10
 603  * - 01010 - Bus clock filter count is 11
 604  * - 01011 - Bus clock filter count is 12
 605  * - 01100 - Bus clock filter count is 13
 606  * - 01101 - Bus clock filter count is 14
 607  * - 01110 - Bus clock filter count is 15
 608  * - 01111 - Bus clock filter count is 16
 609  * - 10000 - Bus clock filter count is 17
 610  * - 10001 - Bus clock filter count is 18
 611  * - 10010 - Bus clock filter count is 19
 612  * - 10011 - Bus clock filter count is 20
 613  * - 10100 - Bus clock filter count is 21
 614  * - 10101 - Bus clock filter count is 22
 615  * - 10110 - Bus clock filter count is 23
 616  * - 10111 - Bus clock filter count is 24
 617  * - 11000 - Bus clock filter count is 25
 618  * - 11001 - Bus clock filter count is 26
 619  * - 11010 - Bus clock filter count is 27
 620  * - 11011 - Bus clock filter count is 28
 621  * - 11100 - Bus clock filter count is 29
 622  * - 11101 - Bus clock filter count is 30
 623  * - 11110 - Bus clock filter count is 31
 624  * - 11111 - Bus clock filter count is 32
 625  */
 626 /*@{*/
 627 #define BP_RCM_RPFW_RSTFLTSEL (0U)         /*!< Bit position for RCM_RPFW_RSTFLTSEL. */
 628 #define BM_RCM_RPFW_RSTFLTSEL (0x1FU)      /*!< Bit mask for RCM_RPFW_RSTFLTSEL. */
 629 #define BS_RCM_RPFW_RSTFLTSEL (5U)         /*!< Bit field size in bits for RCM_RPFW_RSTFLTSEL. */
 630
 631 /*! @brief Read current value of the RCM_RPFW_RSTFLTSEL field. */
 632 #define BR_RCM_RPFW_RSTFLTSEL(x) (HW_RCM_RPFW(x).B.RSTFLTSEL)
 633
 634 /*! @brief Format value for bitfield RCM_RPFW_RSTFLTSEL. */
 635 #define BF_RCM_RPFW_RSTFLTSEL(v) ((uint8_t)((uint8_t)(v) << BP_RCM_RPFW_RSTFLTSEL) & BM_RCM_RPFW_RSTFLTSEL)
 636
 637 /*! @brief Set the RSTFLTSEL field to a new value. */
 638 #define BW_RCM_RPFW_RSTFLTSEL(x, v) (HW_RCM_RPFW_WR(x, (HW_RCM_RPFW_RD(x) & ~BM_RCM_RPFW_RSTFLTSEL) | BF_RCM_RPFW_RSTFLTSEL(v)))
 639 /*@}*/
 640
 641 /*******************************************************************************
 642  * HW_RCM_MR - Mode Register
 643  ******************************************************************************/
 644
 645 /*!
 646  * @brief HW_RCM_MR - Mode Register (RO)
 647  *
 648  * Reset value: 0x00U
 649  *
 650  * This register includes read-only status flags to indicate the state of the
 651  * mode pins during the last Chip Reset.
 652  */
 653 typedef union _hw_rcm_mr
 654 {
 655     uint8_t U;
 656     struct _hw_rcm_mr_bitfields
 657     {
 658         uint8_t RESERVED0 : 1;         /*!< [0]  */
 659         uint8_t EZP_MS : 1;            /*!< [1] EZP_MS_B pin state */
 660         uint8_t RESERVED1 : 6;         /*!< [7:2]  */
 661     } B;
 662 } hw_rcm_mr_t;
 663
 664 /*!
 665  * @name Constants and macros for entire RCM_MR register
 666  */
 667 /*@{*/
 668 #define HW_RCM_MR_ADDR(x)        ((x) + 0x7U)
 669
 670 #define HW_RCM_MR(x)             (*(__I hw_rcm_mr_t *) HW_RCM_MR_ADDR(x))
 671 #define HW_RCM_MR_RD(x)          (HW_RCM_MR(x).U)
 672 /*@}*/
 673
 674 /*
 675  * Constants & macros for individual RCM_MR bitfields
 676  */
 677
 678 /*!
 679  * @name Register RCM_MR, field EZP_MS[1] (RO)
 680  *
 681  * Reflects the state of the EZP_MS pin during the last Chip Reset
 682  *
 683  * Values:
 684  * - 0 - Pin deasserted (logic 1)
 685  * - 1 - Pin asserted (logic 0)
 686  */
 687 /*@{*/
 688 #define BP_RCM_MR_EZP_MS     (1U)          /*!< Bit position for RCM_MR_EZP_MS. */
 689 #define BM_RCM_MR_EZP_MS     (0x02U)       /*!< Bit mask for RCM_MR_EZP_MS. */
 690 #define BS_RCM_MR_EZP_MS     (1U)          /*!< Bit field size in bits for RCM_MR_EZP_MS. */
 691
 692 /*! @brief Read current value of the RCM_MR_EZP_MS field. */
 693 #define BR_RCM_MR_EZP_MS(x)  (BITBAND_ACCESS8(HW_RCM_MR_ADDR(x), BP_RCM_MR_EZP_MS))
 694 /*@}*/
 695
 696 /*******************************************************************************
 697  * hw_rcm_t - module struct
 698  ******************************************************************************/
 699 /*!
 700  * @brief All RCM module registers.
 701  */
 702 #pragma pack(1)
 703 typedef struct _hw_rcm
 704 {
 705     __I hw_rcm_srs0_t SRS0;                /*!< [0x0] System Reset Status Register 0 */
 706     __I hw_rcm_srs1_t SRS1;                /*!< [0x1] System Reset Status Register 1 */
 707     uint8_t _reserved0[2];
 708     __IO hw_rcm_rpfc_t RPFC;               /*!< [0x4] Reset Pin Filter Control register */
 709     __IO hw_rcm_rpfw_t RPFW;               /*!< [0x5] Reset Pin Filter Width register */
 710     uint8_t _reserved1[1];
 711     __I hw_rcm_mr_t MR;                    /*!< [0x7] Mode Register */
 712 } hw_rcm_t;
 713 #pragma pack()
 714
 715 /*! @brief Macro to access all RCM registers. */
 716 /*! @param x RCM module instance base address. */
 717 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
 718  *     use the '&' operator, like <code>&HW_RCM(RCM_BASE)</code>. */
 719 #define HW_RCM(x)      (*(hw_rcm_t *)(x))
 720
 721 #endif /* __HW_RCM_REGISTERS_H__ */
 722 /* EOF */