tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_rng.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
   9 **     Version:             rev. 2.5, 2014-02-10
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-08-12)
  48 **         Initial version.
  49 **     - rev. 2.0 (2013-10-29)
  50 **         Register accessor macros added to the memory map.
  51 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  52 **         Startup file for gcc has been updated according to CMSIS 3.2.
  53 **         System initialization updated.
  54 **         MCG - registers updated.
  55 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-09)
  59 **         DMA - EARS register removed.
  60 **         AIPS0, AIPS1 - MPRA register updated.
  61 **     - rev. 2.3 (2014-01-24)
  62 **         Update according to reference manual rev. 2
  63 **         ENET, MCG, MCM, SIM, USB - registers updated
  64 **     - rev. 2.4 (2014-02-10)
  65 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  66 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  67 **     - rev. 2.5 (2014-02-10)
  68 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  69 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  70 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  71 **
  72 ** ###################################################################
  73 */
  74
  75 /*
  76  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  77  *
  78  * This file was generated automatically and any changes may be lost.
  79  */
  80 #ifndef __HW_RNG_REGISTERS_H__
  81 #define __HW_RNG_REGISTERS_H__
  82
  83 #include "MK64F12.h"
  84 #include "fsl_bitaccess.h"
  85
  86 /*
  87  * MK64F12 RNG
  88  *
  89  * Random Number Generator Accelerator
  90  *
  91  * Registers defined in this header file:
  92  * - HW_RNG_CR - RNGA Control Register
  93  * - HW_RNG_SR - RNGA Status Register
  94  * - HW_RNG_ER - RNGA Entropy Register
  95  * - HW_RNG_OR - RNGA Output Register
  96  *
  97  * - hw_rng_t - Struct containing all module registers.
  98  */
  99
 100 #define HW_RNG_INSTANCE_COUNT (1U) /*!< Number of instances of the RNG module. */
 101
 102 /*******************************************************************************
 103  * HW_RNG_CR - RNGA Control Register
 104  ******************************************************************************/
 105
 106 /*!
 107  * @brief HW_RNG_CR - RNGA Control Register (RW)
 108  *
 109  * Reset value: 0x00000000U
 110  *
 111  * Controls the operation of RNGA.
 112  */
 113 typedef union _hw_rng_cr
 114 {
 115     uint32_t U;
 116     struct _hw_rng_cr_bitfields
 117     {
 118         uint32_t GO : 1;               /*!< [0] Go */
 119         uint32_t HA : 1;               /*!< [1] High Assurance */
 120         uint32_t INTM : 1;             /*!< [2] Interrupt Mask */
 121         uint32_t CLRI : 1;             /*!< [3] Clear Interrupt */
 122         uint32_t SLP : 1;              /*!< [4] Sleep */
 123         uint32_t RESERVED0 : 27;       /*!< [31:5]  */
 124     } B;
 125 } hw_rng_cr_t;
 126
 127 /*!
 128  * @name Constants and macros for entire RNG_CR register
 129  */
 130 /*@{*/
 131 #define HW_RNG_CR_ADDR(x)        ((x) + 0x0U)
 132
 133 #define HW_RNG_CR(x)             (*(__IO hw_rng_cr_t *) HW_RNG_CR_ADDR(x))
 134 #define HW_RNG_CR_RD(x)          (HW_RNG_CR(x).U)
 135 #define HW_RNG_CR_WR(x, v)       (HW_RNG_CR(x).U = (v))
 136 #define HW_RNG_CR_SET(x, v)      (HW_RNG_CR_WR(x, HW_RNG_CR_RD(x) |  (v)))
 137 #define HW_RNG_CR_CLR(x, v)      (HW_RNG_CR_WR(x, HW_RNG_CR_RD(x) & ~(v)))
 138 #define HW_RNG_CR_TOG(x, v)      (HW_RNG_CR_WR(x, HW_RNG_CR_RD(x) ^  (v)))
 139 /*@}*/
 140
 141 /*
 142  * Constants & macros for individual RNG_CR bitfields
 143  */
 144
 145 /*!
 146  * @name Register RNG_CR, field GO[0] (RW)
 147  *
 148  * Specifies whether random-data generation and loading (into OR[RANDOUT]) is
 149  * enabled.This field is sticky. You must reset RNGA to stop RNGA from loading
 150  * OR[RANDOUT] with data.
 151  *
 152  * Values:
 153  * - 0 - Disabled
 154  * - 1 - Enabled
 155  */
 156 /*@{*/
 157 #define BP_RNG_CR_GO         (0U)          /*!< Bit position for RNG_CR_GO. */
 158 #define BM_RNG_CR_GO         (0x00000001U) /*!< Bit mask for RNG_CR_GO. */
 159 #define BS_RNG_CR_GO         (1U)          /*!< Bit field size in bits for RNG_CR_GO. */
 160
 161 /*! @brief Read current value of the RNG_CR_GO field. */
 162 #define BR_RNG_CR_GO(x)      (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_GO))
 163
 164 /*! @brief Format value for bitfield RNG_CR_GO. */
 165 #define BF_RNG_CR_GO(v)      ((uint32_t)((uint32_t)(v) << BP_RNG_CR_GO) & BM_RNG_CR_GO)
 166
 167 /*! @brief Set the GO field to a new value. */
 168 #define BW_RNG_CR_GO(x, v)   (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_GO) = (v))
 169 /*@}*/
 170
 171 /*!
 172  * @name Register RNG_CR, field HA[1] (RW)
 173  *
 174  * Enables notification of security violations (via SR[SECV]). A security
 175  * violation occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0. This field is sticky.
 176  * After enabling notification of security violations, you must reset RNGA to
 177  * disable them again.
 178  *
 179  * Values:
 180  * - 0 - Disabled
 181  * - 1 - Enabled
 182  */
 183 /*@{*/
 184 #define BP_RNG_CR_HA         (1U)          /*!< Bit position for RNG_CR_HA. */
 185 #define BM_RNG_CR_HA         (0x00000002U) /*!< Bit mask for RNG_CR_HA. */
 186 #define BS_RNG_CR_HA         (1U)          /*!< Bit field size in bits for RNG_CR_HA. */
 187
 188 /*! @brief Read current value of the RNG_CR_HA field. */
 189 #define BR_RNG_CR_HA(x)      (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_HA))
 190
 191 /*! @brief Format value for bitfield RNG_CR_HA. */
 192 #define BF_RNG_CR_HA(v)      ((uint32_t)((uint32_t)(v) << BP_RNG_CR_HA) & BM_RNG_CR_HA)
 193
 194 /*! @brief Set the HA field to a new value. */
 195 #define BW_RNG_CR_HA(x, v)   (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_HA) = (v))
 196 /*@}*/
 197
 198 /*!
 199  * @name Register RNG_CR, field INTM[2] (RW)
 200  *
 201  * Masks the triggering of an error interrupt to the interrupt controller when
 202  * an OR underflow condition occurs. An OR underflow condition occurs when you
 203  * read OR[RANDOUT] and SR[OREG_LVL]=0. See the Output Register (OR) description.
 204  *
 205  * Values:
 206  * - 0 - Not masked
 207  * - 1 - Masked
 208  */
 209 /*@{*/
 210 #define BP_RNG_CR_INTM       (2U)          /*!< Bit position for RNG_CR_INTM. */
 211 #define BM_RNG_CR_INTM       (0x00000004U) /*!< Bit mask for RNG_CR_INTM. */
 212 #define BS_RNG_CR_INTM       (1U)          /*!< Bit field size in bits for RNG_CR_INTM. */
 213
 214 /*! @brief Read current value of the RNG_CR_INTM field. */
 215 #define BR_RNG_CR_INTM(x)    (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_INTM))
 216
 217 /*! @brief Format value for bitfield RNG_CR_INTM. */
 218 #define BF_RNG_CR_INTM(v)    ((uint32_t)((uint32_t)(v) << BP_RNG_CR_INTM) & BM_RNG_CR_INTM)
 219
 220 /*! @brief Set the INTM field to a new value. */
 221 #define BW_RNG_CR_INTM(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_INTM) = (v))
 222 /*@}*/
 223
 224 /*!
 225  * @name Register RNG_CR, field CLRI[3] (WORZ)
 226  *
 227  * Clears the interrupt by resetting the error-interrupt indicator (SR[ERRI]).
 228  *
 229  * Values:
 230  * - 0 - Do not clear the interrupt.
 231  * - 1 - Clear the interrupt. When you write 1 to this field, RNGA then resets
 232  *     the error-interrupt indicator (SR[ERRI]). This bit always reads as 0.
 233  */
 234 /*@{*/
 235 #define BP_RNG_CR_CLRI       (3U)          /*!< Bit position for RNG_CR_CLRI. */
 236 #define BM_RNG_CR_CLRI       (0x00000008U) /*!< Bit mask for RNG_CR_CLRI. */
 237 #define BS_RNG_CR_CLRI       (1U)          /*!< Bit field size in bits for RNG_CR_CLRI. */
 238
 239 /*! @brief Format value for bitfield RNG_CR_CLRI. */
 240 #define BF_RNG_CR_CLRI(v)    ((uint32_t)((uint32_t)(v) << BP_RNG_CR_CLRI) & BM_RNG_CR_CLRI)
 241
 242 /*! @brief Set the CLRI field to a new value. */
 243 #define BW_RNG_CR_CLRI(x, v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_CLRI) = (v))
 244 /*@}*/
 245
 246 /*!
 247  * @name Register RNG_CR, field SLP[4] (RW)
 248  *
 249  * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
 250  * mode by asserting the DOZE signal.
 251  *
 252  * Values:
 253  * - 0 - Normal mode
 254  * - 1 - Sleep (low-power) mode
 255  */
 256 /*@{*/
 257 #define BP_RNG_CR_SLP        (4U)          /*!< Bit position for RNG_CR_SLP. */
 258 #define BM_RNG_CR_SLP        (0x00000010U) /*!< Bit mask for RNG_CR_SLP. */
 259 #define BS_RNG_CR_SLP        (1U)          /*!< Bit field size in bits for RNG_CR_SLP. */
 260
 261 /*! @brief Read current value of the RNG_CR_SLP field. */
 262 #define BR_RNG_CR_SLP(x)     (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_SLP))
 263
 264 /*! @brief Format value for bitfield RNG_CR_SLP. */
 265 #define BF_RNG_CR_SLP(v)     ((uint32_t)((uint32_t)(v) << BP_RNG_CR_SLP) & BM_RNG_CR_SLP)
 266
 267 /*! @brief Set the SLP field to a new value. */
 268 #define BW_RNG_CR_SLP(x, v)  (BITBAND_ACCESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_SLP) = (v))
 269 /*@}*/
 270
 271 /*******************************************************************************
 272  * HW_RNG_SR - RNGA Status Register
 273  ******************************************************************************/
 274
 275 /*!
 276  * @brief HW_RNG_SR - RNGA Status Register (RO)
 277  *
 278  * Reset value: 0x00010000U
 279  *
 280  * Indicates the status of RNGA. This register is read-only.
 281  */
 282 typedef union _hw_rng_sr
 283 {
 284     uint32_t U;
 285     struct _hw_rng_sr_bitfields
 286     {
 287         uint32_t SECV : 1;             /*!< [0] Security Violation */
 288         uint32_t LRS : 1;              /*!< [1] Last Read Status */
 289         uint32_t ORU : 1;              /*!< [2] Output Register Underflow */
 290         uint32_t ERRI : 1;             /*!< [3] Error Interrupt */
 291         uint32_t SLP : 1;              /*!< [4] Sleep */
 292         uint32_t RESERVED0 : 3;        /*!< [7:5]  */
 293         uint32_t OREG_LVL : 8;         /*!< [15:8] Output Register Level */
 294         uint32_t OREG_SIZE : 8;        /*!< [23:16] Output Register Size */
 295         uint32_t RESERVED1 : 8;        /*!< [31:24]  */
 296     } B;
 297 } hw_rng_sr_t;
 298
 299 /*!
 300  * @name Constants and macros for entire RNG_SR register
 301  */
 302 /*@{*/
 303 #define HW_RNG_SR_ADDR(x)        ((x) + 0x4U)
 304
 305 #define HW_RNG_SR(x)             (*(__I hw_rng_sr_t *) HW_RNG_SR_ADDR(x))
 306 #define HW_RNG_SR_RD(x)          (HW_RNG_SR(x).U)
 307 /*@}*/
 308
 309 /*
 310  * Constants & macros for individual RNG_SR bitfields
 311  */
 312
 313 /*!
 314  * @name Register RNG_SR, field SECV[0] (RO)
 315  *
 316  * Used only when high assurance is enabled (CR[HA]). Indicates that a security
 317  * violation has occurred.This field is sticky. To clear SR[SECV], you must reset
 318  * RNGA.
 319  *
 320  * Values:
 321  * - 0 - No security violation
 322  * - 1 - Security violation
 323  */
 324 /*@{*/
 325 #define BP_RNG_SR_SECV       (0U)          /*!< Bit position for RNG_SR_SECV. */
 326 #define BM_RNG_SR_SECV       (0x00000001U) /*!< Bit mask for RNG_SR_SECV. */
 327 #define BS_RNG_SR_SECV       (1U)          /*!< Bit field size in bits for RNG_SR_SECV. */
 328
 329 /*! @brief Read current value of the RNG_SR_SECV field. */
 330 #define BR_RNG_SR_SECV(x)    (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_SECV))
 331 /*@}*/
 332
 333 /*!
 334  * @name Register RNG_SR, field LRS[1] (RO)
 335  *
 336  * Indicates whether the most recent read of OR[RANDOUT] caused an OR underflow
 337  * condition, regardless of whether the error interrupt is masked (CR[INTM]). An
 338  * OR underflow condition occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0.
 339  * After you read this register, RNGA writes 0 to this field.
 340  *
 341  * Values:
 342  * - 0 - No underflow
 343  * - 1 - Underflow
 344  */
 345 /*@{*/
 346 #define BP_RNG_SR_LRS        (1U)          /*!< Bit position for RNG_SR_LRS. */
 347 #define BM_RNG_SR_LRS        (0x00000002U) /*!< Bit mask for RNG_SR_LRS. */
 348 #define BS_RNG_SR_LRS        (1U)          /*!< Bit field size in bits for RNG_SR_LRS. */
 349
 350 /*! @brief Read current value of the RNG_SR_LRS field. */
 351 #define BR_RNG_SR_LRS(x)     (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_LRS))
 352 /*@}*/
 353
 354 /*!
 355  * @name Register RNG_SR, field ORU[2] (RO)
 356  *
 357  * Indicates whether an OR underflow condition has occurred since you last read
 358  * this register (SR) or RNGA was reset, regardless of whether the error
 359  * interrupt is masked (CR[INTM]). An OR underflow condition occurs when you read
 360  * OR[RANDOUT] and SR[OREG_LVL]=0. After you read this register, RNGA writes 0 to this
 361  * field.
 362  *
 363  * Values:
 364  * - 0 - No underflow
 365  * - 1 - Underflow
 366  */
 367 /*@{*/
 368 #define BP_RNG_SR_ORU        (2U)          /*!< Bit position for RNG_SR_ORU. */
 369 #define BM_RNG_SR_ORU        (0x00000004U) /*!< Bit mask for RNG_SR_ORU. */
 370 #define BS_RNG_SR_ORU        (1U)          /*!< Bit field size in bits for RNG_SR_ORU. */
 371
 372 /*! @brief Read current value of the RNG_SR_ORU field. */
 373 #define BR_RNG_SR_ORU(x)     (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_ORU))
 374 /*@}*/
 375
 376 /*!
 377  * @name Register RNG_SR, field ERRI[3] (RO)
 378  *
 379  * Indicates whether an OR underflow condition has occurred since you last
 380  * cleared the error interrupt (CR[CLRI]) or RNGA was reset, regardless of whether the
 381  * error interrupt is masked (CR[INTM]). An OR underflow condition occurs when
 382  * you read OR[RANDOUT] and SR[OREG_LVL]=0. After you reset the error-interrupt
 383  * indicator (via CR[CLRI]), RNGA writes 0 to this field.
 384  *
 385  * Values:
 386  * - 0 - No underflow
 387  * - 1 - Underflow
 388  */
 389 /*@{*/
 390 #define BP_RNG_SR_ERRI       (3U)          /*!< Bit position for RNG_SR_ERRI. */
 391 #define BM_RNG_SR_ERRI       (0x00000008U) /*!< Bit mask for RNG_SR_ERRI. */
 392 #define BS_RNG_SR_ERRI       (1U)          /*!< Bit field size in bits for RNG_SR_ERRI. */
 393
 394 /*! @brief Read current value of the RNG_SR_ERRI field. */
 395 #define BR_RNG_SR_ERRI(x)    (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_ERRI))
 396 /*@}*/
 397
 398 /*!
 399  * @name Register RNG_SR, field SLP[4] (RO)
 400  *
 401  * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
 402  * mode by asserting the DOZE signal.
 403  *
 404  * Values:
 405  * - 0 - Normal mode
 406  * - 1 - Sleep (low-power) mode
 407  */
 408 /*@{*/
 409 #define BP_RNG_SR_SLP        (4U)          /*!< Bit position for RNG_SR_SLP. */
 410 #define BM_RNG_SR_SLP        (0x00000010U) /*!< Bit mask for RNG_SR_SLP. */
 411 #define BS_RNG_SR_SLP        (1U)          /*!< Bit field size in bits for RNG_SR_SLP. */
 412
 413 /*! @brief Read current value of the RNG_SR_SLP field. */
 414 #define BR_RNG_SR_SLP(x)     (BITBAND_ACCESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_SLP))
 415 /*@}*/
 416
 417 /*!
 418  * @name Register RNG_SR, field OREG_LVL[15:8] (RO)
 419  *
 420  * Indicates the number of random-data words that are in OR[RANDOUT], which
 421  * indicates whether OR[RANDOUT] is valid.If you read OR[RANDOUT] when SR[OREG_LVL]
 422  * is not 0, then the contents of a random number contained in OR[RANDOUT] are
 423  * returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL].
 424  *
 425  * Values:
 426  * - 0 - No words (empty)
 427  * - 1 - One word (valid)
 428  */
 429 /*@{*/
 430 #define BP_RNG_SR_OREG_LVL   (8U)          /*!< Bit position for RNG_SR_OREG_LVL. */
 431 #define BM_RNG_SR_OREG_LVL   (0x0000FF00U) /*!< Bit mask for RNG_SR_OREG_LVL. */
 432 #define BS_RNG_SR_OREG_LVL   (8U)          /*!< Bit field size in bits for RNG_SR_OREG_LVL. */
 433
 434 /*! @brief Read current value of the RNG_SR_OREG_LVL field. */
 435 #define BR_RNG_SR_OREG_LVL(x) (HW_RNG_SR(x).B.OREG_LVL)
 436 /*@}*/
 437
 438 /*!
 439  * @name Register RNG_SR, field OREG_SIZE[23:16] (RO)
 440  *
 441  * Indicates the size of the Output (OR) register in terms of the number of
 442  * 32-bit random-data words it can hold.
 443  *
 444  * Values:
 445  * - 1 - One word (this value is fixed)
 446  */
 447 /*@{*/
 448 #define BP_RNG_SR_OREG_SIZE  (16U)         /*!< Bit position for RNG_SR_OREG_SIZE. */
 449 #define BM_RNG_SR_OREG_SIZE  (0x00FF0000U) /*!< Bit mask for RNG_SR_OREG_SIZE. */
 450 #define BS_RNG_SR_OREG_SIZE  (8U)          /*!< Bit field size in bits for RNG_SR_OREG_SIZE. */
 451
 452 /*! @brief Read current value of the RNG_SR_OREG_SIZE field. */
 453 #define BR_RNG_SR_OREG_SIZE(x) (HW_RNG_SR(x).B.OREG_SIZE)
 454 /*@}*/
 455
 456 /*******************************************************************************
 457  * HW_RNG_ER - RNGA Entropy Register
 458  ******************************************************************************/
 459
 460 /*!
 461  * @brief HW_RNG_ER - RNGA Entropy Register (WORZ)
 462  *
 463  * Reset value: 0x00000000U
 464  *
 465  * Specifies an entropy value that RNGA uses in addition to its ring oscillators
 466  * to seed its pseudorandom algorithm. This is a write-only register; reads
 467  * return all zeros.
 468  */
 469 typedef union _hw_rng_er
 470 {
 471     uint32_t U;
 472     struct _hw_rng_er_bitfields
 473     {
 474         uint32_t EXT_ENT : 32;         /*!< [31:0] External Entropy */
 475     } B;
 476 } hw_rng_er_t;
 477
 478 /*!
 479  * @name Constants and macros for entire RNG_ER register
 480  */
 481 /*@{*/
 482 #define HW_RNG_ER_ADDR(x)        ((x) + 0x8U)
 483
 484 #define HW_RNG_ER(x)             (*(__O hw_rng_er_t *) HW_RNG_ER_ADDR(x))
 485 #define HW_RNG_ER_RD(x)          (HW_RNG_ER(x).U)
 486 #define HW_RNG_ER_WR(x, v)       (HW_RNG_ER(x).U = (v))
 487 /*@}*/
 488
 489 /*
 490  * Constants & macros for individual RNG_ER bitfields
 491  */
 492
 493 /*!
 494  * @name Register RNG_ER, field EXT_ENT[31:0] (WORZ)
 495  *
 496  * Specifies an entropy value that RNGA uses in addition to its ring oscillators
 497  * to seed its pseudorandom algorithm.Specifying a value for this field is
 498  * optional but recommended. You can write to this field at any time during operation.
 499  */
 500 /*@{*/
 501 #define BP_RNG_ER_EXT_ENT    (0U)          /*!< Bit position for RNG_ER_EXT_ENT. */
 502 #define BM_RNG_ER_EXT_ENT    (0xFFFFFFFFU) /*!< Bit mask for RNG_ER_EXT_ENT. */
 503 #define BS_RNG_ER_EXT_ENT    (32U)         /*!< Bit field size in bits for RNG_ER_EXT_ENT. */
 504
 505 /*! @brief Format value for bitfield RNG_ER_EXT_ENT. */
 506 #define BF_RNG_ER_EXT_ENT(v) ((uint32_t)((uint32_t)(v) << BP_RNG_ER_EXT_ENT) & BM_RNG_ER_EXT_ENT)
 507
 508 /*! @brief Set the EXT_ENT field to a new value. */
 509 #define BW_RNG_ER_EXT_ENT(x, v) (HW_RNG_ER_WR(x, v))
 510 /*@}*/
 511
 512 /*******************************************************************************
 513  * HW_RNG_OR - RNGA Output Register
 514  ******************************************************************************/
 515
 516 /*!
 517  * @brief HW_RNG_OR - RNGA Output Register (RO)
 518  *
 519  * Reset value: 0x00000000U
 520  *
 521  * Stores a random-data word generated by RNGA.
 522  */
 523 typedef union _hw_rng_or
 524 {
 525     uint32_t U;
 526     struct _hw_rng_or_bitfields
 527     {
 528         uint32_t RANDOUT : 32;         /*!< [31:0] Random Output */
 529     } B;
 530 } hw_rng_or_t;
 531
 532 /*!
 533  * @name Constants and macros for entire RNG_OR register
 534  */
 535 /*@{*/
 536 #define HW_RNG_OR_ADDR(x)        ((x) + 0xCU)
 537
 538 #define HW_RNG_OR(x)             (*(__I hw_rng_or_t *) HW_RNG_OR_ADDR(x))
 539 #define HW_RNG_OR_RD(x)          (HW_RNG_OR(x).U)
 540 /*@}*/
 541
 542 /*
 543  * Constants & macros for individual RNG_OR bitfields
 544  */
 545
 546 /*!
 547  * @name Register RNG_OR, field RANDOUT[31:0] (RO)
 548  *
 549  * Stores a random-data word generated by RNGA. This is a read-only field.Before
 550  * reading RANDOUT, be sure it is valid (SR[OREG_LVL]=1).
 551  *
 552  * Values:
 553  * - 0 - Invalid data (if you read this field when it is 0 and SR[OREG_LVL] is
 554  *     0, RNGA then writes 1 to SR[ERRI], SR[ORU], and SR[LRS]; when the error
 555  *     interrupt is not masked (CR[INTM]=0), RNGA also asserts an error interrupt
 556  *     request to the interrupt controller).
 557  */
 558 /*@{*/
 559 #define BP_RNG_OR_RANDOUT    (0U)          /*!< Bit position for RNG_OR_RANDOUT. */
 560 #define BM_RNG_OR_RANDOUT    (0xFFFFFFFFU) /*!< Bit mask for RNG_OR_RANDOUT. */
 561 #define BS_RNG_OR_RANDOUT    (32U)         /*!< Bit field size in bits for RNG_OR_RANDOUT. */
 562
 563 /*! @brief Read current value of the RNG_OR_RANDOUT field. */
 564 #define BR_RNG_OR_RANDOUT(x) (HW_RNG_OR(x).U)
 565 /*@}*/
 566
 567 /*******************************************************************************
 568  * hw_rng_t - module struct
 569  ******************************************************************************/
 570 /*!
 571  * @brief All RNG module registers.
 572  */
 573 #pragma pack(1)
 574 typedef struct _hw_rng
 575 {
 576     __IO hw_rng_cr_t CR;                   /*!< [0x0] RNGA Control Register */
 577     __I hw_rng_sr_t SR;                    /*!< [0x4] RNGA Status Register */
 578     __O hw_rng_er_t ER;                    /*!< [0x8] RNGA Entropy Register */
 579     __I hw_rng_or_t OR;                    /*!< [0xC] RNGA Output Register */
 580 } hw_rng_t;
 581 #pragma pack()
 582
 583 /*! @brief Macro to access all RNG registers. */
 584 /*! @param x RNG module instance base address. */
 585 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
 586  *     use the '&' operator, like <code>&HW_RNG(RNG_BASE)</code>. */
 587 #define HW_RNG(x)      (*(hw_rng_t *)(x))
 588
 589 #endif /* __HW_RNG_REGISTERS_H__ */
 590 /* EOF */