tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_usbdcd.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
   9 **     Version:             rev. 2.5, 2014-02-10
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-08-12)
  48 **         Initial version.
  49 **     - rev. 2.0 (2013-10-29)
  50 **         Register accessor macros added to the memory map.
  51 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  52 **         Startup file for gcc has been updated according to CMSIS 3.2.
  53 **         System initialization updated.
  54 **         MCG - registers updated.
  55 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-09)
  59 **         DMA - EARS register removed.
  60 **         AIPS0, AIPS1 - MPRA register updated.
  61 **     - rev. 2.3 (2014-01-24)
  62 **         Update according to reference manual rev. 2
  63 **         ENET, MCG, MCM, SIM, USB - registers updated
  64 **     - rev. 2.4 (2014-02-10)
  65 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  66 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  67 **     - rev. 2.5 (2014-02-10)
  68 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  69 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  70 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  71 **
  72 ** ###################################################################
  73 */
  74
  75 /*
  76  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  77  *
  78  * This file was generated automatically and any changes may be lost.
  79  */
  80 #ifndef __HW_USBDCD_REGISTERS_H__
  81 #define __HW_USBDCD_REGISTERS_H__
  82
  83 #include "MK64F12.h"
  84 #include "fsl_bitaccess.h"
  85
  86 /*
  87  * MK64F12 USBDCD
  88  *
  89  * USB Device Charger Detection module
  90  *
  91  * Registers defined in this header file:
  92  * - HW_USBDCD_CONTROL - Control register
  93  * - HW_USBDCD_CLOCK - Clock register
  94  * - HW_USBDCD_STATUS - Status register
  95  * - HW_USBDCD_TIMER0 - TIMER0 register
  96  * - HW_USBDCD_TIMER1 - TIMER1 register
  97  * - HW_USBDCD_TIMER2_BC11 - TIMER2_BC11 register
  98  * - HW_USBDCD_TIMER2_BC12 - TIMER2_BC12 register
  99  *
 100  * - hw_usbdcd_t - Struct containing all module registers.
 101  */
 102
 103 #define HW_USBDCD_INSTANCE_COUNT (1U) /*!< Number of instances of the USBDCD module. */
 104
 105 /*******************************************************************************
 106  * HW_USBDCD_CONTROL - Control register
 107  ******************************************************************************/
 108
 109 /*!
 110  * @brief HW_USBDCD_CONTROL - Control register (RW)
 111  *
 112  * Reset value: 0x00010000U
 113  *
 114  * Contains the control and interrupt bit fields.
 115  */
 116 typedef union _hw_usbdcd_control
 117 {
 118     uint32_t U;
 119     struct _hw_usbdcd_control_bitfields
 120     {
 121         uint32_t IACK : 1;             /*!< [0] Interrupt Acknowledge */
 122         uint32_t RESERVED0 : 7;        /*!< [7:1]  */
 123         uint32_t IF : 1;               /*!< [8] Interrupt Flag */
 124         uint32_t RESERVED1 : 7;        /*!< [15:9]  */
 125         uint32_t IE : 1;               /*!< [16] Interrupt Enable */
 126         uint32_t BC12 : 1;             /*!< [17]  */
 127         uint32_t RESERVED2 : 6;        /*!< [23:18]  */
 128         uint32_t START : 1;            /*!< [24] Start Change Detection Sequence */
 129         uint32_t SR : 1;               /*!< [25] Software Reset */
 130         uint32_t RESERVED3 : 6;        /*!< [31:26]  */
 131     } B;
 132 } hw_usbdcd_control_t;
 133
 134 /*!
 135  * @name Constants and macros for entire USBDCD_CONTROL register
 136  */
 137 /*@{*/
 138 #define HW_USBDCD_CONTROL_ADDR(x) ((x) + 0x0U)
 139
 140 #define HW_USBDCD_CONTROL(x)     (*(__IO hw_usbdcd_control_t *) HW_USBDCD_CONTROL_ADDR(x))
 141 #define HW_USBDCD_CONTROL_RD(x)  (HW_USBDCD_CONTROL(x).U)
 142 #define HW_USBDCD_CONTROL_WR(x, v) (HW_USBDCD_CONTROL(x).U = (v))
 143 #define HW_USBDCD_CONTROL_SET(x, v) (HW_USBDCD_CONTROL_WR(x, HW_USBDCD_CONTROL_RD(x) |  (v)))
 144 #define HW_USBDCD_CONTROL_CLR(x, v) (HW_USBDCD_CONTROL_WR(x, HW_USBDCD_CONTROL_RD(x) & ~(v)))
 145 #define HW_USBDCD_CONTROL_TOG(x, v) (HW_USBDCD_CONTROL_WR(x, HW_USBDCD_CONTROL_RD(x) ^  (v)))
 146 /*@}*/
 147
 148 /*
 149  * Constants & macros for individual USBDCD_CONTROL bitfields
 150  */
 151
 152 /*!
 153  * @name Register USBDCD_CONTROL, field IACK[0] (WORZ)
 154  *
 155  * Determines whether the interrupt is cleared.
 156  *
 157  * Values:
 158  * - 0 - Do not clear the interrupt.
 159  * - 1 - Clear the IF bit (interrupt flag).
 160  */
 161 /*@{*/
 162 #define BP_USBDCD_CONTROL_IACK (0U)        /*!< Bit position for USBDCD_CONTROL_IACK. */
 163 #define BM_USBDCD_CONTROL_IACK (0x00000001U) /*!< Bit mask for USBDCD_CONTROL_IACK. */
 164 #define BS_USBDCD_CONTROL_IACK (1U)        /*!< Bit field size in bits for USBDCD_CONTROL_IACK. */
 165
 166 /*! @brief Format value for bitfield USBDCD_CONTROL_IACK. */
 167 #define BF_USBDCD_CONTROL_IACK(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_CONTROL_IACK) & BM_USBDCD_CONTROL_IACK)
 168
 169 /*! @brief Set the IACK field to a new value. */
 170 #define BW_USBDCD_CONTROL_IACK(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_IACK) = (v))
 171 /*@}*/
 172
 173 /*!
 174  * @name Register USBDCD_CONTROL, field IF[8] (RO)
 175  *
 176  * Determines whether an interrupt is pending.
 177  *
 178  * Values:
 179  * - 0 - No interrupt is pending.
 180  * - 1 - An interrupt is pending.
 181  */
 182 /*@{*/
 183 #define BP_USBDCD_CONTROL_IF (8U)          /*!< Bit position for USBDCD_CONTROL_IF. */
 184 #define BM_USBDCD_CONTROL_IF (0x00000100U) /*!< Bit mask for USBDCD_CONTROL_IF. */
 185 #define BS_USBDCD_CONTROL_IF (1U)          /*!< Bit field size in bits for USBDCD_CONTROL_IF. */
 186
 187 /*! @brief Read current value of the USBDCD_CONTROL_IF field. */
 188 #define BR_USBDCD_CONTROL_IF(x) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_IF))
 189 /*@}*/
 190
 191 /*!
 192  * @name Register USBDCD_CONTROL, field IE[16] (RW)
 193  *
 194  * Enables/disables interrupts to the system.
 195  *
 196  * Values:
 197  * - 0 - Disable interrupts to the system.
 198  * - 1 - Enable interrupts to the system.
 199  */
 200 /*@{*/
 201 #define BP_USBDCD_CONTROL_IE (16U)         /*!< Bit position for USBDCD_CONTROL_IE. */
 202 #define BM_USBDCD_CONTROL_IE (0x00010000U) /*!< Bit mask for USBDCD_CONTROL_IE. */
 203 #define BS_USBDCD_CONTROL_IE (1U)          /*!< Bit field size in bits for USBDCD_CONTROL_IE. */
 204
 205 /*! @brief Read current value of the USBDCD_CONTROL_IE field. */
 206 #define BR_USBDCD_CONTROL_IE(x) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_IE))
 207
 208 /*! @brief Format value for bitfield USBDCD_CONTROL_IE. */
 209 #define BF_USBDCD_CONTROL_IE(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_CONTROL_IE) & BM_USBDCD_CONTROL_IE)
 210
 211 /*! @brief Set the IE field to a new value. */
 212 #define BW_USBDCD_CONTROL_IE(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_IE) = (v))
 213 /*@}*/
 214
 215 /*!
 216  * @name Register USBDCD_CONTROL, field BC12[17] (RW)
 217  *
 218  * BC1.2 compatibility. This bit cannot be changed after start detection.
 219  *
 220  * Values:
 221  * - 0 - Compatible with BC1.1 (default)
 222  * - 1 - Compatible with BC1.2
 223  */
 224 /*@{*/
 225 #define BP_USBDCD_CONTROL_BC12 (17U)       /*!< Bit position for USBDCD_CONTROL_BC12. */
 226 #define BM_USBDCD_CONTROL_BC12 (0x00020000U) /*!< Bit mask for USBDCD_CONTROL_BC12. */
 227 #define BS_USBDCD_CONTROL_BC12 (1U)        /*!< Bit field size in bits for USBDCD_CONTROL_BC12. */
 228
 229 /*! @brief Read current value of the USBDCD_CONTROL_BC12 field. */
 230 #define BR_USBDCD_CONTROL_BC12(x) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_BC12))
 231
 232 /*! @brief Format value for bitfield USBDCD_CONTROL_BC12. */
 233 #define BF_USBDCD_CONTROL_BC12(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_CONTROL_BC12) & BM_USBDCD_CONTROL_BC12)
 234
 235 /*! @brief Set the BC12 field to a new value. */
 236 #define BW_USBDCD_CONTROL_BC12(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_BC12) = (v))
 237 /*@}*/
 238
 239 /*!
 240  * @name Register USBDCD_CONTROL, field START[24] (WORZ)
 241  *
 242  * Determines whether the charger detection sequence is initiated.
 243  *
 244  * Values:
 245  * - 0 - Do not start the sequence. Writes of this value have no effect.
 246  * - 1 - Initiate the charger detection sequence. If the sequence is already
 247  *     running, writes of this value have no effect.
 248  */
 249 /*@{*/
 250 #define BP_USBDCD_CONTROL_START (24U)      /*!< Bit position for USBDCD_CONTROL_START. */
 251 #define BM_USBDCD_CONTROL_START (0x01000000U) /*!< Bit mask for USBDCD_CONTROL_START. */
 252 #define BS_USBDCD_CONTROL_START (1U)       /*!< Bit field size in bits for USBDCD_CONTROL_START. */
 253
 254 /*! @brief Format value for bitfield USBDCD_CONTROL_START. */
 255 #define BF_USBDCD_CONTROL_START(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_CONTROL_START) & BM_USBDCD_CONTROL_START)
 256
 257 /*! @brief Set the START field to a new value. */
 258 #define BW_USBDCD_CONTROL_START(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_START) = (v))
 259 /*@}*/
 260
 261 /*!
 262  * @name Register USBDCD_CONTROL, field SR[25] (WORZ)
 263  *
 264  * Determines whether a software reset is performed.
 265  *
 266  * Values:
 267  * - 0 - Do not perform a software reset.
 268  * - 1 - Perform a software reset.
 269  */
 270 /*@{*/
 271 #define BP_USBDCD_CONTROL_SR (25U)         /*!< Bit position for USBDCD_CONTROL_SR. */
 272 #define BM_USBDCD_CONTROL_SR (0x02000000U) /*!< Bit mask for USBDCD_CONTROL_SR. */
 273 #define BS_USBDCD_CONTROL_SR (1U)          /*!< Bit field size in bits for USBDCD_CONTROL_SR. */
 274
 275 /*! @brief Format value for bitfield USBDCD_CONTROL_SR. */
 276 #define BF_USBDCD_CONTROL_SR(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_CONTROL_SR) & BM_USBDCD_CONTROL_SR)
 277
 278 /*! @brief Set the SR field to a new value. */
 279 #define BW_USBDCD_CONTROL_SR(x, v) (BITBAND_ACCESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_SR) = (v))
 280 /*@}*/
 281
 282 /*******************************************************************************
 283  * HW_USBDCD_CLOCK - Clock register
 284  ******************************************************************************/
 285
 286 /*!
 287  * @brief HW_USBDCD_CLOCK - Clock register (RW)
 288  *
 289  * Reset value: 0x000000C1U
 290  */
 291 typedef union _hw_usbdcd_clock
 292 {
 293     uint32_t U;
 294     struct _hw_usbdcd_clock_bitfields
 295     {
 296         uint32_t CLOCK_UNIT : 1;       /*!< [0] Unit of Measurement Encoding for
 297                                         * Clock Speed */
 298         uint32_t RESERVED0 : 1;        /*!< [1]  */
 299         uint32_t CLOCK_SPEED : 10;     /*!< [11:2] Numerical Value of Clock Speed
 300                                         * in Binary */
 301         uint32_t RESERVED1 : 20;       /*!< [31:12]  */
 302     } B;
 303 } hw_usbdcd_clock_t;
 304
 305 /*!
 306  * @name Constants and macros for entire USBDCD_CLOCK register
 307  */
 308 /*@{*/
 309 #define HW_USBDCD_CLOCK_ADDR(x)  ((x) + 0x4U)
 310
 311 #define HW_USBDCD_CLOCK(x)       (*(__IO hw_usbdcd_clock_t *) HW_USBDCD_CLOCK_ADDR(x))
 312 #define HW_USBDCD_CLOCK_RD(x)    (HW_USBDCD_CLOCK(x).U)
 313 #define HW_USBDCD_CLOCK_WR(x, v) (HW_USBDCD_CLOCK(x).U = (v))
 314 #define HW_USBDCD_CLOCK_SET(x, v) (HW_USBDCD_CLOCK_WR(x, HW_USBDCD_CLOCK_RD(x) |  (v)))
 315 #define HW_USBDCD_CLOCK_CLR(x, v) (HW_USBDCD_CLOCK_WR(x, HW_USBDCD_CLOCK_RD(x) & ~(v)))
 316 #define HW_USBDCD_CLOCK_TOG(x, v) (HW_USBDCD_CLOCK_WR(x, HW_USBDCD_CLOCK_RD(x) ^  (v)))
 317 /*@}*/
 318
 319 /*
 320  * Constants & macros for individual USBDCD_CLOCK bitfields
 321  */
 322
 323 /*!
 324  * @name Register USBDCD_CLOCK, field CLOCK_UNIT[0] (RW)
 325  *
 326  * Specifies the unit of measure for the clock speed.
 327  *
 328  * Values:
 329  * - 0 - kHz Speed (between 1 kHz and 1023 kHz)
 330  * - 1 - MHz Speed (between 1 MHz and 1023 MHz)
 331  */
 332 /*@{*/
 333 #define BP_USBDCD_CLOCK_CLOCK_UNIT (0U)    /*!< Bit position for USBDCD_CLOCK_CLOCK_UNIT. */
 334 #define BM_USBDCD_CLOCK_CLOCK_UNIT (0x00000001U) /*!< Bit mask for USBDCD_CLOCK_CLOCK_UNIT. */
 335 #define BS_USBDCD_CLOCK_CLOCK_UNIT (1U)    /*!< Bit field size in bits for USBDCD_CLOCK_CLOCK_UNIT. */
 336
 337 /*! @brief Read current value of the USBDCD_CLOCK_CLOCK_UNIT field. */
 338 #define BR_USBDCD_CLOCK_CLOCK_UNIT(x) (BITBAND_ACCESS32(HW_USBDCD_CLOCK_ADDR(x), BP_USBDCD_CLOCK_CLOCK_UNIT))
 339
 340 /*! @brief Format value for bitfield USBDCD_CLOCK_CLOCK_UNIT. */
 341 #define BF_USBDCD_CLOCK_CLOCK_UNIT(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_CLOCK_CLOCK_UNIT) & BM_USBDCD_CLOCK_CLOCK_UNIT)
 342
 343 /*! @brief Set the CLOCK_UNIT field to a new value. */
 344 #define BW_USBDCD_CLOCK_CLOCK_UNIT(x, v) (BITBAND_ACCESS32(HW_USBDCD_CLOCK_ADDR(x), BP_USBDCD_CLOCK_CLOCK_UNIT) = (v))
 345 /*@}*/
 346
 347 /*!
 348  * @name Register USBDCD_CLOCK, field CLOCK_SPEED[11:2] (RW)
 349  *
 350  * The unit of measure is programmed in CLOCK_UNIT. The valid range is from 1 to
 351  * 1023 when clock unit is MHz and 4 to 1023 when clock unit is kHz. Examples
 352  * with CLOCK_UNIT = 1: For 48 MHz: 0b00_0011_0000 (48) (Default) For 24 MHz:
 353  * 0b00_0001_1000 (24) Examples with CLOCK_UNIT = 0: For 100 kHz: 0b00_0110_0100 (100)
 354  * For 500 kHz: 0b01_1111_0100 (500)
 355  */
 356 /*@{*/
 357 #define BP_USBDCD_CLOCK_CLOCK_SPEED (2U)   /*!< Bit position for USBDCD_CLOCK_CLOCK_SPEED. */
 358 #define BM_USBDCD_CLOCK_CLOCK_SPEED (0x00000FFCU) /*!< Bit mask for USBDCD_CLOCK_CLOCK_SPEED. */
 359 #define BS_USBDCD_CLOCK_CLOCK_SPEED (10U)  /*!< Bit field size in bits for USBDCD_CLOCK_CLOCK_SPEED. */
 360
 361 /*! @brief Read current value of the USBDCD_CLOCK_CLOCK_SPEED field. */
 362 #define BR_USBDCD_CLOCK_CLOCK_SPEED(x) (HW_USBDCD_CLOCK(x).B.CLOCK_SPEED)
 363
 364 /*! @brief Format value for bitfield USBDCD_CLOCK_CLOCK_SPEED. */
 365 #define BF_USBDCD_CLOCK_CLOCK_SPEED(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_CLOCK_CLOCK_SPEED) & BM_USBDCD_CLOCK_CLOCK_SPEED)
 366
 367 /*! @brief Set the CLOCK_SPEED field to a new value. */
 368 #define BW_USBDCD_CLOCK_CLOCK_SPEED(x, v) (HW_USBDCD_CLOCK_WR(x, (HW_USBDCD_CLOCK_RD(x) & ~BM_USBDCD_CLOCK_CLOCK_SPEED) | BF_USBDCD_CLOCK_CLOCK_SPEED(v)))
 369 /*@}*/
 370
 371 /*******************************************************************************
 372  * HW_USBDCD_STATUS - Status register
 373  ******************************************************************************/
 374
 375 /*!
 376  * @brief HW_USBDCD_STATUS - Status register (RO)
 377  *
 378  * Reset value: 0x00000000U
 379  *
 380  * Provides the current state of the module for system software monitoring.
 381  */
 382 typedef union _hw_usbdcd_status
 383 {
 384     uint32_t U;
 385     struct _hw_usbdcd_status_bitfields
 386     {
 387         uint32_t RESERVED0 : 16;       /*!< [15:0]  */
 388         uint32_t SEQ_RES : 2;          /*!< [17:16] Charger Detection Sequence Results
 389                                         * */
 390         uint32_t SEQ_STAT : 2;         /*!< [19:18] Charger Detection Sequence Status
 391                                         * */
 392         uint32_t ERR : 1;              /*!< [20] Error Flag */
 393         uint32_t TO : 1;               /*!< [21] Timeout Flag */
 394         uint32_t ACTIVE : 1;           /*!< [22] Active Status Indicator */
 395         uint32_t RESERVED1 : 9;        /*!< [31:23]  */
 396     } B;
 397 } hw_usbdcd_status_t;
 398
 399 /*!
 400  * @name Constants and macros for entire USBDCD_STATUS register
 401  */
 402 /*@{*/
 403 #define HW_USBDCD_STATUS_ADDR(x) ((x) + 0x8U)
 404
 405 #define HW_USBDCD_STATUS(x)      (*(__I hw_usbdcd_status_t *) HW_USBDCD_STATUS_ADDR(x))
 406 #define HW_USBDCD_STATUS_RD(x)   (HW_USBDCD_STATUS(x).U)
 407 /*@}*/
 408
 409 /*
 410  * Constants & macros for individual USBDCD_STATUS bitfields
 411  */
 412
 413 /*!
 414  * @name Register USBDCD_STATUS, field SEQ_RES[17:16] (RO)
 415  *
 416  * Reports how the charger detection is attached.
 417  *
 418  * Values:
 419  * - 00 - No results to report.
 420  * - 01 - Attached to a standard host. Must comply with USB 2.0 by drawing only
 421  *     2.5 mA (max) until connected.
 422  * - 10 - Attached to a charging port. The exact meaning depends on bit 18: 0:
 423  *     Attached to either a charging host or a dedicated charger. The charger type
 424  *     detection has not completed. 1: Attached to a charging host. The charger
 425  *     type detection has completed.
 426  * - 11 - Attached to a dedicated charger.
 427  */
 428 /*@{*/
 429 #define BP_USBDCD_STATUS_SEQ_RES (16U)     /*!< Bit position for USBDCD_STATUS_SEQ_RES. */
 430 #define BM_USBDCD_STATUS_SEQ_RES (0x00030000U) /*!< Bit mask for USBDCD_STATUS_SEQ_RES. */
 431 #define BS_USBDCD_STATUS_SEQ_RES (2U)      /*!< Bit field size in bits for USBDCD_STATUS_SEQ_RES. */
 432
 433 /*! @brief Read current value of the USBDCD_STATUS_SEQ_RES field. */
 434 #define BR_USBDCD_STATUS_SEQ_RES(x) (HW_USBDCD_STATUS(x).B.SEQ_RES)
 435 /*@}*/
 436
 437 /*!
 438  * @name Register USBDCD_STATUS, field SEQ_STAT[19:18] (RO)
 439  *
 440  * Indicates the status of the charger detection sequence.
 441  *
 442  * Values:
 443  * - 00 - The module is either not enabled, or the module is enabled but the
 444  *     data pins have not yet been detected.
 445  * - 01 - Data pin contact detection is complete.
 446  * - 10 - Charging port detection is complete.
 447  * - 11 - Charger type detection is complete.
 448  */
 449 /*@{*/
 450 #define BP_USBDCD_STATUS_SEQ_STAT (18U)    /*!< Bit position for USBDCD_STATUS_SEQ_STAT. */
 451 #define BM_USBDCD_STATUS_SEQ_STAT (0x000C0000U) /*!< Bit mask for USBDCD_STATUS_SEQ_STAT. */
 452 #define BS_USBDCD_STATUS_SEQ_STAT (2U)     /*!< Bit field size in bits for USBDCD_STATUS_SEQ_STAT. */
 453
 454 /*! @brief Read current value of the USBDCD_STATUS_SEQ_STAT field. */
 455 #define BR_USBDCD_STATUS_SEQ_STAT(x) (HW_USBDCD_STATUS(x).B.SEQ_STAT)
 456 /*@}*/
 457
 458 /*!
 459  * @name Register USBDCD_STATUS, field ERR[20] (RO)
 460  *
 461  * Indicates whether there is an error in the detection sequence.
 462  *
 463  * Values:
 464  * - 0 - No sequence errors.
 465  * - 1 - Error in the detection sequence. See the SEQ_STAT field to determine
 466  *     the phase in which the error occurred.
 467  */
 468 /*@{*/
 469 #define BP_USBDCD_STATUS_ERR (20U)         /*!< Bit position for USBDCD_STATUS_ERR. */
 470 #define BM_USBDCD_STATUS_ERR (0x00100000U) /*!< Bit mask for USBDCD_STATUS_ERR. */
 471 #define BS_USBDCD_STATUS_ERR (1U)          /*!< Bit field size in bits for USBDCD_STATUS_ERR. */
 472
 473 /*! @brief Read current value of the USBDCD_STATUS_ERR field. */
 474 #define BR_USBDCD_STATUS_ERR(x) (BITBAND_ACCESS32(HW_USBDCD_STATUS_ADDR(x), BP_USBDCD_STATUS_ERR))
 475 /*@}*/
 476
 477 /*!
 478  * @name Register USBDCD_STATUS, field TO[21] (RO)
 479  *
 480  * Indicates whether the detection sequence has passed the timeout threshhold.
 481  *
 482  * Values:
 483  * - 0 - The detection sequence has not been running for over 1 s.
 484  * - 1 - It has been over 1 s since the data pin contact was detected and
 485  *     debounced.
 486  */
 487 /*@{*/
 488 #define BP_USBDCD_STATUS_TO  (21U)         /*!< Bit position for USBDCD_STATUS_TO. */
 489 #define BM_USBDCD_STATUS_TO  (0x00200000U) /*!< Bit mask for USBDCD_STATUS_TO. */
 490 #define BS_USBDCD_STATUS_TO  (1U)          /*!< Bit field size in bits for USBDCD_STATUS_TO. */
 491
 492 /*! @brief Read current value of the USBDCD_STATUS_TO field. */
 493 #define BR_USBDCD_STATUS_TO(x) (BITBAND_ACCESS32(HW_USBDCD_STATUS_ADDR(x), BP_USBDCD_STATUS_TO))
 494 /*@}*/
 495
 496 /*!
 497  * @name Register USBDCD_STATUS, field ACTIVE[22] (RO)
 498  *
 499  * Indicates whether the sequence is running.
 500  *
 501  * Values:
 502  * - 0 - The sequence is not running.
 503  * - 1 - The sequence is running.
 504  */
 505 /*@{*/
 506 #define BP_USBDCD_STATUS_ACTIVE (22U)      /*!< Bit position for USBDCD_STATUS_ACTIVE. */
 507 #define BM_USBDCD_STATUS_ACTIVE (0x00400000U) /*!< Bit mask for USBDCD_STATUS_ACTIVE. */
 508 #define BS_USBDCD_STATUS_ACTIVE (1U)       /*!< Bit field size in bits for USBDCD_STATUS_ACTIVE. */
 509
 510 /*! @brief Read current value of the USBDCD_STATUS_ACTIVE field. */
 511 #define BR_USBDCD_STATUS_ACTIVE(x) (BITBAND_ACCESS32(HW_USBDCD_STATUS_ADDR(x), BP_USBDCD_STATUS_ACTIVE))
 512 /*@}*/
 513
 514 /*******************************************************************************
 515  * HW_USBDCD_TIMER0 - TIMER0 register
 516  ******************************************************************************/
 517
 518 /*!
 519  * @brief HW_USBDCD_TIMER0 - TIMER0 register (RW)
 520  *
 521  * Reset value: 0x00100000U
 522  *
 523  * TIMER0 has an TSEQ_INIT field that represents the system latency in ms.
 524  * Latency is measured from the time when VBUS goes active until the time system
 525  * software initiates charger detection sequence in USBDCD module. When software sets
 526  * the CONTROL[START] bit, the Unit Connection Timer (TUNITCON) is initialized
 527  * with the value of TSEQ_INIT. Valid values are 0-1023, however the USB Battery
 528  * Charging Specification requires the entire sequence, including TSEQ_INIT, to be
 529  * completed in 1s or less.
 530  */
 531 typedef union _hw_usbdcd_timer0
 532 {
 533     uint32_t U;
 534     struct _hw_usbdcd_timer0_bitfields
 535     {
 536         uint32_t TUNITCON : 12;        /*!< [11:0] Unit Connection Timer Elapse (in
 537                                         * ms) */
 538         uint32_t RESERVED0 : 4;        /*!< [15:12]  */
 539         uint32_t TSEQ_INIT : 10;       /*!< [25:16] Sequence Initiation Time */
 540         uint32_t RESERVED1 : 6;        /*!< [31:26]  */
 541     } B;
 542 } hw_usbdcd_timer0_t;
 543
 544 /*!
 545  * @name Constants and macros for entire USBDCD_TIMER0 register
 546  */
 547 /*@{*/
 548 #define HW_USBDCD_TIMER0_ADDR(x) ((x) + 0x10U)
 549
 550 #define HW_USBDCD_TIMER0(x)      (*(__IO hw_usbdcd_timer0_t *) HW_USBDCD_TIMER0_ADDR(x))
 551 #define HW_USBDCD_TIMER0_RD(x)   (HW_USBDCD_TIMER0(x).U)
 552 #define HW_USBDCD_TIMER0_WR(x, v) (HW_USBDCD_TIMER0(x).U = (v))
 553 #define HW_USBDCD_TIMER0_SET(x, v) (HW_USBDCD_TIMER0_WR(x, HW_USBDCD_TIMER0_RD(x) |  (v)))
 554 #define HW_USBDCD_TIMER0_CLR(x, v) (HW_USBDCD_TIMER0_WR(x, HW_USBDCD_TIMER0_RD(x) & ~(v)))
 555 #define HW_USBDCD_TIMER0_TOG(x, v) (HW_USBDCD_TIMER0_WR(x, HW_USBDCD_TIMER0_RD(x) ^  (v)))
 556 /*@}*/
 557
 558 /*
 559  * Constants & macros for individual USBDCD_TIMER0 bitfields
 560  */
 561
 562 /*!
 563  * @name Register USBDCD_TIMER0, field TUNITCON[11:0] (RO)
 564  *
 565  * Displays the amount of elapsed time since the event of setting the START bit
 566  * plus the value of TSEQ_INIT. The timer is automatically initialized with the
 567  * value of TSEQ_INIT before starting to count. This timer enables compliance with
 568  * the maximum time allowed to connect T UNIT_CON under the USB Battery Charging
 569  * Specification. If the timer reaches the one second limit, the module triggers
 570  * an interrupt and sets the error flag STATUS[ERR]. The timer continues
 571  * counting throughout the charger detection sequence, even when control has been passed
 572  * to software. As long as the module is active, the timer continues to count
 573  * until it reaches the maximum value of 0xFFF (4095 ms). The timer does not
 574  * rollover to zero. A software reset clears the timer.
 575  */
 576 /*@{*/
 577 #define BP_USBDCD_TIMER0_TUNITCON (0U)     /*!< Bit position for USBDCD_TIMER0_TUNITCON. */
 578 #define BM_USBDCD_TIMER0_TUNITCON (0x00000FFFU) /*!< Bit mask for USBDCD_TIMER0_TUNITCON. */
 579 #define BS_USBDCD_TIMER0_TUNITCON (12U)    /*!< Bit field size in bits for USBDCD_TIMER0_TUNITCON. */
 580
 581 /*! @brief Read current value of the USBDCD_TIMER0_TUNITCON field. */
 582 #define BR_USBDCD_TIMER0_TUNITCON(x) (HW_USBDCD_TIMER0(x).B.TUNITCON)
 583 /*@}*/
 584
 585 /*!
 586  * @name Register USBDCD_TIMER0, field TSEQ_INIT[25:16] (RW)
 587  *
 588  * TSEQ_INIT represents the system latency (in ms) measured from the time VBUS
 589  * goes active to the time system software initiates the charger detection
 590  * sequence in the USBDCD module. When software sets the CONTROL[START] bit, the Unit
 591  * Connection Timer (TUNITCON) is initialized with the value of TSEQ_INIT. Valid
 592  * values are 0-1023, but the USB Battery Charging Specification requires the
 593  * entire sequence, including TSEQ_INIT, to be completed in 1s or less.
 594  */
 595 /*@{*/
 596 #define BP_USBDCD_TIMER0_TSEQ_INIT (16U)   /*!< Bit position for USBDCD_TIMER0_TSEQ_INIT. */
 597 #define BM_USBDCD_TIMER0_TSEQ_INIT (0x03FF0000U) /*!< Bit mask for USBDCD_TIMER0_TSEQ_INIT. */
 598 #define BS_USBDCD_TIMER0_TSEQ_INIT (10U)   /*!< Bit field size in bits for USBDCD_TIMER0_TSEQ_INIT. */
 599
 600 /*! @brief Read current value of the USBDCD_TIMER0_TSEQ_INIT field. */
 601 #define BR_USBDCD_TIMER0_TSEQ_INIT(x) (HW_USBDCD_TIMER0(x).B.TSEQ_INIT)
 602
 603 /*! @brief Format value for bitfield USBDCD_TIMER0_TSEQ_INIT. */
 604 #define BF_USBDCD_TIMER0_TSEQ_INIT(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_TIMER0_TSEQ_INIT) & BM_USBDCD_TIMER0_TSEQ_INIT)
 605
 606 /*! @brief Set the TSEQ_INIT field to a new value. */
 607 #define BW_USBDCD_TIMER0_TSEQ_INIT(x, v) (HW_USBDCD_TIMER0_WR(x, (HW_USBDCD_TIMER0_RD(x) & ~BM_USBDCD_TIMER0_TSEQ_INIT) | BF_USBDCD_TIMER0_TSEQ_INIT(v)))
 608 /*@}*/
 609
 610 /*******************************************************************************
 611  * HW_USBDCD_TIMER1 - TIMER1 register
 612  ******************************************************************************/
 613
 614 /*!
 615  * @brief HW_USBDCD_TIMER1 - TIMER1 register (RW)
 616  *
 617  * Reset value: 0x000A0028U
 618  *
 619  * TIMER1 contains timing parameters. Note that register values can be written
 620  * that are not compliant with the USB Battery Charging Specification, so care
 621  * should be taken when overwriting the default values.
 622  */
 623 typedef union _hw_usbdcd_timer1
 624 {
 625     uint32_t U;
 626     struct _hw_usbdcd_timer1_bitfields
 627     {
 628         uint32_t TVDPSRC_ON : 10;      /*!< [9:0] Time Period Comparator Enabled */
 629         uint32_t RESERVED0 : 6;        /*!< [15:10]  */
 630         uint32_t TDCD_DBNC : 10;       /*!< [25:16] Time Period to Debounce D+
 631                                         * Signal */
 632         uint32_t RESERVED1 : 6;        /*!< [31:26]  */
 633     } B;
 634 } hw_usbdcd_timer1_t;
 635
 636 /*!
 637  * @name Constants and macros for entire USBDCD_TIMER1 register
 638  */
 639 /*@{*/
 640 #define HW_USBDCD_TIMER1_ADDR(x) ((x) + 0x14U)
 641
 642 #define HW_USBDCD_TIMER1(x)      (*(__IO hw_usbdcd_timer1_t *) HW_USBDCD_TIMER1_ADDR(x))
 643 #define HW_USBDCD_TIMER1_RD(x)   (HW_USBDCD_TIMER1(x).U)
 644 #define HW_USBDCD_TIMER1_WR(x, v) (HW_USBDCD_TIMER1(x).U = (v))
 645 #define HW_USBDCD_TIMER1_SET(x, v) (HW_USBDCD_TIMER1_WR(x, HW_USBDCD_TIMER1_RD(x) |  (v)))
 646 #define HW_USBDCD_TIMER1_CLR(x, v) (HW_USBDCD_TIMER1_WR(x, HW_USBDCD_TIMER1_RD(x) & ~(v)))
 647 #define HW_USBDCD_TIMER1_TOG(x, v) (HW_USBDCD_TIMER1_WR(x, HW_USBDCD_TIMER1_RD(x) ^  (v)))
 648 /*@}*/
 649
 650 /*
 651  * Constants & macros for individual USBDCD_TIMER1 bitfields
 652  */
 653
 654 /*!
 655  * @name Register USBDCD_TIMER1, field TVDPSRC_ON[9:0] (RW)
 656  *
 657  * This timing parameter is used after detection of the data pin. See "Charging
 658  * Port Detection". Valid values are 1-1023, but the USB Battery Charging
 659  * Specification requires a minimum value of 40 ms.
 660  */
 661 /*@{*/
 662 #define BP_USBDCD_TIMER1_TVDPSRC_ON (0U)   /*!< Bit position for USBDCD_TIMER1_TVDPSRC_ON. */
 663 #define BM_USBDCD_TIMER1_TVDPSRC_ON (0x000003FFU) /*!< Bit mask for USBDCD_TIMER1_TVDPSRC_ON. */
 664 #define BS_USBDCD_TIMER1_TVDPSRC_ON (10U)  /*!< Bit field size in bits for USBDCD_TIMER1_TVDPSRC_ON. */
 665
 666 /*! @brief Read current value of the USBDCD_TIMER1_TVDPSRC_ON field. */
 667 #define BR_USBDCD_TIMER1_TVDPSRC_ON(x) (HW_USBDCD_TIMER1(x).B.TVDPSRC_ON)
 668
 669 /*! @brief Format value for bitfield USBDCD_TIMER1_TVDPSRC_ON. */
 670 #define BF_USBDCD_TIMER1_TVDPSRC_ON(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_TIMER1_TVDPSRC_ON) & BM_USBDCD_TIMER1_TVDPSRC_ON)
 671
 672 /*! @brief Set the TVDPSRC_ON field to a new value. */
 673 #define BW_USBDCD_TIMER1_TVDPSRC_ON(x, v) (HW_USBDCD_TIMER1_WR(x, (HW_USBDCD_TIMER1_RD(x) & ~BM_USBDCD_TIMER1_TVDPSRC_ON) | BF_USBDCD_TIMER1_TVDPSRC_ON(v)))
 674 /*@}*/
 675
 676 /*!
 677  * @name Register USBDCD_TIMER1, field TDCD_DBNC[25:16] (RW)
 678  *
 679  * Sets the time period (ms) to debounce the D+ signal during the data pin
 680  * contact detection phase. See "Debouncing the data pin contact" Valid values are
 681  * 1-1023, but the USB Battery Charging Specification requires a minimum value of 10
 682  * ms.
 683  */
 684 /*@{*/
 685 #define BP_USBDCD_TIMER1_TDCD_DBNC (16U)   /*!< Bit position for USBDCD_TIMER1_TDCD_DBNC. */
 686 #define BM_USBDCD_TIMER1_TDCD_DBNC (0x03FF0000U) /*!< Bit mask for USBDCD_TIMER1_TDCD_DBNC. */
 687 #define BS_USBDCD_TIMER1_TDCD_DBNC (10U)   /*!< Bit field size in bits for USBDCD_TIMER1_TDCD_DBNC. */
 688
 689 /*! @brief Read current value of the USBDCD_TIMER1_TDCD_DBNC field. */
 690 #define BR_USBDCD_TIMER1_TDCD_DBNC(x) (HW_USBDCD_TIMER1(x).B.TDCD_DBNC)
 691
 692 /*! @brief Format value for bitfield USBDCD_TIMER1_TDCD_DBNC. */
 693 #define BF_USBDCD_TIMER1_TDCD_DBNC(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_TIMER1_TDCD_DBNC) & BM_USBDCD_TIMER1_TDCD_DBNC)
 694
 695 /*! @brief Set the TDCD_DBNC field to a new value. */
 696 #define BW_USBDCD_TIMER1_TDCD_DBNC(x, v) (HW_USBDCD_TIMER1_WR(x, (HW_USBDCD_TIMER1_RD(x) & ~BM_USBDCD_TIMER1_TDCD_DBNC) | BF_USBDCD_TIMER1_TDCD_DBNC(v)))
 697 /*@}*/
 698
 699 /*******************************************************************************
 700  * HW_USBDCD_TIMER2_BC11 - TIMER2_BC11 register
 701  ******************************************************************************/
 702
 703 /*!
 704  * @brief HW_USBDCD_TIMER2_BC11 - TIMER2_BC11 register (RW)
 705  *
 706  * Reset value: 0x00280001U
 707  *
 708  * TIMER2_BC11 contains timing parameters for USB Battery Charging
 709  * Specification, v1.1. Register values can be written that are not compliant with the USB
 710  * Battery Charging Specification, so care should be taken when overwriting the
 711  * default values.
 712  */
 713 typedef union _hw_usbdcd_timer2_bc11
 714 {
 715     uint32_t U;
 716     struct _hw_usbdcd_timer2_bc11_bitfields
 717     {
 718         uint32_t CHECK_DM : 4;         /*!< [3:0] Time Before Check of D- Line */
 719         uint32_t RESERVED0 : 12;       /*!< [15:4]  */
 720         uint32_t TVDPSRC_CON : 10;     /*!< [25:16] Time Period Before Enabling
 721                                         * D+ Pullup */
 722         uint32_t RESERVED1 : 6;        /*!< [31:26]  */
 723     } B;
 724 } hw_usbdcd_timer2_bc11_t;
 725
 726 /*!
 727  * @name Constants and macros for entire USBDCD_TIMER2_BC11 register
 728  */
 729 /*@{*/
 730 #define HW_USBDCD_TIMER2_BC11_ADDR(x) ((x) + 0x18U)
 731
 732 #define HW_USBDCD_TIMER2_BC11(x) (*(__IO hw_usbdcd_timer2_bc11_t *) HW_USBDCD_TIMER2_BC11_ADDR(x))
 733 #define HW_USBDCD_TIMER2_BC11_RD(x) (HW_USBDCD_TIMER2_BC11(x).U)
 734 #define HW_USBDCD_TIMER2_BC11_WR(x, v) (HW_USBDCD_TIMER2_BC11(x).U = (v))
 735 #define HW_USBDCD_TIMER2_BC11_SET(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, HW_USBDCD_TIMER2_BC11_RD(x) |  (v)))
 736 #define HW_USBDCD_TIMER2_BC11_CLR(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, HW_USBDCD_TIMER2_BC11_RD(x) & ~(v)))
 737 #define HW_USBDCD_TIMER2_BC11_TOG(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, HW_USBDCD_TIMER2_BC11_RD(x) ^  (v)))
 738 /*@}*/
 739
 740 /*
 741  * Constants & macros for individual USBDCD_TIMER2_BC11 bitfields
 742  */
 743
 744 /*!
 745  * @name Register USBDCD_TIMER2_BC11, field CHECK_DM[3:0] (RW)
 746  *
 747  * Sets the amount of time (in ms) that the module waits after the device
 748  * connects to the USB bus until checking the state of the D- line to determine the
 749  * type of charging port. See "Charger Type Detection." Valid values are 1-15ms.
 750  */
 751 /*@{*/
 752 #define BP_USBDCD_TIMER2_BC11_CHECK_DM (0U) /*!< Bit position for USBDCD_TIMER2_BC11_CHECK_DM. */
 753 #define BM_USBDCD_TIMER2_BC11_CHECK_DM (0x0000000FU) /*!< Bit mask for USBDCD_TIMER2_BC11_CHECK_DM. */
 754 #define BS_USBDCD_TIMER2_BC11_CHECK_DM (4U) /*!< Bit field size in bits for USBDCD_TIMER2_BC11_CHECK_DM. */
 755
 756 /*! @brief Read current value of the USBDCD_TIMER2_BC11_CHECK_DM field. */
 757 #define BR_USBDCD_TIMER2_BC11_CHECK_DM(x) (HW_USBDCD_TIMER2_BC11(x).B.CHECK_DM)
 758
 759 /*! @brief Format value for bitfield USBDCD_TIMER2_BC11_CHECK_DM. */
 760 #define BF_USBDCD_TIMER2_BC11_CHECK_DM(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_TIMER2_BC11_CHECK_DM) & BM_USBDCD_TIMER2_BC11_CHECK_DM)
 761
 762 /*! @brief Set the CHECK_DM field to a new value. */
 763 #define BW_USBDCD_TIMER2_BC11_CHECK_DM(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, (HW_USBDCD_TIMER2_BC11_RD(x) & ~BM_USBDCD_TIMER2_BC11_CHECK_DM) | BF_USBDCD_TIMER2_BC11_CHECK_DM(v)))
 764 /*@}*/
 765
 766 /*!
 767  * @name Register USBDCD_TIMER2_BC11, field TVDPSRC_CON[25:16] (RW)
 768  *
 769  * Sets the time period (ms) that the module waits after charging port detection
 770  * before system software must enable the D+ pullup to connect to the USB host.
 771  * Valid values are 1-1023, but the USB Battery Charging Specification requires a
 772  * minimum value of 40 ms.
 773  */
 774 /*@{*/
 775 #define BP_USBDCD_TIMER2_BC11_TVDPSRC_CON (16U) /*!< Bit position for USBDCD_TIMER2_BC11_TVDPSRC_CON. */
 776 #define BM_USBDCD_TIMER2_BC11_TVDPSRC_CON (0x03FF0000U) /*!< Bit mask for USBDCD_TIMER2_BC11_TVDPSRC_CON. */
 777 #define BS_USBDCD_TIMER2_BC11_TVDPSRC_CON (10U) /*!< Bit field size in bits for USBDCD_TIMER2_BC11_TVDPSRC_CON. */
 778
 779 /*! @brief Read current value of the USBDCD_TIMER2_BC11_TVDPSRC_CON field. */
 780 #define BR_USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (HW_USBDCD_TIMER2_BC11(x).B.TVDPSRC_CON)
 781
 782 /*! @brief Format value for bitfield USBDCD_TIMER2_BC11_TVDPSRC_CON. */
 783 #define BF_USBDCD_TIMER2_BC11_TVDPSRC_CON(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_TIMER2_BC11_TVDPSRC_CON) & BM_USBDCD_TIMER2_BC11_TVDPSRC_CON)
 784
 785 /*! @brief Set the TVDPSRC_CON field to a new value. */
 786 #define BW_USBDCD_TIMER2_BC11_TVDPSRC_CON(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, (HW_USBDCD_TIMER2_BC11_RD(x) & ~BM_USBDCD_TIMER2_BC11_TVDPSRC_CON) | BF_USBDCD_TIMER2_BC11_TVDPSRC_CON(v)))
 787 /*@}*/
 788 /*******************************************************************************
 789  * HW_USBDCD_TIMER2_BC12 - TIMER2_BC12 register
 790  ******************************************************************************/
 791
 792 /*!
 793  * @brief HW_USBDCD_TIMER2_BC12 - TIMER2_BC12 register (RW)
 794  *
 795  * Reset value: 0x00010028U
 796  *
 797  * TIMER2_BC12 contains timing parameters for USB Battery Charging
 798  * Specification, v1.2. Register values can be written that are not compliant with the USB
 799  * Battery Charging Specification, so care should be taken when overwriting the
 800  * default values.
 801  */
 802 typedef union _hw_usbdcd_timer2_bc12
 803 {
 804     uint32_t U;
 805     struct _hw_usbdcd_timer2_bc12_bitfields
 806     {
 807         uint32_t TVDMSRC_ON : 10;      /*!< [9:0]  */
 808         uint32_t RESERVED0 : 6;        /*!< [15:10]  */
 809         uint32_t TWAIT_AFTER_PRD : 10; /*!< [25:16]  */
 810         uint32_t RESERVED1 : 6;        /*!< [31:26]  */
 811     } B;
 812 } hw_usbdcd_timer2_bc12_t;
 813
 814 /*!
 815  * @name Constants and macros for entire USBDCD_TIMER2_BC12 register
 816  */
 817 /*@{*/
 818 #define HW_USBDCD_TIMER2_BC12_ADDR(x) ((x) + 0x18U)
 819
 820 #define HW_USBDCD_TIMER2_BC12(x) (*(__IO hw_usbdcd_timer2_bc12_t *) HW_USBDCD_TIMER2_BC12_ADDR(x))
 821 #define HW_USBDCD_TIMER2_BC12_RD(x) (HW_USBDCD_TIMER2_BC12(x).U)
 822 #define HW_USBDCD_TIMER2_BC12_WR(x, v) (HW_USBDCD_TIMER2_BC12(x).U = (v))
 823 #define HW_USBDCD_TIMER2_BC12_SET(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, HW_USBDCD_TIMER2_BC12_RD(x) |  (v)))
 824 #define HW_USBDCD_TIMER2_BC12_CLR(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, HW_USBDCD_TIMER2_BC12_RD(x) & ~(v)))
 825 #define HW_USBDCD_TIMER2_BC12_TOG(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, HW_USBDCD_TIMER2_BC12_RD(x) ^  (v)))
 826 /*@}*/
 827
 828 /*
 829  * Constants & macros for individual USBDCD_TIMER2_BC12 bitfields
 830  */
 831
 832 /*!
 833  * @name Register USBDCD_TIMER2_BC12, field TVDMSRC_ON[9:0] (RW)
 834  *
 835  * Sets the amount of time (in ms) that the module enables the VDM_SRC. Valid
 836  * values are 0-40ms.
 837  */
 838 /*@{*/
 839 #define BP_USBDCD_TIMER2_BC12_TVDMSRC_ON (0U) /*!< Bit position for USBDCD_TIMER2_BC12_TVDMSRC_ON. */
 840 #define BM_USBDCD_TIMER2_BC12_TVDMSRC_ON (0x000003FFU) /*!< Bit mask for USBDCD_TIMER2_BC12_TVDMSRC_ON. */
 841 #define BS_USBDCD_TIMER2_BC12_TVDMSRC_ON (10U) /*!< Bit field size in bits for USBDCD_TIMER2_BC12_TVDMSRC_ON. */
 842
 843 /*! @brief Read current value of the USBDCD_TIMER2_BC12_TVDMSRC_ON field. */
 844 #define BR_USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (HW_USBDCD_TIMER2_BC12(x).B.TVDMSRC_ON)
 845
 846 /*! @brief Format value for bitfield USBDCD_TIMER2_BC12_TVDMSRC_ON. */
 847 #define BF_USBDCD_TIMER2_BC12_TVDMSRC_ON(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_TIMER2_BC12_TVDMSRC_ON) & BM_USBDCD_TIMER2_BC12_TVDMSRC_ON)
 848
 849 /*! @brief Set the TVDMSRC_ON field to a new value. */
 850 #define BW_USBDCD_TIMER2_BC12_TVDMSRC_ON(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, (HW_USBDCD_TIMER2_BC12_RD(x) & ~BM_USBDCD_TIMER2_BC12_TVDMSRC_ON) | BF_USBDCD_TIMER2_BC12_TVDMSRC_ON(v)))
 851 /*@}*/
 852
 853 /*!
 854  * @name Register USBDCD_TIMER2_BC12, field TWAIT_AFTER_PRD[25:16] (RW)
 855  *
 856  * Sets the amount of time (in ms) that the module waits after primary detection
 857  * before start to secondary detection. Valid values are 1-1023ms. Default is
 858  * 1ms.
 859  */
 860 /*@{*/
 861 #define BP_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD (16U) /*!< Bit position for USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD. */
 862 #define BM_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD (0x03FF0000U) /*!< Bit mask for USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD. */
 863 #define BS_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD (10U) /*!< Bit field size in bits for USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD. */
 864
 865 /*! @brief Read current value of the USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD field. */
 866 #define BR_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (HW_USBDCD_TIMER2_BC12(x).B.TWAIT_AFTER_PRD)
 867
 868 /*! @brief Format value for bitfield USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD. */
 869 #define BF_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD) & BM_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD)
 870
 871 /*! @brief Set the TWAIT_AFTER_PRD field to a new value. */
 872 #define BW_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, (HW_USBDCD_TIMER2_BC12_RD(x) & ~BM_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD) | BF_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(v)))
 873 /*@}*/
 874
 875 /*
 876 ** Start of section using anonymous unions
 877 */
 878
 879 #if defined(__ARMCC_VERSION)
 880   #pragma push
 881   #pragma anon_unions
 882 #elif defined(__CWCC__)
 883   #pragma push
 884   #pragma cpp_extensions on
 885 #elif defined(__GNUC__)
 886   /* anonymous unions are enabled by default */
 887 #elif defined(__IAR_SYSTEMS_ICC__)
 888   #pragma language=extended
 889 #else
 890   #error Not supported compiler type
 891 #endif
 892
 893 /*******************************************************************************
 894  * hw_usbdcd_t - module struct
 895  ******************************************************************************/
 896 /*!
 897  * @brief All USBDCD module registers.
 898  */
 899 #pragma pack(1)
 900 typedef struct _hw_usbdcd
 901 {
 902     __IO hw_usbdcd_control_t CONTROL;      /*!< [0x0] Control register */
 903     __IO hw_usbdcd_clock_t CLOCK;          /*!< [0x4] Clock register */
 904     __I hw_usbdcd_status_t STATUS;         /*!< [0x8] Status register */
 905     uint8_t _reserved0[4];
 906     __IO hw_usbdcd_timer0_t TIMER0;        /*!< [0x10] TIMER0 register */
 907     __IO hw_usbdcd_timer1_t TIMER1;        /*!< [0x14] TIMER1 register */
 908     union {
 909         __IO hw_usbdcd_timer2_bc11_t TIMER2_BC11; /*!< [0x18] TIMER2_BC11 register */
 910         __IO hw_usbdcd_timer2_bc12_t TIMER2_BC12; /*!< [0x18] TIMER2_BC12 register */
 911     };
 912 } hw_usbdcd_t;
 913 #pragma pack()
 914
 915 /*! @brief Macro to access all USBDCD registers. */
 916 /*! @param x USBDCD module instance base address. */
 917 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
 918  *     use the '&' operator, like <code>&HW_USBDCD(USBDCD_BASE)</code>. */
 919 #define HW_USBDCD(x)   (*(hw_usbdcd_t *)(x))
 920
 921 /*
 922 ** End of section using anonymous unions
 923 */
 924
 925 #if defined(__ARMCC_VERSION)
 926   #pragma pop
 927 #elif defined(__CWCC__)
 928   #pragma pop
 929 #elif defined(__GNUC__)
 930   /* leave anonymous unions enabled */
 931 #elif defined(__IAR_SYSTEMS_ICC__)
 932   #pragma language=default
 933 #else
 934   #error Not supported compiler type
 935 #endif
 936
 937 #endif /* __HW_USBDCD_REGISTERS_H__ */
 938 /* EOF */