tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_vref.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
   9 **     Version:             rev. 2.5, 2014-02-10
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-08-12)
  48 **         Initial version.
  49 **     - rev. 2.0 (2013-10-29)
  50 **         Register accessor macros added to the memory map.
  51 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  52 **         Startup file for gcc has been updated according to CMSIS 3.2.
  53 **         System initialization updated.
  54 **         MCG - registers updated.
  55 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-09)
  59 **         DMA - EARS register removed.
  60 **         AIPS0, AIPS1 - MPRA register updated.
  61 **     - rev. 2.3 (2014-01-24)
  62 **         Update according to reference manual rev. 2
  63 **         ENET, MCG, MCM, SIM, USB - registers updated
  64 **     - rev. 2.4 (2014-02-10)
  65 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  66 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  67 **     - rev. 2.5 (2014-02-10)
  68 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  69 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  70 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  71 **
  72 ** ###################################################################
  73 */
  74
  75 /*
  76  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  77  *
  78  * This file was generated automatically and any changes may be lost.
  79  */
  80 #ifndef __HW_VREF_REGISTERS_H__
  81 #define __HW_VREF_REGISTERS_H__
  82
  83 #include "MK64F12.h"
  84 #include "fsl_bitaccess.h"
  85
  86 /*
  87  * MK64F12 VREF
  88  *
  89  * Voltage Reference
  90  *
  91  * Registers defined in this header file:
  92  * - HW_VREF_TRM - VREF Trim Register
  93  * - HW_VREF_SC - VREF Status and Control Register
  94  *
  95  * - hw_vref_t - Struct containing all module registers.
  96  */
  97
  98 #define HW_VREF_INSTANCE_COUNT (1U) /*!< Number of instances of the VREF module. */
  99
 100 /*******************************************************************************
 101  * HW_VREF_TRM - VREF Trim Register
 102  ******************************************************************************/
 103
 104 /*!
 105  * @brief HW_VREF_TRM - VREF Trim Register (RW)
 106  *
 107  * Reset value: 0x00U
 108  *
 109  * This register contains bits that contain the trim data for the Voltage
 110  * Reference.
 111  */
 112 typedef union _hw_vref_trm
 113 {
 114     uint8_t U;
 115     struct _hw_vref_trm_bitfields
 116     {
 117         uint8_t TRIM : 6;              /*!< [5:0] Trim bits */
 118         uint8_t CHOPEN : 1;            /*!< [6] Chop oscillator enable. When set,
 119                                         * internal chopping operation is enabled and the internal analog offset will be
 120                                         * minimized. */
 121         uint8_t RESERVED0 : 1;         /*!< [7]  */
 122     } B;
 123 } hw_vref_trm_t;
 124
 125 /*!
 126  * @name Constants and macros for entire VREF_TRM register
 127  */
 128 /*@{*/
 129 #define HW_VREF_TRM_ADDR(x)      ((x) + 0x0U)
 130
 131 #define HW_VREF_TRM(x)           (*(__IO hw_vref_trm_t *) HW_VREF_TRM_ADDR(x))
 132 #define HW_VREF_TRM_RD(x)        (HW_VREF_TRM(x).U)
 133 #define HW_VREF_TRM_WR(x, v)     (HW_VREF_TRM(x).U = (v))
 134 #define HW_VREF_TRM_SET(x, v)    (HW_VREF_TRM_WR(x, HW_VREF_TRM_RD(x) |  (v)))
 135 #define HW_VREF_TRM_CLR(x, v)    (HW_VREF_TRM_WR(x, HW_VREF_TRM_RD(x) & ~(v)))
 136 #define HW_VREF_TRM_TOG(x, v)    (HW_VREF_TRM_WR(x, HW_VREF_TRM_RD(x) ^  (v)))
 137 /*@}*/
 138
 139 /*
 140  * Constants & macros for individual VREF_TRM bitfields
 141  */
 142
 143 /*!
 144  * @name Register VREF_TRM, field TRIM[5:0] (RW)
 145  *
 146  * These bits change the resulting VREF by approximately +/- 0.5 mV for each
 147  * step. Min = minimum and max = maximum voltage reference output. For minimum and
 148  * maximum voltage reference output values, refer to the Data Sheet for this chip.
 149  *
 150  * Values:
 151  * - 000000 - Min
 152  * - 111111 - Max
 153  */
 154 /*@{*/
 155 #define BP_VREF_TRM_TRIM     (0U)          /*!< Bit position for VREF_TRM_TRIM. */
 156 #define BM_VREF_TRM_TRIM     (0x3FU)       /*!< Bit mask for VREF_TRM_TRIM. */
 157 #define BS_VREF_TRM_TRIM     (6U)          /*!< Bit field size in bits for VREF_TRM_TRIM. */
 158
 159 /*! @brief Read current value of the VREF_TRM_TRIM field. */
 160 #define BR_VREF_TRM_TRIM(x)  (HW_VREF_TRM(x).B.TRIM)
 161
 162 /*! @brief Format value for bitfield VREF_TRM_TRIM. */
 163 #define BF_VREF_TRM_TRIM(v)  ((uint8_t)((uint8_t)(v) << BP_VREF_TRM_TRIM) & BM_VREF_TRM_TRIM)
 164
 165 /*! @brief Set the TRIM field to a new value. */
 166 #define BW_VREF_TRM_TRIM(x, v) (HW_VREF_TRM_WR(x, (HW_VREF_TRM_RD(x) & ~BM_VREF_TRM_TRIM) | BF_VREF_TRM_TRIM(v)))
 167 /*@}*/
 168
 169 /*!
 170  * @name Register VREF_TRM, field CHOPEN[6] (RW)
 171  *
 172  * This bit is set during factory trimming of the VREF voltage. This bit should
 173  * be written to 1 to achieve the performance stated in the data sheet.
 174  *
 175  * Values:
 176  * - 0 - Chop oscillator is disabled.
 177  * - 1 - Chop oscillator is enabled.
 178  */
 179 /*@{*/
 180 #define BP_VREF_TRM_CHOPEN   (6U)          /*!< Bit position for VREF_TRM_CHOPEN. */
 181 #define BM_VREF_TRM_CHOPEN   (0x40U)       /*!< Bit mask for VREF_TRM_CHOPEN. */
 182 #define BS_VREF_TRM_CHOPEN   (1U)          /*!< Bit field size in bits for VREF_TRM_CHOPEN. */
 183
 184 /*! @brief Read current value of the VREF_TRM_CHOPEN field. */
 185 #define BR_VREF_TRM_CHOPEN(x) (BITBAND_ACCESS8(HW_VREF_TRM_ADDR(x), BP_VREF_TRM_CHOPEN))
 186
 187 /*! @brief Format value for bitfield VREF_TRM_CHOPEN. */
 188 #define BF_VREF_TRM_CHOPEN(v) ((uint8_t)((uint8_t)(v) << BP_VREF_TRM_CHOPEN) & BM_VREF_TRM_CHOPEN)
 189
 190 /*! @brief Set the CHOPEN field to a new value. */
 191 #define BW_VREF_TRM_CHOPEN(x, v) (BITBAND_ACCESS8(HW_VREF_TRM_ADDR(x), BP_VREF_TRM_CHOPEN) = (v))
 192 /*@}*/
 193
 194 /*******************************************************************************
 195  * HW_VREF_SC - VREF Status and Control Register
 196  ******************************************************************************/
 197
 198 /*!
 199  * @brief HW_VREF_SC - VREF Status and Control Register (RW)
 200  *
 201  * Reset value: 0x00U
 202  *
 203  * This register contains the control bits used to enable the internal voltage
 204  * reference and to select the buffer mode to be used.
 205  */
 206 typedef union _hw_vref_sc
 207 {
 208     uint8_t U;
 209     struct _hw_vref_sc_bitfields
 210     {
 211         uint8_t MODE_LV : 2;           /*!< [1:0] Buffer Mode selection */
 212         uint8_t VREFST : 1;            /*!< [2] Internal Voltage Reference stable */
 213         uint8_t RESERVED0 : 2;         /*!< [4:3]  */
 214         uint8_t ICOMPEN : 1;           /*!< [5] Second order curvature compensation
 215                                         * enable */
 216         uint8_t REGEN : 1;             /*!< [6] Regulator enable */
 217         uint8_t VREFEN : 1;            /*!< [7] Internal Voltage Reference enable */
 218     } B;
 219 } hw_vref_sc_t;
 220
 221 /*!
 222  * @name Constants and macros for entire VREF_SC register
 223  */
 224 /*@{*/
 225 #define HW_VREF_SC_ADDR(x)       ((x) + 0x1U)
 226
 227 #define HW_VREF_SC(x)            (*(__IO hw_vref_sc_t *) HW_VREF_SC_ADDR(x))
 228 #define HW_VREF_SC_RD(x)         (HW_VREF_SC(x).U)
 229 #define HW_VREF_SC_WR(x, v)      (HW_VREF_SC(x).U = (v))
 230 #define HW_VREF_SC_SET(x, v)     (HW_VREF_SC_WR(x, HW_VREF_SC_RD(x) |  (v)))
 231 #define HW_VREF_SC_CLR(x, v)     (HW_VREF_SC_WR(x, HW_VREF_SC_RD(x) & ~(v)))
 232 #define HW_VREF_SC_TOG(x, v)     (HW_VREF_SC_WR(x, HW_VREF_SC_RD(x) ^  (v)))
 233 /*@}*/
 234
 235 /*
 236  * Constants & macros for individual VREF_SC bitfields
 237  */
 238
 239 /*!
 240  * @name Register VREF_SC, field MODE_LV[1:0] (RW)
 241  *
 242  * These bits select the buffer modes for the Voltage Reference module.
 243  *
 244  * Values:
 245  * - 00 - Bandgap on only, for stabilization and startup
 246  * - 01 - High power buffer mode enabled
 247  * - 10 - Low-power buffer mode enabled
 248  * - 11 - Reserved
 249  */
 250 /*@{*/
 251 #define BP_VREF_SC_MODE_LV   (0U)          /*!< Bit position for VREF_SC_MODE_LV. */
 252 #define BM_VREF_SC_MODE_LV   (0x03U)       /*!< Bit mask for VREF_SC_MODE_LV. */
 253 #define BS_VREF_SC_MODE_LV   (2U)          /*!< Bit field size in bits for VREF_SC_MODE_LV. */
 254
 255 /*! @brief Read current value of the VREF_SC_MODE_LV field. */
 256 #define BR_VREF_SC_MODE_LV(x) (HW_VREF_SC(x).B.MODE_LV)
 257
 258 /*! @brief Format value for bitfield VREF_SC_MODE_LV. */
 259 #define BF_VREF_SC_MODE_LV(v) ((uint8_t)((uint8_t)(v) << BP_VREF_SC_MODE_LV) & BM_VREF_SC_MODE_LV)
 260
 261 /*! @brief Set the MODE_LV field to a new value. */
 262 #define BW_VREF_SC_MODE_LV(x, v) (HW_VREF_SC_WR(x, (HW_VREF_SC_RD(x) & ~BM_VREF_SC_MODE_LV) | BF_VREF_SC_MODE_LV(v)))
 263 /*@}*/
 264
 265 /*!
 266  * @name Register VREF_SC, field VREFST[2] (RO)
 267  *
 268  * This bit indicates that the bandgap reference within the Voltage Reference
 269  * module has completed its startup and stabilization.
 270  *
 271  * Values:
 272  * - 0 - The module is disabled or not stable.
 273  * - 1 - The module is stable.
 274  */
 275 /*@{*/
 276 #define BP_VREF_SC_VREFST    (2U)          /*!< Bit position for VREF_SC_VREFST. */
 277 #define BM_VREF_SC_VREFST    (0x04U)       /*!< Bit mask for VREF_SC_VREFST. */
 278 #define BS_VREF_SC_VREFST    (1U)          /*!< Bit field size in bits for VREF_SC_VREFST. */
 279
 280 /*! @brief Read current value of the VREF_SC_VREFST field. */
 281 #define BR_VREF_SC_VREFST(x) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_VREFST))
 282 /*@}*/
 283
 284 /*!
 285  * @name Register VREF_SC, field ICOMPEN[5] (RW)
 286  *
 287  * This bit is set during factory trimming of the VREF voltage. This bit should
 288  * be written to 1 to achieve the performance stated in the data sheet.
 289  *
 290  * Values:
 291  * - 0 - Disabled
 292  * - 1 - Enabled
 293  */
 294 /*@{*/
 295 #define BP_VREF_SC_ICOMPEN   (5U)          /*!< Bit position for VREF_SC_ICOMPEN. */
 296 #define BM_VREF_SC_ICOMPEN   (0x20U)       /*!< Bit mask for VREF_SC_ICOMPEN. */
 297 #define BS_VREF_SC_ICOMPEN   (1U)          /*!< Bit field size in bits for VREF_SC_ICOMPEN. */
 298
 299 /*! @brief Read current value of the VREF_SC_ICOMPEN field. */
 300 #define BR_VREF_SC_ICOMPEN(x) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_ICOMPEN))
 301
 302 /*! @brief Format value for bitfield VREF_SC_ICOMPEN. */
 303 #define BF_VREF_SC_ICOMPEN(v) ((uint8_t)((uint8_t)(v) << BP_VREF_SC_ICOMPEN) & BM_VREF_SC_ICOMPEN)
 304
 305 /*! @brief Set the ICOMPEN field to a new value. */
 306 #define BW_VREF_SC_ICOMPEN(x, v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_ICOMPEN) = (v))
 307 /*@}*/
 308
 309 /*!
 310  * @name Register VREF_SC, field REGEN[6] (RW)
 311  *
 312  * This bit is used to enable the internal 1.75 V regulator to produce a
 313  * constant internal voltage supply in order to reduce the sensitivity to external
 314  * supply noise and variation. If it is desired to keep the regulator enabled in very
 315  * low power modes, refer to the Chip Configuration details for a description on
 316  * how this can be achieved. This bit is set during factory trimming of the VREF
 317  * voltage. This bit should be written to 1 to achieve the performance stated in
 318  * the data sheet.
 319  *
 320  * Values:
 321  * - 0 - Internal 1.75 V regulator is disabled.
 322  * - 1 - Internal 1.75 V regulator is enabled.
 323  */
 324 /*@{*/
 325 #define BP_VREF_SC_REGEN     (6U)          /*!< Bit position for VREF_SC_REGEN. */
 326 #define BM_VREF_SC_REGEN     (0x40U)       /*!< Bit mask for VREF_SC_REGEN. */
 327 #define BS_VREF_SC_REGEN     (1U)          /*!< Bit field size in bits for VREF_SC_REGEN. */
 328
 329 /*! @brief Read current value of the VREF_SC_REGEN field. */
 330 #define BR_VREF_SC_REGEN(x)  (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_REGEN))
 331
 332 /*! @brief Format value for bitfield VREF_SC_REGEN. */
 333 #define BF_VREF_SC_REGEN(v)  ((uint8_t)((uint8_t)(v) << BP_VREF_SC_REGEN) & BM_VREF_SC_REGEN)
 334
 335 /*! @brief Set the REGEN field to a new value. */
 336 #define BW_VREF_SC_REGEN(x, v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_REGEN) = (v))
 337 /*@}*/
 338
 339 /*!
 340  * @name Register VREF_SC, field VREFEN[7] (RW)
 341  *
 342  * This bit is used to enable the bandgap reference within the Voltage Reference
 343  * module. After the VREF is enabled, turning off the clock to the VREF module
 344  * via the corresponding clock gate register will not disable the VREF. VREF must
 345  * be disabled via this VREFEN bit.
 346  *
 347  * Values:
 348  * - 0 - The module is disabled.
 349  * - 1 - The module is enabled.
 350  */
 351 /*@{*/
 352 #define BP_VREF_SC_VREFEN    (7U)          /*!< Bit position for VREF_SC_VREFEN. */
 353 #define BM_VREF_SC_VREFEN    (0x80U)       /*!< Bit mask for VREF_SC_VREFEN. */
 354 #define BS_VREF_SC_VREFEN    (1U)          /*!< Bit field size in bits for VREF_SC_VREFEN. */
 355
 356 /*! @brief Read current value of the VREF_SC_VREFEN field. */
 357 #define BR_VREF_SC_VREFEN(x) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_VREFEN))
 358
 359 /*! @brief Format value for bitfield VREF_SC_VREFEN. */
 360 #define BF_VREF_SC_VREFEN(v) ((uint8_t)((uint8_t)(v) << BP_VREF_SC_VREFEN) & BM_VREF_SC_VREFEN)
 361
 362 /*! @brief Set the VREFEN field to a new value. */
 363 #define BW_VREF_SC_VREFEN(x, v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_VREFEN) = (v))
 364 /*@}*/
 365
 366 /*******************************************************************************
 367  * hw_vref_t - module struct
 368  ******************************************************************************/
 369 /*!
 370  * @brief All VREF module registers.
 371  */
 372 #pragma pack(1)
 373 typedef struct _hw_vref
 374 {
 375     __IO hw_vref_trm_t TRM;                /*!< [0x0] VREF Trim Register */
 376     __IO hw_vref_sc_t SC;                  /*!< [0x1] VREF Status and Control Register */
 377 } hw_vref_t;
 378 #pragma pack()
 379
 380 /*! @brief Macro to access all VREF registers. */
 381 /*! @param x VREF module instance base address. */
 382 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
 383  *     use the '&' operator, like <code>&HW_VREF(VREF_BASE)</code>. */
 384 #define HW_VREF(x)     (*(hw_vref_t *)(x))
 385
 386 #endif /* __HW_VREF_REGISTERS_H__ */
 387 /* EOF */