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git.gir.st - tmk_keyboard.git/blob - tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/PeripheralPins.c
1 /*******************************************************************************
2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Except as contained in this notice, the name of Maxim Integrated
23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
24 * Products, Inc. Branding Policy.
26 * The mere transfer of this software does not imply any licenses
27 * of trade secrets, proprietary technology, copyrights, patents,
28 * trademarks, maskwork rights, or any other form of intellectual
29 * property whatsoever. Maxim Integrated Products, Inc. retains all
31 *******************************************************************************
35 #include "PeripheralPins.h"
36 #include "ioman_regs.h"
39 * To select a peripheral function on Maxim microcontrollers, multiple
40 * configurations must be made. The mbed PinMap structure only includes one
41 * data member to hold this information. To extend the configuration storage,
42 * the "function" data member is used as a pointer to a pin_function_t
43 * structure. This structure is defined in objects.h. The definitions below
44 * include the creation of the pin_function_t structures and the assignment of
45 * the pointers to the "function" data members.
48 #ifdef TOOLCHAIN_ARM_STD
49 #pragma diag_suppress 1296
52 /************I2C***************/
53 const PinMap PinMap_I2C_SDA
[] = {
54 { P2_4
, I2C_0
, (int)&((pin_function_t
){&MXC_IOMAN
->i2cm0_req
, &MXC_IOMAN
->i2cm0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_A
| MXC_F_IOMAN_I2CM_CORE_IO
), (MXC_F_IOMAN_I2CM_MAPPING
| MXC_F_IOMAN_I2CM_CORE_IO
)}) },
55 { P2_6
, I2C_1
, (int)&((pin_function_t
){&MXC_IOMAN
->i2cm1_req
, &MXC_IOMAN
->i2cm1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_A
| MXC_F_IOMAN_I2CM_CORE_IO
), (MXC_F_IOMAN_I2CM_MAPPING
| MXC_F_IOMAN_I2CM_CORE_IO
)}) },
56 { P1_6
, I2C_0
, (int)&((pin_function_t
){&MXC_IOMAN
->i2cm0_req
, &MXC_IOMAN
->i2cm0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_B
| MXC_F_IOMAN_I2CM_CORE_IO
), (MXC_F_IOMAN_I2CM_MAPPING
| MXC_F_IOMAN_I2CM_CORE_IO
)}) },
57 { P2_2
, I2C_1
, (int)&((pin_function_t
){&MXC_IOMAN
->i2cm1_req
, &MXC_IOMAN
->i2cm1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_B
| MXC_F_IOMAN_I2CM_CORE_IO
), (MXC_F_IOMAN_I2CM_MAPPING
| MXC_F_IOMAN_I2CM_CORE_IO
)}) },
58 { P7_4
, I2C_0
, (int)&((pin_function_t
){&MXC_IOMAN
->i2cm0_req
, &MXC_IOMAN
->i2cm0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_C
| MXC_F_IOMAN_I2CM_CORE_IO
), (MXC_F_IOMAN_I2CM_MAPPING
| MXC_F_IOMAN_I2CM_CORE_IO
)}) },
59 { P7_6
, I2C_1
, (int)&((pin_function_t
){&MXC_IOMAN
->i2cm1_req
, &MXC_IOMAN
->i2cm1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_C
| MXC_F_IOMAN_I2CM_CORE_IO
), (MXC_F_IOMAN_I2CM_MAPPING
| MXC_F_IOMAN_I2CM_CORE_IO
)}) },
60 { P7_4
, I2C_0
, (int)&((pin_function_t
){&MXC_IOMAN
->i2cm0_req
, &MXC_IOMAN
->i2cm0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_C
| MXC_F_IOMAN_I2CM_CORE_IO
), (MXC_F_IOMAN_I2CM_MAPPING
| MXC_F_IOMAN_I2CM_CORE_IO
)}) },
61 { P7_6
, I2C_1
, (int)&((pin_function_t
){&MXC_IOMAN
->i2cm1_req
, &MXC_IOMAN
->i2cm1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_C
| MXC_F_IOMAN_I2CM_CORE_IO
), (MXC_F_IOMAN_I2CM_MAPPING
| MXC_F_IOMAN_I2CM_CORE_IO
)}) },
62 { P0_4
, I2C_0
, (int)&((pin_function_t
){&MXC_IOMAN
->i2cm0_req
, &MXC_IOMAN
->i2cm0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_D
| MXC_F_IOMAN_I2CM_CORE_IO
), (MXC_F_IOMAN_I2CM_MAPPING
| MXC_F_IOMAN_I2CM_CORE_IO
)}) },
63 { P0_6
, I2C_1
, (int)&((pin_function_t
){&MXC_IOMAN
->i2cm1_req
, &MXC_IOMAN
->i2cm1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_D
| MXC_F_IOMAN_I2CM_CORE_IO
), (MXC_F_IOMAN_I2CM_MAPPING
| MXC_F_IOMAN_I2CM_CORE_IO
)}) },
67 const PinMap PinMap_I2C_SCL
[] = {
68 { P2_5
, I2C_0
, (int)&((pin_function_t
){&MXC_IOMAN
->i2cm0_req
, &MXC_IOMAN
->i2cm0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_A
| MXC_F_IOMAN_I2CM_CORE_IO
), (MXC_F_IOMAN_I2CM_MAPPING
| MXC_F_IOMAN_I2CM_CORE_IO
)}) },
69 { P2_7
, I2C_1
, (int)&((pin_function_t
){&MXC_IOMAN
->i2cm1_req
, &MXC_IOMAN
->i2cm1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_A
| MXC_F_IOMAN_I2CM_CORE_IO
), (MXC_F_IOMAN_I2CM_MAPPING
| MXC_F_IOMAN_I2CM_CORE_IO
)}) },
70 { P1_7
, I2C_0
, (int)&((pin_function_t
){&MXC_IOMAN
->i2cm0_req
, &MXC_IOMAN
->i2cm0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_B
| MXC_F_IOMAN_I2CM_CORE_IO
), (MXC_F_IOMAN_I2CM_MAPPING
| MXC_F_IOMAN_I2CM_CORE_IO
)}) },
71 { P2_3
, I2C_1
, (int)&((pin_function_t
){&MXC_IOMAN
->i2cm1_req
, &MXC_IOMAN
->i2cm1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_B
| MXC_F_IOMAN_I2CM_CORE_IO
), (MXC_F_IOMAN_I2CM_MAPPING
| MXC_F_IOMAN_I2CM_CORE_IO
)}) },
72 { P7_5
, I2C_0
, (int)&((pin_function_t
){&MXC_IOMAN
->i2cm0_req
, &MXC_IOMAN
->i2cm0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_C
| MXC_F_IOMAN_I2CM_CORE_IO
), (MXC_F_IOMAN_I2CM_MAPPING
| MXC_F_IOMAN_I2CM_CORE_IO
)}) },
73 { P7_7
, I2C_1
, (int)&((pin_function_t
){&MXC_IOMAN
->i2cm1_req
, &MXC_IOMAN
->i2cm1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_C
| MXC_F_IOMAN_I2CM_CORE_IO
), (MXC_F_IOMAN_I2CM_MAPPING
| MXC_F_IOMAN_I2CM_CORE_IO
)}) },
74 { P7_5
, I2C_0
, (int)&((pin_function_t
){&MXC_IOMAN
->i2cm0_req
, &MXC_IOMAN
->i2cm0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_C
| MXC_F_IOMAN_I2CM_CORE_IO
), (MXC_F_IOMAN_I2CM_MAPPING
| MXC_F_IOMAN_I2CM_CORE_IO
)}) },
75 { P7_7
, I2C_1
, (int)&((pin_function_t
){&MXC_IOMAN
->i2cm1_req
, &MXC_IOMAN
->i2cm1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_C
| MXC_F_IOMAN_I2CM_CORE_IO
), (MXC_F_IOMAN_I2CM_MAPPING
| MXC_F_IOMAN_I2CM_CORE_IO
)}) },
76 { P0_5
, I2C_0
, (int)&((pin_function_t
){&MXC_IOMAN
->i2cm0_req
, &MXC_IOMAN
->i2cm0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_D
| MXC_F_IOMAN_I2CM_CORE_IO
), (MXC_F_IOMAN_I2CM_MAPPING
| MXC_F_IOMAN_I2CM_CORE_IO
)}) },
77 { P0_7
, I2C_1
, (int)&((pin_function_t
){&MXC_IOMAN
->i2cm1_req
, &MXC_IOMAN
->i2cm1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_D
| MXC_F_IOMAN_I2CM_CORE_IO
), (MXC_F_IOMAN_I2CM_MAPPING
| MXC_F_IOMAN_I2CM_CORE_IO
)}) },
81 /************UART***************/
82 const PinMap PinMap_UART_TX
[] = {
83 { P1_1
, UART_0
, (int)&((pin_function_t
){&MXC_IOMAN
->uart0_req
, &MXC_IOMAN
->uart0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_A
| MXC_F_IOMAN_UART_CORE_IO
), (MXC_F_IOMAN_UART_MAPPING
| MXC_F_IOMAN_UART_CORE_IO
)}) },
84 { P1_3
, UART_1
, (int)&((pin_function_t
){&MXC_IOMAN
->uart1_req
, &MXC_IOMAN
->uart1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_A
| MXC_F_IOMAN_UART_CORE_IO
), (MXC_F_IOMAN_UART_MAPPING
| MXC_F_IOMAN_UART_CORE_IO
)}) },
85 { P2_1
, UART_0
, (int)&((pin_function_t
){&MXC_IOMAN
->uart0_req
, &MXC_IOMAN
->uart0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_B
| MXC_F_IOMAN_UART_CORE_IO
), (MXC_F_IOMAN_UART_MAPPING
| MXC_F_IOMAN_UART_CORE_IO
)}) },
86 { P2_5
, UART_1
, (int)&((pin_function_t
){&MXC_IOMAN
->uart1_req
, &MXC_IOMAN
->uart1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_B
| MXC_F_IOMAN_UART_CORE_IO
), (MXC_F_IOMAN_UART_MAPPING
| MXC_F_IOMAN_UART_CORE_IO
)}) },
87 { P7_1
, UART_0
, (int)&((pin_function_t
){&MXC_IOMAN
->uart0_req
, &MXC_IOMAN
->uart0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_C
| MXC_F_IOMAN_UART_CORE_IO
), (MXC_F_IOMAN_UART_MAPPING
| MXC_F_IOMAN_UART_CORE_IO
)}) },
88 { P7_3
, UART_1
, (int)&((pin_function_t
){&MXC_IOMAN
->uart1_req
, &MXC_IOMAN
->uart1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_C
| MXC_F_IOMAN_UART_CORE_IO
), (MXC_F_IOMAN_UART_MAPPING
| MXC_F_IOMAN_UART_CORE_IO
)}) },
89 { P0_1
, UART_0
, (int)&((pin_function_t
){&MXC_IOMAN
->uart0_req
, &MXC_IOMAN
->uart0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_D
| MXC_F_IOMAN_UART_CORE_IO
), (MXC_F_IOMAN_UART_MAPPING
| MXC_F_IOMAN_UART_CORE_IO
)}) },
90 { P1_7
, UART_1
, (int)&((pin_function_t
){&MXC_IOMAN
->uart1_req
, &MXC_IOMAN
->uart1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_D
| MXC_F_IOMAN_UART_CORE_IO
), (MXC_F_IOMAN_UART_MAPPING
| MXC_F_IOMAN_UART_CORE_IO
)}) },
94 const PinMap PinMap_UART_RX
[] = {
95 { P1_0
, UART_0
, (int)&((pin_function_t
){&MXC_IOMAN
->uart0_req
, &MXC_IOMAN
->uart0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_A
| MXC_F_IOMAN_UART_CORE_IO
), (MXC_F_IOMAN_UART_MAPPING
| MXC_F_IOMAN_UART_CORE_IO
)}) },
96 { P1_2
, UART_1
, (int)&((pin_function_t
){&MXC_IOMAN
->uart1_req
, &MXC_IOMAN
->uart1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_A
| MXC_F_IOMAN_UART_CORE_IO
), (MXC_F_IOMAN_UART_MAPPING
| MXC_F_IOMAN_UART_CORE_IO
)}) },
97 { P2_0
, UART_0
, (int)&((pin_function_t
){&MXC_IOMAN
->uart0_req
, &MXC_IOMAN
->uart0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_B
| MXC_F_IOMAN_UART_CORE_IO
), (MXC_F_IOMAN_UART_MAPPING
| MXC_F_IOMAN_UART_CORE_IO
)}) },
98 { P2_4
, UART_1
, (int)&((pin_function_t
){&MXC_IOMAN
->uart1_req
, &MXC_IOMAN
->uart1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_B
| MXC_F_IOMAN_UART_CORE_IO
), (MXC_F_IOMAN_UART_MAPPING
| MXC_F_IOMAN_UART_CORE_IO
)}) },
99 { P7_0
, UART_0
, (int)&((pin_function_t
){&MXC_IOMAN
->uart0_req
, &MXC_IOMAN
->uart0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_C
| MXC_F_IOMAN_UART_CORE_IO
), (MXC_F_IOMAN_UART_MAPPING
| MXC_F_IOMAN_UART_CORE_IO
)}) },
100 { P7_2
, UART_1
, (int)&((pin_function_t
){&MXC_IOMAN
->uart1_req
, &MXC_IOMAN
->uart1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_C
| MXC_F_IOMAN_UART_CORE_IO
), (MXC_F_IOMAN_UART_MAPPING
| MXC_F_IOMAN_UART_CORE_IO
)}) },
101 { P0_0
, UART_0
, (int)&((pin_function_t
){&MXC_IOMAN
->uart0_req
, &MXC_IOMAN
->uart0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_D
| MXC_F_IOMAN_UART_CORE_IO
), (MXC_F_IOMAN_UART_MAPPING
| MXC_F_IOMAN_UART_CORE_IO
)}) },
102 { P1_6
, UART_1
, (int)&((pin_function_t
){&MXC_IOMAN
->uart1_req
, &MXC_IOMAN
->uart1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_D
| MXC_F_IOMAN_UART_CORE_IO
), (MXC_F_IOMAN_UART_MAPPING
| MXC_F_IOMAN_UART_CORE_IO
)}) },
106 const PinMap PinMap_UART_CTS
[] = {
107 { P1_2
, UART_0
, (int)&((pin_function_t
){&MXC_IOMAN
->uart0_req
, &MXC_IOMAN
->uart0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_A
| MXC_F_IOMAN_UART_CTS_IO
), (MXC_F_IOMAN_UART_MAPPING
| MXC_F_IOMAN_UART_CTS_IO
)}) },
108 { P2_6
, UART_1
, (int)&((pin_function_t
){&MXC_IOMAN
->uart1_req
, &MXC_IOMAN
->uart1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_A
| MXC_F_IOMAN_UART_CTS_IO
), (MXC_F_IOMAN_UART_MAPPING
| MXC_F_IOMAN_UART_CTS_IO
)}) },
109 { P1_4
, UART_0
, (int)&((pin_function_t
){&MXC_IOMAN
->uart0_req
, &MXC_IOMAN
->uart0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_B
| MXC_F_IOMAN_UART_CTS_IO
), (MXC_F_IOMAN_UART_MAPPING
| MXC_F_IOMAN_UART_CTS_IO
)}) },
110 { P1_6
, UART_1
, (int)&((pin_function_t
){&MXC_IOMAN
->uart1_req
, &MXC_IOMAN
->uart1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_B
| MXC_F_IOMAN_UART_CTS_IO
), (MXC_F_IOMAN_UART_MAPPING
| MXC_F_IOMAN_UART_CTS_IO
)}) },
111 { P7_2
, UART_0
, (int)&((pin_function_t
){&MXC_IOMAN
->uart0_req
, &MXC_IOMAN
->uart0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_C
| MXC_F_IOMAN_UART_CTS_IO
), (MXC_F_IOMAN_UART_MAPPING
| MXC_F_IOMAN_UART_CTS_IO
)}) },
112 { P7_6
, UART_1
, (int)&((pin_function_t
){&MXC_IOMAN
->uart1_req
, &MXC_IOMAN
->uart1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_C
| MXC_F_IOMAN_UART_CTS_IO
), (MXC_F_IOMAN_UART_MAPPING
| MXC_F_IOMAN_UART_CTS_IO
)}) },
113 { P0_2
, UART_0
, (int)&((pin_function_t
){&MXC_IOMAN
->uart0_req
, &MXC_IOMAN
->uart0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_D
| MXC_F_IOMAN_UART_CTS_IO
), (MXC_F_IOMAN_UART_MAPPING
| MXC_F_IOMAN_UART_CTS_IO
)}) },
117 const PinMap PinMap_UART_RTS
[] = {
118 { P1_3
, UART_0
, (int)&((pin_function_t
){&MXC_IOMAN
->uart0_req
, &MXC_IOMAN
->uart0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_A
| MXC_F_IOMAN_UART_RTS_IO
), (MXC_F_IOMAN_UART_MAPPING
| MXC_F_IOMAN_UART_RTS_IO
)}) },
119 { P2_7
, UART_1
, (int)&((pin_function_t
){&MXC_IOMAN
->uart1_req
, &MXC_IOMAN
->uart1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_A
| MXC_F_IOMAN_UART_RTS_IO
), (MXC_F_IOMAN_UART_MAPPING
| MXC_F_IOMAN_UART_RTS_IO
)}) },
120 { P1_5
, UART_0
, (int)&((pin_function_t
){&MXC_IOMAN
->uart0_req
, &MXC_IOMAN
->uart0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_B
| MXC_F_IOMAN_UART_RTS_IO
), (MXC_F_IOMAN_UART_MAPPING
| MXC_F_IOMAN_UART_RTS_IO
)}) },
121 { P1_7
, UART_1
, (int)&((pin_function_t
){&MXC_IOMAN
->uart1_req
, &MXC_IOMAN
->uart1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_B
| MXC_F_IOMAN_UART_RTS_IO
), (MXC_F_IOMAN_UART_MAPPING
| MXC_F_IOMAN_UART_RTS_IO
)}) },
122 { P7_3
, UART_0
, (int)&((pin_function_t
){&MXC_IOMAN
->uart0_req
, &MXC_IOMAN
->uart0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_C
| MXC_F_IOMAN_UART_RTS_IO
), (MXC_F_IOMAN_UART_MAPPING
| MXC_F_IOMAN_UART_RTS_IO
)}) },
123 { P7_7
, UART_1
, (int)&((pin_function_t
){&MXC_IOMAN
->uart1_req
, &MXC_IOMAN
->uart1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_C
| MXC_F_IOMAN_UART_RTS_IO
), (MXC_F_IOMAN_UART_MAPPING
| MXC_F_IOMAN_UART_RTS_IO
)}) },
124 { P0_3
, UART_0
, (int)&((pin_function_t
){&MXC_IOMAN
->uart0_req
, &MXC_IOMAN
->uart0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_D
| MXC_F_IOMAN_UART_RTS_IO
), (MXC_F_IOMAN_UART_MAPPING
| MXC_F_IOMAN_UART_RTS_IO
)}) },
128 /************SPI***************/
129 const PinMap PinMap_SPI_SCLK
[] = {
130 { P0_0
, SPI_0
, (int)&((pin_function_t
){&MXC_IOMAN
->spi0_req
, &MXC_IOMAN
->spi0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_A
| MXC_F_IOMAN_SPI_CORE_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_CORE_IO
)}) },
131 { P0_4
, SPI_1
, (int)&((pin_function_t
){&MXC_IOMAN
->spi1_req
, &MXC_IOMAN
->spi1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_A
| MXC_F_IOMAN_SPI_CORE_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_CORE_IO
)}) },
132 { P2_0
, SPI_2
, (int)&((pin_function_t
){&MXC_IOMAN
->spi2_req
, &MXC_IOMAN
->spi2_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_A
| MXC_F_IOMAN_SPI_CORE_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_CORE_IO
)}) },
133 { P1_0
, SPI_0
, (int)&((pin_function_t
){&MXC_IOMAN
->spi0_req
, &MXC_IOMAN
->spi0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_B
| MXC_F_IOMAN_SPI_CORE_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_CORE_IO
)}) },
134 { P2_4
, SPI_1
, (int)&((pin_function_t
){&MXC_IOMAN
->spi1_req
, &MXC_IOMAN
->spi1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_B
| MXC_F_IOMAN_SPI_CORE_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_CORE_IO
)}) },
135 { P2_0
, SPI_2
, (int)&((pin_function_t
){&MXC_IOMAN
->spi2_req
, &MXC_IOMAN
->spi2_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_B
| MXC_F_IOMAN_SPI_CORE_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_CORE_IO
)}) },
136 { P6_0
, SPI_0
, (int)&((pin_function_t
){&MXC_IOMAN
->spi0_req
, &MXC_IOMAN
->spi0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_C
| MXC_F_IOMAN_SPI_CORE_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_CORE_IO
)}) },
137 { P6_4
, SPI_1
, (int)&((pin_function_t
){&MXC_IOMAN
->spi1_req
, &MXC_IOMAN
->spi1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_C
| MXC_F_IOMAN_SPI_CORE_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_CORE_IO
)}) },
141 const PinMap PinMap_SPI_MOSI
[] = {
142 { P0_1
, SPI_0
, (int)&((pin_function_t
){&MXC_IOMAN
->spi0_req
, &MXC_IOMAN
->spi0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_A
| MXC_F_IOMAN_SPI_CORE_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_CORE_IO
)}) },
143 { P0_5
, SPI_1
, (int)&((pin_function_t
){&MXC_IOMAN
->spi1_req
, &MXC_IOMAN
->spi1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_A
| MXC_F_IOMAN_SPI_CORE_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_CORE_IO
)}) },
144 { P2_1
, SPI_2
, (int)&((pin_function_t
){&MXC_IOMAN
->spi2_req
, &MXC_IOMAN
->spi2_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_A
| MXC_F_IOMAN_SPI_CORE_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_CORE_IO
)}) },
145 { P1_1
, SPI_0
, (int)&((pin_function_t
){&MXC_IOMAN
->spi0_req
, &MXC_IOMAN
->spi0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_B
| MXC_F_IOMAN_SPI_CORE_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_CORE_IO
)}) },
146 { P2_5
, SPI_1
, (int)&((pin_function_t
){&MXC_IOMAN
->spi1_req
, &MXC_IOMAN
->spi1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_B
| MXC_F_IOMAN_SPI_CORE_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_CORE_IO
)}) },
147 { P2_1
, SPI_2
, (int)&((pin_function_t
){&MXC_IOMAN
->spi2_req
, &MXC_IOMAN
->spi2_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_B
| MXC_F_IOMAN_SPI_CORE_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_CORE_IO
)}) },
148 { P6_1
, SPI_0
, (int)&((pin_function_t
){&MXC_IOMAN
->spi0_req
, &MXC_IOMAN
->spi0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_C
| MXC_F_IOMAN_SPI_CORE_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_CORE_IO
)}) },
149 { P6_5
, SPI_1
, (int)&((pin_function_t
){&MXC_IOMAN
->spi1_req
, &MXC_IOMAN
->spi1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_C
| MXC_F_IOMAN_SPI_CORE_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_CORE_IO
)}) },
153 const PinMap PinMap_SPI_MISO
[] = {
154 { P0_2
, SPI_0
, (int)&((pin_function_t
){&MXC_IOMAN
->spi0_req
, &MXC_IOMAN
->spi0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_A
| MXC_F_IOMAN_SPI_CORE_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_CORE_IO
)}) },
155 { P0_6
, SPI_1
, (int)&((pin_function_t
){&MXC_IOMAN
->spi1_req
, &MXC_IOMAN
->spi1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_A
| MXC_F_IOMAN_SPI_CORE_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_CORE_IO
)}) },
156 { P2_2
, SPI_2
, (int)&((pin_function_t
){&MXC_IOMAN
->spi2_req
, &MXC_IOMAN
->spi2_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_A
| MXC_F_IOMAN_SPI_CORE_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_CORE_IO
)}) },
157 { P1_2
, SPI_0
, (int)&((pin_function_t
){&MXC_IOMAN
->spi0_req
, &MXC_IOMAN
->spi0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_B
| MXC_F_IOMAN_SPI_CORE_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_CORE_IO
)}) },
158 { P2_6
, SPI_1
, (int)&((pin_function_t
){&MXC_IOMAN
->spi1_req
, &MXC_IOMAN
->spi1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_B
| MXC_F_IOMAN_SPI_CORE_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_CORE_IO
)}) },
159 { P2_2
, SPI_2
, (int)&((pin_function_t
){&MXC_IOMAN
->spi2_req
, &MXC_IOMAN
->spi2_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_B
| MXC_F_IOMAN_SPI_CORE_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_CORE_IO
)}) },
160 { P6_2
, SPI_0
, (int)&((pin_function_t
){&MXC_IOMAN
->spi0_req
, &MXC_IOMAN
->spi0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_C
| MXC_F_IOMAN_SPI_CORE_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_CORE_IO
)}) },
161 { P6_6
, SPI_1
, (int)&((pin_function_t
){&MXC_IOMAN
->spi1_req
, &MXC_IOMAN
->spi1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_C
| MXC_F_IOMAN_SPI_CORE_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_CORE_IO
)}) },
165 const PinMap PinMap_SPI_SSEL
[] = {
166 #if (defined(EM9301_CSN) && (EM9301_CSN == P0_3))
167 { P0_3
, SPI_0
, (int)&((pin_function_t
){&MXC_IOMAN
->spi0_req
, &MXC_IOMAN
->spi0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_A
| MXC_F_IOMAN_SPI_SS0_IO
| MXC_F_IOMAN_SPI_SR0_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_SS0_IO
| MXC_F_IOMAN_SPI_SR0_IO
)}) },
169 { P0_3
, SPI_0
, (int)&((pin_function_t
){&MXC_IOMAN
->spi0_req
, &MXC_IOMAN
->spi0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_A
| MXC_F_IOMAN_SPI_SS0_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_SS0_IO
)}) },
171 { P0_7
, SPI_1
, (int)&((pin_function_t
){&MXC_IOMAN
->spi1_req
, &MXC_IOMAN
->spi1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_A
| MXC_F_IOMAN_SPI_SS0_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_SS0_IO
)}) },
172 { P2_3
, SPI_2
, (int)&((pin_function_t
){&MXC_IOMAN
->spi2_req
, &MXC_IOMAN
->spi2_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_A
| MXC_F_IOMAN_SPI_SS0_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_SS0_IO
)}) },
173 { P1_3
, SPI_0
, (int)&((pin_function_t
){&MXC_IOMAN
->spi0_req
, &MXC_IOMAN
->spi0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_B
| MXC_F_IOMAN_SPI_SS0_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_SS0_IO
)}) },
174 { P2_7
, SPI_1
, (int)&((pin_function_t
){&MXC_IOMAN
->spi1_req
, &MXC_IOMAN
->spi1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_B
| MXC_F_IOMAN_SPI_SS0_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_SS0_IO
)}) },
175 #if (defined(EM9301_CSN) && (EM9301_CSN == P2_3))
176 { P2_3
, SPI_2
, (int)&((pin_function_t
){&MXC_IOMAN
->spi2_req
, &MXC_IOMAN
->spi2_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_A
| MXC_F_IOMAN_SPI_SS0_IO
| MXC_F_IOMAN_SPI_SR0_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_SS0_IO
| MXC_F_IOMAN_SPI_SR0_IO
)}) },
178 { P2_3
, SPI_2
, (int)&((pin_function_t
){&MXC_IOMAN
->spi2_req
, &MXC_IOMAN
->spi2_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_B
| MXC_F_IOMAN_SPI_SS0_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_SS0_IO
)}) },
180 { P6_3
, SPI_0
, (int)&((pin_function_t
){&MXC_IOMAN
->spi0_req
, &MXC_IOMAN
->spi0_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_C
| MXC_F_IOMAN_SPI_SS0_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_SS0_IO
)}) },
181 { P6_7
, SPI_1
, (int)&((pin_function_t
){&MXC_IOMAN
->spi1_req
, &MXC_IOMAN
->spi1_ack
, ((uint32_t)MXC_E_IOMAN_MAPPING_C
| MXC_F_IOMAN_SPI_SS0_IO
), (MXC_F_IOMAN_SPI_MAPPING
| MXC_F_IOMAN_SPI_SS0_IO
)}) },
185 /************PWM***************/
186 const PinMap PinMap_PWM
[] = {
187 {P0_0
, PWM_0
, 1}, {P0_0
, PWM_0
, 2}, {P0_0
, PWM_4
, 3},
188 {P0_1
, PWM_0
, 3}, {P0_1
, PWM_1
, 1}, {P0_1
, PWM_4
, 2},
189 {P0_2
, PWM_1
, 2}, {P0_2
, PWM_2
, 1}, {P0_2
, PWM_5
, 3},
190 {P0_3
, PWM_1
, 3}, {P0_3
, PWM_3
, 1}, {P0_3
, PWM_5
, 2},
191 {P0_4
, PWM_2
, 2}, {P0_4
, PWM_4
, 1}, {P0_4
, PWM_6
, 3},
192 {P0_5
, PWM_2
, 3}, {P0_5
, PWM_5
, 1}, {P0_5
, PWM_6
, 2},
193 {P0_6
, PWM_3
, 2}, {P0_6
, PWM_6
, 1}, {P0_6
, PWM_7
, 3},
194 {P0_7
, PWM_3
, 3}, {P0_7
, PWM_7
, 1}, {P0_7
, PWM_7
, 2},
196 {P1_0
, PWM_0
, 1}, {P1_0
, PWM_0
, 2}, {P1_0
, PWM_4
, 3},
197 {P1_1
, PWM_0
, 3}, {P1_1
, PWM_1
, 1}, {P1_1
, PWM_4
, 2},
198 {P1_2
, PWM_1
, 2}, {P1_2
, PWM_2
, 1}, {P1_2
, PWM_5
, 3},
199 {P1_3
, PWM_1
, 3}, {P1_3
, PWM_3
, 1}, {P1_3
, PWM_5
, 2},
200 {P1_4
, PWM_2
, 2}, {P1_4
, PWM_4
, 1}, {P1_4
, PWM_6
, 3},
201 {P1_5
, PWM_2
, 3}, {P1_5
, PWM_5
, 1}, {P1_5
, PWM_6
, 2},
202 {P1_6
, PWM_3
, 2}, {P1_6
, PWM_6
, 1}, {P1_6
, PWM_7
, 3},
203 {P1_7
, PWM_3
, 3}, {P1_7
, PWM_7
, 1}, {P1_7
, PWM_7
, 2},
205 {P2_0
, PWM_0
, 1}, {P2_0
, PWM_0
, 2}, {P2_0
, PWM_4
, 3},
206 {P2_1
, PWM_0
, 3}, {P2_1
, PWM_1
, 1}, {P2_1
, PWM_4
, 2},
207 {P2_2
, PWM_1
, 2}, {P2_2
, PWM_2
, 1}, {P2_2
, PWM_5
, 3},
208 {P2_3
, PWM_1
, 3}, {P2_3
, PWM_3
, 1}, {P2_3
, PWM_5
, 2},
209 {P2_4
, PWM_2
, 2}, {P2_4
, PWM_4
, 1}, {P2_4
, PWM_6
, 3},
210 {P2_5
, PWM_2
, 3}, {P2_5
, PWM_5
, 1}, {P2_5
, PWM_6
, 2},
211 {P2_6
, PWM_3
, 2}, {P2_6
, PWM_6
, 1}, {P2_6
, PWM_7
, 3},
212 {P2_7
, PWM_3
, 3}, {P2_7
, PWM_7
, 1}, {P2_7
, PWM_7
, 2},
214 {P6_0
, PWM_0
, 1}, {P6_0
, PWM_0
, 2}, {P6_0
, PWM_4
, 3},
215 {P6_1
, PWM_0
, 3}, {P6_1
, PWM_1
, 1}, {P6_1
, PWM_4
, 2},
216 {P6_2
, PWM_1
, 2}, {P6_2
, PWM_2
, 1}, {P6_2
, PWM_5
, 3},
217 {P6_3
, PWM_1
, 3}, {P6_3
, PWM_3
, 1}, {P6_3
, PWM_5
, 2},
218 {P6_4
, PWM_2
, 2}, {P6_4
, PWM_4
, 1}, {P6_4
, PWM_6
, 3},
219 {P6_5
, PWM_2
, 3}, {P6_5
, PWM_5
, 1}, {P6_5
, PWM_6
, 2},
220 {P6_6
, PWM_3
, 2}, {P6_6
, PWM_6
, 1}, {P6_6
, PWM_7
, 3},
221 {P6_7
, PWM_3
, 3}, {P6_7
, PWM_7
, 1}, {P6_7
, PWM_7
, 2},
223 {P7_0
, PWM_0
, 1}, {P7_0
, PWM_0
, 2}, {P7_0
, PWM_4
, 3},
224 {P7_1
, PWM_0
, 3}, {P7_1
, PWM_1
, 1}, {P7_1
, PWM_4
, 2},
225 {P7_2
, PWM_1
, 2}, {P7_2
, PWM_2
, 1}, {P7_2
, PWM_5
, 3},
226 {P7_3
, PWM_1
, 3}, {P7_3
, PWM_3
, 1}, {P7_3
, PWM_5
, 2},
227 {P7_4
, PWM_2
, 2}, {P7_4
, PWM_4
, 1}, {P7_4
, PWM_6
, 3},
228 {P7_5
, PWM_2
, 3}, {P7_5
, PWM_5
, 1}, {P7_5
, PWM_6
, 2},
229 {P7_6
, PWM_3
, 2}, {P7_6
, PWM_6
, 1}, {P7_6
, PWM_7
, 3},
230 {P7_7
, PWM_3
, 3}, {P7_7
, PWM_7
, 1}, {P7_7
, PWM_7
, 2},
234 /************ADC***************/
235 const PinMap PinMap_ADC
[] = {
265 /************DAC***************/
266 const PinMap PinMap_DAC
[] = {