tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/gpio_irq_api.c

   1 /*******************************************************************************
   2  * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
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   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
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  11  * The above copyright notice and this permission notice shall be included
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  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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  23  * Products, Inc. shall not be used except as stated in the Maxim Integrated
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  26  * The mere transfer of this software does not imply any licenses
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  32  */
  33
  34 #include <stddef.h>
  35 #include "cmsis.h"
  36 #include "gpio_irq_api.h"
  37 #include "mbed_error.h"
  38
  39 #define NUM_PORTS           8
  40 #define NUM_PINS_PER_PORT   8
  41
  42 static uint32_t ids[NUM_PORTS][NUM_PINS_PER_PORT] = {{0}};
  43 static gpio_irq_handler irq_handler;
  44
  45 static void handle_irq(unsigned int port)
  46 {
  47     uint32_t intfl, in_val;
  48     uint32_t mask;
  49     unsigned int pin;
  50
  51     /* Read pin state */
  52     in_val = MXC_GPIO->in_val[port];
  53
  54     /* Read interrupts */
  55     intfl = MXC_GPIO->intfl[port] & MXC_GPIO->inten[port];
  56
  57     mask = 1;
  58
  59     for (pin = 0; pin < NUM_PINS_PER_PORT; pin++) {
  60         if (intfl & mask) {
  61             if (ids[port][pin]) {
  62                 if (in_val & mask) {
  63                     irq_handler(ids[port][pin], IRQ_RISE);
  64                 } else {
  65                     irq_handler(ids[port][pin], IRQ_FALL);
  66                 }
  67             }
  68             MXC_GPIO->intfl[port] = mask;    /* clear interrupt */
  69         }
  70         mask <<= 1;
  71     }
  72 }
  73
  74 void gpio_irq_0(void) { handle_irq(0); }
  75 void gpio_irq_1(void) { handle_irq(1); }
  76 void gpio_irq_2(void) { handle_irq(2); }
  77 void gpio_irq_3(void) { handle_irq(3); }
  78 void gpio_irq_4(void) { handle_irq(4); }
  79 void gpio_irq_5(void) { handle_irq(5); }
  80 void gpio_irq_6(void) { handle_irq(6); }
  81 void gpio_irq_7(void) { handle_irq(7); }
  82
  83 int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uint32_t id)
  84 {
  85     if (name == NC)
  86         return -1;
  87
  88     uint8_t port = PINNAME_TO_PORT(name);
  89     uint8_t pin = PINNAME_TO_PIN(name);
  90
  91     if ((port > NUM_PORTS) || (pin > NUM_PINS_PER_PORT)) {
  92         return 1;
  93     }
  94
  95     obj->port = port;
  96     obj->pin = pin;
  97
  98     irq_handler = handler;
  99
 100     ids[port][pin] = id;
 101
 102     /* register handlers */
 103     NVIC_SetVector(GPIO_P0_IRQn, (uint32_t)gpio_irq_0);
 104     NVIC_SetVector(GPIO_P1_IRQn, (uint32_t)gpio_irq_1);
 105     NVIC_SetVector(GPIO_P2_IRQn, (uint32_t)gpio_irq_2);
 106     NVIC_SetVector(GPIO_P3_IRQn, (uint32_t)gpio_irq_3);
 107     NVIC_SetVector(GPIO_P4_IRQn, (uint32_t)gpio_irq_4);
 108     NVIC_SetVector(GPIO_P5_IRQn, (uint32_t)gpio_irq_5);
 109     NVIC_SetVector(GPIO_P6_IRQn, (uint32_t)gpio_irq_6);
 110     NVIC_SetVector(GPIO_P7_IRQn, (uint32_t)gpio_irq_7);
 111
 112     /* disable the interrupt locally */
 113     MXC_GPIO->int_mode[port] &= ~(0xF << (pin*4));
 114
 115     /* clear a pending request */
 116     MXC_GPIO->intfl[port] = 1 << pin;
 117
 118     /* enable the requested interrupt */
 119     MXC_GPIO->inten[port] |= (1 << pin);
 120     NVIC_EnableIRQ((IRQn_Type)((uint32_t)GPIO_P0_IRQn + port));
 121
 122     return 0;
 123 }
 124
 125 void gpio_irq_free(gpio_irq_t *obj)
 126 {
 127     /* disable interrupt */
 128     MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin);
 129     MXC_GPIO->int_mode[obj->port] &= ~(0xF << (obj->pin*4));
 130
 131     ids[obj->port][obj->pin] = 0;
 132 }
 133
 134 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
 135 {
 136     uint32_t int_mode = MXC_GPIO->int_mode[obj->port];
 137     uint32_t curr_mode = (int_mode >> (obj->pin*4)) & 0x3;   /* only supporting edge interrupts */
 138
 139     uint32_t new_mode = curr_mode;
 140     if (event == IRQ_FALL) {
 141         if (enable) {
 142             new_mode |= 0x1;
 143         } else {
 144             new_mode &= ~0x1;
 145         }
 146     } else if (event == IRQ_RISE) {
 147         if (enable) {
 148             new_mode |= 0x2;
 149         } else {
 150             new_mode &= ~0x2;
 151         }
 152     }
 153
 154     int_mode &= ~(0xF << (obj->pin*4));
 155     int_mode |= (new_mode << (obj->pin*4));
 156     MXC_GPIO->int_mode[obj->port] = int_mode;
 157 }
 158
 159 void gpio_irq_enable(gpio_irq_t *obj)
 160 {
 161     MXC_GPIO->inten[obj->port] |= (1 << obj->pin);
 162 }
 163
 164 void gpio_irq_disable(gpio_irq_t *obj)
 165 {
 166     MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin);
 167 }