tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/PeripheralPins.c

   1 /*******************************************************************************
   2  * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  16  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  17  * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
  18  * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Except as contained in this notice, the name of Maxim Integrated
  23  * Products, Inc. shall not be used except as stated in the Maxim Integrated
  24  * Products, Inc. Branding Policy.
  25  *
  26  * The mere transfer of this software does not imply any licenses
  27  * of trade secrets, proprietary technology, copyrights, patents,
  28  * trademarks, maskwork rights, or any other form of intellectual
  29  * property whatsoever. Maxim Integrated Products, Inc. retains all
  30  * ownership rights.
  31  *******************************************************************************
  32  */
  33
  34 #include "device.h"
  35 #include "PeripheralPins.h"
  36 #include "ioman_regs.h"
  37
  38 /*
  39  * To select a peripheral function on Maxim microcontrollers, multiple
  40  * configurations must be made. The mbed PinMap structure only includes one
  41  * data member to hold this information. To extend the configuration storage,
  42  * the "function" data member is used as a pointer to a pin_function_t
  43  * structure. This structure is defined in objects.h. The definitions below
  44  * include the creation of the pin_function_t structures and the assignment of
  45  * the pointers to the "function" data members.
  46  */
  47
  48 #ifdef TOOLCHAIN_ARM_STD
  49 #pragma diag_suppress 1296
  50 #endif
  51
  52 /************I2C***************/
  53 const PinMap PinMap_I2C_SDA[] = {
  54     { P0_4,  I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
  55     { P0_6,  I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_H | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
  56     { NC,    NC,    0 }
  57 };
  58
  59 const PinMap PinMap_I2C_SCL[] = {
  60     { P0_5,  I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
  61     { P0_7,  I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_H | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
  62     { NC,    NC,    0 }
  63 };
  64
  65 /************UART***************/
  66 const PinMap PinMap_UART_TX[] = {
  67     { P1_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
  68     { P1_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
  69     { P2_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
  70     { P2_5, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
  71     { P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
  72     { P1_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
  73     { NC,   NC,     0 }
  74 };
  75
  76 const PinMap PinMap_UART_RX[] = {
  77     { P1_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
  78     { P1_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
  79     { P2_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
  80     { P2_4, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
  81     { P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
  82     { P1_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
  83     { NC,   NC,     0 }
  84 };
  85
  86 const PinMap PinMap_UART_CTS[] = {
  87     { P1_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
  88     { P1_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
  89     { P2_4, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
  90     { P2_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
  91     { P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
  92     { NC,   NC,     0 }
  93 };
  94
  95 const PinMap PinMap_UART_RTS[] = {
  96     { P1_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
  97     { P1_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
  98     { P2_5, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
  99     { P2_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
 100     { P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
 101     { NC,   NC,     0 }
 102 };
 103
 104 /************SPI***************/
 105 const PinMap PinMap_SPI_SCLK[] = {
 106     { P0_0, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
 107     { P2_0, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
 108     { NC,   NC,    0}
 109 };
 110
 111 const PinMap PinMap_SPI_MOSI[] = {
 112     { P0_1, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
 113     { P2_1, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
 114     { NC,   NC,    0}
 115 };
 116
 117 const PinMap PinMap_SPI_MISO[] = {
 118     { P0_2, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
 119     { P2_2, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
 120     { NC,   NC,    0}
 121 };
 122
 123 const PinMap PinMap_SPI_SSEL[] = {
 124     { P0_3, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) },
 125     { P2_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_SS0_IO | MXC_F_IOMAN_SPI_SR0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO | MXC_F_IOMAN_SPI_SR0_IO)}) },
 126     { NC,   NC,    0}
 127 };
 128
 129 /************PWM***************/
 130 const PinMap PinMap_PWM[] = {
 131     {P0_0, PWM_0, 1}, {P0_0, PWM_0, 2}, {P0_0, PWM_4, 3},
 132     {P0_1, PWM_0, 3}, {P0_1, PWM_1, 1}, {P0_1, PWM_4, 2},
 133     {P0_2, PWM_1, 2}, {P0_2, PWM_2, 1}, {P0_2, PWM_5, 3},
 134     {P0_3, PWM_1, 3}, {P0_3, PWM_3, 1}, {P0_3, PWM_5, 2},
 135     {P0_4, PWM_2, 2}, {P0_4, PWM_4, 1}, {P0_4, PWM_6, 3},
 136     {P0_5, PWM_2, 3}, {P0_5, PWM_5, 1}, {P0_5, PWM_6, 2},
 137     {P0_6, PWM_3, 2}, {P0_6, PWM_6, 1}, {P0_6, PWM_7, 3},
 138     {P0_7, PWM_3, 3}, {P0_7, PWM_7, 1}, {P0_7, PWM_7, 2},
 139
 140     {P1_0, PWM_0, 1}, {P1_0, PWM_0, 2}, {P1_0, PWM_4, 3},
 141     {P1_1, PWM_0, 3}, {P1_1, PWM_1, 1}, {P1_1, PWM_4, 2},
 142     {P1_2, PWM_1, 2}, {P1_2, PWM_2, 1}, {P1_2, PWM_5, 3},
 143     {P1_3, PWM_1, 3}, {P1_3, PWM_3, 1}, {P1_3, PWM_5, 2},
 144     {P1_4, PWM_2, 2}, {P1_4, PWM_4, 1}, {P1_4, PWM_6, 3},
 145     {P1_5, PWM_2, 3}, {P1_5, PWM_5, 1}, {P1_5, PWM_6, 2},
 146     {P1_6, PWM_3, 2}, {P1_6, PWM_6, 1}, {P1_6, PWM_7, 3},
 147     {P1_7, PWM_3, 3}, {P1_7, PWM_7, 1}, {P1_7, PWM_7, 2},
 148
 149     {P2_0, PWM_0, 1}, {P2_0, PWM_0, 2}, {P2_0, PWM_4, 3},
 150     {P2_1, PWM_0, 3}, {P2_1, PWM_1, 1}, {P2_1, PWM_4, 2},
 151     {P2_2, PWM_1, 2}, {P2_2, PWM_2, 1}, {P2_2, PWM_5, 3},
 152     {P2_3, PWM_1, 3}, {P2_3, PWM_3, 1}, {P2_3, PWM_5, 2},
 153     {P2_4, PWM_2, 2}, {P2_4, PWM_4, 1}, {P2_4, PWM_6, 3},
 154     {P2_5, PWM_2, 3}, {P2_5, PWM_5, 1}, {P2_5, PWM_6, 2},
 155     {P2_6, PWM_3, 2}, {P2_6, PWM_6, 1}, {P2_6, PWM_7, 3},
 156     {P2_7, PWM_3, 3}, {P2_7, PWM_7, 1}, {P2_7, PWM_7, 2},
 157     {NC,   NC,    0}
 158 };
 159
 160 /************ADC***************/
 161 const PinMap PinMap_ADC[] = {
 162     {AIN_0P, ADC, 0},
 163     {AIN_1P, ADC, 0},
 164     {AIN_2P, ADC, 0},
 165     {AIN_3P, ADC, 0},
 166     {AIN_4P, ADC, 0},
 167     {AIN_5P, ADC, 0},
 168     {AIN_0N, ADC, 0},
 169     {AIN_1N, ADC, 0},
 170     {AIN_2N, ADC, 0},
 171     {AIN_3N, ADC, 0},
 172     {AIN_4N, ADC, 0},
 173     {AIN_5N, ADC, 0},
 174     {AIN_0D, ADC, 1},
 175     {AIN_1D, ADC, 1},
 176     {AIN_2D, ADC, 1},
 177     {AIN_3D, ADC, 1},
 178     {AIN_4D, ADC, 1},
 179     {AIN_5D, ADC, 1},
 180     {NC,     NC,  0}
 181 };
 182
 183 /************DAC***************/
 184 const PinMap PinMap_DAC[] = {
 185     {AOUT_AO, DAC0, 0},
 186     {AOUT_BO, DAC1, 0},
 187     {AOUT_CO, DAC2, 0},
 188     {AOUT_DO, DAC3, 0},
 189     {NC,      NC,   0}
 190 };