1 /*******************************************************************************
2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
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31 *******************************************************************************
34 #include "sleep_api.h"
35 #include "us_ticker_api.h"
37 #include "pwrman_regs.h"
38 #include "pwrseq_regs.h"
39 #include "ioman_regs.h"
42 #define MIN_DEEP_SLEEP_US 500
44 uint64_t rtc_read_us(void);
45 void rtc_set_wakeup(uint64_t wakeupUs
);
46 void us_ticker_deinit(void);
47 void us_ticker_set(timestamp_t timestamp
);
49 static mxc_uart_regs_t
*stdio_uart
= (mxc_uart_regs_t
*)STDIO_UART
;
54 // Normal sleep mode for ARM core
61 // Work-around for issue of clearing power sequencer I/O flag
62 static void clearAllGPIOWUD(void)
64 uint32_t wud_req0
= MXC_IOMAN
->wud_req0
;
65 uint32_t wud_req1
= MXC_IOMAN
->wud_req1
;
67 // I/O must be a wakeup detect to clear
68 MXC_IOMAN
->wud_req0
= 0xffffffff;
69 MXC_IOMAN
->wud_req1
= 0xffffffff;
72 MXC_PWRMAN
->wud_ctrl
= (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET
<< MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS
) | MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL
;
73 MXC_PWRMAN
->wud_pulse0
= 1;
75 // Restore WUD requests
76 MXC_IOMAN
->wud_req0
= wud_req0
;
77 MXC_IOMAN
->wud_req1
= wud_req1
;
80 // Low-power stop mode
83 uint64_t sleepStartRtcUs
;
84 uint32_t sleepStartTickerUs
;
85 int32_t sleepDurationUs
;
86 uint64_t sleepEndRtcUs
;
91 // Wait for all STDIO characters to be sent. The UART clock will stop.
92 while (stdio_uart
->status
& MXC_F_UART_STATUS_TX_BUSY
);
94 // Record the current times
95 sleepStartRtcUs
= rtc_read_us();
96 sleepStartTickerUs
= us_ticker_read();
98 // Get the next mbed timer expiration
99 timestamp_t next_event
= 0;
100 us_ticker_get_next_timestamp(&next_event
);
101 sleepDurationUs
= next_event
- sleepStartTickerUs
;
103 if (sleepDurationUs
< MIN_DEEP_SLEEP_US
) {
104 /* The next wakeup is too soon. */
109 // Disable the us_ticker. It won't be clocked in DeepSleep
112 // Prepare to wakeup from the RTC
113 rtc_set_wakeup(sleepStartRtcUs
+ sleepDurationUs
);
116 uint32_t reg0
= MXC_PWRSEQ
->reg0
;
117 reg0
&= ~MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP
; // disable VDD3 SVM during sleep mode
118 reg0
&= ~MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP
; // disable VREG18 SVM during sleep mode
119 if (reg0
& MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN
) { // if real-time clock enabled during run
120 reg0
|= MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP
; // enable real-time clock during sleep mode
122 reg0
&= ~MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP
; // disable real-time clock during sleep mode
124 reg0
|= MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP
; // enable CHZY regulator during sleep mode
125 reg0
|= MXC_F_PWRSEQ_REG0_PWR_LP1
; // go into LP1
126 reg0
&= ~MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT
; // clear first boot flag
127 MXC_PWRSEQ
->reg0
= reg0
;
129 MXC_PWRSEQ
->reg3
= (MXC_PWRSEQ
->reg3
& ~MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK
) | (3 << MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS
);
131 // Deep sleep for ARM core
132 SCB
->SCR
= SCB_SCR_SLEEPDEEP_Msk
;
134 // clear latches for wakeup detect
135 MXC_PWRSEQ
->flags
= MXC_PWRSEQ
->flags
;
136 if (MXC_PWRSEQ
->flags
& MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP
) {
137 // attempt work-around for I/O flag clearing issue
139 MXC_PWRSEQ
->flags
= MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP
;
142 // Wait for pending RTC transaction
143 while (MXC_RTCTMR
->ctrl
& MXC_F_RTC_CTRL_PENDING
);
145 // Ensure that the event register is clear
146 __SEV(); // set event
147 __WFE(); // clear event
153 // The RTC timer does not update until the next tick
154 uint64_t tempUs
= rtc_read_us();
156 sleepEndRtcUs
= rtc_read_us();
157 } while(sleepEndRtcUs
== tempUs
);
159 // Get the elapsed time from the RTC. Wakeup could have been from some other event.
160 elapsedUs
= sleepEndRtcUs
- sleepStartRtcUs
;
162 // Update the us_ticker. It was not clocked during DeepSleep
164 us_ticker_set(sleepStartTickerUs
+ elapsedUs
);
165 us_ticker_get_next_timestamp(&next_event
);
166 us_ticker_set_interrupt(next_event
);