tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC11U6X/gpio_irq_api.c

   1 /* mbed Microcontroller Library
   2  * Copyright (c) 2006-2013 ARM Limited
   3  *
   4  * Licensed under the Apache License, Version 2.0 (the "License");
   5  * you may not use this file except in compliance with the License.
   6  * You may obtain a copy of the License at
   7  *
   8  *     http://www.apache.org/licenses/LICENSE-2.0
   9  *
  10  * Unless required by applicable law or agreed to in writing, software
  11  * distributed under the License is distributed on an "AS IS" BASIS,
  12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13  * See the License for the specific language governing permissions and
  14  * limitations under the License.
  15  */
  16 #include <stddef.h>
  17
  18 #include "cmsis.h"
  19 #include "gpio_irq_api.h"
  20 #include "mbed_error.h"
  21
  22 #if DEVICE_INTERRUPTIN
  23
  24 #define CHANNEL_NUM 8
  25 #define LPC_GPIO_X LPC_PINT
  26 #define PININT_IRQ PIN_INT0_IRQn
  27
  28 static uint32_t channel_ids[CHANNEL_NUM] = {0};
  29 static gpio_irq_handler irq_handler;
  30
  31 static inline void handle_interrupt_in(uint32_t channel) {
  32     uint32_t ch_bit = (1 << channel);
  33     // Return immediately if:
  34     //   * The interrupt was already served
  35     //   * There is no user handler
  36     //   * It is a level interrupt, not an edge interrupt
  37     if ( ((LPC_GPIO_X->IST & ch_bit) == 0) ||
  38          (channel_ids[channel] == 0      ) ||
  39          (LPC_GPIO_X->ISEL & ch_bit      ) ) return;
  40
  41     if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) {
  42         irq_handler(channel_ids[channel], IRQ_RISE);
  43         LPC_GPIO_X->RISE = ch_bit;
  44     }
  45     if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) {
  46         irq_handler(channel_ids[channel], IRQ_FALL);
  47         LPC_GPIO_X->FALL = ch_bit;
  48     }
  49     LPC_GPIO_X->IST = ch_bit;
  50 }
  51
  52 void gpio_irq0(void) {handle_interrupt_in(0);}
  53 void gpio_irq1(void) {handle_interrupt_in(1);}
  54 void gpio_irq2(void) {handle_interrupt_in(2);}
  55 void gpio_irq3(void) {handle_interrupt_in(3);}
  56 void gpio_irq4(void) {handle_interrupt_in(4);}
  57 void gpio_irq5(void) {handle_interrupt_in(5);}
  58 void gpio_irq6(void) {handle_interrupt_in(6);}
  59 void gpio_irq7(void) {handle_interrupt_in(7);}
  60
  61 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
  62     // PINT only supprt PIO0_*, PIO1_* and from PIO2_0 to PIO0_7 interrupt
  63     if (pin >= P2_8) return -1;
  64
  65     irq_handler = handler;
  66
  67     int found_free_channel = 0;
  68     int i = 0;
  69     for (i=0; i<CHANNEL_NUM; i++) {
  70         if (channel_ids[i] == 0) {
  71             channel_ids[i] = id;
  72             obj->ch = i;
  73             found_free_channel = 1;
  74             break;
  75         }
  76     }
  77     if (!found_free_channel) return -1;
  78
  79     /* Enable AHB clock to the PIN, GPIO and IOCON domain. */
  80     LPC_SYSCON->SYSAHBCLKCTRL |= ((1 << 19) | (1 << 16) | (1 << 7));
  81
  82     LPC_SYSCON->PINTSEL[obj->ch] = ((((pin >> PORT_SHIFT) & 0x3) * 24) + ((pin >> PIN_SHIFT) & 0x1F));
  83
  84     // Interrupt Wake-Up Enable
  85     LPC_SYSCON->STARTERP0 |= (1 << obj->ch);
  86
  87     LPC_GPIO_PORT->DIR[(pin >> PORT_SHIFT) & 0x3]  &= ~(1 << ((pin >> PIN_SHIFT) & 0x1F));
  88
  89     void (*channels_irq)(void) = NULL;
  90     switch (obj->ch) {
  91         case 0: channels_irq = &gpio_irq0; break;
  92         case 1: channels_irq = &gpio_irq1; break;
  93         case 2: channels_irq = &gpio_irq2; break;
  94         case 3: channels_irq = &gpio_irq3; break;
  95         case 4: channels_irq = &gpio_irq4; break;
  96         case 5: channels_irq = &gpio_irq5; break;
  97         case 6: channels_irq = &gpio_irq6; break;
  98         case 7: channels_irq = &gpio_irq7; break;
  99     }
 100     NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
 101     NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
 102
 103     return 0;
 104 }
 105
 106 void gpio_irq_free(gpio_irq_t *obj) {
 107     channel_ids[obj->ch] = 0;
 108     LPC_SYSCON->STARTERP0 &= ~(1 << obj->ch);
 109 }
 110
 111 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
 112     unsigned int ch_bit = (1 << obj->ch);
 113
 114     // Clear interrupt
 115     if (!(LPC_GPIO_X->ISEL & ch_bit))
 116         LPC_GPIO_X->IST = ch_bit;
 117
 118     // Edge trigger
 119     LPC_GPIO_X->ISEL &= ~ch_bit;
 120     if (event == IRQ_RISE) {
 121         if (enable) {
 122             LPC_GPIO_X->IENR |= ch_bit;
 123         } else {
 124             LPC_GPIO_X->IENR &= ~ch_bit;
 125         }
 126     } else {
 127         if (enable) {
 128             LPC_GPIO_X->IENF |= ch_bit;
 129         } else {
 130             LPC_GPIO_X->IENF &= ~ch_bit;
 131         }
 132     }
 133 }
 134
 135 void gpio_irq_enable(gpio_irq_t *obj) {
 136     NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
 137 }
 138
 139 void gpio_irq_disable(gpio_irq_t *obj) {
 140     NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
 141 }
 142
 143 #endif