tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/analogin_api.c

   1 /* mbed Microcontroller Library
   2  * Copyright (c) 2006-2013 ARM Limited
   3  *
   4  * Licensed under the Apache License, Version 2.0 (the "License");
   5  * you may not use this file except in compliance with the License.
   6  * You may obtain a copy of the License at
   7  *
   8  *     http://www.apache.org/licenses/LICENSE-2.0
   9  *
  10  * Unless required by applicable law or agreed to in writing, software
  11  * distributed under the License is distributed on an "AS IS" BASIS,
  12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13  * See the License for the specific language governing permissions and
  14  * limitations under the License.
  15  */
  16 #include "mbed_assert.h"
  17 #include "analogin_api.h"
  18 #include "cmsis.h"
  19 #include "pinmap.h"
  20
  21 #define ANALOGIN_MEDIAN_FILTER      1
  22
  23 #define ADC_10BIT_RANGE             0x3FF
  24 #define ADC_12BIT_RANGE             0xFFF
  25
  26 #define ADC_RANGE    ADC_12BIT_RANGE
  27
  28 static const PinMap PinMap_ADC[] = {
  29     {P0_8 , ADC0_0, 0},
  30     {P0_7 , ADC0_1, 0},
  31     {P0_6 , ADC0_2, 0},
  32     {P0_5 , ADC0_3, 0},
  33     {P0_4 , ADC0_4, 0},
  34     {P0_3 , ADC0_5, 0},
  35     {P0_2 , ADC0_6, 0},
  36     {P0_1 , ADC0_7, 0},
  37     {P1_0 , ADC0_8, 0},
  38     {P0_31, ADC0_9, 0},
  39     {P0_0 , ADC0_10,0},
  40     {P0_30, ADC0_11,0},
  41     {P1_1 , ADC1_0, 0},
  42     {P0_9 , ADC1_1, 0},
  43     {P0_10, ADC1_2, 0},
  44     {P0_11, ADC1_3, 0},
  45     {P1_2 , ADC1_4, 0},
  46     {P1_3 , ADC1_5, 0},
  47     {P0_13, ADC1_6, 0},
  48     {P0_14, ADC1_7, 0},
  49     {P0_15, ADC1_8, 0},
  50     {P0_16, ADC1_9, 0},
  51     {P1_4 , ADC1_10,0},
  52     {P1_5 , ADC1_11,0},
  53 };
  54
  55 void analogin_init(analogin_t *obj, PinName pin) {
  56     obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
  57     MBED_ASSERT(obj->adc != (ADCName)NC);
  58
  59     uint32_t port = (pin >> 5);
  60     // enable clock for GPIOx
  61     LPC_SYSCON->SYSAHBCLKCTRL0 |= (1UL << (14 + port));
  62     // pin enable
  63     LPC_SWM->PINENABLE0 &= ~(1UL << obj->adc);
  64     // configure GPIO as input
  65     LPC_GPIO_PORT->DIR[port] &= ~(1UL << (pin & 0x1F));
  66
  67     // power up ADC
  68     if (obj->adc < ADC1_0)
  69     {
  70         // ADC0
  71         LPC_SYSCON->PDRUNCFG &= ~(1 << 10);
  72         LPC_SYSCON->SYSAHBCLKCTRL0 |= (1 << 27);
  73     }
  74     else {
  75         // ADC1
  76         LPC_SYSCON->PDRUNCFG &= ~(1 << 11);
  77         LPC_SYSCON->SYSAHBCLKCTRL0 |= (1 << 28);
  78     }
  79
  80     // select IRC as asynchronous clock, divided by 1
  81     LPC_SYSCON->ADCASYNCCLKSEL  = 0;
  82     LPC_SYSCON->ADCASYNCCLKDIV  = 1;
  83
  84     __IO LPC_ADC0_Type *adc_reg = (obj->adc < ADC1_0) ? (__IO LPC_ADC0_Type*)(LPC_ADC0) : (__IO LPC_ADC0_Type*)(LPC_ADC1);
  85
  86     // determine the system clock divider for a 500kHz ADC clock during calibration
  87     uint32_t clkdiv = (SystemCoreClock / 500000) - 1;
  88
  89     // perform a self-calibration
  90     adc_reg->CTRL = (1UL << 30) | (clkdiv & 0xFF);
  91     while ((adc_reg->CTRL & (1UL << 30)) != 0);
  92
  93     // switch to asynchronous mode
  94     adc_reg->CTRL = (1UL << 8);
  95 }
  96
  97 static inline uint32_t adc_read(analogin_t *obj) {
  98     uint32_t channels;
  99
 100     __IO LPC_ADC0_Type *adc_reg = (obj->adc < ADC1_0) ? (__IO LPC_ADC0_Type*)(LPC_ADC0) : (__IO LPC_ADC0_Type*)(LPC_ADC1);
 101
 102     if (obj->adc >= ADC1_0)
 103         channels = ((obj->adc - ADC1_0) & 0x1F);
 104     else
 105         channels = (obj->adc & 0x1F);
 106
 107     // select channel
 108     adc_reg->SEQA_CTRL &= ~(0xFFF);
 109     adc_reg->SEQA_CTRL |= (1UL << channels);
 110
 111     // start conversion and sequence enable
 112     adc_reg->SEQA_CTRL |= ((1UL << 26) | (1UL << 31));
 113
 114     // Repeatedly get the sample data until DONE bit
 115     volatile uint32_t data;
 116     do {
 117         data = adc_reg->SEQA_GDAT;
 118     } while ((data & (1UL << 31)) == 0);
 119
 120     // Stop conversion
 121     adc_reg->SEQA_CTRL &= ~(1UL << 31);
 122
 123     return ((data >> 4) & ADC_RANGE);
 124 }
 125
 126 static inline void order(uint32_t *a, uint32_t *b) {
 127     if (*a > *b) {
 128         uint32_t t = *a;
 129         *a = *b;
 130         *b = t;
 131     }
 132 }
 133
 134 static inline uint32_t adc_read_u32(analogin_t *obj) {
 135     uint32_t value;
 136 #if ANALOGIN_MEDIAN_FILTER
 137     uint32_t v1 = adc_read(obj);
 138     uint32_t v2 = adc_read(obj);
 139     uint32_t v3 = adc_read(obj);
 140     order(&v1, &v2);
 141     order(&v2, &v3);
 142     order(&v1, &v2);
 143     value = v2;
 144 #else
 145     value = adc_read(obj);
 146 #endif
 147     return value;
 148 }
 149
 150 uint16_t analogin_read_u16(analogin_t *obj) {
 151     uint32_t value = adc_read_u32(obj);
 152     return (value << 4) | ((value >> 8) & 0x000F); // 12 bit
 153 }
 154
 155 float analogin_read(analogin_t *obj) {
 156     uint32_t value = adc_read_u32(obj);
 157     return (float)value * (1.0f / (float)ADC_RANGE);
 158 }