tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC176X/spi_api.c

   1 /* mbed Microcontroller Library
   2  * Copyright (c) 2006-2013 ARM Limited
   3  *
   4  * Licensed under the Apache License, Version 2.0 (the "License");
   5  * you may not use this file except in compliance with the License.
   6  * You may obtain a copy of the License at
   7  *
   8  *     http://www.apache.org/licenses/LICENSE-2.0
   9  *
  10  * Unless required by applicable law or agreed to in writing, software
  11  * distributed under the License is distributed on an "AS IS" BASIS,
  12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13  * See the License for the specific language governing permissions and
  14  * limitations under the License.
  15  */
  16 #include "mbed_assert.h"
  17 #include <math.h>
  18
  19 #include "spi_api.h"
  20 #include "cmsis.h"
  21 #include "pinmap.h"
  22 #include "mbed_error.h"
  23
  24 static const PinMap PinMap_SPI_SCLK[] = {
  25     {P0_7 , SPI_1, 2},
  26     {P0_15, SPI_0, 2},
  27     {P1_20, SPI_0, 3},
  28     {P1_31, SPI_1, 2},
  29     {NC   , NC   , 0}
  30 };
  31
  32 static const PinMap PinMap_SPI_MOSI[] = {
  33     {P0_9 , SPI_1, 2},
  34     {P0_13, SPI_1, 2},
  35     {P0_18, SPI_0, 2},
  36     {P1_24, SPI_0, 3},
  37     {NC   , NC   , 0}
  38 };
  39
  40 static const PinMap PinMap_SPI_MISO[] = {
  41     {P0_8 , SPI_1, 2},
  42     {P0_12, SPI_1, 2},
  43     {P0_17, SPI_0, 2},
  44     {P1_23, SPI_0, 3},
  45     {NC   , NC   , 0}
  46 };
  47
  48 static const PinMap PinMap_SPI_SSEL[] = {
  49     {P0_6 , SPI_1, 2},
  50     {P0_11, SPI_1, 2},
  51     {P0_16, SPI_0, 2},
  52     {P1_21, SPI_0, 3},
  53     {NC   , NC   , 0}
  54 };
  55
  56 static inline int ssp_disable(spi_t *obj);
  57 static inline int ssp_enable(spi_t *obj);
  58
  59 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
  60     // determine the SPI to use
  61     SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
  62     SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
  63     SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
  64     SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
  65     SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
  66     SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
  67     obj->spi = (LPC_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
  68     MBED_ASSERT((int)obj->spi != NC);
  69
  70     // enable power and clocking
  71     switch ((int)obj->spi) {
  72         case SPI_0: LPC_SC->PCONP |= 1 << 21; break;
  73         case SPI_1: LPC_SC->PCONP |= 1 << 10; break;
  74     }
  75
  76     // set default format and frequency
  77     if (ssel == NC) {
  78         spi_format(obj, 8, 0, 0);  // 8 bits, mode 0, master
  79     } else {
  80         spi_format(obj, 8, 0, 1);  // 8 bits, mode 0, slave
  81     }
  82     spi_frequency(obj, 1000000);
  83
  84     // enable the ssp channel
  85     ssp_enable(obj);
  86
  87     // pin out the spi pins
  88     pinmap_pinout(mosi, PinMap_SPI_MOSI);
  89     pinmap_pinout(miso, PinMap_SPI_MISO);
  90     pinmap_pinout(sclk, PinMap_SPI_SCLK);
  91     if (ssel != NC) {
  92         pinmap_pinout(ssel, PinMap_SPI_SSEL);
  93     }
  94 }
  95
  96 void spi_free(spi_t *obj) {}
  97
  98 void spi_format(spi_t *obj, int bits, int mode, int slave) {
  99     ssp_disable(obj);
 100     MBED_ASSERT(((bits >= 4) && (bits <= 16)) && (mode >= 0 && mode <= 3));
 101
 102     int polarity = (mode & 0x2) ? 1 : 0;
 103     int phase = (mode & 0x1) ? 1 : 0;
 104
 105     // set it up
 106     int DSS = bits - 1;            // DSS (data select size)
 107     int SPO = (polarity) ? 1 : 0;  // SPO - clock out polarity
 108     int SPH = (phase) ? 1 : 0;     // SPH - clock out phase
 109
 110     int FRF = 0;                   // FRF (frame format) = SPI
 111     uint32_t tmp = obj->spi->CR0;
 112     tmp &= ~(0xFFFF);
 113     tmp |= DSS << 0
 114         | FRF << 4
 115         | SPO << 6
 116         | SPH << 7;
 117     obj->spi->CR0 = tmp;
 118
 119     tmp = obj->spi->CR1;
 120     tmp &= ~(0xD);
 121     tmp |= 0 << 0                   // LBM - loop back mode - off
 122         | ((slave) ? 1 : 0) << 2   // MS - master slave mode, 1 = slave
 123         | 0 << 3;                  // SOD - slave output disable - na
 124     obj->spi->CR1 = tmp;
 125
 126     ssp_enable(obj);
 127 }
 128
 129 void spi_frequency(spi_t *obj, int hz) {
 130     ssp_disable(obj);
 131
 132     // setup the spi clock diveder to /1
 133     switch ((int)obj->spi) {
 134         case SPI_0:
 135             LPC_SC->PCLKSEL1 &= ~(3 << 10);
 136             LPC_SC->PCLKSEL1 |=  (1 << 10);
 137             break;
 138         case SPI_1:
 139             LPC_SC->PCLKSEL0 &= ~(3 << 20);
 140             LPC_SC->PCLKSEL0 |=  (1 << 20);
 141             break;
 142     }
 143
 144     uint32_t PCLK = SystemCoreClock;
 145
 146     int prescaler;
 147
 148     for (prescaler = 2; prescaler <= 254; prescaler += 2) {
 149         int prescale_hz = PCLK / prescaler;
 150
 151         // calculate the divider
 152         int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
 153
 154         // check we can support the divider
 155         if (divider < 256) {
 156             // prescaler
 157             obj->spi->CPSR = prescaler;
 158
 159             // divider
 160             obj->spi->CR0 &= ~(0xFFFF << 8);
 161             obj->spi->CR0 |= (divider - 1) << 8;
 162             ssp_enable(obj);
 163             return;
 164         }
 165     }
 166     error("Couldn't setup requested SPI frequency");
 167 }
 168
 169 static inline int ssp_disable(spi_t *obj) {
 170     return obj->spi->CR1 &= ~(1 << 1);
 171 }
 172
 173 static inline int ssp_enable(spi_t *obj) {
 174     return obj->spi->CR1 |= (1 << 1);
 175 }
 176
 177 static inline int ssp_readable(spi_t *obj) {
 178     return obj->spi->SR & (1 << 2);
 179 }
 180
 181 static inline int ssp_writeable(spi_t *obj) {
 182     return obj->spi->SR & (1 << 1);
 183 }
 184
 185 static inline void ssp_write(spi_t *obj, int value) {
 186     while (!ssp_writeable(obj));
 187     obj->spi->DR = value;
 188 }
 189
 190 static inline int ssp_read(spi_t *obj) {
 191     while (!ssp_readable(obj));
 192     return obj->spi->DR;
 193 }
 194
 195 static inline int ssp_busy(spi_t *obj) {
 196     return (obj->spi->SR & (1 << 4)) ? (1) : (0);
 197 }
 198
 199 int spi_master_write(spi_t *obj, int value) {
 200     ssp_write(obj, value);
 201     return ssp_read(obj);
 202 }
 203
 204 int spi_slave_receive(spi_t *obj) {
 205     return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
 206 }
 207
 208 int spi_slave_read(spi_t *obj) {
 209     return obj->spi->DR;
 210 }
 211
 212 void spi_slave_write(spi_t *obj, int value) {
 213     while (ssp_writeable(obj) == 0) ;
 214     obj->spi->DR = value;
 215 }
 216
 217 int spi_busy(spi_t *obj) {
 218     return ssp_busy(obj);
 219 }