tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC23XX/gpio_irq_api.c

   1 /* mbed Microcontroller Library
   2  * Copyright (c) 2006-2013 ARM Limited
   3  *
   4  * Licensed under the Apache License, Version 2.0 (the "License");
   5  * you may not use this file except in compliance with the License.
   6  * You may obtain a copy of the License at
   7  *
   8  *     http://www.apache.org/licenses/LICENSE-2.0
   9  *
  10  * Unless required by applicable law or agreed to in writing, software
  11  * distributed under the License is distributed on an "AS IS" BASIS,
  12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13  * See the License for the specific language governing permissions and
  14  * limitations under the License.
  15  */
  16 #include "gpio_irq_api.h"
  17 #include "mbed_error.h"
  18 #include <stddef.h>
  19 #include "cmsis.h"
  20
  21 #define CHANNEL_NUM     48
  22
  23 static uint32_t channel_ids[CHANNEL_NUM] = {0};
  24 static gpio_irq_handler irq_handler;
  25
  26 static void handle_interrupt_in(void) {
  27     // Read in all current interrupt registers. We do this once as the
  28     // GPIO interrupt registers are on the APB bus, and this is slow.
  29     uint32_t rise0 = LPC_GPIOINT->IO0IntStatR;
  30     uint32_t fall0 = LPC_GPIOINT->IO0IntStatF;
  31     uint32_t rise2 = LPC_GPIOINT->IO2IntStatR;
  32     uint32_t fall2 = LPC_GPIOINT->IO2IntStatF;
  33     uint32_t mask0 = 0;
  34     uint32_t mask2 = 0;
  35     int i;
  36
  37     // P0.0-0.31
  38     for (i = 0; i < 32; i++) {
  39         uint32_t pmask = (1 << i);
  40         if (rise0 & pmask) {
  41             mask0 |= pmask;
  42             if (channel_ids[i] != 0)
  43                 irq_handler(channel_ids[i], IRQ_RISE);
  44         }
  45         if (fall0 & pmask) {
  46             mask0 |= pmask;
  47             if (channel_ids[i] != 0)
  48                 irq_handler(channel_ids[i], IRQ_FALL);
  49         }
  50     }
  51
  52     // P2.0-2.15
  53     for (i = 0; i < 16; i++) {
  54         uint32_t pmask = (1 << i);
  55         int channel_index = i + 32;
  56         if (rise2 & pmask) {
  57             mask2 |= pmask;
  58             if (channel_ids[channel_index] != 0)
  59                 irq_handler(channel_ids[channel_index], IRQ_RISE);
  60         }
  61         if (fall2 & pmask) {
  62             mask2 |= pmask;
  63             if (channel_ids[channel_index] != 0)
  64                 irq_handler(channel_ids[channel_index], IRQ_FALL);
  65         }
  66     }
  67
  68     // Clear the interrupts we just handled
  69     LPC_GPIOINT->IO0IntClr = mask0;
  70     LPC_GPIOINT->IO2IntClr = mask2;
  71 }
  72
  73 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
  74     if (pin == NC) return -1;
  75
  76     irq_handler = handler;
  77
  78     obj->port = (int)pin & ~0x1F;
  79     obj->pin = (int)pin & 0x1F;
  80
  81     // Interrupts available only on GPIO0 and GPIO2
  82     if (obj->port != LPC_GPIO0_BASE && obj->port != LPC_GPIO2_BASE) {
  83         error("pins on this port cannot generate interrupts");
  84     }
  85
  86     // put us in the interrupt table
  87     int index = (obj->port == LPC_GPIO0_BASE) ? obj->pin : obj->pin + 32;
  88     channel_ids[index] = id;
  89     obj->ch = index;
  90
  91     NVIC_SetVector(EINT3_IRQn, (uint32_t)handle_interrupt_in);
  92     NVIC_EnableIRQ(EINT3_IRQn);
  93
  94     return 0;
  95 }
  96
  97 void gpio_irq_free(gpio_irq_t *obj) {
  98     channel_ids[obj->ch] = 0;
  99 }
 100
 101 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
 102     // ensure nothing is pending
 103     switch (obj->port) {
 104          case LPC_GPIO0_BASE: LPC_GPIOINT->IO0IntClr = 1 << obj->pin; break;
 105          case LPC_GPIO2_BASE: LPC_GPIOINT->IO2IntClr = 1 << obj->pin; break;
 106     }
 107
 108     // enable the pin interrupt
 109     if (event == IRQ_RISE) {
 110         switch (obj->port) {
 111             case LPC_GPIO0_BASE:
 112                 if (enable) {
 113                     LPC_GPIOINT->IO0IntEnR |= 1 << obj->pin;
 114                 } else {
 115                     LPC_GPIOINT->IO0IntEnR &= ~(1 << obj->pin);
 116                 }
 117                 break;
 118             case LPC_GPIO2_BASE:
 119                 if (enable) {
 120                     LPC_GPIOINT->IO2IntEnR |= 1 << obj->pin;
 121                 } else {
 122                     LPC_GPIOINT->IO2IntEnR &= ~(1 << obj->pin);
 123                 }
 124                 break;
 125         }
 126     } else {
 127         switch (obj->port) {
 128             case LPC_GPIO0_BASE:
 129                 if (enable) {
 130                     LPC_GPIOINT->IO0IntEnF |= 1 << obj->pin;
 131                 } else {
 132                     LPC_GPIOINT->IO0IntEnF &= ~(1 << obj->pin);
 133                 }
 134                 break;
 135
 136             case LPC_GPIO2_BASE:
 137                 if (enable) {
 138                     LPC_GPIOINT->IO2IntEnF |= 1 << obj->pin;
 139                 } else {
 140                     LPC_GPIOINT->IO2IntEnF &= ~(1 << obj->pin);
 141                 }
 142                 break;
 143         }
 144     }
 145 }
 146
 147 void gpio_irq_enable(gpio_irq_t *obj) {
 148     NVIC_EnableIRQ(EINT3_IRQn);
 149 }
 150
 151 void gpio_irq_disable(gpio_irq_t *obj) {
 152     NVIC_DisableIRQ(EINT3_IRQn);
 153 }
 154