tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC43XX/README.txt

   1 mbed port to NXP LPC43xx
   2 ========================
   3 Updated: 07/11/14
   4
   5 The NXP LPC43xx microcontrollers includes multiple Cortex-M cores in a single
   6 microcontroller package. This port allows mbed developers to take advantage
   7 of the LPC43xx in their application using APIs that they are familiar with.
   8 Some of the key features of the LPC43xx include:
   9
  10 * Dual core ARM Cortex-M4/M0 both capable of up to 204 MHz
  11 * Up to 264 KB SRAM, 1 MB internal flash
  12 * Two High-speed USB 2.0 interfaces
  13 * Ethernet MAC
  14 * LCD interface
  15 * Quad-SPI Flash Interface (SPIFI)
  16 * State Configurable Timer (SCT)
  17 * Serial GPIO (SGPIO)
  18 * Up to 164 GPIO
  19
  20 The NXP LPC18xx is a single core Cortex-M3 implementation that is compatible
  21 with the LPC43XX for cost-sensitive applications not requiring multiple cores.
  22
  23 mbed port to the LPC43XX - Micromint USA <support@micromint.com>
  24
  25 Compatibility
  26 -------------
  27 * This port has been tested with the following boards:
  28     Board                    MCU        RAM/Flash
  29     Micromint Bambino 200    LPC4330    264K SRAM/4 MB SPIFI flash
  30     Micromint Bambino 200E   LPC4330    264K SRAM/8 MB SPIFI flash
  31     Micromint Bambino 210    LPC4330    264K SRAM/4 MB SPIFI flash
  32     Micromint Bambino 210E   LPC4330    264K SRAM/8 MB SPIFI flash
  33
  34 * CMSIS-DAP debugging is implemented with the Micromint Bambino 210/210E.
  35   To debug other LPC4330 targets, use a JTAG. The NXP DFU tool can be used
  36   for flash programming.
  37
  38 * This port should support NXP LPC43XX and LPC18XX variants with a single
  39   codebase. The core declaration specifies the binaries to be built:
  40     mbed define      CMSIS define  MCU Target
  41     __CORTEX_M4      CORE_M4       LPC43xx Cortex-M4
  42     __CORTEX_M0      CORE_M0       LPC43xx Cortex-M0
  43     __CORTEX_M3      CORE_M3       LPC18xx Cortex-M3
  44   These MCUs all share the peripheral IP, common driver code is feasible.
  45   Yet each variant can have different memory segments, peripherals, etc.
  46   Plus, each board design can integrate different external peripherals
  47   or interfaces. A future release of the mbed SDK and its build tools will
  48   support specifying the target board when building binaries. At this time
  49   building binaries for different targets requires an external project or
  50   Makefile.
  51
  52 * No testing has been done with LPC18xx hardware.
  53
  54 Notes
  55 -----
  56 * On the LPC43xx the hardware pin name and the GPIO pin name are not the same,
  57   requiring different offsets for the SCU and GPIO registers. To simplify logic
  58   the pin identifier encodes the offsets. Macros are used for decoding.
  59   For example, P6_11 corresponds to GPIO3[7] and is encoded/decoded as follows:
  60
  61     P6_11 = MBED_PIN(0x06, 11, 3, 7) = 0x032C0067
  62
  63     MBED_SCU_REG(P6_11)  = 0x4008632C      MBED_GPIO_PORT(P6_11) = 3
  64     MBED_GPIO_REG(P6_11) = 0x400F4000      MBED_GPIO_PIN(P6_11)  = 7
  65
  66 * Pin names use multiple aliases to support Arduino naming conventions as well
  67   as others. For example, to use pin p21 on the Bambino 210 from mbed applications
  68   the following aliases are equivalent: p21, D0, UART0_TX, COM1_TX, P6_4.
  69   See the board pinout graphic and the PinNames.h for available aliases.
  70
  71 * The LPC43xx implements GPIO pin and group interrupts. Any pin in the 8 32-bit
  72   GPIO ports can interrupt (LPC4350 supports up to 164). On group interrupts a
  73   pin can only interrupt on the rising or falling edge, not both as required
  74   by the mbed InterruptIn class. Also, group interrupts can't be cleared
  75   individually. This implementation uses pin interrupts (8 on M4/M3, 1 on M0).
  76   A future implementation may provide group interrupt support.
  77
  78 * The LPC3xx PWM driver uses the State Configurable Timer (SCT). The default
  79   build (PWM_MODE=0) uses the unified 32-bit times. Applications that use PWM
  80   and require other SCT uses can use the dual 16-bit mode by changing PWM_MODE
  81   when building the library.