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git.gir.st - tmk_keyboard.git/blob - tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/spi_api.c
1 /* mbed Microcontroller Library
2 * Copyright (c) 2006-2013 ARM Limited
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
16 #include "mbed_assert.h"
22 #include "mbed_error.h"
24 static const SWM_Map SWM_SPI_SSEL
[] = {
29 static const SWM_Map SWM_SPI_SCLK
[] = {
34 static const SWM_Map SWM_SPI_MOSI
[] = {
39 static const SWM_Map SWM_SPI_MISO
[] = {
44 // bit flags for used SPIs
45 static unsigned char spi_used
= 0;
46 static int get_available_spi(void) {
49 if ((spi_used
& (1 << i
)) == 0)
55 static inline int ssp_disable(spi_t
*obj
);
56 static inline int ssp_enable(spi_t
*obj
);
58 void spi_init(spi_t
*obj
, PinName mosi
, PinName miso
, PinName sclk
, PinName ssel
) {
59 int spi_n
= get_available_spi();
61 error("No available SPI");
64 spi_used
|= (1 << spi_n
);
66 obj
->spi
= (spi_n
) ? (LPC_SPI_TypeDef
*)(LPC_SPI1_BASE
) : (LPC_SPI_TypeDef
*)(LPC_SPI0_BASE
);
71 swm
= &SWM_SPI_SCLK
[obj
->spi_n
];
72 regVal
= LPC_SWM
->PINASSIGN
[swm
->n
] & ~(0xFF << swm
->offset
);
73 LPC_SWM
->PINASSIGN
[swm
->n
] = regVal
| (sclk
<< swm
->offset
);
75 swm
= &SWM_SPI_MOSI
[obj
->spi_n
];
76 regVal
= LPC_SWM
->PINASSIGN
[swm
->n
] & ~(0xFF << swm
->offset
);
77 LPC_SWM
->PINASSIGN
[swm
->n
] = regVal
| (mosi
<< swm
->offset
);
79 swm
= &SWM_SPI_MISO
[obj
->spi_n
];
80 regVal
= LPC_SWM
->PINASSIGN
[swm
->n
] & ~(0xFF << swm
->offset
);
81 LPC_SWM
->PINASSIGN
[swm
->n
] = regVal
| (miso
<< swm
->offset
);
83 swm
= &SWM_SPI_SSEL
[obj
->spi_n
];
84 regVal
= LPC_SWM
->PINASSIGN
[swm
->n
] & ~(0xFF << swm
->offset
);
85 LPC_SWM
->PINASSIGN
[swm
->n
] = regVal
| (ssel
<< swm
->offset
);
88 obj
->spi
->INTENCLR
= 0x3f;
90 // enable power and clocking
93 LPC_SYSCON
->SYSAHBCLKCTRL
|= (1<<11);
94 LPC_SYSCON
->PRESETCTRL
&= ~(0x1<<0);
95 LPC_SYSCON
->PRESETCTRL
|= (0x1<<0);
98 LPC_SYSCON
->SYSAHBCLKCTRL
|= (1<<12);
99 LPC_SYSCON
->PRESETCTRL
&= ~(0x1<<1);
100 LPC_SYSCON
->PRESETCTRL
|= (0x1<<1);
104 // set default format and frequency
106 spi_format(obj
, 8, 0, 0); // 8 bits, mode 0, master
108 spi_format(obj
, 8, 0, 1); // 8 bits, mode 0, slave
110 spi_frequency(obj
, 1000000);
112 // enable the ssp channel
116 void spi_free(spi_t
*obj
) {}
118 void spi_format(spi_t
*obj
, int bits
, int mode
, int slave
) {
119 MBED_ASSERT(((bits
>= 1) && (bits
<= 16)) && ((mode
>= 0) && (mode
<= 3)));
122 int polarity
= (mode
& 0x2) ? 1 : 0;
123 int phase
= (mode
& 0x1) ? 1 : 0;
126 int DSS
= bits
- 1; // DSS (data select size)
127 int SPO
= (polarity
) ? 1 : 0; // SPO - clock out polarity
128 int SPH
= (phase
) ? 1 : 0; // SPH - clock out phase
130 uint32_t tmp
= obj
->spi
->CFG
;
131 tmp
&= ~((1 << 2) | (1 << 4) | (1 << 5));
132 tmp
|= (SPH
<< 4) | (SPO
<< 5) | ((slave
? 0 : 1) << 2);
135 // select frame length
136 tmp
= obj
->spi
->TXDATCTL
;
139 obj
->spi
->TXDATCTL
= tmp
;
144 void spi_frequency(spi_t
*obj
, int hz
) {
147 uint32_t PCLK
= SystemCoreClock
;
149 obj
->spi
->DIV
= PCLK
/hz
- 1;
154 static inline int ssp_disable(spi_t
*obj
) {
155 return obj
->spi
->CFG
&= ~(1 << 0);
158 static inline int ssp_enable(spi_t
*obj
) {
159 return obj
->spi
->CFG
|= (1 << 0);
162 static inline int ssp_readable(spi_t
*obj
) {
163 return obj
->spi
->STAT
& (1 << 0);
166 static inline int ssp_writeable(spi_t
*obj
) {
167 return obj
->spi
->STAT
& (1 << 1);
170 static inline void ssp_write(spi_t
*obj
, int value
) {
171 while (!ssp_writeable(obj
));
173 obj
->spi
->TXDATCTL
|= (1 << 20);
174 obj
->spi
->TXDAT
= value
;
177 static inline int ssp_read(spi_t
*obj
) {
178 while (!ssp_readable(obj
));
179 return obj
->spi
->RXDAT
;
182 static inline int ssp_busy(spi_t
*obj
) {
183 // checking RXOV(Receiver Overrun interrupt flag)
184 return obj
->spi
->STAT
& (1 << 2);
187 int spi_master_write(spi_t
*obj
, int value
) {
188 ssp_write(obj
, value
);
189 return ssp_read(obj
);
192 int spi_slave_receive(spi_t
*obj
) {
193 return (ssp_readable(obj
) && !ssp_busy(obj
)) ? (1) : (0);
196 int spi_slave_read(spi_t
*obj
) {
197 return obj
->spi
->RXDAT
;
200 void spi_slave_write(spi_t
*obj
, int value
) {
201 while (ssp_writeable(obj
) == 0) ;
202 obj
->spi
->TXDAT
= value
;
205 int spi_busy(spi_t
*obj
) {
206 return ssp_busy(obj
);