tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/us_ticker.c

   1 /* mbed Microcontroller Library
   2  * Copyright (c) 2006-2013 ARM Limited
   3  *
   4  * Licensed under the Apache License, Version 2.0 (the "License");
   5  * you may not use this file except in compliance with the License.
   6  * You may obtain a copy of the License at
   7  *
   8  *     http://www.apache.org/licenses/LICENSE-2.0
   9  *
  10  * Unless required by applicable law or agreed to in writing, software
  11  * distributed under the License is distributed on an "AS IS" BASIS,
  12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13  * See the License for the specific language governing permissions and
  14  * limitations under the License.
  15  */
  16 #include <stddef.h>
  17 #include "us_ticker_api.h"
  18 #include "PeripheralNames.h"
  19
  20 //New, using MRT instead of SCT, needed to free up SCT for PWM
  21 //Ported from LPC824 libs
  22 static int us_ticker_inited = 0;
  23 unsigned int ticker_fullcount_us;
  24 unsigned long int ticker_expired_count_us = 0;
  25 int MRT_Clock_MHz;
  26
  27 #define US_TICKER_TIMER_IRQn     MRT_IRQn
  28
  29 void us_ticker_init(void) {
  30
  31     if (us_ticker_inited)
  32         return;
  33
  34     us_ticker_inited = 1;
  35
  36     // Calculate MRT clock value (MRT has no prescaler)
  37     MRT_Clock_MHz = (SystemCoreClock / 1000000);
  38     // Calculate fullcounter value in us (MRT has 31 bits and clock is 30 MHz)
  39     ticker_fullcount_us = 0x80000000UL/MRT_Clock_MHz;
  40
  41     // Enable the MRT clock
  42     LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 10);
  43
  44     // Clear peripheral reset the MRT
  45     LPC_SYSCON->PRESETCTRL |= (1 << 7);
  46
  47     // Force load interval value (Bit 0-30 is interval value, Bit 31 is Force Load bit)
  48     LPC_MRT->INTVAL0 = 0xFFFFFFFFUL;
  49     // Enable Ch0 interrupt, Mode 0 is Repeat Interrupt
  50     LPC_MRT->CTRL0 = (0x0 << 1) | (0x1 << 0);
  51
  52     // Force load interval value (Bit 0-30 is interval value, Bit 31 is Force Load bit)
  53     LPC_MRT->INTVAL1 = 0x80000000UL;
  54     // Disable ch1 interrupt, Mode 0 is Repeat Interrupt
  55     LPC_MRT->CTRL1 = (0x0 << 1) | (0x0 << 0);
  56
  57     // Set MRT interrupt vector
  58     NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
  59     NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
  60 }
  61
  62 //TIMER0 is used for us ticker and timers (Timer, wait(), wait_us() etc)
  63 uint32_t us_ticker_read() {
  64
  65     if (!us_ticker_inited)
  66         us_ticker_init();
  67
  68     // Generate ticker value
  69     // MRT source clock is SystemCoreClock (30MHz) and MRT is a 31-bit countdown timer
  70     // Calculate expected value using current count and number of expired times to mimic a 32bit timer @ 1 MHz
  71     //
  72     // ticker_expired_count_us
  73     // The variable ticker_expired_count_us keeps track of the number of 31bits overflows (counted by TIMER0) and
  74     // corrects that back to us counts.
  75     //
  76     // (0x7FFFFFFFUL - LPC_MRT->TIMER0)/MRT_Clock_MHz
  77     // The counter is a 31bit downcounter from 7FFFFFFF so correct to actual count-up value and correct
  78     // for 30 counts per us.
  79     //
  80     // Added up these 2 parts result in current us time returned as 32 bits.
  81     return (0x7FFFFFFFUL - LPC_MRT->TIMER0)/MRT_Clock_MHz + ticker_expired_count_us;
  82 }
  83
  84 //TIMER1 is used for Timestamped interrupts (Ticker(), Timeout())
  85 void us_ticker_set_interrupt(timestamp_t timestamp) {
  86
  87     // MRT source clock is SystemCoreClock (30MHz) and MRT is a 31-bit countdown timer
  88     // Force load interval value (Bit 0-30 is interval value, Bit 31 is Force Load bit)
  89     // Note: The MRT has less counter headroom available than the typical mbed 32bit timer @ 1 MHz.
  90     //       The calculated counter interval until the next timestamp will be truncated and an
  91     //       'early' interrupt will be generated in case the max required count interval exceeds
  92     //       the available 31 bits space. However, the mbed us_ticker interrupt handler will
  93     //       check current time against the next scheduled timestamp and simply re-issue the
  94     //       same interrupt again when needed. The calculated counter interval will now be smaller.
  95     LPC_MRT->INTVAL1 = (((timestamp - us_ticker_read()) * MRT_Clock_MHz) | 0x80000000UL);
  96
  97     // Enable interrupt
  98     LPC_MRT->CTRL1 |= 1;
  99 }
 100
 101 //Disable Timestamped interrupts triggered by TIMER1
 102 void us_ticker_disable_interrupt() {
 103     //Timer1 for Timestamped interrupts (31 bits downcounter @ SystemCoreClock)
 104     LPC_MRT->CTRL1 &= ~1;
 105 }
 106
 107 void us_ticker_clear_interrupt() {
 108
 109     //Timer1 for Timestamped interrupts (31 bits downcounter @ SystemCoreClock)
 110     if (LPC_MRT->STAT1 & 1)
 111         LPC_MRT->STAT1 = 1;
 112
 113     //Timer0 for us counter (31 bits downcounter @ SystemCoreClock)
 114     if (LPC_MRT->STAT0 & 1) {
 115         LPC_MRT->STAT0 = 1;
 116         // ticker_expired_count_us = (ticker_expired * 0x80000000UL) / MRT_Clock_MHz
 117         // The variable ticker_expired_count_us keeps track of the number of 31bits overflows (counted by TIMER0) and
 118         // the multiplication/division corrects that back to us counts.
 119         ticker_expired_count_us += ticker_fullcount_us;
 120     }
 121 }