tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/spi_api.c

   1 /* mbed Microcontroller Library
   2  * Copyright (c) 2006-2013 ARM Limited
   3  *
   4  * Licensed under the Apache License, Version 2.0 (the "License");
   5  * you may not use this file except in compliance with the License.
   6  * You may obtain a copy of the License at
   7  *
   8  *     http://www.apache.org/licenses/LICENSE-2.0
   9  *
  10  * Unless required by applicable law or agreed to in writing, software
  11  * distributed under the License is distributed on an "AS IS" BASIS,
  12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13  * See the License for the specific language governing permissions and
  14  * limitations under the License.
  15  */
  16 #include "mbed_assert.h"
  17
  18 #include "spi_api.h"
  19 #include "cmsis.h"
  20 #include "pinmap.h"
  21 #include "mbed_error.h"
  22
  23 #if DEVICE_SPI
  24
  25 static const SWM_Map SWM_SPI_SSEL[] = {
  26     {4, 16},
  27     {6, 8},
  28 };
  29
  30 static const SWM_Map SWM_SPI_SCLK[] = {
  31     {3, 24},
  32     {5, 16},
  33 };
  34
  35 static const SWM_Map SWM_SPI_MOSI[] = {
  36     {4, 0},
  37     {5, 24},
  38 };
  39
  40 static const SWM_Map SWM_SPI_MISO[] = {
  41     {4, 8},
  42     {6, 0},
  43 };
  44
  45 // bit flags for used SPIs
  46 static unsigned char spi_used = 0;
  47
  48 static int get_available_spi(void)
  49 {
  50     int i;
  51     for (i=0; i<2; i++) {
  52         if ((spi_used & (1 << i)) == 0)
  53             return i;
  54     }
  55     return -1;
  56 }
  57
  58 static inline void spi_disable(spi_t *obj);
  59 static inline void spi_enable(spi_t *obj);
  60
  61 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
  62 {
  63     int spi_n = get_available_spi();
  64     if (spi_n == -1) {
  65         error("No available SPI");
  66     }
  67     obj->spi_n = spi_n;
  68     spi_used |= (1 << spi_n);
  69
  70     obj->spi = (spi_n) ? (LPC_SPI0_Type *)(LPC_SPI1_BASE) : (LPC_SPI0_Type *)(LPC_SPI0_BASE);
  71
  72     const SWM_Map *swm;
  73     uint32_t regVal;
  74
  75     if (sclk != (PinName)NC) {
  76         swm = &SWM_SPI_SCLK[obj->spi_n];
  77         regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
  78         LPC_SWM->PINASSIGN[swm->n] = regVal |  ((sclk >> PIN_SHIFT) << swm->offset);
  79     }
  80
  81     if (mosi != (PinName)NC) {
  82         swm = &SWM_SPI_MOSI[obj->spi_n];
  83         regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
  84         LPC_SWM->PINASSIGN[swm->n] = regVal |  ((mosi >> PIN_SHIFT) << swm->offset);
  85     }
  86
  87     if (miso != (PinName)NC) {
  88         swm = &SWM_SPI_MISO[obj->spi_n];
  89         regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
  90         LPC_SWM->PINASSIGN[swm->n] = regVal |  ((miso >> PIN_SHIFT) << swm->offset);
  91     }
  92
  93     if (ssel != (PinName)NC) {
  94         swm = &SWM_SPI_SSEL[obj->spi_n];
  95         regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
  96         LPC_SWM->PINASSIGN[swm->n] = regVal |  ((ssel >> PIN_SHIFT) << swm->offset);
  97     }
  98
  99     // clear interrupts
 100     obj->spi->INTENCLR = 0x3f;
 101
 102     LPC_SYSCON->SYSAHBCLKCTRL |=  (1 << (11 + obj->spi_n));
 103     LPC_SYSCON->PRESETCTRL    &= ~(1 << obj->spi_n);
 104     LPC_SYSCON->PRESETCTRL    |=  (1 << obj->spi_n);
 105
 106     // set default format and frequency
 107     if (ssel == (PinName)NC) {
 108         spi_format(obj, 8, 0, 0);  // 8 bits, mode 0, master
 109     } else {
 110         spi_format(obj, 8, 0, 1);  // 8 bits, mode 0, slave
 111     }
 112     spi_frequency(obj, 1000000);
 113     obj->spi->DLY = 2;             // 2 SPI clock times pre-delay
 114
 115     // enable the ssp channel
 116     spi_enable(obj);
 117 }
 118
 119 void spi_free(spi_t *obj)
 120 {
 121 }
 122
 123 void spi_format(spi_t *obj, int bits, int mode, int slave)
 124 {
 125     MBED_ASSERT(((bits >= 1) && (bits <= 16)) && ((mode >= 0) && (mode <= 3)));
 126     spi_disable(obj);
 127
 128     obj->spi->CFG &= ~((0x3 << 4) | (1 << 2));
 129     obj->spi->CFG |=  ((mode & 0x3) << 4) | ((slave ? 0 : 1) << 2);
 130
 131     obj->spi->TXCTL &= ~( 0xF << 24);
 132     obj->spi->TXCTL |=  ((bits - 1) << 24);
 133
 134     spi_enable(obj);
 135 }
 136
 137 void spi_frequency(spi_t *obj, int hz)
 138 {
 139     spi_disable(obj);
 140
 141     // rise DIV value if it cannot be divided
 142     obj->spi->DIV = (SystemCoreClock + (hz - 1))/hz - 1;
 143
 144     spi_enable(obj);
 145 }
 146
 147 static inline void spi_disable(spi_t *obj)
 148 {
 149     obj->spi->CFG &= ~(1 << 0);
 150 }
 151
 152 static inline void spi_enable(spi_t *obj)
 153 {
 154     obj->spi->CFG |= (1 << 0);
 155 }
 156
 157 static inline int spi_readable(spi_t *obj)
 158 {
 159     return obj->spi->STAT & (1 << 0);
 160 }
 161
 162 static inline int spi_writeable(spi_t *obj)
 163 {
 164     return obj->spi->STAT & (1 << 1);
 165 }
 166
 167 static inline void spi_write(spi_t *obj, int value)
 168 {
 169     while (!spi_writeable(obj));
 170     // end of transfer
 171     obj->spi->TXCTL |= (1 << 20);
 172     obj->spi->TXDAT = (value & 0xffff);
 173 }
 174
 175 static inline int spi_read(spi_t *obj)
 176 {
 177     while (!spi_readable(obj));
 178     return (obj->spi->RXDAT & 0xFFFF);
 179 }
 180
 181 int spi_master_write(spi_t *obj, int value)
 182 {
 183     spi_write(obj, value);
 184     return spi_read(obj);
 185 }
 186
 187 int spi_busy(spi_t *obj)
 188 {
 189     // checking RXOV(Receiver Overrun interrupt flag)
 190     return obj->spi->STAT & (1 << 2);
 191 }
 192
 193 int spi_slave_receive(spi_t *obj)
 194 {
 195     return (spi_readable(obj) && !spi_busy(obj)) ? (1) : (0);
 196 }
 197
 198 int spi_slave_read(spi_t *obj)
 199 {
 200     return (obj->spi->RXDAT & 0xFFFF);
 201 }
 202
 203 void spi_slave_write(spi_t *obj, int value)
 204 {
 205     while (spi_writeable(obj) == 0);
 206     obj->spi->TXDAT = value;
 207 }
 208
 209 #endif