tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c

   1 /* mbed Microcontroller Library
   2  * Copyright (c) 2006-2013 ARM Limited
   3  *
   4  * Licensed under the Apache License, Version 2.0 (the "License");
   5  * you may not use this file except in compliance with the License.
   6  * You may obtain a copy of the License at
   7  *
   8  *     http://www.apache.org/licenses/LICENSE-2.0
   9  *
  10  * Unless required by applicable law or agreed to in writing, software
  11  * distributed under the License is distributed on an "AS IS" BASIS,
  12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13  * See the License for the specific language governing permissions and
  14  * limitations under the License.
  15  */
  16 #include "mbed_assert.h"
  17 #include "i2c_api.h"
  18 #include "cmsis.h"
  19 #include "pinmap.h"
  20 #include "r_typedefs.h"
  21
  22 #include "riic_iodefine.h"
  23 #include "RZ_A1_Init.h"
  24 #include "MBRZA1H.h"
  25
  26 volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST;
  27
  28 #define REG(N) \
  29     RIIC[obj->i2c]->RIICn##N
  30
  31 /* RIICnCR1 */
  32 #define CR1_RST   (1 << 6)
  33 #define CR1_ICE   (1 << 7)
  34
  35 /* RIICnCR2 */
  36 #define CR2_ST    (1 << 1)
  37 #define CR2_RS    (1 << 2)
  38 #define CR2_SP    (1 << 3)
  39 #define CR2_TRS   (1 << 5)
  40 #define CR2_BBSY  (1 << 7)
  41
  42 /* RIICnMR3 */
  43 #define MR3_ACKBT (1 << 3)
  44 #define MR3_ACKWP (1 << 4)
  45 #define MR3_WAIT  (1 << 6)
  46
  47 /* RIICnSER */
  48 #define SER_SAR0E (1 << 0)
  49
  50 /* RIICnSR1 */
  51 #define SR1_AAS0  (1 << 0)
  52
  53 /* RIICnSR2 */
  54 #define SR2_START (1 << 2)
  55 #define SR2_STOP  (1 << 3)
  56 #define SR2_NACKF (1 << 4)
  57 #define SR2_RDRF  (1 << 5)
  58 #define SR2_TEND  (1 << 6)
  59 #define SR2_TDRE  (1 << 7)
  60
  61 #define WAIT_TIMEOUT    (4200)  /* Loop counter : Time-out is about 1ms. By 4200 loops, measured value is 1009ms. */
  62
  63 static const PinMap PinMap_I2C_SDA[] = {
  64     {P1_1 , I2C_0, 1},
  65     {P1_3 , I2C_1, 1},
  66     {P1_7 , I2C_3, 1},
  67     {NC   , NC   , 0}
  68 };
  69
  70 static const PinMap PinMap_I2C_SCL[] = {
  71     {P1_0 , I2C_0, 1},
  72     {P1_2 , I2C_1, 1},
  73     {P1_6 , I2C_3, 1},
  74     {NC   , NC,    0}
  75 };
  76
  77
  78 static inline int i2c_status(i2c_t *obj) {
  79     return REG(SR2.UINT8[0]);
  80 }
  81
  82 static void i2c_reg_reset(i2c_t *obj) {
  83     /* full reset */
  84     REG(CR1.UINT8[0]) &= ~CR1_ICE; // CR1.ICE off
  85     REG(CR1.UINT8[0]) |=  CR1_RST; // CR1.IICRST on
  86     REG(CR1.UINT8[0]) |=  CR1_ICE; // CR1.ICE on
  87
  88     REG(MR1.UINT8[0])  =  0x08;    // P_phi /x  9bit (including Ack)
  89     REG(SER.UINT8[0])  =  0x00;    // no slave addr enabled
  90
  91     /* set frequency */
  92     REG(MR1.UINT8[0]) |=  obj->pclk_bit;
  93     REG(BRL.UINT8[0])  =  obj->width_low;
  94     REG(BRH.UINT8[0])  =  obj->width_hi;
  95
  96     REG(MR2.UINT8[0])  =  0x07;
  97     REG(MR3.UINT8[0])  =  0x00;
  98
  99     REG(FER.UINT8[0])  =  0x72;    // SCLE, NFE enabled, TMOT
 100     REG(IER.UINT8[0])  =  0x00;    // no interrupt
 101
 102     REG(CR1.UINT32) &= ~CR1_RST;   // CR1.IICRST negate reset
 103 }
 104
 105 static inline int i2c_wait_RDRF(i2c_t *obj) {
 106     int timeout = 0;
 107
 108     /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
 109     while (!(i2c_status(obj) & SR2_RDRF)) {
 110         timeout ++;
 111         if (timeout >= WAIT_TIMEOUT) {
 112             return -1;
 113         }
 114     }
 115
 116     return 0;
 117 }
 118
 119 static int i2c_wait_TDRE(i2c_t *obj) {
 120     int timeout = 0;
 121
 122     /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
 123     while (!(i2c_status(obj) & SR2_TDRE)) {
 124         timeout ++;
 125         if (timeout >= WAIT_TIMEOUT) {
 126             return -1;
 127         }
 128     }
 129
 130     return 0;
 131 }
 132
 133 static int i2c_wait_TEND(i2c_t *obj) {
 134     int timeout = 0;
 135
 136     /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
 137     while (!(i2c_status(obj) & SR2_TEND)) {
 138         timeout ++;
 139         if (timeout >= WAIT_TIMEOUT) {
 140             return -1;
 141         }
 142     }
 143
 144     return 0;
 145 }
 146
 147
 148 static int i2c_wait_START(i2c_t *obj) {
 149     int timeout = 0;
 150
 151     /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
 152     while (!(i2c_status(obj) & SR2_START)) {
 153         timeout ++;
 154         if (timeout >= WAIT_TIMEOUT) {
 155             return -1;
 156         }
 157     }
 158
 159     return 0;
 160 }
 161
 162 static int i2c_wait_STOP(i2c_t *obj) {
 163     int timeout = 0;
 164
 165     /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
 166     while (!(i2c_status(obj) & SR2_STOP)) {
 167         timeout ++;
 168         if (timeout >= WAIT_TIMEOUT) {
 169             return -1;
 170         }
 171     }
 172
 173     return 0;
 174 }
 175
 176 static void i2c_set_SR2_NACKF_STOP(i2c_t *obj) {
 177     /* SR2.NACKF = 0 */
 178     REG(SR2.UINT32) &= ~SR2_NACKF;
 179     /* SR2.STOP = 0 */
 180     REG(SR2.UINT32) &= ~SR2_STOP;
 181 }
 182
 183 static void i2c_set_MR3_NACK(i2c_t *obj) {
 184     /* send a NOT ACK */
 185     REG(MR3.UINT32) |=  MR3_ACKWP;
 186     REG(MR3.UINT32) |=  MR3_ACKBT;
 187     REG(MR3.UINT32) &= ~MR3_ACKWP;
 188 }
 189
 190 static void i2c_set_MR3_ACK(i2c_t *obj) {
 191     /* send a ACK */
 192     REG(MR3.UINT32) |=  MR3_ACKWP;
 193     REG(MR3.UINT32) &= ~MR3_ACKBT;
 194     REG(MR3.UINT32) &= ~MR3_ACKWP;
 195 }
 196
 197 static inline void i2c_power_enable(i2c_t *obj) {
 198     volatile uint8_t dummy;
 199     switch ((int)obj->i2c) {
 200         case I2C_0:
 201             CPGSTBCR9 &= ~(0x80);
 202             break;
 203         case I2C_1:
 204             CPGSTBCR9 &= ~(0x40);
 205             break;
 206         case I2C_2:
 207             CPGSTBCR9 &= ~(0x20);
 208             break;
 209         case I2C_3:
 210             CPGSTBCR9 &= ~(0x10);
 211             break;
 212     }
 213     dummy = CPGSTBCR9;
 214 }
 215
 216 void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
 217     /* determine the I2C to use */
 218     I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
 219     I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
 220     obj->i2c = pinmap_merge(i2c_sda, i2c_scl);
 221     MBED_ASSERT((int)obj->i2c != NC);
 222
 223     /* enable power */
 224     i2c_power_enable(obj);
 225
 226     /* set default frequency at 100k */
 227     i2c_frequency(obj, 100000);
 228
 229     pinmap_pinout(sda, PinMap_I2C_SDA);
 230     pinmap_pinout(scl, PinMap_I2C_SCL);
 231
 232     obj->last_stop_flag = 1;
 233 }
 234
 235 inline int i2c_start(i2c_t *obj) {
 236     int timeout = 0;
 237
 238     while (REG(CR2.UINT32) & CR2_BBSY) {
 239         timeout ++;
 240         if (timeout >= obj->bbsy_wait_cnt) {
 241             break;
 242         }
 243     }
 244     /* Start Condition */
 245     REG(CR2.UINT8[0]) |= CR2_ST;
 246
 247     return 0;
 248 }
 249
 250 static inline int i2c_restart(i2c_t *obj) {
 251     /* SR2.START = 0 */
 252     REG(SR2.UINT32) &= ~SR2_START;
 253     /* ReStart condition */
 254     REG(CR2.UINT32) |= CR2_RS;
 255
 256     return 0;
 257 }
 258
 259 inline int i2c_stop(i2c_t *obj) {
 260     /* SR2.STOP = 0 */
 261     REG(SR2.UINT32) &= ~SR2_STOP;
 262     /* Stop condition */
 263     REG(CR2.UINT32) |= CR2_SP;
 264
 265     return 0;
 266 }
 267
 268 static void i2c_set_err_noslave(i2c_t *obj) {
 269     (void)i2c_stop(obj);
 270     (void)i2c_wait_STOP(obj);
 271     i2c_set_SR2_NACKF_STOP(obj);
 272     obj->last_stop_flag = 1;
 273 }
 274
 275 static inline int i2c_do_write(i2c_t *obj, int value) {
 276     int timeout = 0;
 277
 278     if (!(i2c_status(obj) & SR2_NACKF)) {
 279         /* RIICnSR2.NACKF=0 */
 280         /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
 281         while (!(i2c_status(obj) & SR2_TDRE)) {
 282             /* RIICnSR2.TDRE=0 */
 283             timeout ++;
 284             if (timeout >= WAIT_TIMEOUT) {
 285                 return -1;
 286             }
 287             if (i2c_status(obj) & SR2_NACKF) {
 288                 /* RIICnSR2.NACKF=1 */
 289                 return -1;
 290             }
 291         }
 292         /* write the data */
 293         REG(DRT.UINT32) = value;
 294     } else {
 295         return -1;
 296     }
 297
 298     return 0;
 299 }
 300
 301 static inline int i2c_read_address_write(i2c_t *obj, int value) {
 302     int status;
 303
 304     status = i2c_wait_TDRE(obj);
 305     if (status == 0) {
 306         /* write the data */
 307         REG(DRT.UINT32) = value;
 308     }
 309
 310     return status;
 311
 312 }
 313
 314 static inline int i2c_do_read(i2c_t *obj, int last) {
 315     if (last == 2) {
 316         /* this time is befor last byte read */
 317         /* Set MR3 WAIT bit is 1 */;
 318         REG(MR3.UINT32) |= MR3_WAIT;
 319     } else if (last == 1) {
 320         i2c_set_MR3_NACK(obj);
 321     } else {
 322         i2c_set_MR3_ACK(obj);
 323     }
 324
 325     /* return the data */
 326     return (REG(DRR.UINT32) & 0xFF);
 327 }
 328
 329 void i2c_frequency(i2c_t *obj, int hz) {
 330     float64_t pclk_val;
 331     float64_t wait_utime;
 332     volatile float64_t bps;
 333     volatile float64_t L_time;         /* H Width period */
 334     volatile float64_t H_time;         /* L Width period */
 335     uint32_t tmp_L_width;
 336     uint32_t tmp_H_width;
 337     uint32_t remainder;
 338     uint32_t wk_cks = 0;
 339
 340     /* set PCLK */
 341     if (false == RZ_A1_IsClockMode0()) {
 342         pclk_val = (float64_t)CM1_RENESAS_RZ_A1_P0_CLK;
 343     } else {
 344         pclk_val = (float64_t)CM0_RENESAS_RZ_A1_P0_CLK;
 345     }
 346
 347     /* Min 10kHz, Max 400kHz */
 348     if (hz < 10000) {
 349         bps = 10000;
 350     } else if (hz > 400000) {
 351         bps = 400000;
 352     } else {
 353         bps = (float64_t)hz;
 354     }
 355
 356     /* Calculation L width time */
 357     L_time = (1 / (2 * bps));   /* Harf period of frequency */
 358     H_time = L_time;
 359
 360     /* Check I2C mode of Speed */
 361     if (bps > 100000) {
 362         /* Fast-mode */
 363         L_time -= 102E-9;    /* Falling time of SCL clock. */
 364         H_time -= 138E-9;    /* Rising time of SCL clock. */
 365         /* Check L wideth */
 366         if (L_time < 1.3E-6) {
 367             /* Wnen L width less than 1.3us */
 368             /* Subtract Rise up and down time for SCL from H/L width */
 369             L_time = 1.3E-6;
 370             H_time = (1 / bps) - L_time - 138E-9 - 102E-9;
 371         }
 372     }
 373
 374     tmp_L_width   = (uint32_t)(L_time * pclk_val * 10);
 375     tmp_L_width >>= 1;
 376     wk_cks++;
 377     while (tmp_L_width >= 341) {
 378         tmp_L_width >>= 1;
 379         wk_cks++;
 380     }
 381     remainder   = tmp_L_width % 10;
 382     tmp_L_width = ((tmp_L_width + 9) / 10) - 3;       /* carry */
 383
 384     tmp_H_width   = (uint32_t)(H_time * pclk_val * 10);
 385     tmp_H_width >>= wk_cks;
 386     if (remainder == 0) {
 387         tmp_H_width   = ((tmp_H_width + 9) / 10) - 3; /* carry */
 388     } else {
 389         remainder    += tmp_H_width % 10;
 390         tmp_H_width   = (tmp_H_width / 10) - 3;
 391         if (remainder > 10) {
 392             tmp_H_width += 1;                         /* fine adjustment */
 393         }
 394     }
 395     /* timeout of BBSY bit is minimum low width by frequency */
 396     /* so timeout calculates "(low width) * 2" by frequency */
 397     wait_utime = (L_time * 2) * 1000000;
 398     /* 1 wait of BBSY bit is about 0.3us. if it's below 0.3us, wait count is set as 1. */
 399     if (wait_utime <= 0.3) {
 400         obj->bbsy_wait_cnt = 1;
 401     } else {
 402         obj->bbsy_wait_cnt = (int)(wait_utime / 0.3);
 403     }
 404
 405
 406     /* I2C Rate */
 407     obj->pclk_bit  = (uint8_t)(0x10 * wk_cks);        /* P_phi / xx */
 408     obj->width_low = (uint8_t)(tmp_L_width | 0x000000E0);
 409     obj->width_hi  = (uint8_t)(tmp_H_width | 0x000000E0);
 410
 411     /* full reset */
 412     i2c_reg_reset(obj);
 413 }
 414
 415 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
 416     int count = 0;
 417     int status;
 418     int value;
 419     volatile uint32_t work_reg = 0;
 420
 421     if(length <= 0) {
 422         return 0;
 423     }
 424     i2c_set_MR3_ACK(obj);
 425     /* There is a STOP condition for last processing */
 426     if (obj->last_stop_flag != 0) {
 427         status = i2c_start(obj);
 428         if (status != 0) {
 429             i2c_set_err_noslave(obj);
 430             return I2C_ERROR_BUS_BUSY;
 431         }
 432     }
 433     obj->last_stop_flag = stop;
 434     /*  Send Slave address */
 435     status = i2c_read_address_write(obj, (address | 0x01));
 436     if (status != 0) {
 437         i2c_set_err_noslave(obj);
 438         return I2C_ERROR_NO_SLAVE;
 439     }
 440     /* wait RDRF */
 441     status = i2c_wait_RDRF(obj);
 442     /* check ACK/NACK */
 443     if ((status != 0) || (REG(SR2.UINT32) & SR2_NACKF == 1)) {
 444         /* Slave sends NACK */
 445         i2c_stop(obj);
 446         /* dummy read */
 447         value = REG(DRR.UINT32);
 448         (void)i2c_wait_STOP(obj);
 449         i2c_set_SR2_NACKF_STOP(obj);
 450         obj->last_stop_flag = 1;
 451         return I2C_ERROR_NO_SLAVE;
 452     }
 453     /* Read in all except last byte */
 454     if (length > 2) {
 455         /* dummy read */
 456         value = REG(DRR.UINT32);
 457         for (count = 0; count < (length - 1); count++) {
 458             /* wait for it to arrive */
 459             status = i2c_wait_RDRF(obj);
 460             if (status != 0) {
 461                 i2c_set_err_noslave(obj);
 462                 return I2C_ERROR_NO_SLAVE;
 463             }
 464             /* Recieve the data */
 465             if (count == (length - 2)) {
 466                 value = i2c_do_read(obj, 1);
 467             } else if ((length >= 3) && (count == (length - 3))) {
 468                 value = i2c_do_read(obj, 2);
 469             } else {
 470                 value = i2c_do_read(obj, 0);
 471             }
 472             data[count] = (char)value;
 473         }
 474     } else if (length == 2) {
 475         /* Set MR3 WATI bit is 1 */
 476         REG(MR3.UINT32) |= MR3_WAIT;
 477         /* dummy read */
 478         value = REG(DRR.UINT32);
 479         /* wait for it to arrive */
 480         status = i2c_wait_RDRF(obj);
 481         if (status != 0) {
 482             i2c_set_err_noslave(obj);
 483             return I2C_ERROR_NO_SLAVE;
 484         }
 485         i2c_set_MR3_NACK(obj);
 486         data[count] = (char)REG(DRR.UINT32);
 487         count++;
 488     } else {
 489         /* length == 1 */
 490         /* Set MR3 WATI bit is 1 */;
 491         REG(MR3.UINT32) |=  MR3_WAIT;
 492         i2c_set_MR3_NACK(obj);
 493         /* dummy read */
 494         value = REG(DRR.UINT32);
 495     }
 496     /* wait for it to arrive */
 497     status = i2c_wait_RDRF(obj);
 498     if (status != 0) {
 499         i2c_set_err_noslave(obj);
 500         return I2C_ERROR_NO_SLAVE;
 501     }
 502
 503     /* If not repeated start, send stop. */
 504     if (stop) {
 505         (void)i2c_stop(obj);
 506         /* RIICnDRR read */
 507         value = REG(DRR.UINT32) & 0xFF;
 508         data[count] = (char)value;
 509         /* RIICnMR3.WAIT = 0 */
 510         REG(MR3.UINT32) &= ~MR3_WAIT;
 511         (void)i2c_wait_STOP(obj);
 512         i2c_set_SR2_NACKF_STOP(obj);
 513     } else {
 514         (void)i2c_restart(obj);
 515         /* RIICnDRR read */
 516         value = REG(DRR.UINT32) & 0xFF;
 517         data[count] = (char)value;
 518         /* RIICnMR3.WAIT = 0 */
 519         REG(MR3.UINT32) &= ~MR3_WAIT;
 520         (void)i2c_wait_START(obj);
 521         /* SR2.START = 0 */
 522         REG(SR2.UINT32) &= ~SR2_START;
 523     }
 524
 525     return length;
 526 }
 527
 528 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
 529     int cnt;
 530     int status;
 531
 532     if(length <= 0) {
 533         return 0;
 534     }
 535
 536     /* There is a STOP condition for last processing */
 537     if (obj->last_stop_flag != 0) {
 538         status = i2c_start(obj);
 539         if (status != 0) {
 540             i2c_set_err_noslave(obj);
 541             return I2C_ERROR_BUS_BUSY;
 542         }
 543     }
 544     obj->last_stop_flag = stop;
 545     /*  Send Slave address */
 546     status = i2c_do_write(obj, address);
 547     if (status != 0) {
 548         i2c_set_err_noslave(obj);
 549         return I2C_ERROR_NO_SLAVE;
 550     }
 551     /* Send Write data */
 552     for (cnt=0; cnt<length; cnt++) {
 553         status = i2c_do_write(obj, data[cnt]);
 554         if(status != 0) {
 555             i2c_set_err_noslave(obj);
 556             return cnt;
 557         }
 558     }
 559     /* Wait send end */
 560     status = i2c_wait_TEND(obj);
 561     if (status != 0) {
 562         i2c_set_err_noslave(obj);
 563         return I2C_ERROR_NO_SLAVE;
 564     }
 565     /* If not repeated start, send stop. */
 566     if (stop) {
 567         (void)i2c_stop(obj);
 568         (void)i2c_wait_STOP(obj);
 569         i2c_set_SR2_NACKF_STOP(obj);
 570     } else {
 571         (void)i2c_restart(obj);
 572         (void)i2c_wait_START(obj);
 573         /* SR2.START = 0 */
 574         REG(SR2.UINT32) &= ~SR2_START;
 575
 576     }
 577
 578     return length;
 579 }
 580
 581 void i2c_reset(i2c_t *obj) {
 582     i2c_stop(obj);
 583     (void)i2c_wait_STOP(obj);
 584     i2c_set_SR2_NACKF_STOP(obj);
 585 }
 586
 587 int i2c_byte_read(i2c_t *obj, int last) {
 588     int status;
 589
 590     /* wait for it to arrive */
 591     status = i2c_wait_RDRF(obj);
 592     if (status != 0) {
 593         i2c_set_err_noslave(obj);
 594         return I2C_ERROR_NO_SLAVE;
 595     }
 596
 597     return (i2c_do_read(obj, last));
 598 }
 599
 600 int i2c_byte_write(i2c_t *obj, int data) {
 601     int ack;
 602     int status;
 603
 604     status = i2c_do_write(obj, (data & 0xFF));
 605     if (status != 0) {
 606         i2c_set_err_noslave(obj);
 607         ack = 0;
 608     } else {
 609         ack = 1;
 610     }
 611
 612     return ack;
 613 }
 614
 615 void i2c_slave_mode(i2c_t *obj, int enable_slave) {
 616     if (enable_slave != 0) {
 617         REG(SER.UINT32) |= SER_SAR0E;   // only slave addr 0 is enabled
 618     } else {
 619         REG(SER.UINT32) &= ~SER_SAR0E;  // no slave addr enabled
 620     }
 621 }
 622
 623 int i2c_slave_receive(i2c_t *obj) {
 624     int status;
 625     int retval;
 626
 627     status = REG(SR1.UINT8[0]) & SR1_AAS0;
 628     status |= (REG(CR2.UINT8[0]) & CR2_TRS) >> 4;
 629
 630     switch(status) {
 631         case 0x01:
 632             /* the master is writing to this slave */
 633             retval = 3;
 634             break;
 635         case 0x02:
 636             /* the master is writing to all slave  */
 637             retval = 2;
 638             break;
 639         case 0x03:
 640             /* the master has requested a read from this slave */
 641             retval = 1;
 642             break;
 643         default :
 644             /* no data */
 645             retval = 0;
 646             break;
 647     }
 648
 649     return retval;
 650 }
 651
 652 int i2c_slave_read(i2c_t *obj, char *data, int length) {
 653     int timeout = 0;
 654     int count;
 655     int break_flg = 0;
 656
 657     if(length <= 0) {
 658         return 0;
 659     }
 660     for (count = 0; ((count < (length + 1)) && (break_flg == 0)); count++) {
 661         /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
 662         while ((i2c_status(obj) & SR2_STOP) || (!(i2c_status(obj) & SR2_RDRF))) {
 663             /* RIICnSR2.STOP = 1 or RIICnSR2.RDRF = 0 */
 664             if (i2c_status(obj) & SR2_STOP) {
 665                 /* RIICnSR2.STOP = 1 */
 666                 break_flg = 1;
 667                 break;
 668             }
 669             timeout ++;
 670             if (timeout >= WAIT_TIMEOUT) {
 671                 return -1;
 672             }
 673         }
 674         if (break_flg == 0) {
 675             if (count == 0) {
 676                 /* dummy read */
 677                 (void)REG(DRR.UINT32);
 678             } else {
 679                 data[count - 1] = (char)(REG(DRR.UINT32) & 0xFF);
 680             }
 681         }
 682     }
 683     if (break_flg == 0) {
 684         (void)i2c_wait_STOP(obj);
 685     } else {
 686         if (i2c_status(obj) & SR2_RDRF) {
 687             if (count <= 1) {
 688                 /* fail safe */
 689                 /* dummy read */
 690                 (void)REG(DRR.UINT32);
 691             } else {
 692                 data[count - 2] = (char)(REG(DRR.UINT32) & 0xFF);
 693             }
 694         }
 695     }
 696     /* SR2.STOP = 0 */
 697     REG(SR2.UINT32) &= ~SR2_STOP;
 698
 699     return (count - 1);
 700 }
 701
 702 int i2c_slave_write(i2c_t *obj, const char *data, int length) {
 703     int count = 0;
 704     int status = 0;
 705
 706     if(length <= 0) {
 707         return 0;
 708     }
 709
 710     while ((count < length) && (status == 0)) {
 711         status = i2c_do_write(obj, data[count]);
 712         count++;
 713     }
 714     if (status == 0) {
 715         /* Wait send end */
 716         status = i2c_wait_TEND(obj);
 717         if (status != 0) {
 718             i2c_set_err_noslave(obj);
 719             return 0;
 720         }
 721     }
 722     /* dummy read */
 723     (void)REG(DRR.UINT32);
 724     (void)i2c_wait_STOP(obj);
 725     i2c_set_SR2_NACKF_STOP(obj);
 726
 727     return count;
 728 }
 729
 730 void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
 731     REG(SAR0.UINT32) = address & 0xfffffffe;
 732 }