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[tmk_keyboard.git] / tool / mbed / mbed-sdk / libraries / mbed / targets / hal / TARGET_STM / TARGET_STM32F3 / gpio_irq_api.c
1 /* mbed Microcontroller Library
2 *******************************************************************************
3 * Copyright (c) 2014, STMicroelectronics
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright notice,
10 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *******************************************************************************
29 */
30 #include <stddef.h>
31 #include "cmsis.h"
32 #include "gpio_irq_api.h"
33 #include "pinmap.h"
34 #include "mbed_error.h"
35
36 #define EDGE_NONE (0)
37 #define EDGE_RISE (1)
38 #define EDGE_FALL (2)
39 #define EDGE_BOTH (3)
40
41 // Number of EXTI irq vectors (EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5_9, EXTI10_15)
42 #define CHANNEL_NUM (7)
43
44 // Max pins for one line (max with EXTI10_15)
45 #define MAX_PIN_LINE (6)
46
47 typedef struct gpio_channel {
48 uint32_t pin_mask; // bitmask representing which pins are configured for receiving interrupts
49 uint32_t channel_ids[MAX_PIN_LINE]; // mbed "gpio_irq_t gpio_irq" field of instance
50 uint32_t channel_gpio[MAX_PIN_LINE]; // base address of gpio port group
51 uint32_t channel_pin[MAX_PIN_LINE]; // pin number in port group
52 } gpio_channel_t;
53
54 static gpio_channel_t channels[CHANNEL_NUM] = {
55 {.pin_mask = 0},
56 {.pin_mask = 0},
57 {.pin_mask = 0},
58 {.pin_mask = 0},
59 {.pin_mask = 0},
60 {.pin_mask = 0},
61 {.pin_mask = 0}
62 };
63
64 // Used to return the index for channels array.
65 static uint32_t pin_base_nr[16] = {
66 // EXTI0
67 0, // pin 0
68 // EXTI1
69 0, // pin 1
70 // EXTI2
71 0, // pin 2
72 // EXTI3
73 0, // pin 3
74 // EXTI4
75 0, // pin 4
76 // EXTI5_9
77 0, // pin 5
78 1, // pin 6
79 2, // pin 7
80 3, // pin 8
81 4, // pin 9
82 // EXTI10_15
83 0, // pin 10
84 1, // pin 11
85 2, // pin 12
86 3, // pin 13
87 4, // pin 14
88 5 // pin 15
89 };
90
91 static gpio_irq_handler irq_handler;
92
93 static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line)
94 {
95 gpio_channel_t *gpio_channel = &channels[irq_index];
96 uint32_t gpio_idx;
97
98 for (gpio_idx = 0; gpio_idx < max_num_pin_line; gpio_idx++) {
99 uint32_t current_mask = (1 << gpio_idx);
100
101 if (gpio_channel->pin_mask & current_mask) {
102 // Retrieve the gpio and pin that generate the irq
103 GPIO_TypeDef *gpio = (GPIO_TypeDef *)(gpio_channel->channel_gpio[gpio_idx]);
104 uint32_t pin = (uint32_t)(1 << (gpio_channel->channel_pin[gpio_idx]));
105
106 // Clear interrupt flag
107 if (__HAL_GPIO_EXTI_GET_FLAG(pin) != RESET) {
108 __HAL_GPIO_EXTI_CLEAR_FLAG(pin);
109
110 if (gpio_channel->channel_ids[gpio_idx] == 0) continue;
111
112 // Check which edge has generated the irq
113 if ((gpio->IDR & pin) == 0) {
114 irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_FALL);
115 } else {
116 irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_RISE);
117 }
118 }
119 }
120 }
121 }
122
123 // EXTI line 0
124 static void gpio_irq0(void)
125 {
126 handle_interrupt_in(0, 1);
127 }
128
129 // EXTI line 1
130 static void gpio_irq1(void)
131 {
132 handle_interrupt_in(1, 1);
133 }
134
135 // EXTI line 2
136 static void gpio_irq2(void)
137 {
138 handle_interrupt_in(2, 1);
139 }
140
141 // EXTI line 3
142 static void gpio_irq3(void)
143 {
144 handle_interrupt_in(3, 1);
145 }
146
147 // EXTI line 4
148 static void gpio_irq4(void)
149 {
150 handle_interrupt_in(4, 1);
151 }
152
153 // EXTI lines 5 to 9
154 static void gpio_irq5(void)
155 {
156 handle_interrupt_in(5, 5);
157 }
158
159 // EXTI lines 10 to 15
160 static void gpio_irq6(void)
161 {
162 handle_interrupt_in(6, 6);
163 }
164
165 extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
166
167 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
168 {
169 IRQn_Type irq_n = (IRQn_Type)0;
170 uint32_t vector = 0;
171 uint32_t irq_index;
172 gpio_channel_t *gpio_channel;
173 uint32_t gpio_idx;
174
175 if (pin == NC) return -1;
176
177 uint32_t port_index = STM_PORT(pin);
178 uint32_t pin_index = STM_PIN(pin);
179
180 // Select irq number and interrupt routine
181 switch (pin_index) {
182 case 0:
183 irq_n = EXTI0_IRQn;
184 vector = (uint32_t)&gpio_irq0;
185 irq_index = 0;
186 break;
187 case 1:
188 irq_n = EXTI1_IRQn;
189 vector = (uint32_t)&gpio_irq1;
190 irq_index = 1;
191 break;
192 case 2:
193 irq_n = EXTI2_TSC_IRQn;
194 vector = (uint32_t)&gpio_irq2;
195 irq_index = 2;
196 break;
197 case 3:
198 irq_n = EXTI3_IRQn;
199 vector = (uint32_t)&gpio_irq3;
200 irq_index = 3;
201 break;
202 case 4:
203 irq_n = EXTI4_IRQn;
204 vector = (uint32_t)&gpio_irq4;
205 irq_index = 4;
206 break;
207 case 5:
208 case 6:
209 case 7:
210 case 8:
211 case 9:
212 irq_n = EXTI9_5_IRQn;
213 vector = (uint32_t)&gpio_irq5;
214 irq_index = 5;
215 break;
216 case 10:
217 case 11:
218 case 12:
219 case 13:
220 case 14:
221 case 15:
222 irq_n = EXTI15_10_IRQn;
223 vector = (uint32_t)&gpio_irq6;
224 irq_index = 6;
225 break;
226 default:
227 error("InterruptIn error: pin not supported.\n");
228 return -1;
229 }
230
231 // Enable GPIO clock
232 uint32_t gpio_add = Set_GPIO_Clock(port_index);
233
234 // Configure GPIO
235 pin_function(pin, STM_PIN_DATA(STM_MODE_IT_FALLING, GPIO_NOPULL, 0));
236
237 // Enable EXTI interrupt
238 NVIC_SetVector(irq_n, vector);
239 NVIC_EnableIRQ(irq_n);
240
241 // Save informations for future use
242 obj->irq_n = irq_n;
243 obj->irq_index = irq_index;
244 obj->event = EDGE_NONE;
245 obj->pin = pin;
246
247 gpio_channel = &channels[irq_index];
248 gpio_idx = pin_base_nr[pin_index];
249 gpio_channel->pin_mask |= (1 << gpio_idx);
250 gpio_channel->channel_ids[gpio_idx] = id;
251 gpio_channel->channel_gpio[gpio_idx] = gpio_add;
252 gpio_channel->channel_pin[gpio_idx] = pin_index;
253
254 irq_handler = handler;
255
256 return 0;
257 }
258
259 void gpio_irq_free(gpio_irq_t *obj)
260 {
261 gpio_channel_t *gpio_channel = &channels[obj->irq_index];
262 uint32_t pin_index = STM_PIN(obj->pin);
263 uint32_t gpio_idx = pin_base_nr[pin_index];
264
265 gpio_channel->pin_mask &= ~(1 << gpio_idx);
266 gpio_channel->channel_ids[gpio_idx] = 0;
267 gpio_channel->channel_gpio[gpio_idx] = 0;
268 gpio_channel->channel_pin[gpio_idx] = 0;
269
270 // Disable EXTI line
271 pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
272 obj->event = EDGE_NONE;
273 }
274
275 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
276 {
277 uint32_t mode = STM_MODE_IT_EVT_RESET;
278 uint32_t pull = GPIO_NOPULL;
279
280 if (enable) {
281 if (event == IRQ_RISE) {
282 if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) {
283 mode = STM_MODE_IT_RISING_FALLING;
284 obj->event = EDGE_BOTH;
285 } else { // NONE or RISE
286 mode = STM_MODE_IT_RISING;
287 obj->event = EDGE_RISE;
288 }
289 }
290 if (event == IRQ_FALL) {
291 if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) {
292 mode = STM_MODE_IT_RISING_FALLING;
293 obj->event = EDGE_BOTH;
294 } else { // NONE or FALL
295 mode = STM_MODE_IT_FALLING;
296 obj->event = EDGE_FALL;
297 }
298 }
299 } else { // Disable
300 if (event == IRQ_RISE) {
301 if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) {
302 mode = STM_MODE_IT_FALLING;
303 obj->event = EDGE_FALL;
304 } else { // NONE or RISE
305 mode = STM_MODE_IT_EVT_RESET;
306 obj->event = EDGE_NONE;
307 }
308 }
309 if (event == IRQ_FALL) {
310 if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) {
311 mode = STM_MODE_IT_RISING;
312 obj->event = EDGE_RISE;
313 } else { // NONE or FALL
314 mode = STM_MODE_IT_EVT_RESET;
315 obj->event = EDGE_NONE;
316 }
317 }
318 }
319
320 pin_function(obj->pin, STM_PIN_DATA(mode, pull, 0));
321 }
322
323 void gpio_irq_enable(gpio_irq_t *obj)
324 {
325 NVIC_EnableIRQ(obj->irq_n);
326 }
327
328 void gpio_irq_disable(gpio_irq_t *obj)
329 {
330 NVIC_DisableIRQ(obj->irq_n);
331 obj->event = EDGE_NONE;
332 }
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