tool/mbed/mbed-sdk/libraries/net/eth/lwip-eth/arch/TARGET_Freescale/hardware_init_MK64F12.c

   1 /*
   2  * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without modification,
   6  * are permitted provided that the following conditions are met:
   7  *
   8  * o Redistributions of source code must retain the above copyright notice, this list
   9  *   of conditions and the following disclaimer.
  10  *
  11  * o Redistributions in binary form must reproduce the above copyright notice, this
  12  *   list of conditions and the following disclaimer in the documentation and/or
  13  *   other materials provided with the distribution.
  14  *
  15  * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  16  *   contributors may be used to endorse or promote products derived from this
  17  *   software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  21  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  22  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  23  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  25  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  26  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  28  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29  */
  30
  31 #include "fsl_port_hal.h"
  32 #include "fsl_clock_manager.h"
  33 #include "fsl_device_registers.h"
  34 #include "fsl_sim_hal.h"
  35
  36 /*******************************************************************************
  37  * Code
  38  ******************************************************************************/
  39 void k64f_init_eth_hardware(void)
  40 {
  41     uint8_t count;
  42
  43     /* Disable the mpu*/
  44     BW_MPU_CESR_VLD(MPU_BASE, 0);
  45
  46     /* Open POTR clock gate*/
  47     for (count = 0; count < HW_PORT_INSTANCE_COUNT; count++)
  48     {
  49         CLOCK_SYS_EnablePortClock(count);
  50     }
  51
  52     /* Configure gpio*/
  53     PORT_HAL_SetMuxMode(PORTA_BASE, 12, kPortMuxAlt4);  /*!< ENET RMII0_RXD1/MII0_RXD1*/
  54     PORT_HAL_SetMuxMode(PORTA_BASE, 13, kPortMuxAlt4);  /*!< ENET RMII0_RXD0/MII0_RXD0*/
  55     PORT_HAL_SetMuxMode(PORTA_BASE, 14, kPortMuxAlt4);  /*!< ENET RMII0_CRS_DV/MII0_RXDV*/
  56     PORT_HAL_SetMuxMode(PORTA_BASE, 15, kPortMuxAlt4);  /*!< ENET RMII0_TXEN/MII0_TXEN*/
  57     PORT_HAL_SetMuxMode(PORTA_BASE, 16, kPortMuxAlt4);  /*!< ENET RMII0_TXD0/MII0_TXD0*/
  58     PORT_HAL_SetMuxMode(PORTA_BASE, 17, kPortMuxAlt4);  /*!< ENET RMII0_TXD01/MII0_TXD1*/
  59     PORT_HAL_SetMuxMode(PORTB_BASE, 0, kPortMuxAlt4);   /*!< ENET RMII0_MDIO/MII0_MDIO*/
  60     PORT_HAL_SetOpenDrainCmd(PORTB_BASE,0, true);   /*!< ENET RMII0_MDC/MII0_MDC*/
  61
  62     // Added for FRDM-K64F
  63     PORT_HAL_SetPullMode(PORTB_BASE, 0, kPortPullUp);
  64     PORT_HAL_SetPullCmd(PORTB_BASE, 0, true);
  65
  66     PORT_HAL_SetMuxMode(PORTB_BASE, 1, kPortMuxAlt4);
  67     /* Configure GPIO for MII interface */
  68     PORT_HAL_SetMuxMode(PORTA_BASE, 9, kPortMuxAlt4);   /*!< ENET MII0_RXD3*/
  69     PORT_HAL_SetMuxMode(PORTA_BASE, 10, kPortMuxAlt4);   /*!< ENET MII0_RXD2*/
  70     PORT_HAL_SetMuxMode(PORTA_BASE, 11, kPortMuxAlt4);   /*!< ENET MII0_RXCLK*/
  71     PORT_HAL_SetMuxMode(PORTA_BASE, 24, kPortMuxAlt4);   /*!< ENET MII0_TXD2*/
  72     PORT_HAL_SetMuxMode(PORTA_BASE, 25, kPortMuxAlt4);   /*!< ENET MII0_TXCLK*/
  73     PORT_HAL_SetMuxMode(PORTA_BASE, 26, kPortMuxAlt4);   /*!< ENET MII0_TXD3*/
  74     PORT_HAL_SetMuxMode(PORTA_BASE, 27, kPortMuxAlt4);   /*!< ENET MII0_CRS*/
  75     PORT_HAL_SetMuxMode(PORTA_BASE, 28, kPortMuxAlt4);   /*!< ENET MII0_TXER*/
  76     PORT_HAL_SetMuxMode(PORTA_BASE, 29, kPortMuxAlt4);   /*!< ENET MII0_COL*/
  77 #if FSL_FEATURE_ENET_SUPPORT_PTP
  78     PORT_HAL_SetMuxMode(PORTC_BASE, (16 + ENET_TIMER_CHANNEL_NUM), kPortMuxAlt4); /* ENET ENET0_1588_TMR0*/
  79     PORT_HAL_SetDriveStrengthMode(PORTC_BASE, (16 + ENET_TIMER_CHANNEL_NUM), kPortHighDriveStrength);
  80 #endif
  81
  82     /* Open ENET clock gate*/
  83     CLOCK_SYS_EnableEnetClock( 0U);
  84
  85     /* Select the ptp timer  outclk*/
  86     CLOCK_HAL_SetSource(g_simBaseAddr[0], kClockTimeSrc, 2);
  87 }
  88
  89 /*******************************************************************************
  90  * EOF
  91  ******************************************************************************/
  92
  93