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[tmk_keyboard.git] / tool / mbed / mbed-sdk / libraries / net / eth / lwip-eth / arch / TARGET_NXP / lpc17xx_emac.h
1 /**********************************************************************
2 * $Id$ lpc17xx_emac.h 2010-05-21
3 *//**
4 * @file lpc17xx_emac.h
5 * @brief Contains all macro definitions and function prototypes
6 * support for Ethernet MAC firmware library on LPC17xx
7 * @version 2.0
8 * @date 21. May. 2010
9 * @author NXP MCU SW Application Team
10 *
11 * Copyright(C) 2010, NXP Semiconductor
12 * All rights reserved.
13 *
14 ***********************************************************************
15 * Software that is described herein is for illustrative purposes only
16 * which provides customers with programming information regarding the
17 * products. This software is supplied "AS IS" without any warranties.
18 * NXP Semiconductors assumes no responsibility or liability for the
19 * use of the software, conveys no license or title under any patent,
20 * copyright, or mask work right to the product. NXP Semiconductors
21 * reserves the right to make changes in the software without
22 * notification. NXP Semiconductors also make no representation or
23 * warranty that such application will be suitable for the specified
24 * use without further testing or modification.
25 **********************************************************************/
26
27 /* Peripheral group ----------------------------------------------------------- */
28 /** @defgroup EMAC EMAC (Ethernet Media Access Controller)
29 * @ingroup LPC1700CMSIS_FwLib_Drivers
30 * @{
31 */
32
33 #ifndef LPC17XX_EMAC_H_
34 #define LPC17XX_EMAC_H_
35
36 /* Includes ------------------------------------------------------------------- */
37 #include "cmsis.h"
38
39 #ifdef __cplusplus
40 extern "C"
41 {
42 #endif
43
44 #define MCB_LPC_1768
45 //#define IAR_LPC_1768
46
47 /* Public Macros -------------------------------------------------------------- */
48 /** @defgroup EMAC_Public_Macros EMAC Public Macros
49 * @{
50 */
51
52
53 /* EMAC PHY status type definitions */
54 #define EMAC_PHY_STAT_LINK (0) /**< Link Status */
55 #define EMAC_PHY_STAT_SPEED (1) /**< Speed Status */
56 #define EMAC_PHY_STAT_DUP (2) /**< Duplex Status */
57
58 /* EMAC PHY device Speed definitions */
59 #define EMAC_MODE_AUTO (0) /**< Auto-negotiation mode */
60 #define EMAC_MODE_10M_FULL (1) /**< 10Mbps FullDuplex mode */
61 #define EMAC_MODE_10M_HALF (2) /**< 10Mbps HalfDuplex mode */
62 #define EMAC_MODE_100M_FULL (3) /**< 100Mbps FullDuplex mode */
63 #define EMAC_MODE_100M_HALF (4) /**< 100Mbps HalfDuplex mode */
64
65 /**
66 * @}
67 */
68 /* Private Macros ------------------------------------------------------------- */
69 /** @defgroup EMAC_Private_Macros EMAC Private Macros
70 * @{
71 */
72
73
74 /* EMAC Memory Buffer configuration for 16K Ethernet RAM */
75 #define EMAC_NUM_RX_FRAG 4 /**< Num.of RX Fragments 4*1536= 6.0kB */
76 #define EMAC_NUM_TX_FRAG 3 /**< Num.of TX Fragments 3*1536= 4.6kB */
77 #define EMAC_ETH_MAX_FLEN 1536 /**< Max. Ethernet Frame Size */
78 #define EMAC_TX_FRAME_TOUT 0x00100000 /**< Frame Transmit timeout count */
79
80 /* --------------------- BIT DEFINITIONS -------------------------------------- */
81 /*********************************************************************//**
82 * Macro defines for MAC Configuration Register 1
83 **********************************************************************/
84 #define EMAC_MAC1_REC_EN 0x00000001 /**< Receive Enable */
85 #define EMAC_MAC1_PASS_ALL 0x00000002 /**< Pass All Receive Frames */
86 #define EMAC_MAC1_RX_FLOWC 0x00000004 /**< RX Flow Control */
87 #define EMAC_MAC1_TX_FLOWC 0x00000008 /**< TX Flow Control */
88 #define EMAC_MAC1_LOOPB 0x00000010 /**< Loop Back Mode */
89 #define EMAC_MAC1_RES_TX 0x00000100 /**< Reset TX Logic */
90 #define EMAC_MAC1_RES_MCS_TX 0x00000200 /**< Reset MAC TX Control Sublayer */
91 #define EMAC_MAC1_RES_RX 0x00000400 /**< Reset RX Logic */
92 #define EMAC_MAC1_RES_MCS_RX 0x00000800 /**< Reset MAC RX Control Sublayer */
93 #define EMAC_MAC1_SIM_RES 0x00004000 /**< Simulation Reset */
94 #define EMAC_MAC1_SOFT_RES 0x00008000 /**< Soft Reset MAC */
95
96 /*********************************************************************//**
97 * Macro defines for MAC Configuration Register 2
98 **********************************************************************/
99 #define EMAC_MAC2_FULL_DUP 0x00000001 /**< Full-Duplex Mode */
100 #define EMAC_MAC2_FRM_LEN_CHK 0x00000002 /**< Frame Length Checking */
101 #define EMAC_MAC2_HUGE_FRM_EN 0x00000004 /**< Huge Frame Enable */
102 #define EMAC_MAC2_DLY_CRC 0x00000008 /**< Delayed CRC Mode */
103 #define EMAC_MAC2_CRC_EN 0x00000010 /**< Append CRC to every Frame */
104 #define EMAC_MAC2_PAD_EN 0x00000020 /**< Pad all Short Frames */
105 #define EMAC_MAC2_VLAN_PAD_EN 0x00000040 /**< VLAN Pad Enable */
106 #define EMAC_MAC2_ADET_PAD_EN 0x00000080 /**< Auto Detect Pad Enable */
107 #define EMAC_MAC2_PPREAM_ENF 0x00000100 /**< Pure Preamble Enforcement */
108 #define EMAC_MAC2_LPREAM_ENF 0x00000200 /**< Long Preamble Enforcement */
109 #define EMAC_MAC2_NO_BACKOFF 0x00001000 /**< No Backoff Algorithm */
110 #define EMAC_MAC2_BACK_PRESSURE 0x00002000 /**< Backoff Presurre / No Backoff */
111 #define EMAC_MAC2_EXCESS_DEF 0x00004000 /**< Excess Defer */
112
113 /*********************************************************************//**
114 * Macro defines for Back-to-Back Inter-Packet-Gap Register
115 **********************************************************************/
116 /** Programmable field representing the nibble time offset of the minimum possible period
117 * between the end of any transmitted packet to the beginning of the next */
118 #define EMAC_IPGT_BBIPG(n) (n&0x7F)
119 /** Recommended value for Full Duplex of Programmable field representing the nibble time
120 * offset of the minimum possible period between the end of any transmitted packet to the
121 * beginning of the next */
122 #define EMAC_IPGT_FULL_DUP (EMAC_IPGT_BBIPG(0x15))
123 /** Recommended value for Half Duplex of Programmable field representing the nibble time
124 * offset of the minimum possible period between the end of any transmitted packet to the
125 * beginning of the next */
126 #define EMAC_IPGT_HALF_DUP (EMAC_IPGT_BBIPG(0x12))
127
128 /*********************************************************************//**
129 * Macro defines for Non Back-to-Back Inter-Packet-Gap Register
130 **********************************************************************/
131 /** Programmable field representing the Non-Back-to-Back Inter-Packet-Gap */
132 #define EMAC_IPGR_NBBIPG_P2(n) (n&0x7F)
133 /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1 */
134 #define EMAC_IPGR_P2_DEF (EMAC_IPGR_NBBIPG_P2(0x12))
135 /** Programmable field representing the optional carrierSense window referenced in
136 * IEEE 802.3/4.2.3.2.1 'Carrier Deference' */
137 #define EMAC_IPGR_NBBIPG_P1(n) ((n&0x7F)<<8)
138 /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2 */
139 #define EMAC_IPGR_P1_DEF EMAC_IPGR_NBBIPG_P1(0x0C)
140
141 /*********************************************************************//**
142 * Macro defines for Collision Window/Retry Register
143 **********************************************************************/
144 /** Programmable field specifying the number of retransmission attempts following a collision before
145 * aborting the packet due to excessive collisions */
146 #define EMAC_CLRT_MAX_RETX(n) (n&0x0F)
147 /** Programmable field representing the slot time or collision window during which collisions occur
148 * in properly configured networks */
149 #define EMAC_CLRT_COLL(n) ((n&0x3F)<<8)
150 /** Default value for Collision Window / Retry register */
151 #define EMAC_CLRT_DEF ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37)))
152
153 /*********************************************************************//**
154 * Macro defines for Maximum Frame Register
155 **********************************************************************/
156 /** Represents a maximum receive frame of 1536 octets */
157 #define EMAC_MAXF_MAXFRMLEN(n) (n&0xFFFF)
158
159 /*********************************************************************//**
160 * Macro defines for PHY Support Register
161 **********************************************************************/
162 #define EMAC_SUPP_SPEED 0x00000100 /**< Reduced MII Logic Current Speed */
163 #define EMAC_SUPP_RES_RMII 0x00000800 /**< Reset Reduced MII Logic */
164
165 /*********************************************************************//**
166 * Macro defines for Test Register
167 **********************************************************************/
168 #define EMAC_TEST_SHCUT_PQUANTA 0x00000001 /**< Shortcut Pause Quanta */
169 #define EMAC_TEST_TST_PAUSE 0x00000002 /**< Test Pause */
170 #define EMAC_TEST_TST_BACKP 0x00000004 /**< Test Back Pressure */
171
172 /*********************************************************************//**
173 * Macro defines for MII Management Configuration Register
174 **********************************************************************/
175 #define EMAC_MCFG_SCAN_INC 0x00000001 /**< Scan Increment PHY Address */
176 #define EMAC_MCFG_SUPP_PREAM 0x00000002 /**< Suppress Preamble */
177 #define EMAC_MCFG_CLK_SEL(n) ((n&0x0F)<<2) /**< Clock Select Field */
178 #define EMAC_MCFG_RES_MII 0x00008000 /**< Reset MII Management Hardware */
179 #define EMAC_MCFG_MII_MAXCLK 2500000UL /**< MII Clock max */
180
181 /*********************************************************************//**
182 * Macro defines for MII Management Command Register
183 **********************************************************************/
184 #define EMAC_MCMD_READ 0x00000001 /**< MII Read */
185 #define EMAC_MCMD_SCAN 0x00000002 /**< MII Scan continuously */
186
187 #define EMAC_MII_WR_TOUT 0x00050000 /**< MII Write timeout count */
188 #define EMAC_MII_RD_TOUT 0x00050000 /**< MII Read timeout count */
189
190 /*********************************************************************//**
191 * Macro defines for MII Management Address Register
192 **********************************************************************/
193 #define EMAC_MADR_REG_ADR(n) (n&0x1F) /**< MII Register Address field */
194 #define EMAC_MADR_PHY_ADR(n) ((n&0x1F)<<8) /**< PHY Address Field */
195
196 /*********************************************************************//**
197 * Macro defines for MII Management Write Data Register
198 **********************************************************************/
199 #define EMAC_MWTD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Write Data register */
200
201 /*********************************************************************//**
202 * Macro defines for MII Management Read Data Register
203 **********************************************************************/
204 #define EMAC_MRDD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Read Data register */
205
206 /*********************************************************************//**
207 * Macro defines for MII Management Indicators Register
208 **********************************************************************/
209 #define EMAC_MIND_BUSY 0x00000001 /**< MII is Busy */
210 #define EMAC_MIND_SCAN 0x00000002 /**< MII Scanning in Progress */
211 #define EMAC_MIND_NOT_VAL 0x00000004 /**< MII Read Data not valid */
212 #define EMAC_MIND_MII_LINK_FAIL 0x00000008 /**< MII Link Failed */
213
214 /* Station Address 0 Register */
215 /* Station Address 1 Register */
216 /* Station Address 2 Register */
217
218
219 /* Control register definitions --------------------------------------------------------------------------- */
220 /*********************************************************************//**
221 * Macro defines for Command Register
222 **********************************************************************/
223 #define EMAC_CR_RX_EN 0x00000001 /**< Enable Receive */
224 #define EMAC_CR_TX_EN 0x00000002 /**< Enable Transmit */
225 #define EMAC_CR_REG_RES 0x00000008 /**< Reset Host Registers */
226 #define EMAC_CR_TX_RES 0x00000010 /**< Reset Transmit Datapath */
227 #define EMAC_CR_RX_RES 0x00000020 /**< Reset Receive Datapath */
228 #define EMAC_CR_PASS_RUNT_FRM 0x00000040 /**< Pass Runt Frames */
229 #define EMAC_CR_PASS_RX_FILT 0x00000080 /**< Pass RX Filter */
230 #define EMAC_CR_TX_FLOW_CTRL 0x00000100 /**< TX Flow Control */
231 #define EMAC_CR_RMII 0x00000200 /**< Reduced MII Interface */
232 #define EMAC_CR_FULL_DUP 0x00000400 /**< Full Duplex */
233
234 /*********************************************************************//**
235 * Macro defines for Status Register
236 **********************************************************************/
237 #define EMAC_SR_RX_EN 0x00000001 /**< Enable Receive */
238 #define EMAC_SR_TX_EN 0x00000002 /**< Enable Transmit */
239
240 /*********************************************************************//**
241 * Macro defines for Transmit Status Vector 0 Register
242 **********************************************************************/
243 #define EMAC_TSV0_CRC_ERR 0x00000001 /**< CRC error */
244 #define EMAC_TSV0_LEN_CHKERR 0x00000002 /**< Length Check Error */
245 #define EMAC_TSV0_LEN_OUTRNG 0x00000004 /**< Length Out of Range */
246 #define EMAC_TSV0_DONE 0x00000008 /**< Tramsmission Completed */
247 #define EMAC_TSV0_MCAST 0x00000010 /**< Multicast Destination */
248 #define EMAC_TSV0_BCAST 0x00000020 /**< Broadcast Destination */
249 #define EMAC_TSV0_PKT_DEFER 0x00000040 /**< Packet Deferred */
250 #define EMAC_TSV0_EXC_DEFER 0x00000080 /**< Excessive Packet Deferral */
251 #define EMAC_TSV0_EXC_COLL 0x00000100 /**< Excessive Collision */
252 #define EMAC_TSV0_LATE_COLL 0x00000200 /**< Late Collision Occured */
253 #define EMAC_TSV0_GIANT 0x00000400 /**< Giant Frame */
254 #define EMAC_TSV0_UNDERRUN 0x00000800 /**< Buffer Underrun */
255 #define EMAC_TSV0_BYTES 0x0FFFF000 /**< Total Bytes Transferred */
256 #define EMAC_TSV0_CTRL_FRAME 0x10000000 /**< Control Frame */
257 #define EMAC_TSV0_PAUSE 0x20000000 /**< Pause Frame */
258 #define EMAC_TSV0_BACK_PRESS 0x40000000 /**< Backpressure Method Applied */
259 #define EMAC_TSV0_VLAN 0x80000000 /**< VLAN Frame */
260
261 /*********************************************************************//**
262 * Macro defines for Transmit Status Vector 1 Register
263 **********************************************************************/
264 #define EMAC_TSV1_BYTE_CNT 0x0000FFFF /**< Transmit Byte Count */
265 #define EMAC_TSV1_COLL_CNT 0x000F0000 /**< Transmit Collision Count */
266
267 /*********************************************************************//**
268 * Macro defines for Receive Status Vector Register
269 **********************************************************************/
270 #define EMAC_RSV_BYTE_CNT 0x0000FFFF /**< Receive Byte Count */
271 #define EMAC_RSV_PKT_IGNORED 0x00010000 /**< Packet Previously Ignored */
272 #define EMAC_RSV_RXDV_SEEN 0x00020000 /**< RXDV Event Previously Seen */
273 #define EMAC_RSV_CARR_SEEN 0x00040000 /**< Carrier Event Previously Seen */
274 #define EMAC_RSV_REC_CODEV 0x00080000 /**< Receive Code Violation */
275 #define EMAC_RSV_CRC_ERR 0x00100000 /**< CRC Error */
276 #define EMAC_RSV_LEN_CHKERR 0x00200000 /**< Length Check Error */
277 #define EMAC_RSV_LEN_OUTRNG 0x00400000 /**< Length Out of Range */
278 #define EMAC_RSV_REC_OK 0x00800000 /**< Frame Received OK */
279 #define EMAC_RSV_MCAST 0x01000000 /**< Multicast Frame */
280 #define EMAC_RSV_BCAST 0x02000000 /**< Broadcast Frame */
281 #define EMAC_RSV_DRIB_NIBB 0x04000000 /**< Dribble Nibble */
282 #define EMAC_RSV_CTRL_FRAME 0x08000000 /**< Control Frame */
283 #define EMAC_RSV_PAUSE 0x10000000 /**< Pause Frame */
284 #define EMAC_RSV_UNSUPP_OPC 0x20000000 /**< Unsupported Opcode */
285 #define EMAC_RSV_VLAN 0x40000000 /**< VLAN Frame */
286
287 /*********************************************************************//**
288 * Macro defines for Flow Control Counter Register
289 **********************************************************************/
290 #define EMAC_FCC_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter */
291 #define EMAC_FCC_PAUSE_TIM(n) ((n&0xFFFF)<<16) /**< Pause Timer */
292
293 /*********************************************************************//**
294 * Macro defines for Flow Control Status Register
295 **********************************************************************/
296 #define EMAC_FCS_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter Current */
297
298
299 /* Receive filter register definitions -------------------------------------------------------- */
300 /*********************************************************************//**
301 * Macro defines for Receive Filter Control Register
302 **********************************************************************/
303 #define EMAC_RFC_UCAST_EN 0x00000001 /**< Accept Unicast Frames Enable */
304 #define EMAC_RFC_BCAST_EN 0x00000002 /**< Accept Broadcast Frames Enable */
305 #define EMAC_RFC_MCAST_EN 0x00000004 /**< Accept Multicast Frames Enable */
306 #define EMAC_RFC_UCAST_HASH_EN 0x00000008 /**< Accept Unicast Hash Filter Frames */
307 #define EMAC_RFC_MCAST_HASH_EN 0x00000010 /**< Accept Multicast Hash Filter Fram.*/
308 #define EMAC_RFC_PERFECT_EN 0x00000020 /**< Accept Perfect Match Enable */
309 #define EMAC_RFC_MAGP_WOL_EN 0x00001000 /**< Magic Packet Filter WoL Enable */
310 #define EMAC_RFC_PFILT_WOL_EN 0x00002000 /**< Perfect Filter WoL Enable */
311
312 /*********************************************************************//**
313 * Macro defines for Receive Filter WoL Status/Clear Registers
314 **********************************************************************/
315 #define EMAC_WOL_UCAST 0x00000001 /**< Unicast Frame caused WoL */
316 #define EMAC_WOL_BCAST 0x00000002 /**< Broadcast Frame caused WoL */
317 #define EMAC_WOL_MCAST 0x00000004 /**< Multicast Frame caused WoL */
318 #define EMAC_WOL_UCAST_HASH 0x00000008 /**< Unicast Hash Filter Frame WoL */
319 #define EMAC_WOL_MCAST_HASH 0x00000010 /**< Multicast Hash Filter Frame WoL */
320 #define EMAC_WOL_PERFECT 0x00000020 /**< Perfect Filter WoL */
321 #define EMAC_WOL_RX_FILTER 0x00000080 /**< RX Filter caused WoL */
322 #define EMAC_WOL_MAG_PACKET 0x00000100 /**< Magic Packet Filter caused WoL */
323 #define EMAC_WOL_BITMASK 0x01BF /**< Receive Filter WoL Status/Clear bitmasl value */
324
325
326 /* Module control register definitions ---------------------------------------------------- */
327 /*********************************************************************//**
328 * Macro defines for Interrupt Status/Enable/Clear/Set Registers
329 **********************************************************************/
330 #define EMAC_INT_RX_OVERRUN 0x00000001 /**< Overrun Error in RX Queue */
331 #define EMAC_INT_RX_ERR 0x00000002 /**< Receive Error */
332 #define EMAC_INT_RX_FIN 0x00000004 /**< RX Finished Process Descriptors */
333 #define EMAC_INT_RX_DONE 0x00000008 /**< Receive Done */
334 #define EMAC_INT_TX_UNDERRUN 0x00000010 /**< Transmit Underrun */
335 #define EMAC_INT_TX_ERR 0x00000020 /**< Transmit Error */
336 #define EMAC_INT_TX_FIN 0x00000040 /**< TX Finished Process Descriptors */
337 #define EMAC_INT_TX_DONE 0x00000080 /**< Transmit Done */
338 #define EMAC_INT_SOFT_INT 0x00001000 /**< Software Triggered Interrupt */
339 #define EMAC_INT_WAKEUP 0x00002000 /**< Wakeup Event Interrupt */
340
341 /*********************************************************************//**
342 * Macro defines for Power Down Register
343 **********************************************************************/
344 #define EMAC_PD_POWER_DOWN 0x80000000 /**< Power Down MAC */
345
346 /* Descriptor and status formats ---------------------------------------------------- */
347 /*********************************************************************//**
348 * Macro defines for RX Descriptor Control Word
349 **********************************************************************/
350 #define EMAC_RCTRL_SIZE(n) (n&0x7FF) /**< Buffer size field */
351 #define EMAC_RCTRL_INT 0x80000000 /**< Generate RxDone Interrupt */
352
353 /*********************************************************************//**
354 * Macro defines for RX Status Hash CRC Word
355 **********************************************************************/
356 #define EMAC_RHASH_SA 0x000001FF /**< Hash CRC for Source Address */
357 #define EMAC_RHASH_DA 0x001FF000 /**< Hash CRC for Destination Address */
358
359 /*********************************************************************//**
360 * Macro defines for RX Status Information Word
361 **********************************************************************/
362 #define EMAC_RINFO_SIZE 0x000007FF /**< Data size in bytes */
363 #define EMAC_RINFO_CTRL_FRAME 0x00040000 /**< Control Frame */
364 #define EMAC_RINFO_VLAN 0x00080000 /**< VLAN Frame */
365 #define EMAC_RINFO_FAIL_FILT 0x00100000 /**< RX Filter Failed */
366 #define EMAC_RINFO_MCAST 0x00200000 /**< Multicast Frame */
367 #define EMAC_RINFO_BCAST 0x00400000 /**< Broadcast Frame */
368 #define EMAC_RINFO_CRC_ERR 0x00800000 /**< CRC Error in Frame */
369 #define EMAC_RINFO_SYM_ERR 0x01000000 /**< Symbol Error from PHY */
370 #define EMAC_RINFO_LEN_ERR 0x02000000 /**< Length Error */
371 #define EMAC_RINFO_RANGE_ERR 0x04000000 /**< Range Error (exceeded max. size) */
372 #define EMAC_RINFO_ALIGN_ERR 0x08000000 /**< Alignment Error */
373 #define EMAC_RINFO_OVERRUN 0x10000000 /**< Receive overrun */
374 #define EMAC_RINFO_NO_DESCR 0x20000000 /**< No new Descriptor available */
375 #define EMAC_RINFO_LAST_FLAG 0x40000000 /**< Last Fragment in Frame */
376 #define EMAC_RINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
377 #define EMAC_RINFO_ERR_MASK (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR | EMAC_RINFO_SYM_ERR | \
378 EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN)
379
380 /*********************************************************************//**
381 * Macro defines for TX Descriptor Control Word
382 **********************************************************************/
383 #define EMAC_TCTRL_SIZE 0x000007FF /**< Size of data buffer in bytes */
384 #define EMAC_TCTRL_OVERRIDE 0x04000000 /**< Override Default MAC Registers */
385 #define EMAC_TCTRL_HUGE 0x08000000 /**< Enable Huge Frame */
386 #define EMAC_TCTRL_PAD 0x10000000 /**< Pad short Frames to 64 bytes */
387 #define EMAC_TCTRL_CRC 0x20000000 /**< Append a hardware CRC to Frame */
388 #define EMAC_TCTRL_LAST 0x40000000 /**< Last Descriptor for TX Frame */
389 #define EMAC_TCTRL_INT 0x80000000 /**< Generate TxDone Interrupt */
390
391 /*********************************************************************//**
392 * Macro defines for TX Status Information Word
393 **********************************************************************/
394 #define EMAC_TINFO_COL_CNT 0x01E00000 /**< Collision Count */
395 #define EMAC_TINFO_DEFER 0x02000000 /**< Packet Deferred (not an error) */
396 #define EMAC_TINFO_EXCESS_DEF 0x04000000 /**< Excessive Deferral */
397 #define EMAC_TINFO_EXCESS_COL 0x08000000 /**< Excessive Collision */
398 #define EMAC_TINFO_LATE_COL 0x10000000 /**< Late Collision Occured */
399 #define EMAC_TINFO_UNDERRUN 0x20000000 /**< Transmit Underrun */
400 #define EMAC_TINFO_NO_DESCR 0x40000000 /**< No new Descriptor available */
401 #define EMAC_TINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
402
403 #ifdef MCB_LPC_1768
404 /* DP83848C PHY definition ------------------------------------------------------------ */
405
406 /** PHY device reset time out definition */
407 #define EMAC_PHY_RESP_TOUT 0x100000UL
408
409 /* ENET Device Revision ID */
410 #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
411
412 /*********************************************************************//**
413 * Macro defines for DP83848C PHY Registers
414 **********************************************************************/
415 #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
416 #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
417 #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
418 #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
419 #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
420 #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
421 #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
422 #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
423 #define EMAC_PHY_REG_LPNPA 0x08
424
425 /*********************************************************************//**
426 * Macro defines for PHY Extended Registers
427 **********************************************************************/
428 #define EMAC_PHY_REG_STS 0x10 /**< Status Register */
429 #define EMAC_PHY_REG_MICR 0x11 /**< MII Interrupt Control Register */
430 #define EMAC_PHY_REG_MISR 0x12 /**< MII Interrupt Status Register */
431 #define EMAC_PHY_REG_FCSCR 0x14 /**< False Carrier Sense Counter */
432 #define EMAC_PHY_REG_RECR 0x15 /**< Receive Error Counter */
433 #define EMAC_PHY_REG_PCSR 0x16 /**< PCS Sublayer Config. and Status */
434 #define EMAC_PHY_REG_RBR 0x17 /**< RMII and Bypass Register */
435 #define EMAC_PHY_REG_LEDCR 0x18 /**< LED Direct Control Register */
436 #define EMAC_PHY_REG_PHYCR 0x19 /**< PHY Control Register */
437 #define EMAC_PHY_REG_10BTSCR 0x1A /**< 10Base-T Status/Control Register */
438 #define EMAC_PHY_REG_CDCTRL1 0x1B /**< CD Test Control and BIST Extens. */
439 #define EMAC_PHY_REG_EDCR 0x1D /**< Energy Detect Control Register */
440
441 /*********************************************************************//**
442 * Macro defines for PHY Basic Mode Control Register
443 **********************************************************************/
444 #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
445 #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
446 #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
447 #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
448 #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
449 #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
450 #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
451 #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
452
453 /*********************************************************************//**
454 * Macro defines for PHY Basic Mode Status Status Register
455 **********************************************************************/
456 #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
457 #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
458 #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
459 #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
460 #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
461 #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
462 #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
463 #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
464 #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
465 #define EMAC_PHY_BMSR_LINK_ESTABLISHED (1<<2) /**< Link status */
466
467 /*********************************************************************//**
468 * Macro defines for PHY Status Register
469 **********************************************************************/
470 #define EMAC_PHY_SR_REMOTE_FAULT (1<<6) /**< Remote Fault */
471 #define EMAC_PHY_SR_JABBER (1<<5) /**< Jabber detect */
472 #define EMAC_PHY_SR_AUTO_DONE (1<<4) /**< Auto Negotiation complete */
473 #define EMAC_PHY_SR_LOOPBACK (1<<3) /**< Loop back status */
474 #define EMAC_PHY_SR_DUP (1<<2) /**< Duplex status */
475 #define EMAC_PHY_SR_SPEED (1<<1) /**< Speed status */
476 #define EMAC_PHY_SR_LINK (1<<0) /**< Link Status */
477
478 #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
479 #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
480 #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
481 #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
482 #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
483
484 #define EMAC_DEF_ADR 0x0100 /**< Default PHY device address */
485 #define EMAC_DP83848C_ID 0x20005C90 /**< PHY Identifier */
486
487 #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
488 #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
489 #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
490
491 #elif defined(IAR_LPC_1768)
492 /* KSZ8721BL PHY definition ------------------------------------------------------------ */
493 /** PHY device reset time out definition */
494 #define EMAC_PHY_RESP_TOUT 0x100000UL
495
496 /* ENET Device Revision ID */
497 #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
498
499 /*********************************************************************//**
500 * Macro defines for KSZ8721BL PHY Registers
501 **********************************************************************/
502 #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
503 #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
504 #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
505 #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
506 #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
507 #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
508 #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
509 #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
510 #define EMAC_PHY_REG_LPNPA 0x08 /**< Link Partner Next Page Ability */
511 #define EMAC_PHY_REG_REC 0x15 /**< RXError Counter Register */
512 #define EMAC_PHY_REG_ISC 0x1b /**< Interrupt Control/Status Register */
513 #define EMAC_PHY_REG_100BASE 0x1f /**< 100BASE-TX PHY Control Register */
514
515 /*********************************************************************//**
516 * Macro defines for PHY Basic Mode Control Register
517 **********************************************************************/
518 #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
519 #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
520 #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
521 #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
522 #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
523 #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
524 #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
525 #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
526 #define EMAC_PHY_BMCR_COLLISION (1<<7) /**< Collision test */
527 #define EMAC_PHY_BMCR_TXDIS (1<<0) /**< Disable transmit */
528
529 /*********************************************************************//**
530 * Macro defines for PHY Basic Mode Status Register
531 **********************************************************************/
532 #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
533 #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
534 #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
535 #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
536 #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
537 #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
538 #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
539 #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
540 #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
541 #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
542 #define EMAC_PHY_BMSR_JABBER_DETECT (1<<1) /**< Jabber detect */
543 #define EMAC_PHY_BMSR_EXTEND (1<<0) /**< Extended support */
544
545 /*********************************************************************//**
546 * Macro defines for PHY Identifier
547 **********************************************************************/
548 /* PHY Identifier 1 bitmap definitions */
549 #define EMAC_PHY_IDR1(n) (n & 0xFFFF) /**< PHY ID1 Number */
550
551 /* PHY Identifier 2 bitmap definitions */
552 #define EMAC_PHY_IDR2(n) (n & 0xFFFF) /**< PHY ID2 Number */
553
554 /*********************************************************************//**
555 * Macro defines for Auto-Negotiation Advertisement
556 **********************************************************************/
557 #define EMAC_PHY_AN_NEXTPAGE (1<<15) /**< Next page capable */
558 #define EMAC_PHY_AN_REMOTE_FAULT (1<<13) /**< Remote Fault support */
559 #define EMAC_PHY_AN_PAUSE (1<<10) /**< Pause support */
560 #define EMAC_PHY_AN_100BASE_T4 (1<<9) /**< T4 capable */
561 #define EMAC_PHY_AN_100BASE_TX_FD (1<<8) /**< TX with Full-duplex capable */
562 #define EMAC_PHY_AN_100BASE_TX (1<<7) /**< TX capable */
563 #define EMAC_PHY_AN_10BASE_T_FD (1<<6) /**< 10Mbps with full-duplex capable */
564 #define EMAC_PHY_AN_10BASE_T (1<<5) /**< 10Mbps capable */
565 #define EMAC_PHY_AN_FIELD(n) (n & 0x1F) /**< Selector Field */
566
567 #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
568 #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
569 #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
570 #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
571 #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
572
573 #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
574 #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
575
576 #define EMAC_DEF_ADR (0x01<<8) /**< Default PHY device address */
577 #define EMAC_KSZ8721BL_ID ((0x22 << 16) | 0x1619 ) /**< PHY Identifier */
578 #endif
579
580 /**
581 * @}
582 */
583
584
585 /* Public Types --------------------------------------------------------------- */
586 /** @defgroup EMAC_Public_Types EMAC Public Types
587 * @{
588 */
589
590 /* Descriptor and status formats ---------------------------------------------- */
591
592 /**
593 * @brief RX Descriptor structure type definition
594 */
595 typedef struct {
596 uint32_t Packet; /**< Receive Packet Descriptor */
597 uint32_t Ctrl; /**< Receive Control Descriptor */
598 } RX_Desc;
599
600 /**
601 * @brief RX Status structure type definition
602 */
603 typedef struct {
604 uint32_t Info; /**< Receive Information Status */
605 uint32_t HashCRC; /**< Receive Hash CRC Status */
606 } RX_Stat;
607
608 /**
609 * @brief TX Descriptor structure type definition
610 */
611 typedef struct {
612 uint32_t Packet; /**< Transmit Packet Descriptor */
613 uint32_t Ctrl; /**< Transmit Control Descriptor */
614 } TX_Desc;
615
616 /**
617 * @brief TX Status structure type definition
618 */
619 typedef struct {
620 uint32_t Info; /**< Transmit Information Status */
621 } TX_Stat;
622
623
624 /**
625 * @brief TX Data Buffer structure definition
626 */
627 typedef struct {
628 uint32_t ulDataLen; /**< Data length */
629 uint32_t *pbDataBuf; /**< A word-align data pointer to data buffer */
630 } EMAC_PACKETBUF_Type;
631
632 /**
633 * @brief EMAC configuration structure definition
634 */
635 typedef struct {
636 uint32_t Mode; /**< Supported EMAC PHY device speed, should be one of the following:
637 - EMAC_MODE_AUTO
638 - EMAC_MODE_10M_FULL
639 - EMAC_MODE_10M_HALF
640 - EMAC_MODE_100M_FULL
641 - EMAC_MODE_100M_HALF
642 */
643 uint8_t *pbEMAC_Addr; /**< Pointer to EMAC Station address that contains 6-bytes
644 of MAC address, it must be sorted in order (bEMAC_Addr[0]..[5])
645 */
646 } EMAC_CFG_Type;
647
648 /** Ethernet block power/clock control bit*/
649 #define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30))
650
651 #ifdef __cplusplus
652 }
653 #endif
654
655 #endif /* LPC17XX_EMAC_H_ */
656
657 /**
658 * @}
659 */
660
661 /* --------------------------------- End Of File ------------------------------ */
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