tool/mbed/mbed-sdk/libraries/rtos/rtx/TARGET_CORTEX_A/rt_HAL_CA.h

   1 /*----------------------------------------------------------------------------
   2  *      RL-ARM - RTX
   3  *----------------------------------------------------------------------------
   4  *      Name:    RT_HAL_CM.H
   5  *      Purpose: Hardware Abstraction Layer for Cortex-A definitions
   6  *      Rev.:    21 Aug 2013
   7  *----------------------------------------------------------------------------
   8  *
   9  * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
  10  * All rights reserved.
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions are met:
  13  *  - Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  *  - Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *  - Neither the name of ARM  nor the names of its contributors may be used
  19  *    to endorse or promote products derived from this software without
  20  *    specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
  26  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  32  * POSSIBILITY OF SUCH DAMAGE.
  33  *---------------------------------------------------------------------------*/
  34
  35 /* Definitions */
  36 #define INIT_CPSR_SYS   0x4000001F
  37 #define INIT_CPSR_USER  0x40000010
  38
  39 #define CPSR_T_BIT      0x20
  40 #define CPSR_I_BIT      0x80
  41 #define CPSR_F_BIT      0x40
  42
  43 #define MODE_USR        0x10
  44 #define MODE_FIQ        0x11
  45 #define MODE_IRQ        0x12
  46 #define MODE_SVC        0x13
  47 #define MODE_ABT        0x17
  48 #define MODE_UND        0x1B
  49 #define MODE_SYS        0x1F
  50
  51 #define MAGIC_WORD      0xE25A2EA5
  52
  53 #include "core_ca9.h"
  54
  55 #if defined (__CC_ARM)          /* ARM Compiler */
  56
  57 #if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M || __TARGET_ARCH_7_A) && !defined(NO_EXCLUSIVE_ACCESS))
  58  #define __USE_EXCLUSIVE_ACCESS
  59 #else
  60  #undef  __USE_EXCLUSIVE_ACCESS
  61 #endif
  62
  63 #elif defined (__GNUC__)        /* GNU Compiler */
  64
  65 #undef  __USE_EXCLUSIVE_ACCESS
  66
  67 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
  68 #define __TARGET_FPU_VFP 1
  69 #else
  70 #define __TARGET_FPU_VFP 0
  71 #endif
  72
  73 #define __inline inline
  74 #define __weak   __attribute__((weak))
  75
  76 #elif defined (__ICCARM__)      /* IAR Compiler */
  77
  78 #error IAR Compiler support not implemented for Cortex-A
  79
  80 #endif
  81
  82 static U8 priority = 0xff;
  83
  84 extern const U32 GICDistributor_BASE;
  85 extern const U32 GICInterface_BASE;
  86
  87 /* GIC registers - Distributor */
  88 #define GICD_ICDICER0   (*((volatile U32 *)(GICDistributor_BASE + 0x180))) /* - RW - Interrupt Clear-Enable Registers */
  89 #define GICD_ICDISER0   (*((volatile U32 *)(GICDistributor_BASE + 0x100))) /* - RW - Interrupt Set-Enable Registers */
  90 #define GICD_ICDIPR0    (*((volatile U32 *)(GICDistributor_BASE + 0x400))) /* - RW - Interrupt Priority Registers */
  91 #define GICD_ICDSGIR    (*((volatile U32 *)(GICDistributor_BASE + 0xf00))) /* - RW - Interrupt Software Interrupt Register */
  92 #define GICD_ICDICERx(irq)   *(volatile U32 *)(&GICD_ICDICER0 + irq/32)
  93 #define GICD_ICDISERx(irq)   *(volatile U32 *)(&GICD_ICDISER0 + irq/32)
  94
  95 /* GIC register  - CPU Interface  */
  96 #define GICI_ICCPMR     (*((volatile U32 *)(GICInterface_BASE + 0x004))) /* - RW - Interrupt Priority Mask Register */
  97
  98 #define SGI_PENDSV      0 /* SGI0 */
  99 #define SGI_PENDSV_BIT  ((U32)(1 << (SGI_PENDSV & 0xf)))
 100
 101 //Increase priority filter to prevent timer and PendSV interrupts signaling. Guarantees that interrupts will not be forwarded.
 102 #define OS_LOCK() int irq_dis = __disable_irq();\
 103                   priority = GICI_ICCPMR; \
 104                   GICI_ICCPMR = 0xff; \
 105                   GICI_ICCPMR = GICI_ICCPMR - 1; \
 106                   __DSB();\
 107                   if(!irq_dis) __enable_irq(); \
 108
 109 //Restore priority filter. Re-enable timer and PendSV signaling
 110 #define OS_UNLOCK() __DSB(); \
 111                     GICI_ICCPMR = priority; \
 112
 113 #define OS_PEND_IRQ() GICD_ICDSGIR = 0x0010000 | SGI_PENDSV
 114 #define OS_PEND(fl,p) if(p) OS_PEND_IRQ();
 115 #define OS_UNPEND(fl)
 116
 117 /* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c-
 118  * OS_X_INIT enables the IRQ n in the GIC */
 119 #define OS_X_INIT(n) volatile char *reg; \
 120                      reg = (char *)(&GICD_ICDIPR0 + n / 4); \
 121                      reg += n % 4; \
 122                      *reg = (char)0xff; \
 123                      *reg = *reg - 1; \
 124                      GICD_ICDISERx(n) = (U32)(1 << n % 32);
 125 #define OS_X_LOCK(n) OS_LOCK()
 126 #define OS_X_UNLOCK(n) OS_UNLOCK()
 127 #define OS_X_PEND_IRQ() OS_PEND_IRQ()
 128 #define OS_X_PEND(fl,p) if(p) OS_X_PEND_IRQ();
 129 #define OS_X_UNPEND(fl)
 130
 131
 132 /* Functions */
 133 #ifdef __USE_EXCLUSIVE_ACCESS
 134  #define rt_inc(p)     while(__strex((__ldrex(p)+1),p))
 135  #define rt_dec(p)     while(__strex((__ldrex(p)-1),p))
 136 #else
 137  #define rt_inc(p)     { int irq_dis = __disable_irq();(*p)++;if(!irq_dis) __enable_irq(); }
 138  #define rt_dec(p)     { int irq_dis = __disable_irq();(*p)--;if(!irq_dis) __enable_irq(); }
 139 #endif
 140
 141 __inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
 142   U32 cnt,c2;
 143 #ifdef __USE_EXCLUSIVE_ACCESS
 144   do {
 145     if ((cnt = __ldrex(count)) == size) {
 146       __clrex();
 147       return (cnt); }
 148   } while (__strex(cnt+1, count));
 149   do {
 150     c2 = (cnt = __ldrex(first)) + 1;
 151     if (c2 == size) c2 = 0;
 152   } while (__strex(c2, first));
 153 #else
 154   int irq_dis;
 155   irq_dis = __disable_irq();
 156   if ((cnt = *count) < size) {
 157     *count = cnt+1;
 158     c2 = (cnt = *first) + 1;
 159     if (c2 == size) c2 = 0;
 160     *first = c2;
 161   }
 162   if(!irq_dis) __enable_irq ();
 163 #endif
 164   return (cnt);
 165 }
 166
 167 __inline static void rt_systick_init (void) {
 168   /* Cortex-A doesn't have a Systick. User needs to provide an alternative timer using RTX_Conf_CM configuration */
 169   /* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c- */
 170 }
 171
 172 __inline static void rt_svc_init (void) {
 173   /* Register pendSV - through SGI */
 174   volatile char *reg;
 175
 176   reg = (char *)(&GICD_ICDIPR0 + SGI_PENDSV/4);
 177   reg += SGI_PENDSV % 4;
 178   /* Write 0xff to read priority level */
 179   *reg = (char)0xff;
 180   /* Read priority level and set the lowest possible*/
 181   *reg = *reg - 1;
 182
 183   GICD_ICDISERx(SGI_PENDSV) = (U32)SGI_PENDSV_BIT;
 184 }
 185
 186 extern void rt_set_PSP (U32 stack);
 187 extern U32  rt_get_PSP (void);
 188 extern void os_set_env (P_TCB p_TCB);
 189 extern void *_alloc_box (void *box_mem);
 190 extern int  _free_box (void *box_mem, void *box);
 191
 192 extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
 193 extern void rt_ret_val  (P_TCB p_TCB, U32 v0);
 194 extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1);
 195
 196 extern void dbg_init (void);
 197 extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
 198 extern void dbg_task_switch (U32 task_id);
 199
 200 #define DBG_INIT()
 201 #define DBG_TASK_NOTIFY(p_tcb,create)
 202 #define DBG_TASK_SWITCH(task_id)
 203
 204 /*----------------------------------------------------------------------------
 205  * end of file
 206  *---------------------------------------------------------------------------*/
 207