tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_mcm.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manual:    K22P121M120SF7RM, Rev. 1, March 24, 2014
   9 **     Version:             rev. 2.5, 2014-05-06
  10 **     Build:               b140604
  11 **
  12 **     Abstract:
  13 **         Extension to the CMSIS register access layer header.
  14 **
  15 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  16 **     All rights reserved.
  17 **
  18 **     Redistribution and use in source and binary forms, with or without modification,
  19 **     are permitted provided that the following conditions are met:
  20 **
  21 **     o Redistributions of source code must retain the above copyright notice, this list
  22 **       of conditions and the following disclaimer.
  23 **
  24 **     o Redistributions in binary form must reproduce the above copyright notice, this
  25 **       list of conditions and the following disclaimer in the documentation and/or
  26 **       other materials provided with the distribution.
  27 **
  28 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  29 **       contributors may be used to endorse or promote products derived from this
  30 **       software without specific prior written permission.
  31 **
  32 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  36 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  39 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42 **
  43 **     http:                 www.freescale.com
  44 **     mail:                 support@freescale.com
  45 **
  46 **     Revisions:
  47 **     - rev. 1.0 (2013-07-23)
  48 **         Initial version.
  49 **     - rev. 1.1 (2013-09-17)
  50 **         RM rev. 0.4 update.
  51 **     - rev. 2.0 (2013-10-29)
  52 **         Register accessor macros added to the memory map.
  53 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  54 **         Startup file for gcc has been updated according to CMSIS 3.2.
  55 **         System initialization updated.
  56 **     - rev. 2.1 (2013-10-30)
  57 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  58 **     - rev. 2.2 (2013-12-20)
  59 **         Update according to reference manual rev. 0.6,
  60 **     - rev. 2.3 (2014-01-13)
  61 **         Update according to reference manual rev. 0.61,
  62 **     - rev. 2.4 (2014-02-10)
  63 **         The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
  64 **     - rev. 2.5 (2014-05-06)
  65 **         Update according to reference manual rev. 1.0,
  66 **         Update of system and startup files.
  67 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  68 **
  69 ** ###################################################################
  70 */
  71
  72 /*
  73  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
  74  *
  75  * This file was generated automatically and any changes may be lost.
  76  */
  77 #ifndef __HW_MCM_REGISTERS_H__
  78 #define __HW_MCM_REGISTERS_H__
  79
  80 #include "MK22F51212.h"
  81 #include "fsl_bitaccess.h"
  82
  83 /*
  84  * MK22F51212 MCM
  85  *
  86  * Core Platform Miscellaneous Control Module
  87  *
  88  * Registers defined in this header file:
  89  * - HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
  90  * - HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
  91  * - HW_MCM_PLACR - Crossbar Switch (AXBS) Control Register
  92  * - HW_MCM_ISCR - Interrupt Status and Control Register
  93  * - HW_MCM_CPO - Compute Operation Control Register
  94  *
  95  * - hw_mcm_t - Struct containing all module registers.
  96  */
  97
  98 #define HW_MCM_INSTANCE_COUNT (1U) /*!< Number of instances of the MCM module. */
  99
 100 /*******************************************************************************
 101  * HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
 102  ******************************************************************************/
 103
 104 /*!
 105  * @brief HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration (RO)
 106  *
 107  * Reset value: 0x001FU
 108  *
 109  * PLASC is a 16-bit read-only register identifying the presence/absence of bus
 110  * slave connections to the device's crossbar switch.
 111  */
 112 typedef union _hw_mcm_plasc
 113 {
 114     uint16_t U;
 115     struct _hw_mcm_plasc_bitfields
 116     {
 117         uint16_t ASC : 8;              /*!< [7:0] Each bit in the ASC field indicates
 118                                         * whether there is a corresponding connection to the crossbar switch's slave
 119                                         * input port. */
 120         uint16_t RESERVED0 : 8;        /*!< [15:8]  */
 121     } B;
 122 } hw_mcm_plasc_t;
 123
 124 /*!
 125  * @name Constants and macros for entire MCM_PLASC register
 126  */
 127 /*@{*/
 128 #define HW_MCM_PLASC_ADDR(x)     ((x) + 0x8U)
 129
 130 #define HW_MCM_PLASC(x)          (*(__I hw_mcm_plasc_t *) HW_MCM_PLASC_ADDR(x))
 131 #define HW_MCM_PLASC_RD(x)       (HW_MCM_PLASC(x).U)
 132 /*@}*/
 133
 134 /*
 135  * Constants & macros for individual MCM_PLASC bitfields
 136  */
 137
 138 /*!
 139  * @name Register MCM_PLASC, field ASC[7:0] (RO)
 140  *
 141  * Values:
 142  * - 0 - A bus slave connection to AXBS input port n is absent
 143  * - 1 - A bus slave connection to AXBS input port n is present
 144  */
 145 /*@{*/
 146 #define BP_MCM_PLASC_ASC     (0U)          /*!< Bit position for MCM_PLASC_ASC. */
 147 #define BM_MCM_PLASC_ASC     (0x00FFU)     /*!< Bit mask for MCM_PLASC_ASC. */
 148 #define BS_MCM_PLASC_ASC     (8U)          /*!< Bit field size in bits for MCM_PLASC_ASC. */
 149
 150 /*! @brief Read current value of the MCM_PLASC_ASC field. */
 151 #define BR_MCM_PLASC_ASC(x)  (HW_MCM_PLASC(x).B.ASC)
 152 /*@}*/
 153
 154 /*******************************************************************************
 155  * HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
 156  ******************************************************************************/
 157
 158 /*!
 159  * @brief HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration (RO)
 160  *
 161  * Reset value: 0x0017U
 162  *
 163  * PLAMC is a 16-bit read-only register identifying the presence/absence of bus
 164  * master connections to the device's crossbar switch.
 165  */
 166 typedef union _hw_mcm_plamc
 167 {
 168     uint16_t U;
 169     struct _hw_mcm_plamc_bitfields
 170     {
 171         uint16_t AMC : 8;              /*!< [7:0] Each bit in the AMC field indicates
 172                                         * whether there is a corresponding connection to the AXBS master input port. */
 173         uint16_t RESERVED0 : 8;        /*!< [15:8]  */
 174     } B;
 175 } hw_mcm_plamc_t;
 176
 177 /*!
 178  * @name Constants and macros for entire MCM_PLAMC register
 179  */
 180 /*@{*/
 181 #define HW_MCM_PLAMC_ADDR(x)     ((x) + 0xAU)
 182
 183 #define HW_MCM_PLAMC(x)          (*(__I hw_mcm_plamc_t *) HW_MCM_PLAMC_ADDR(x))
 184 #define HW_MCM_PLAMC_RD(x)       (HW_MCM_PLAMC(x).U)
 185 /*@}*/
 186
 187 /*
 188  * Constants & macros for individual MCM_PLAMC bitfields
 189  */
 190
 191 /*!
 192  * @name Register MCM_PLAMC, field AMC[7:0] (RO)
 193  *
 194  * Values:
 195  * - 0 - A bus master connection to AXBS input port n is absent
 196  * - 1 - A bus master connection to AXBS input port n is present
 197  */
 198 /*@{*/
 199 #define BP_MCM_PLAMC_AMC     (0U)          /*!< Bit position for MCM_PLAMC_AMC. */
 200 #define BM_MCM_PLAMC_AMC     (0x00FFU)     /*!< Bit mask for MCM_PLAMC_AMC. */
 201 #define BS_MCM_PLAMC_AMC     (8U)          /*!< Bit field size in bits for MCM_PLAMC_AMC. */
 202
 203 /*! @brief Read current value of the MCM_PLAMC_AMC field. */
 204 #define BR_MCM_PLAMC_AMC(x)  (HW_MCM_PLAMC(x).B.AMC)
 205 /*@}*/
 206
 207 /*******************************************************************************
 208  * HW_MCM_PLACR - Crossbar Switch (AXBS) Control Register
 209  ******************************************************************************/
 210
 211 /*!
 212  * @brief HW_MCM_PLACR - Crossbar Switch (AXBS) Control Register (RW)
 213  *
 214  * Reset value: 0x00000000U
 215  *
 216  * The PLACR register selects the arbitration policy for the crossbar masters.
 217  */
 218 typedef union _hw_mcm_placr
 219 {
 220     uint32_t U;
 221     struct _hw_mcm_placr_bitfields
 222     {
 223         uint32_t RESERVED0 : 9;        /*!< [8:0]  */
 224         uint32_t ARB : 1;              /*!< [9] Arbitration select */
 225         uint32_t RESERVED1 : 22;       /*!< [31:10]  */
 226     } B;
 227 } hw_mcm_placr_t;
 228
 229 /*!
 230  * @name Constants and macros for entire MCM_PLACR register
 231  */
 232 /*@{*/
 233 #define HW_MCM_PLACR_ADDR(x)     ((x) + 0xCU)
 234
 235 #define HW_MCM_PLACR(x)          (*(__IO hw_mcm_placr_t *) HW_MCM_PLACR_ADDR(x))
 236 #define HW_MCM_PLACR_RD(x)       (HW_MCM_PLACR(x).U)
 237 #define HW_MCM_PLACR_WR(x, v)    (HW_MCM_PLACR(x).U = (v))
 238 #define HW_MCM_PLACR_SET(x, v)   (HW_MCM_PLACR_WR(x, HW_MCM_PLACR_RD(x) |  (v)))
 239 #define HW_MCM_PLACR_CLR(x, v)   (HW_MCM_PLACR_WR(x, HW_MCM_PLACR_RD(x) & ~(v)))
 240 #define HW_MCM_PLACR_TOG(x, v)   (HW_MCM_PLACR_WR(x, HW_MCM_PLACR_RD(x) ^  (v)))
 241 /*@}*/
 242
 243 /*
 244  * Constants & macros for individual MCM_PLACR bitfields
 245  */
 246
 247 /*!
 248  * @name Register MCM_PLACR, field ARB[9] (RW)
 249  *
 250  * Values:
 251  * - 0 - Fixed-priority arbitration for the crossbar masters
 252  * - 1 - Round-robin arbitration for the crossbar masters
 253  */
 254 /*@{*/
 255 #define BP_MCM_PLACR_ARB     (9U)          /*!< Bit position for MCM_PLACR_ARB. */
 256 #define BM_MCM_PLACR_ARB     (0x00000200U) /*!< Bit mask for MCM_PLACR_ARB. */
 257 #define BS_MCM_PLACR_ARB     (1U)          /*!< Bit field size in bits for MCM_PLACR_ARB. */
 258
 259 /*! @brief Read current value of the MCM_PLACR_ARB field. */
 260 #define BR_MCM_PLACR_ARB(x)  (HW_MCM_PLACR(x).B.ARB)
 261
 262 /*! @brief Format value for bitfield MCM_PLACR_ARB. */
 263 #define BF_MCM_PLACR_ARB(v)  ((uint32_t)((uint32_t)(v) << BP_MCM_PLACR_ARB) & BM_MCM_PLACR_ARB)
 264
 265 /*! @brief Set the ARB field to a new value. */
 266 #define BW_MCM_PLACR_ARB(x, v) (HW_MCM_PLACR_WR(x, (HW_MCM_PLACR_RD(x) & ~BM_MCM_PLACR_ARB) | BF_MCM_PLACR_ARB(v)))
 267 /*@}*/
 268
 269 /*******************************************************************************
 270  * HW_MCM_ISCR - Interrupt Status and Control Register
 271  ******************************************************************************/
 272
 273 /*!
 274  * @brief HW_MCM_ISCR - Interrupt Status and Control Register (RW)
 275  *
 276  * Reset value: 0x00020000U
 277  *
 278  * The MCM_ISCR register includes the enable and status bits associated with the
 279  * core's floating-point exceptions. The individual event indicators are first
 280  * qualified with their exception enables and then logically summed to form an
 281  * interrupt request sent to the core's NVIC. Bits 15-8 are read-only indicator
 282  * flags based on the processor's FPSCR register. Attempted writes to these bits are
 283  * ignored. Once set, the flags remain asserted until software clears the
 284  * corresponding FPSCR bit.
 285  */
 286 typedef union _hw_mcm_iscr
 287 {
 288     uint32_t U;
 289     struct _hw_mcm_iscr_bitfields
 290     {
 291         uint32_t RESERVED0 : 8;        /*!< [7:0]  */
 292         uint32_t FIOC : 1;             /*!< [8] FPU invalid operation interrupt status */
 293         uint32_t FDZC : 1;             /*!< [9] FPU divide-by-zero interrupt status */
 294         uint32_t FOFC : 1;             /*!< [10] FPU overflow interrupt status */
 295         uint32_t FUFC : 1;             /*!< [11] FPU underflow interrupt status */
 296         uint32_t FIXC : 1;             /*!< [12] FPU inexact interrupt status */
 297         uint32_t RESERVED1 : 2;        /*!< [14:13]  */
 298         uint32_t FIDC : 1;             /*!< [15] FPU input denormal interrupt status */
 299         uint32_t RESERVED2 : 8;        /*!< [23:16]  */
 300         uint32_t FIOCE : 1;            /*!< [24] FPU invalid operation interrupt enable
 301                                         * */
 302         uint32_t FDZCE : 1;            /*!< [25] FPU divide-by-zero interrupt enable */
 303         uint32_t FOFCE : 1;            /*!< [26] FPU overflow interrupt enable */
 304         uint32_t FUFCE : 1;            /*!< [27] FPU underflow interrupt enable */
 305         uint32_t FIXCE : 1;            /*!< [28] FPU inexact interrupt enable */
 306         uint32_t RESERVED3 : 2;        /*!< [30:29]  */
 307         uint32_t FIDCE : 1;            /*!< [31] FPU input denormal interrupt enable */
 308     } B;
 309 } hw_mcm_iscr_t;
 310
 311 /*!
 312  * @name Constants and macros for entire MCM_ISCR register
 313  */
 314 /*@{*/
 315 #define HW_MCM_ISCR_ADDR(x)      ((x) + 0x10U)
 316
 317 #define HW_MCM_ISCR(x)           (*(__IO hw_mcm_iscr_t *) HW_MCM_ISCR_ADDR(x))
 318 #define HW_MCM_ISCR_RD(x)        (HW_MCM_ISCR(x).U)
 319 #define HW_MCM_ISCR_WR(x, v)     (HW_MCM_ISCR(x).U = (v))
 320 #define HW_MCM_ISCR_SET(x, v)    (HW_MCM_ISCR_WR(x, HW_MCM_ISCR_RD(x) |  (v)))
 321 #define HW_MCM_ISCR_CLR(x, v)    (HW_MCM_ISCR_WR(x, HW_MCM_ISCR_RD(x) & ~(v)))
 322 #define HW_MCM_ISCR_TOG(x, v)    (HW_MCM_ISCR_WR(x, HW_MCM_ISCR_RD(x) ^  (v)))
 323 /*@}*/
 324
 325 /*
 326  * Constants & macros for individual MCM_ISCR bitfields
 327  */
 328
 329 /*!
 330  * @name Register MCM_ISCR, field FIOC[8] (RO)
 331  *
 332  * This read-only bit is a copy of the core's FPSCR[IOC] bit and signals an
 333  * illegal operation has been detected in the processor's FPU. Once set, this bit
 334  * remains set until software clears the FPSCR[IOC] bit.
 335  *
 336  * Values:
 337  * - 0 - No interrupt
 338  * - 1 - Interrupt occurred
 339  */
 340 /*@{*/
 341 #define BP_MCM_ISCR_FIOC     (8U)          /*!< Bit position for MCM_ISCR_FIOC. */
 342 #define BM_MCM_ISCR_FIOC     (0x00000100U) /*!< Bit mask for MCM_ISCR_FIOC. */
 343 #define BS_MCM_ISCR_FIOC     (1U)          /*!< Bit field size in bits for MCM_ISCR_FIOC. */
 344
 345 /*! @brief Read current value of the MCM_ISCR_FIOC field. */
 346 #define BR_MCM_ISCR_FIOC(x)  (HW_MCM_ISCR(x).B.FIOC)
 347 /*@}*/
 348
 349 /*!
 350  * @name Register MCM_ISCR, field FDZC[9] (RO)
 351  *
 352  * This read-only bit is a copy of the core's FPSCR[DZC] bit and signals a
 353  * divide by zero has been detected in the processor's FPU. Once set, this bit remains
 354  * set until software clears the FPSCR[DZC] bit.
 355  *
 356  * Values:
 357  * - 0 - No interrupt
 358  * - 1 - Interrupt occurred
 359  */
 360 /*@{*/
 361 #define BP_MCM_ISCR_FDZC     (9U)          /*!< Bit position for MCM_ISCR_FDZC. */
 362 #define BM_MCM_ISCR_FDZC     (0x00000200U) /*!< Bit mask for MCM_ISCR_FDZC. */
 363 #define BS_MCM_ISCR_FDZC     (1U)          /*!< Bit field size in bits for MCM_ISCR_FDZC. */
 364
 365 /*! @brief Read current value of the MCM_ISCR_FDZC field. */
 366 #define BR_MCM_ISCR_FDZC(x)  (HW_MCM_ISCR(x).B.FDZC)
 367 /*@}*/
 368
 369 /*!
 370  * @name Register MCM_ISCR, field FOFC[10] (RO)
 371  *
 372  * This read-only bit is a copy of the core's FPSCR[OFC] bit and signals an
 373  * overflow has been detected in the processor's FPU. Once set, this bit remains set
 374  * until software clears the FPSCR[OFC] bit.
 375  *
 376  * Values:
 377  * - 0 - No interrupt
 378  * - 1 - Interrupt occurred
 379  */
 380 /*@{*/
 381 #define BP_MCM_ISCR_FOFC     (10U)         /*!< Bit position for MCM_ISCR_FOFC. */
 382 #define BM_MCM_ISCR_FOFC     (0x00000400U) /*!< Bit mask for MCM_ISCR_FOFC. */
 383 #define BS_MCM_ISCR_FOFC     (1U)          /*!< Bit field size in bits for MCM_ISCR_FOFC. */
 384
 385 /*! @brief Read current value of the MCM_ISCR_FOFC field. */
 386 #define BR_MCM_ISCR_FOFC(x)  (HW_MCM_ISCR(x).B.FOFC)
 387 /*@}*/
 388
 389 /*!
 390  * @name Register MCM_ISCR, field FUFC[11] (RO)
 391  *
 392  * This read-only bit is a copy of the core's FPSCR[UFC] bit and signals an
 393  * underflow has been detected in the processor's FPU. Once set, this bit remains set
 394  * until software clears the FPSCR[UFC] bit.
 395  *
 396  * Values:
 397  * - 0 - No interrupt
 398  * - 1 - Interrupt occurred
 399  */
 400 /*@{*/
 401 #define BP_MCM_ISCR_FUFC     (11U)         /*!< Bit position for MCM_ISCR_FUFC. */
 402 #define BM_MCM_ISCR_FUFC     (0x00000800U) /*!< Bit mask for MCM_ISCR_FUFC. */
 403 #define BS_MCM_ISCR_FUFC     (1U)          /*!< Bit field size in bits for MCM_ISCR_FUFC. */
 404
 405 /*! @brief Read current value of the MCM_ISCR_FUFC field. */
 406 #define BR_MCM_ISCR_FUFC(x)  (HW_MCM_ISCR(x).B.FUFC)
 407 /*@}*/
 408
 409 /*!
 410  * @name Register MCM_ISCR, field FIXC[12] (RO)
 411  *
 412  * This read-only bit is a copy of the core's FPSCR[IXC] bit and signals an
 413  * inexact number has been detected in the processor's FPU. Once set, this bit
 414  * remains set until software clears the FPSCR[IXC] bit.
 415  *
 416  * Values:
 417  * - 0 - No interrupt
 418  * - 1 - Interrupt occurred
 419  */
 420 /*@{*/
 421 #define BP_MCM_ISCR_FIXC     (12U)         /*!< Bit position for MCM_ISCR_FIXC. */
 422 #define BM_MCM_ISCR_FIXC     (0x00001000U) /*!< Bit mask for MCM_ISCR_FIXC. */
 423 #define BS_MCM_ISCR_FIXC     (1U)          /*!< Bit field size in bits for MCM_ISCR_FIXC. */
 424
 425 /*! @brief Read current value of the MCM_ISCR_FIXC field. */
 426 #define BR_MCM_ISCR_FIXC(x)  (HW_MCM_ISCR(x).B.FIXC)
 427 /*@}*/
 428
 429 /*!
 430  * @name Register MCM_ISCR, field FIDC[15] (RO)
 431  *
 432  * This read-only bit is a copy of the core's FPSCR[IDC] bit and signals input
 433  * denormalized number has been detected in the processor's FPU. Once set, this
 434  * bit remains set until software clears the FPSCR[IDC] bit.
 435  *
 436  * Values:
 437  * - 0 - No interrupt
 438  * - 1 - Interrupt occurred
 439  */
 440 /*@{*/
 441 #define BP_MCM_ISCR_FIDC     (15U)         /*!< Bit position for MCM_ISCR_FIDC. */
 442 #define BM_MCM_ISCR_FIDC     (0x00008000U) /*!< Bit mask for MCM_ISCR_FIDC. */
 443 #define BS_MCM_ISCR_FIDC     (1U)          /*!< Bit field size in bits for MCM_ISCR_FIDC. */
 444
 445 /*! @brief Read current value of the MCM_ISCR_FIDC field. */
 446 #define BR_MCM_ISCR_FIDC(x)  (HW_MCM_ISCR(x).B.FIDC)
 447 /*@}*/
 448
 449 /*!
 450  * @name Register MCM_ISCR, field FIOCE[24] (RW)
 451  *
 452  * Values:
 453  * - 0 - Disable interrupt
 454  * - 1 - Enable interrupt
 455  */
 456 /*@{*/
 457 #define BP_MCM_ISCR_FIOCE    (24U)         /*!< Bit position for MCM_ISCR_FIOCE. */
 458 #define BM_MCM_ISCR_FIOCE    (0x01000000U) /*!< Bit mask for MCM_ISCR_FIOCE. */
 459 #define BS_MCM_ISCR_FIOCE    (1U)          /*!< Bit field size in bits for MCM_ISCR_FIOCE. */
 460
 461 /*! @brief Read current value of the MCM_ISCR_FIOCE field. */
 462 #define BR_MCM_ISCR_FIOCE(x) (HW_MCM_ISCR(x).B.FIOCE)
 463
 464 /*! @brief Format value for bitfield MCM_ISCR_FIOCE. */
 465 #define BF_MCM_ISCR_FIOCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FIOCE) & BM_MCM_ISCR_FIOCE)
 466
 467 /*! @brief Set the FIOCE field to a new value. */
 468 #define BW_MCM_ISCR_FIOCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FIOCE) | BF_MCM_ISCR_FIOCE(v)))
 469 /*@}*/
 470
 471 /*!
 472  * @name Register MCM_ISCR, field FDZCE[25] (RW)
 473  *
 474  * Values:
 475  * - 0 - Disable interrupt
 476  * - 1 - Enable interrupt
 477  */
 478 /*@{*/
 479 #define BP_MCM_ISCR_FDZCE    (25U)         /*!< Bit position for MCM_ISCR_FDZCE. */
 480 #define BM_MCM_ISCR_FDZCE    (0x02000000U) /*!< Bit mask for MCM_ISCR_FDZCE. */
 481 #define BS_MCM_ISCR_FDZCE    (1U)          /*!< Bit field size in bits for MCM_ISCR_FDZCE. */
 482
 483 /*! @brief Read current value of the MCM_ISCR_FDZCE field. */
 484 #define BR_MCM_ISCR_FDZCE(x) (HW_MCM_ISCR(x).B.FDZCE)
 485
 486 /*! @brief Format value for bitfield MCM_ISCR_FDZCE. */
 487 #define BF_MCM_ISCR_FDZCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FDZCE) & BM_MCM_ISCR_FDZCE)
 488
 489 /*! @brief Set the FDZCE field to a new value. */
 490 #define BW_MCM_ISCR_FDZCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FDZCE) | BF_MCM_ISCR_FDZCE(v)))
 491 /*@}*/
 492
 493 /*!
 494  * @name Register MCM_ISCR, field FOFCE[26] (RW)
 495  *
 496  * Values:
 497  * - 0 - Disable interrupt
 498  * - 1 - Enable interrupt
 499  */
 500 /*@{*/
 501 #define BP_MCM_ISCR_FOFCE    (26U)         /*!< Bit position for MCM_ISCR_FOFCE. */
 502 #define BM_MCM_ISCR_FOFCE    (0x04000000U) /*!< Bit mask for MCM_ISCR_FOFCE. */
 503 #define BS_MCM_ISCR_FOFCE    (1U)          /*!< Bit field size in bits for MCM_ISCR_FOFCE. */
 504
 505 /*! @brief Read current value of the MCM_ISCR_FOFCE field. */
 506 #define BR_MCM_ISCR_FOFCE(x) (HW_MCM_ISCR(x).B.FOFCE)
 507
 508 /*! @brief Format value for bitfield MCM_ISCR_FOFCE. */
 509 #define BF_MCM_ISCR_FOFCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FOFCE) & BM_MCM_ISCR_FOFCE)
 510
 511 /*! @brief Set the FOFCE field to a new value. */
 512 #define BW_MCM_ISCR_FOFCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FOFCE) | BF_MCM_ISCR_FOFCE(v)))
 513 /*@}*/
 514
 515 /*!
 516  * @name Register MCM_ISCR, field FUFCE[27] (RW)
 517  *
 518  * Values:
 519  * - 0 - Disable interrupt
 520  * - 1 - Enable interrupt
 521  */
 522 /*@{*/
 523 #define BP_MCM_ISCR_FUFCE    (27U)         /*!< Bit position for MCM_ISCR_FUFCE. */
 524 #define BM_MCM_ISCR_FUFCE    (0x08000000U) /*!< Bit mask for MCM_ISCR_FUFCE. */
 525 #define BS_MCM_ISCR_FUFCE    (1U)          /*!< Bit field size in bits for MCM_ISCR_FUFCE. */
 526
 527 /*! @brief Read current value of the MCM_ISCR_FUFCE field. */
 528 #define BR_MCM_ISCR_FUFCE(x) (HW_MCM_ISCR(x).B.FUFCE)
 529
 530 /*! @brief Format value for bitfield MCM_ISCR_FUFCE. */
 531 #define BF_MCM_ISCR_FUFCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FUFCE) & BM_MCM_ISCR_FUFCE)
 532
 533 /*! @brief Set the FUFCE field to a new value. */
 534 #define BW_MCM_ISCR_FUFCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FUFCE) | BF_MCM_ISCR_FUFCE(v)))
 535 /*@}*/
 536
 537 /*!
 538  * @name Register MCM_ISCR, field FIXCE[28] (RW)
 539  *
 540  * Values:
 541  * - 0 - Disable interrupt
 542  * - 1 - Enable interrupt
 543  */
 544 /*@{*/
 545 #define BP_MCM_ISCR_FIXCE    (28U)         /*!< Bit position for MCM_ISCR_FIXCE. */
 546 #define BM_MCM_ISCR_FIXCE    (0x10000000U) /*!< Bit mask for MCM_ISCR_FIXCE. */
 547 #define BS_MCM_ISCR_FIXCE    (1U)          /*!< Bit field size in bits for MCM_ISCR_FIXCE. */
 548
 549 /*! @brief Read current value of the MCM_ISCR_FIXCE field. */
 550 #define BR_MCM_ISCR_FIXCE(x) (HW_MCM_ISCR(x).B.FIXCE)
 551
 552 /*! @brief Format value for bitfield MCM_ISCR_FIXCE. */
 553 #define BF_MCM_ISCR_FIXCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FIXCE) & BM_MCM_ISCR_FIXCE)
 554
 555 /*! @brief Set the FIXCE field to a new value. */
 556 #define BW_MCM_ISCR_FIXCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FIXCE) | BF_MCM_ISCR_FIXCE(v)))
 557 /*@}*/
 558
 559 /*!
 560  * @name Register MCM_ISCR, field FIDCE[31] (RW)
 561  *
 562  * Values:
 563  * - 0 - Disable interrupt
 564  * - 1 - Enable interrupt
 565  */
 566 /*@{*/
 567 #define BP_MCM_ISCR_FIDCE    (31U)         /*!< Bit position for MCM_ISCR_FIDCE. */
 568 #define BM_MCM_ISCR_FIDCE    (0x80000000U) /*!< Bit mask for MCM_ISCR_FIDCE. */
 569 #define BS_MCM_ISCR_FIDCE    (1U)          /*!< Bit field size in bits for MCM_ISCR_FIDCE. */
 570
 571 /*! @brief Read current value of the MCM_ISCR_FIDCE field. */
 572 #define BR_MCM_ISCR_FIDCE(x) (HW_MCM_ISCR(x).B.FIDCE)
 573
 574 /*! @brief Format value for bitfield MCM_ISCR_FIDCE. */
 575 #define BF_MCM_ISCR_FIDCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FIDCE) & BM_MCM_ISCR_FIDCE)
 576
 577 /*! @brief Set the FIDCE field to a new value. */
 578 #define BW_MCM_ISCR_FIDCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FIDCE) | BF_MCM_ISCR_FIDCE(v)))
 579 /*@}*/
 580
 581 /*******************************************************************************
 582  * HW_MCM_CPO - Compute Operation Control Register
 583  ******************************************************************************/
 584
 585 /*!
 586  * @brief HW_MCM_CPO - Compute Operation Control Register (RW)
 587  *
 588  * Reset value: 0x00000000U
 589  *
 590  * This register controls the Compute Operation.
 591  */
 592 typedef union _hw_mcm_cpo
 593 {
 594     uint32_t U;
 595     struct _hw_mcm_cpo_bitfields
 596     {
 597         uint32_t CPOREQ : 1;           /*!< [0] Compute Operation request */
 598         uint32_t CPOACK : 1;           /*!< [1] Compute Operation acknowledge */
 599         uint32_t CPOWOI : 1;           /*!< [2] Compute Operation wakeup on interrupt */
 600         uint32_t RESERVED0 : 29;       /*!< [31:3]  */
 601     } B;
 602 } hw_mcm_cpo_t;
 603
 604 /*!
 605  * @name Constants and macros for entire MCM_CPO register
 606  */
 607 /*@{*/
 608 #define HW_MCM_CPO_ADDR(x)       ((x) + 0x40U)
 609
 610 #define HW_MCM_CPO(x)            (*(__IO hw_mcm_cpo_t *) HW_MCM_CPO_ADDR(x))
 611 #define HW_MCM_CPO_RD(x)         (HW_MCM_CPO(x).U)
 612 #define HW_MCM_CPO_WR(x, v)      (HW_MCM_CPO(x).U = (v))
 613 #define HW_MCM_CPO_SET(x, v)     (HW_MCM_CPO_WR(x, HW_MCM_CPO_RD(x) |  (v)))
 614 #define HW_MCM_CPO_CLR(x, v)     (HW_MCM_CPO_WR(x, HW_MCM_CPO_RD(x) & ~(v)))
 615 #define HW_MCM_CPO_TOG(x, v)     (HW_MCM_CPO_WR(x, HW_MCM_CPO_RD(x) ^  (v)))
 616 /*@}*/
 617
 618 /*
 619  * Constants & macros for individual MCM_CPO bitfields
 620  */
 621
 622 /*!
 623  * @name Register MCM_CPO, field CPOREQ[0] (RW)
 624  *
 625  * This bit is auto-cleared by vector fetching if CPOWOI = 1.
 626  *
 627  * Values:
 628  * - 0 - Request is cleared.
 629  * - 1 - Request Compute Operation.
 630  */
 631 /*@{*/
 632 #define BP_MCM_CPO_CPOREQ    (0U)          /*!< Bit position for MCM_CPO_CPOREQ. */
 633 #define BM_MCM_CPO_CPOREQ    (0x00000001U) /*!< Bit mask for MCM_CPO_CPOREQ. */
 634 #define BS_MCM_CPO_CPOREQ    (1U)          /*!< Bit field size in bits for MCM_CPO_CPOREQ. */
 635
 636 /*! @brief Read current value of the MCM_CPO_CPOREQ field. */
 637 #define BR_MCM_CPO_CPOREQ(x) (HW_MCM_CPO(x).B.CPOREQ)
 638
 639 /*! @brief Format value for bitfield MCM_CPO_CPOREQ. */
 640 #define BF_MCM_CPO_CPOREQ(v) ((uint32_t)((uint32_t)(v) << BP_MCM_CPO_CPOREQ) & BM_MCM_CPO_CPOREQ)
 641
 642 /*! @brief Set the CPOREQ field to a new value. */
 643 #define BW_MCM_CPO_CPOREQ(x, v) (HW_MCM_CPO_WR(x, (HW_MCM_CPO_RD(x) & ~BM_MCM_CPO_CPOREQ) | BF_MCM_CPO_CPOREQ(v)))
 644 /*@}*/
 645
 646 /*!
 647  * @name Register MCM_CPO, field CPOACK[1] (RO)
 648  *
 649  * Values:
 650  * - 0 - Compute operation entry has not completed or compute operation exit has
 651  *     completed.
 652  * - 1 - Compute operation entry has completed or compute operation exit has not
 653  *     completed.
 654  */
 655 /*@{*/
 656 #define BP_MCM_CPO_CPOACK    (1U)          /*!< Bit position for MCM_CPO_CPOACK. */
 657 #define BM_MCM_CPO_CPOACK    (0x00000002U) /*!< Bit mask for MCM_CPO_CPOACK. */
 658 #define BS_MCM_CPO_CPOACK    (1U)          /*!< Bit field size in bits for MCM_CPO_CPOACK. */
 659
 660 /*! @brief Read current value of the MCM_CPO_CPOACK field. */
 661 #define BR_MCM_CPO_CPOACK(x) (HW_MCM_CPO(x).B.CPOACK)
 662 /*@}*/
 663
 664 /*!
 665  * @name Register MCM_CPO, field CPOWOI[2] (RW)
 666  *
 667  * Values:
 668  * - 0 - No effect.
 669  * - 1 - When set, the CPOREQ is cleared on any interrupt or exception vector
 670  *     fetch.
 671  */
 672 /*@{*/
 673 #define BP_MCM_CPO_CPOWOI    (2U)          /*!< Bit position for MCM_CPO_CPOWOI. */
 674 #define BM_MCM_CPO_CPOWOI    (0x00000004U) /*!< Bit mask for MCM_CPO_CPOWOI. */
 675 #define BS_MCM_CPO_CPOWOI    (1U)          /*!< Bit field size in bits for MCM_CPO_CPOWOI. */
 676
 677 /*! @brief Read current value of the MCM_CPO_CPOWOI field. */
 678 #define BR_MCM_CPO_CPOWOI(x) (HW_MCM_CPO(x).B.CPOWOI)
 679
 680 /*! @brief Format value for bitfield MCM_CPO_CPOWOI. */
 681 #define BF_MCM_CPO_CPOWOI(v) ((uint32_t)((uint32_t)(v) << BP_MCM_CPO_CPOWOI) & BM_MCM_CPO_CPOWOI)
 682
 683 /*! @brief Set the CPOWOI field to a new value. */
 684 #define BW_MCM_CPO_CPOWOI(x, v) (HW_MCM_CPO_WR(x, (HW_MCM_CPO_RD(x) & ~BM_MCM_CPO_CPOWOI) | BF_MCM_CPO_CPOWOI(v)))
 685 /*@}*/
 686
 687 /*******************************************************************************
 688  * hw_mcm_t - module struct
 689  ******************************************************************************/
 690 /*!
 691  * @brief All MCM module registers.
 692  */
 693 #pragma pack(1)
 694 typedef struct _hw_mcm
 695 {
 696     uint8_t _reserved0[8];
 697     __I hw_mcm_plasc_t PLASC;              /*!< [0x8] Crossbar Switch (AXBS) Slave Configuration */
 698     __I hw_mcm_plamc_t PLAMC;              /*!< [0xA] Crossbar Switch (AXBS) Master Configuration */
 699     __IO hw_mcm_placr_t PLACR;             /*!< [0xC] Crossbar Switch (AXBS) Control Register */
 700     __IO hw_mcm_iscr_t ISCR;               /*!< [0x10] Interrupt Status and Control Register */
 701     uint8_t _reserved1[44];
 702     __IO hw_mcm_cpo_t CPO;                 /*!< [0x40] Compute Operation Control Register */
 703 } hw_mcm_t;
 704 #pragma pack()
 705
 706 /*! @brief Macro to access all MCM registers. */
 707 /*! @param x MCM module instance base address. */
 708 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
 709  *     use the '&' operator, like <code>&HW_MCM(MCM_BASE)</code>. */
 710 #define HW_MCM(x)      (*(hw_mcm_t *)(x))
 711
 712 #endif /* __HW_MCM_REGISTERS_H__ */
 713 /* EOF */