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git.gir.st - tmk_keyboard.git/blob - tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/system_LPC11U6x.c
1 /**************************************************************************//**
2 * @file system_LPC11U6x.c
3 * @brief CMSIS Cortex-M3 Device System Source File for
4 * NXP LPC11U6x Device Series
9 * Copyright (C) 2013 ARM Limited. All rights reserved.
12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
13 * processor based microcontrollers. This file can be freely distributed
14 * within development tools that are supporting such ARM based processors.
17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23 ******************************************************************************/
30 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
33 /*- SystemCoreClock Configuration -------------------------------------------*/
34 // <e0> SystemCoreClock Configuration
37 // <h> System Oscillator Control (SYSOSCCTRL)
38 // <o.0> BYPASS: System Oscillator Bypass Enable
39 // <i> If enabled then PLL input (sys_osc_clk) is fed
40 // <i> directly from XTALIN and XTALOUT pins.
41 // <o.1> FREQRANGE: System Oscillator Frequency Range
42 // <i> Determines frequency range for Low-power oscillator.
46 #define SYSOSCCTRL_Val 0x00000000 // Reset value: 0x000
48 // <o.0..1> System PLL Clock Source Select (SYSPLLCLKSEL)
49 // <0=> IRC Oscillator
50 // <1=> Crystal Oscillator (SYSOSC)
51 // <3=> RTC Oscillator (32 kHz)
52 #define SYSPLLCLKSEL_Val 0x00000001 // Reset value: 0x000
54 // <e> Clock Configuration (Manual)
55 #define CLOCK_SETUP_REG 1
57 // <h> WD Oscillator Setting (WDTOSCCTRL)
58 // <o.0..4> DIVSEL: Select Divider for Fclkana
59 // <i> wd_osc_clk = Fclkana / (2 × (1 + DIVSEL))
61 // <o.5..8> FREQSEL: Select WD Oscillator Analog Output Frequency (Fclkana)
78 #define WDTOSCCTRL_Val 0x000000A0 // Reset value: 0x0A0
80 // <h> System PLL Setting (SYSPLLCTRL)
81 // <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
82 // <i> F_clkin must be in the range of 10 MHz to 25 MHz
83 // <i> F_CCO must be in the range of 156 MHz to 320 MHz
84 // <o.0..4> MSEL: Feedback Divider Selection
87 // <o.5..6> PSEL: Post Divider Selection
88 // <i> Post divider ratio P. Division ratio is 2 * P
94 #define SYSPLLCTRL_Val 0x00000023 // Reset value: 0x000
96 // <o.0..1> Main Clock Source Select (MAINCLKSEL)
97 // <0=> IRC Oscillator
101 #define MAINCLKSEL_Val 0x00000003 // Reset value: 0x000
103 // <o.0..7> System AHB Clock Divider (SYSAHBCLKDIV.DIV)
104 // <i> Divides main clock to provide system clock to core, memories, and peripherals.
105 // <i> 0 = is disabled
107 #define SYSAHBCLKDIV_Val 0x00000001 // Reset value: 0x001
110 // <e> Clock Configuration (via ROM PLL API)
111 #define CLOCK_SETUP_API 0
113 // <o> PLL API Mode Select
115 // <1=> Less than or equal
116 // <2=> Greater than or equal
117 // <3=> As close as possible
118 #define PLL_API_MODE_Val 0
120 // <o> CPU Frequency [Hz] <1000000-50000000:1000>
121 #define PLL_API_FREQ_Val 48000000
124 // <e> USB Clock Configuration
125 #define USB_CLOCK_SETUP 1
126 // <h> USB PLL Control (USBPLLCTRL)
127 // <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
128 // <i> F_clkin must be in the range of 10 MHz to 25 MHz
129 // <i> F_CCO must be in the range of 156 MHz to 320 MHz
130 // <o.0..4> MSEL: Feedback Divider Selection
133 // <o.5..6> PSEL: Post Divider Selection
134 // <i> Post divider ratio P. Division ratio is 2 * P
140 #define USBPLLCTRL_Val 0x00000023 // Reset value: 0x000
142 // <o.0..1> USB PLL Clock Source Select (USBPLLCLKSEL.SEL)
143 // <i> USB PLL clock source must be switched to System Oscillator for correct USB operation
144 // <0=> IRC Oscillator
145 // <1=> System Oscillator
146 #define USBPLLCLKSEL_Val 0x00000001 // Reset value: 0x000
148 // <o.0..1> USB Clock Source Select (USBCLKSEL.SEL)
151 #define USBCLKSEL_Val 0x00000000 // Reset value: 0x000
153 // <o.0..7> USB Clock Divider (USBCLKDIV.DIV)
154 // <i> Divides USB clock to 48 MHz.
155 // <i> 0 = is disabled
157 #define USBCLKDIV_Val 0x00000001 // Reset Value: 0x001
162 // <o0>System Oscillator (XTAL) Frequency [Hz] <1000000-25000000>
163 // <i> XTAL frequency must be in the range of 1 MHz to 25 MHz
165 #define XTAL_CLK_Val 12000000
168 //-------- <<< end of configuration section >>> ------------------------------
171 /*----------------------------------------------------------------------------
173 *----------------------------------------------------------------------------*/
174 #define __XTAL_CLK ( XTAL_CLK_Val) /* Oscillator freq */
175 #define __SYS_OSC_CLK ( __XTAL_CLK) /* System oscillator freq */
176 #define __IRC_OSC_CLK ( 12000000UL) /* Internal RC oscillator freq */
177 #define __RTC_OSC_CLK ( 32768UL) /* RTC oscillator freq */
179 /*----------------------------------------------------------------------------
180 Check the register settings
181 *----------------------------------------------------------------------------*/
182 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
183 #define CHECK_RSVD(val, mask) (val & mask)
185 #if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
186 #error "SYSOSCCTRL: Invalid values of reserved bits!"
189 #if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
190 #error "WDTOSCCTRL: Invalid values of reserved bits!"
193 #if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3))
194 #error "SYSPLLCLKSEL: Value out of range!"
197 #if (SYSPLLCLKSEL_Val == 3) // RTC Oscillator used as PLL input
198 #if (CLOCK_SETUP_API == 1)
199 #error "SYSPLLCLKSEL: RTC oscillator not allowed as PLL clock source!"
201 #if (CLOCK_SETUP_REG == 1) && (MAINCLKSEL_Val == 3) // RTC Oscillator used as PLL input
202 #error "SYSPLLCLKSEL: RTC oscillator not allowed as PLL clock source!"
206 #if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x0000007F))
207 #error "SYSPLLCTRL: Invalid values of reserved bits!"
210 #if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
211 #error "MAINCLKSEL: Invalid values of reserved bits!"
214 #if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
215 #error "SYSAHBCLKDIV: Value out of range!"
218 #if ( CLOCK_SETUP_REG == CLOCK_SETUP_API )
219 #error "You must select either manual or API based Clock Configuration!"
222 #if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
223 #error "USBPLLCLKSEL: Value out of range!"
226 #if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000007F))
227 #error "USBPLLCTRL: Invalid values of reserved bits!"
230 #if (CHECK_RANGE((USBCLKSEL_Val), 0, 1))
231 #error "USBCLKSEL: Value out of range!"
234 #if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))
235 #error "USBCLKDIV: Value out of range!"
238 #if (CHECK_RANGE(XTAL_CLK_Val, 1000000, 25000000))
239 #error "XTAL frequency is out of bounds"
242 #if (CHECK_RANGE(PLL_API_MODE_Val, 0, 3))
243 #error "PLL API Mode Select not valid"
246 #if (CHECK_RANGE(PLL_API_FREQ_Val, 1000000, 50000000))
247 #error "CPU Frequency (API mode) not valid"
252 /*----------------------------------------------------------------------------
253 Calculate system core clock
254 *----------------------------------------------------------------------------*/
255 #if (CLOCK_SETUP) /* Clock Setup */
257 /* sys_pllclkin calculation */
258 #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
259 #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
260 #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
261 #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
262 #elif ((SYSPLLCLKSEL_Val & 0x03) == 3)
263 #define __SYS_PLLCLKIN (__RTC_OSC_CLK)
268 #if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */
270 #define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
271 #define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
274 #error "WDTOSCCTRL.FREQSEL undefined!"
275 #elif (__FREQSEL == 1)
276 #define __OSC_CLK ( 500000 / __DIVSEL)
277 #elif (__FREQSEL == 2)
278 #define __OSC_CLK ( 800000 / __DIVSEL)
279 #elif (__FREQSEL == 3)
280 #define __OSC_CLK (1100000 / __DIVSEL)
281 #elif (__FREQSEL == 4)
282 #define __OSC_CLK (1400000 / __DIVSEL)
283 #elif (__FREQSEL == 5)
284 #define __OSC_CLK (1600000 / __DIVSEL)
285 #elif (__FREQSEL == 6)
286 #define __OSC_CLK (1800000 / __DIVSEL)
287 #elif (__FREQSEL == 7)
288 #define __OSC_CLK (2000000 / __DIVSEL)
289 #elif (__FREQSEL == 8)
290 #define __OSC_CLK (2200000 / __DIVSEL)
291 #elif (__FREQSEL == 9)
292 #define __OSC_CLK (2400000 / __DIVSEL)
293 #elif (__FREQSEL == 10)
294 #define __OSC_CLK (2600000 / __DIVSEL)
295 #elif (__FREQSEL == 11)
296 #define __OSC_CLK (2700000 / __DIVSEL)
297 #elif (__FREQSEL == 12)
298 #define __OSC_CLK (2900000 / __DIVSEL)
299 #elif (__FREQSEL == 13)
300 #define __OSC_CLK (3100000 / __DIVSEL)
301 #elif (__FREQSEL == 14)
302 #define __OSC_CLK (3200000 / __DIVSEL)
304 #define __OSC_CLK (3400000 / __DIVSEL)
307 #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
309 /* main clock calculation */
310 #if ((MAINCLKSEL_Val & 0x03) == 0)
311 #define __MAIN_CLOCK (__IRC_OSC_CLK)
312 #elif ((MAINCLKSEL_Val & 0x03) == 1)
313 #define __MAIN_CLOCK (__SYS_PLLCLKIN)
314 #elif ((MAINCLKSEL_Val & 0x03) == 2)
315 #define __MAIN_CLOCK (__OSC_CLK)
316 #elif ((MAINCLKSEL_Val & 0x03) == 3)
317 #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
322 #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
323 #endif /* Clock Setup via Register */
325 #if (CLOCK_SETUP_API == 1) /* Clock Setup via ROM API */
326 #define __SYSTEM_CLOCK (PLL_API_FREQ_Val)
327 #endif /* Clock Setup via PLL API */
330 #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
331 #endif /* CLOCK_SETUP */
335 #if ((CLOCK_SETUP == 1) && (CLOCK_SETUP_API == 1)) /* PLL Setup via PLL API */
336 #include "power_api.h"
338 typedef struct _ROM
{
339 const unsigned p_dev0
;
340 const unsigned p_dev1
;
341 const unsigned p_dev2
;
342 const PWRD
* pPWRD
; /* ROM Power Management API */
343 const unsigned p_dev4
;
344 const unsigned p_dev5
;
345 const unsigned p_dev6
;
346 const unsigned p_dev7
;
349 /*----------------------------------------------------------------------------
351 *----------------------------------------------------------------------------*/
352 static void setPLL(const uint32_t pllMode
, const uint32_t pllInFreq
, const uint32_t reqCpuFreq
)
354 uint32_t cmd
[5], res
[5];
355 ROM
** rom
= (ROM
**) 0x1FFF1FF8; /* pointer to power API calls */
357 cmd
[0] = pllInFreq
; /* PLL's input freq in KHz */
358 cmd
[1] = reqCpuFreq
; /* requested CPU freq in KHz */
360 cmd
[3] = 0; /* no timeout for PLL to lock */
362 /* Execute API call */
363 (*rom
)->pPWRD
->set_pll(cmd
, res
); /* call API function */
364 if ((res
[0] != PLL_CMD_SUCCESS
)){ /* in case of an error ... */
365 while(1); /* ... stay here */
373 /*----------------------------------------------------------------------------
374 Clock Variable definitions
375 *----------------------------------------------------------------------------*/
376 uint32_t SystemCoreClock
= __SYSTEM_CLOCK
; /* System Clock Frequency */
379 /*----------------------------------------------------------------------------
381 *----------------------------------------------------------------------------*/
382 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
386 /* Determine clock frequency according to clock register values */
387 switch ((LPC_SYSCON
->WDTOSCCTRL
>> 5) & 0x0F) {
388 case 0: oscClk
= 0; break;
389 case 1: oscClk
= 500000; break;
390 case 2: oscClk
= 800000; break;
391 case 3: oscClk
= 1100000; break;
392 case 4: oscClk
= 1400000; break;
393 case 5: oscClk
= 1600000; break;
394 case 6: oscClk
= 1800000; break;
395 case 7: oscClk
= 2000000; break;
396 case 8: oscClk
= 2200000; break;
397 case 9: oscClk
= 2400000; break;
398 case 10: oscClk
= 2600000; break;
399 case 11: oscClk
= 2700000; break;
400 case 12: oscClk
= 2900000; break;
401 case 13: oscClk
= 3100000; break;
402 case 14: oscClk
= 3200000; break;
403 case 15: oscClk
= 3400000; break;
405 oscClk
/= ((LPC_SYSCON
->WDTOSCCTRL
& 0x1F) << 1) + 2;
407 switch (LPC_SYSCON
->MAINCLKSEL
& 0x03) {
408 case 0: /* Internal RC oscillator */
409 SystemCoreClock
= __IRC_OSC_CLK
;
411 case 1: /* Input Clock to System PLL */
412 switch (LPC_SYSCON
->SYSPLLCLKSEL
& 0x03) {
413 case 0: /* Internal RC oscillator */
414 SystemCoreClock
= __IRC_OSC_CLK
;
416 case 1: /* System oscillator */
417 SystemCoreClock
= __SYS_OSC_CLK
;
419 case 2: /* Reserved */
420 case 3: /* Reserved */
425 case 2: /* WDT Oscillator */
426 SystemCoreClock
= oscClk
;
428 case 3: /* System PLL Clock Out */
429 switch (LPC_SYSCON
->SYSPLLCLKSEL
& 0x03) {
430 case 0: /* Internal RC oscillator */
431 SystemCoreClock
= __IRC_OSC_CLK
* ((LPC_SYSCON
->SYSPLLCTRL
& 0x01F) + 1);
433 case 1: /* System oscillator */
434 SystemCoreClock
= __SYS_OSC_CLK
* ((LPC_SYSCON
->SYSPLLCTRL
& 0x01F) + 1);
436 case 2: /* Reserved */
437 case 3: /* Reserved */
444 SystemCoreClock
/= LPC_SYSCON
->SYSAHBCLKDIV
;
448 #define PDRUN_VALID_BITS 0x000025FFL
449 #define PDRUN_RESERVED_ONE 0x0000C800L
451 static void power_down_config(uint32_t val
)
453 volatile uint32_t tmp
;
454 tmp
= (LPC_SYSCON
->PDRUNCFG
& PDRUN_VALID_BITS
);
455 tmp
|= (val
& PDRUN_VALID_BITS
);
456 LPC_SYSCON
->PDRUNCFG
= (tmp
| PDRUN_RESERVED_ONE
);
459 static void power_up_config(uint32_t val
)
461 volatile uint32_t tmp
;
462 tmp
= (LPC_SYSCON
->PDRUNCFG
& PDRUN_VALID_BITS
);
463 tmp
&= ~(val
& PDRUN_VALID_BITS
);
464 LPC_SYSCON
->PDRUNCFG
= (tmp
| PDRUN_RESERVED_ONE
);
468 * Initialize the system
473 * @brief Setup the microcontroller system.
475 void SystemInit (void) {
479 LPC_SYSCON
->SYSAHBCLKCTRL
|= (1<<16);
480 LPC_SYSCON
->SYSPLLCTRL
= SYSPLLCTRL_Val
;
482 #if (CLOCK_SETUP) /* Clock Setup */
484 #if ((SYSPLLCLKSEL_Val & 0x03) == 1)
485 // Initialize XTALIN/XTALOUT pins
486 LPC_IOCON
->PIO2_0
= 0x01;
487 LPC_IOCON
->PIO2_1
= 0x01;
489 LPC_SYSCON
->SYSOSCCTRL
= SYSOSCCTRL_Val
;
490 power_up_config(1<<5); /* Power-up sysosc */
491 for (i
= 0; i
< 2500; i
++) __NOP(); /* Wait for osc to stabilize */
494 #if ((SYSPLLCLKSEL_Val & 0x03) == 3)
495 LPC_SYSCON
->RTCOSCCTRL
= (1 << 0); /* Enable 32 kHz output */
496 for (i
= 0; i
< 200; i
++) __NOP(); /* Wait for osc to stabilize */
499 LPC_SYSCON
->SYSPLLCLKSEL
= SYSPLLCLKSEL_Val
; /* Select PLL Input */
500 LPC_SYSCON
->SYSPLLCLKUEN
= 0x01; /* Update Clock Source */
501 LPC_SYSCON
->SYSPLLCLKUEN
= 0x00; /* Toggle Update Register */
502 LPC_SYSCON
->SYSPLLCLKUEN
= 0x01;
503 while (!(LPC_SYSCON
->SYSPLLCLKUEN
& 0x01)); /* Wait Until Updated */
505 #if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */
507 #if (((MAINCLKSEL_Val & 0x03) == 2) )
508 LPC_SYSCON
->WDTOSCCTRL
= WDTOSCCTRL_Val
;
509 LPC_SYSCON
->PDRUNCFG
&= ~(1 << 6); /* Power-up WDT Clock */
510 for (i
= 0; i
< 2000; i
++) __NOP(); /* Wait for osc to stabilize */
513 #if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
514 power_down_config(1<<7); /* Power-down SYSPLL */
515 LPC_SYSCON
->SYSPLLCTRL
= SYSPLLCTRL_Val
;
516 power_up_config(1<<7); /* Power-up SYSPLL */
517 while (!(LPC_SYSCON
->SYSPLLSTAT
& 0x01)); /* Wait Until PLL Locked */
520 LPC_SYSCON
->MAINCLKSEL
= MAINCLKSEL_Val
; /* Select Clock Source */
521 LPC_SYSCON
->MAINCLKUEN
= 0x01; /* Update MCLK Clock Source */
522 LPC_SYSCON
->MAINCLKUEN
= 0x00; /* Toggle Update Register */
523 LPC_SYSCON
->MAINCLKUEN
= 0x01;
524 while (!(LPC_SYSCON
->MAINCLKUEN
& 0x01)); /* Wait Until Updated */
526 LPC_SYSCON
->SYSAHBCLKDIV
= SYSAHBCLKDIV_Val
;
527 #endif /* Clock Setup via Register */
529 #if (CLOCK_SETUP_API == 1) /* Clock Setup via PLL API */
530 // LPC_SYSCON->SYSPLLCLKSEL = 0x00; /* Use IRC */
531 // LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
532 // LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */
533 // LPC_SYSCON->SYSPLLCLKUEN = 0x01;
534 // while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
536 LPC_SYSCON
->MAINCLKSEL
= SYSPLLCLKSEL_Val
; /* Select same as SYSPLL */
537 LPC_SYSCON
->MAINCLKUEN
= 0x01; /* Update MCLK Clock Source */
538 LPC_SYSCON
->MAINCLKUEN
= 0x00; /* Toggle Update Register */
539 LPC_SYSCON
->MAINCLKUEN
= 0x01;
540 while (!(LPC_SYSCON
->MAINCLKUEN
& 0x01)); /* Wait Until Updated */
542 LPC_SYSCON
->SYSAHBCLKDIV
= 1;
544 setPLL(PLL_API_MODE_Val
, __SYS_PLLCLKIN
/ 1000, PLL_API_FREQ_Val
/ 1000);
545 #endif /* Clock Setup via PLL API */
547 #if (USB_CLOCK_SETUP == 1) /* USB clock is used */
548 LPC_SYSCON
->PDRUNCFG
&= ~(1 << 10); /* Power-up USB PHY */
550 #if ((USBCLKSEL_Val & 0x003) == 0) /* USB clock is USB PLL out */
551 LPC_SYSCON
->PDRUNCFG
&= ~(1 << 8); /* Power-up USB PLL */
552 LPC_SYSCON
->USBPLLCLKSEL
= USBPLLCLKSEL_Val
; /* Select PLL Input */
553 LPC_SYSCON
->USBPLLCLKUEN
= 0x01; /* Update Clock Source */
554 LPC_SYSCON
->USBPLLCLKUEN
= 0x00; /* Toggle Update Register */
555 LPC_SYSCON
->USBPLLCLKUEN
= 0x01;
556 while (!(LPC_SYSCON
->USBPLLCLKUEN
& 0x01)); /* Wait Until Updated */
558 LPC_SYSCON
->USBPLLCTRL
= USBPLLCTRL_Val
;
559 while (!(LPC_SYSCON
->USBPLLSTAT
& 0x01)); /* Wait Until PLL Locked */
561 LPC_SYSCON
->USBCLKSEL
= 0x00; /* Select USB PLL */
564 LPC_SYSCON
->USBCLKSEL
= USBCLKSEL_Val
; /* Select USB Clock */
565 LPC_SYSCON
->USBCLKDIV
= USBCLKDIV_Val
; /* Set USB clock divider */
567 #else /* USB clock is not used */
568 LPC_SYSCON
->PDRUNCFG
|= (1 << 10); /* Power-down USB PHY */
569 LPC_SYSCON
->PDRUNCFG
|= (1 << 8); /* Power-down USB PLL */
572 #endif /* Clock Setup */