1 ;/*****************************************************************************
2 ; * @file: startup_LPC17xx.s
3 ; * @purpose: CMSIS Cortex-M3 Core Device Startup File
4 ; * for the NXP LPC17xx Device Series
6 ; * @date: 09. February 2010
7 ; *----------------------------------------------------------------------------
9 ; * Copyright (C) 2010 ARM Limited. All rights reserved.
11 ; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
12 ; * processor based microcontrollers. This file can be freely distributed
13 ; * within development tools that are supporting such ARM based processors.
15 ; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
16 ; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
17 ; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
18 ; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
19 ; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
21 ; ******************************************************************************/
25 ; The modules in this file are included in the libraries, and may be replaced
26 ; by any user-defined modules that define the PUBLIC symbol _program_start or
27 ; a user defined start symbol.
28 ; To override the cstartup defined in the library, simply add your modified
29 ; version to the workbench project.
31 ; The vector table is normally located at address 0.
32 ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
33 ; The name "__vector_table" has special meaning for C-SPY:
34 ; it is where the SP start value is found, and the NVIC vector
35 ; table register (VTOR) is initialized to this address if != 0.
42 ;; Forward declaration of sections.
43 SECTION CSTACK:DATA:NOROOT(3)
45 SECTION .intvec:CODE:NOROOT(2)
47 EXTERN __iar_program_start
50 PUBLIC __vector_table_0x1c
65 DCD UsageFault_Handler
78 DCD WDT_IRQHandler ; 16: Watchdog Timer
79 DCD TIMER0_IRQHandler ; 17: Timer0
80 DCD TIMER1_IRQHandler ; 18: Timer1
81 DCD TIMER2_IRQHandler ; 19: Timer2
82 DCD TIMER3_IRQHandler ; 20: Timer3
83 DCD UART0_IRQHandler ; 21: UART0
84 DCD UART1_IRQHandler ; 22: UART1
85 DCD UART2_IRQHandler ; 23: UART2
86 DCD UART3_IRQHandler ; 24: UART3
87 DCD PWM1_IRQHandler ; 25: PWM1
88 DCD I2C0_IRQHandler ; 26: I2C0
89 DCD I2C1_IRQHandler ; 27: I2C1
90 DCD I2C2_IRQHandler ; 28: I2C2
91 DCD SPI_IRQHandler ; 29: SPI
92 DCD SSP0_IRQHandler ; 30: SSP0
93 DCD SSP1_IRQHandler ; 31: SSP1
94 DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)
95 DCD RTC_IRQHandler ; 33: Real Time Clock
96 DCD EINT0_IRQHandler ; 34: External Interrupt 0
97 DCD EINT1_IRQHandler ; 35: External Interrupt 1
98 DCD EINT2_IRQHandler ; 36: External Interrupt 2
99 DCD EINT3_IRQHandler ; 37: External Interrupt 3
100 DCD ADC_IRQHandler ; 38: A/D Converter
101 DCD BOD_IRQHandler ; 39: Brown-Out Detect
102 DCD USB_IRQHandler ; 40: USB
103 DCD CAN_IRQHandler ; 41: CAN
104 DCD DMA_IRQHandler ; 42: General Purpose DMA
105 DCD I2S_IRQHandler ; 43: I2S
106 DCD ENET_IRQHandler ; 44: Ethernet
107 DCD RIT_IRQHandler ; 45: Repetitive Interrupt Timer
108 DCD MCPWM_IRQHandler ; 46: Motor Control PWM
109 DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface
110 DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)
111 DCD USBActivity_IRQHandler ; 49: USB Activity Interrupt
112 DCD CANActivity_IRQHandler ; 50: CAN Activity Interrupt
115 __Vectors EQU __vector_table
116 __Vectors_Size EQU __Vectors_End - __Vectors
119 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
121 ;; Default interrupt handlers.
125 PUBWEAK Reset_Handler
126 SECTION .text:CODE:REORDER(2)
130 LDR R0, =__iar_program_start
134 SECTION .text:CODE:REORDER(1)
138 PUBWEAK HardFault_Handler
139 SECTION .text:CODE:REORDER(1)
143 PUBWEAK MemManage_Handler
144 SECTION .text:CODE:REORDER(1)
148 PUBWEAK BusFault_Handler
149 SECTION .text:CODE:REORDER(1)
153 PUBWEAK UsageFault_Handler
154 SECTION .text:CODE:REORDER(1)
159 SECTION .text:CODE:REORDER(1)
163 PUBWEAK DebugMon_Handler
164 SECTION .text:CODE:REORDER(1)
168 PUBWEAK PendSV_Handler
169 SECTION .text:CODE:REORDER(1)
173 PUBWEAK SysTick_Handler
174 SECTION .text:CODE:REORDER(1)
178 PUBWEAK WDT_IRQHandler
179 SECTION .text:CODE:REORDER(1)
183 PUBWEAK TIMER0_IRQHandler
184 SECTION .text:CODE:REORDER(1)
188 PUBWEAK TIMER1_IRQHandler
189 SECTION .text:CODE:REORDER(1)
193 PUBWEAK TIMER2_IRQHandler
194 SECTION .text:CODE:REORDER(1)
198 PUBWEAK TIMER3_IRQHandler
199 SECTION .text:CODE:REORDER(1)
203 PUBWEAK UART0_IRQHandler
204 SECTION .text:CODE:REORDER(1)
208 PUBWEAK UART1_IRQHandler
209 SECTION .text:CODE:REORDER(1)
213 PUBWEAK UART2_IRQHandler
214 SECTION .text:CODE:REORDER(1)
218 PUBWEAK UART3_IRQHandler
219 SECTION .text:CODE:REORDER(1)
223 PUBWEAK PWM1_IRQHandler
224 SECTION .text:CODE:REORDER(1)
228 PUBWEAK I2C0_IRQHandler
229 SECTION .text:CODE:REORDER(1)
233 PUBWEAK I2C1_IRQHandler
234 SECTION .text:CODE:REORDER(1)
238 PUBWEAK I2C2_IRQHandler
239 SECTION .text:CODE:REORDER(1)
243 PUBWEAK SPI_IRQHandler
244 SECTION .text:CODE:REORDER(1)
248 PUBWEAK SSP0_IRQHandler
249 SECTION .text:CODE:REORDER(1)
253 PUBWEAK SSP1_IRQHandler
254 SECTION .text:CODE:REORDER(1)
258 PUBWEAK PLL0_IRQHandler
259 SECTION .text:CODE:REORDER(1)
263 PUBWEAK RTC_IRQHandler
264 SECTION .text:CODE:REORDER(1)
268 PUBWEAK EINT0_IRQHandler
269 SECTION .text:CODE:REORDER(1)
273 PUBWEAK EINT1_IRQHandler
274 SECTION .text:CODE:REORDER(1)
278 PUBWEAK EINT2_IRQHandler
279 SECTION .text:CODE:REORDER(1)
283 PUBWEAK EINT3_IRQHandler
284 SECTION .text:CODE:REORDER(1)
288 PUBWEAK ADC_IRQHandler
289 SECTION .text:CODE:REORDER(1)
293 PUBWEAK BOD_IRQHandler
294 SECTION .text:CODE:REORDER(1)
298 PUBWEAK USB_IRQHandler
299 SECTION .text:CODE:REORDER(1)
303 PUBWEAK CAN_IRQHandler
304 SECTION .text:CODE:REORDER(1)
308 PUBWEAK DMA_IRQHandler
309 SECTION .text:CODE:REORDER(1)
313 PUBWEAK I2S_IRQHandler
314 SECTION .text:CODE:REORDER(1)
318 PUBWEAK ENET_IRQHandler
319 SECTION .text:CODE:REORDER(1)
323 PUBWEAK RIT_IRQHandler
324 SECTION .text:CODE:REORDER(1)
328 PUBWEAK MCPWM_IRQHandler
329 SECTION .text:CODE:REORDER(1)
333 PUBWEAK QEI_IRQHandler
334 SECTION .text:CODE:REORDER(1)
338 PUBWEAK PLL1_IRQHandler
339 SECTION .text:CODE:REORDER(1)
343 PUBWEAK USBActivity_IRQHandler
344 SECTION .text:CODE:REORDER(1)
345 USBActivity_IRQHandler
346 B USBActivity_IRQHandler
348 PUBWEAK CANActivity_IRQHandler
349 SECTION .text:CODE:REORDER(1)
350 CANActivity_IRQHandler
351 B CANActivity_IRQHandler
354 SECTION .crp:CODE:ROOT(2)
356 /* Code Read Protection
357 CRP1 0x12345678 - Write to RAM command can not access RAM below 0x10000200.
358 - Read Memory command: disabled.
359 - Copy RAM to Flash command: cannot write to Sector 0.
360 - "Go" command: disabled.
361 - Erase sector(s) command: can erase any individual sector except
362 sector 0 only, or can erase all sectors at once.
363 - Compare command: disabled
364 CRP2 0x87654321 - Write to RAM command: disabled.
365 - Copy RAM to Flash: disabled.
366 - Erase command: only allows erase of all sectors.
367 CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
368 by pulling PIO0_1 LOW is disabled if a valid user code is
369 present in flash sector 0.
370 Caution: If CRP3 is selected, no future factory testing can be
371 performed on the device.