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git.gir.st - tmk_keyboard.git/blob - tmk_core/tool/mbed/mbed-sdk/libraries/net/eth/lwip-eth/arch/TARGET_Freescale/hardware_init_MK64F12.c
2 * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
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31 #include "fsl_port_hal.h"
32 #include "fsl_clock_manager.h"
33 #include "fsl_device_registers.h"
34 #include "fsl_sim_hal.h"
36 /*******************************************************************************
38 ******************************************************************************/
39 void k64f_init_eth_hardware(void)
44 BW_MPU_CESR_VLD(MPU_BASE
, 0);
46 /* Open POTR clock gate*/
47 for (count
= 0; count
< HW_PORT_INSTANCE_COUNT
; count
++)
49 CLOCK_SYS_EnablePortClock(count
);
53 PORT_HAL_SetMuxMode(PORTA_BASE
, 12, kPortMuxAlt4
); /*!< ENET RMII0_RXD1/MII0_RXD1*/
54 PORT_HAL_SetMuxMode(PORTA_BASE
, 13, kPortMuxAlt4
); /*!< ENET RMII0_RXD0/MII0_RXD0*/
55 PORT_HAL_SetMuxMode(PORTA_BASE
, 14, kPortMuxAlt4
); /*!< ENET RMII0_CRS_DV/MII0_RXDV*/
56 PORT_HAL_SetMuxMode(PORTA_BASE
, 15, kPortMuxAlt4
); /*!< ENET RMII0_TXEN/MII0_TXEN*/
57 PORT_HAL_SetMuxMode(PORTA_BASE
, 16, kPortMuxAlt4
); /*!< ENET RMII0_TXD0/MII0_TXD0*/
58 PORT_HAL_SetMuxMode(PORTA_BASE
, 17, kPortMuxAlt4
); /*!< ENET RMII0_TXD01/MII0_TXD1*/
59 PORT_HAL_SetMuxMode(PORTB_BASE
, 0, kPortMuxAlt4
); /*!< ENET RMII0_MDIO/MII0_MDIO*/
60 PORT_HAL_SetOpenDrainCmd(PORTB_BASE
,0, true); /*!< ENET RMII0_MDC/MII0_MDC*/
62 // Added for FRDM-K64F
63 PORT_HAL_SetPullMode(PORTB_BASE
, 0, kPortPullUp
);
64 PORT_HAL_SetPullCmd(PORTB_BASE
, 0, true);
66 PORT_HAL_SetMuxMode(PORTB_BASE
, 1, kPortMuxAlt4
);
67 /* Configure GPIO for MII interface */
68 PORT_HAL_SetMuxMode(PORTA_BASE
, 9, kPortMuxAlt4
); /*!< ENET MII0_RXD3*/
69 PORT_HAL_SetMuxMode(PORTA_BASE
, 10, kPortMuxAlt4
); /*!< ENET MII0_RXD2*/
70 PORT_HAL_SetMuxMode(PORTA_BASE
, 11, kPortMuxAlt4
); /*!< ENET MII0_RXCLK*/
71 PORT_HAL_SetMuxMode(PORTA_BASE
, 24, kPortMuxAlt4
); /*!< ENET MII0_TXD2*/
72 PORT_HAL_SetMuxMode(PORTA_BASE
, 25, kPortMuxAlt4
); /*!< ENET MII0_TXCLK*/
73 PORT_HAL_SetMuxMode(PORTA_BASE
, 26, kPortMuxAlt4
); /*!< ENET MII0_TXD3*/
74 PORT_HAL_SetMuxMode(PORTA_BASE
, 27, kPortMuxAlt4
); /*!< ENET MII0_CRS*/
75 PORT_HAL_SetMuxMode(PORTA_BASE
, 28, kPortMuxAlt4
); /*!< ENET MII0_TXER*/
76 PORT_HAL_SetMuxMode(PORTA_BASE
, 29, kPortMuxAlt4
); /*!< ENET MII0_COL*/
77 #if FSL_FEATURE_ENET_SUPPORT_PTP
78 PORT_HAL_SetMuxMode(PORTC_BASE
, (16 + ENET_TIMER_CHANNEL_NUM
), kPortMuxAlt4
); /* ENET ENET0_1588_TMR0*/
79 PORT_HAL_SetDriveStrengthMode(PORTC_BASE
, (16 + ENET_TIMER_CHANNEL_NUM
), kPortHighDriveStrength
);
82 /* Open ENET clock gate*/
83 CLOCK_SYS_EnableEnetClock( 0U);
85 /* Select the ptp timer outclk*/
86 CLOCK_HAL_SetSource(g_simBaseAddr
[0], kClockTimeSrc
, 2);
89 /*******************************************************************************
91 ******************************************************************************/