tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f0xx_hal_smbus.h
   4   * @author  MCD Application Team
   5   * @version V1.2.0
   6   * @date    11-December-2014
   7   * @brief   Header file of SMBUS HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32F0xx_HAL_SMBUS_H
  40 #define __STM32F0xx_HAL_SMBUS_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #include "stm32f0xx_hal_def.h"
  48
  49 /** @addtogroup STM32F0xx_HAL_Driver
  50   * @{
  51   */
  52
  53 /** @addtogroup SMBUS
  54   * @{
  55   */
  56
  57 /* Exported types ------------------------------------------------------------*/
  58 /** @defgroup SMBUS_Exported_Types SMBUS Exported Types
  59   * @{
  60   */
  61
  62 /**
  63   * @brief  SMBUS Configuration Structure definition
  64   */
  65 typedef struct
  66 {
  67   uint32_t Timing;                 /*!< Specifies the SMBUS_TIMINGR_register value.
  68                                      This parameter calculated by referring to SMBUS initialization
  69                                             section in Reference manual */
  70   uint32_t AnalogFilter;           /*!< Specifies if Analog Filter is enable or not.
  71                                      This parameter can be a a value of @ref SMBUS_Analog_Filter */
  72
  73   uint32_t OwnAddress1;            /*!< Specifies the first device own address.
  74                                      This parameter can be a 7-bit or 10-bit address. */
  75
  76   uint32_t AddressingMode;         /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
  77                                      This parameter can be a value of @ref SMBUS_addressing_mode */
  78
  79   uint32_t DualAddressMode;        /*!< Specifies if dual addressing mode is selected.
  80                                      This parameter can be a value of @ref SMBUS_dual_addressing_mode */
  81
  82   uint32_t OwnAddress2;            /*!< Specifies the second device own address if dual addressing mode is selected
  83                                      This parameter can be a 7-bit address. */
  84
  85   uint32_t OwnAddress2Masks;       /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
  86                                      This parameter can be a value of @ref SMBUS_own_address2_masks. */
  87
  88   uint32_t GeneralCallMode;        /*!< Specifies if general call mode is selected.
  89                                      This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
  90
  91   uint32_t NoStretchMode;          /*!< Specifies if nostretch mode is selected.
  92                                      This parameter can be a value of @ref SMBUS_nostretch_mode */
  93
  94   uint32_t PacketErrorCheckMode;   /*!< Specifies if Packet Error Check mode is selected.
  95                                      This parameter can be a value of @ref SMBUS_packet_error_check_mode */
  96
  97   uint32_t PeripheralMode;         /*!< Specifies which mode of Periphal is selected.
  98                                      This parameter can be a value of @ref SMBUS_peripheral_mode */
  99
 100   uint32_t SMBusTimeout;           /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
 101                                                                                                                                                 (Enable bits and different timeout values)
 102                                      This parameter calculated by referring to SMBUS initialization
 103                                          section in Reference manual */
 104 } SMBUS_InitTypeDef;
 105
 106 /**
 107   * @brief  SMBUS handle Structure definition
 108   */
 109 typedef struct
 110 {
 111   I2C_TypeDef                  *Instance;       /*!< SMBUS registers base address       */
 112
 113   SMBUS_InitTypeDef            Init;            /*!< SMBUS communication parameters     */
 114
 115   uint8_t                      *pBuffPtr;       /*!< Pointer to SMBUS transfer buffer   */
 116
 117   uint16_t                     XferSize;        /*!< SMBUS transfer size                */
 118
 119   __IO uint16_t                XferCount;       /*!< SMBUS transfer counter             */
 120
 121   __IO uint32_t                XferOptions;     /*!< SMBUS transfer options             */
 122
 123   __IO uint32_t                PreviousState;   /*!< SMBUS communication Previous state
 124                                                      This parameter can be a value of @ref SMBUS_State */
 125
 126   HAL_LockTypeDef              Lock;            /*!< SMBUS locking object               */
 127
 128   __IO uint32_t                State;           /*!< SMBUS communication state
 129                                                      This parameter can be a value of @ref SMBUS_State */
 130
 131   __IO uint32_t                ErrorCode;       /*!< SMBUS Error code
 132                                                      This parameter can be a value of @ref SMBUS_Error */
 133
 134 }SMBUS_HandleTypeDef;
 135 /**
 136   * @}
 137   */
 138
 139 /* Exported constants --------------------------------------------------------*/
 140
 141 /** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
 142   * @{
 143   */
 144
 145 /** @defgroup SMBUS_Error SMBUS Error
 146   * @{
 147   */
 148 #define HAL_SMBUS_ERROR_NONE        ((uint32_t)0x00000000)    /*!< No error             */
 149 #define HAL_SMBUS_ERROR_BERR        ((uint32_t)0x00000001)    /*!< BERR error           */
 150 #define HAL_SMBUS_ERROR_ARLO        ((uint32_t)0x00000002)    /*!< ARLO error           */
 151 #define HAL_SMBUS_ERROR_ACKF        ((uint32_t)0x00000004)    /*!< ACKF error           */
 152 #define HAL_SMBUS_ERROR_OVR         ((uint32_t)0x00000008)    /*!< OVR error            */
 153 #define HAL_SMBUS_ERROR_HALTIMEOUT  ((uint32_t)0x00000010)    /*!< Timeout error        */
 154 #define HAL_SMBUS_ERROR_BUSTIMEOUT  ((uint32_t)0x00000020)    /*!< Bus Timeout error    */
 155 #define HAL_SMBUS_ERROR_ALERT       ((uint32_t)0x00000040)    /*!< Alert error          */
 156 #define HAL_SMBUS_ERROR_PECERR      ((uint32_t)0x00000080)    /*!< PEC error            */
 157 /**
 158   * @}
 159   */
 160
 161 /** @defgroup SMBUS_State SMBUS State
 162   * @{
 163   */
 164
 165 #define HAL_SMBUS_STATE_RESET           ((uint32_t)0x00000000)  /*!< SMBUS not yet initialized or disabled         */
 166 #define HAL_SMBUS_STATE_READY           ((uint32_t)0x00000001)  /*!< SMBUS initialized and ready for use           */
 167 #define HAL_SMBUS_STATE_BUSY            ((uint32_t)0x00000002)  /*!< SMBUS internal process is ongoing             */
 168 #define HAL_SMBUS_STATE_MASTER_BUSY_TX  ((uint32_t)0x00000012)  /*!< Master Data Transmission process is ongoing   */
 169 #define HAL_SMBUS_STATE_MASTER_BUSY_RX  ((uint32_t)0x00000022)  /*!< Master Data Reception process is ongoing      */
 170 #define HAL_SMBUS_STATE_SLAVE_BUSY_TX   ((uint32_t)0x00000032)  /*!< Slave Data Transmission process is ongoing    */
 171 #define HAL_SMBUS_STATE_SLAVE_BUSY_RX   ((uint32_t)0x00000042)  /*!< Slave Data Reception process is ongoing       */
 172 #define HAL_SMBUS_STATE_TIMEOUT         ((uint32_t)0x00000003)  /*!< Timeout state                                 */
 173 #define HAL_SMBUS_STATE_ERROR           ((uint32_t)0x00000004)  /*!< Reception process is ongoing                  */
 174 #define HAL_SMBUS_STATE_SLAVE_LISTEN    ((uint32_t)0x00000008)  /*!< Address Listen Mode is ongoing                */
 175   /* Aliases for inter STM32 series compatibility */
 176 #define HAL_SMBUS_STATE_LISTEN          HAL_SMBUS_STATE_SLAVE_LISTEN
 177
 178 /**
 179   * @}
 180   */
 181
 182 /** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
 183   * @{
 184   */
 185 #define SMBUS_ANALOGFILTER_ENABLED              ((uint32_t)0x00000000)
 186 #define SMBUS_ANALOGFILTER_DISABLED             I2C_CR1_ANFOFF
 187
 188 #define IS_SMBUS_ANALOG_FILTER(FILTER)          (((FILTER) == SMBUS_ANALOGFILTER_ENABLED) || \
 189                                                  ((FILTER) == SMBUS_ANALOGFILTER_DISABLED))
 190 /**
 191   * @}
 192   */
 193
 194 /** @defgroup SMBUS_addressing_mode SMBUS addressing mode
 195   * @{
 196   */
 197 #define SMBUS_ADDRESSINGMODE_7BIT               ((uint32_t)0x00000001)
 198 #define SMBUS_ADDRESSINGMODE_10BIT              ((uint32_t)0x00000002)
 199
 200 #define IS_SMBUS_ADDRESSING_MODE(MODE)          (((MODE) == SMBUS_ADDRESSINGMODE_7BIT)  || \
 201                                                  ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
 202 /**
 203   * @}
 204   */
 205
 206 /** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
 207   * @{
 208   */
 209
 210 #define SMBUS_DUALADDRESS_DISABLED              ((uint32_t)0x00000000)
 211 #define SMBUS_DUALADDRESS_ENABLED               I2C_OAR2_OA2EN
 212
 213 #define IS_SMBUS_DUAL_ADDRESS(ADDRESS)          (((ADDRESS) == SMBUS_DUALADDRESS_DISABLED) || \
 214                                                  ((ADDRESS) == SMBUS_DUALADDRESS_ENABLED))
 215 /**
 216   * @}
 217   */
 218
 219 /** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks
 220   * @{
 221   */
 222
 223 #define SMBUS_OA2_NOMASK                        ((uint8_t)0x00)
 224 #define SMBUS_OA2_MASK01                        ((uint8_t)0x01)
 225 #define SMBUS_OA2_MASK02                        ((uint8_t)0x02)
 226 #define SMBUS_OA2_MASK03                        ((uint8_t)0x03)
 227 #define SMBUS_OA2_MASK04                        ((uint8_t)0x04)
 228 #define SMBUS_OA2_MASK05                        ((uint8_t)0x05)
 229 #define SMBUS_OA2_MASK06                        ((uint8_t)0x06)
 230 #define SMBUS_OA2_MASK07                        ((uint8_t)0x07)
 231
 232 #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK)        (((MASK) == SMBUS_OA2_NOMASK)   || \
 233                                                  ((MASK) == SMBUS_OA2_MASK01)    || \
 234                                                  ((MASK) == SMBUS_OA2_MASK02)    || \
 235                                                  ((MASK) == SMBUS_OA2_MASK03)    || \
 236                                                  ((MASK) == SMBUS_OA2_MASK04)    || \
 237                                                  ((MASK) == SMBUS_OA2_MASK05)    || \
 238                                                  ((MASK) == SMBUS_OA2_MASK06)    || \
 239                                                  ((MASK) == SMBUS_OA2_MASK07))
 240 /**
 241   * @}
 242   */
 243
 244
 245 /** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
 246   * @{
 247   */
 248 #define SMBUS_GENERALCALL_DISABLED              ((uint32_t)0x00000000)
 249 #define SMBUS_GENERALCALL_ENABLED               I2C_CR1_GCEN
 250
 251 #define IS_SMBUS_GENERAL_CALL(CALL)             (((CALL) == SMBUS_GENERALCALL_DISABLED) || \
 252                                                  ((CALL) == SMBUS_GENERALCALL_ENABLED))
 253 /**
 254   * @}
 255   */
 256
 257 /** @defgroup SMBUS_nostretch_mode  SMBUS nostretch mode
 258   * @{
 259   */
 260 #define SMBUS_NOSTRETCH_DISABLED                ((uint32_t)0x00000000)
 261 #define SMBUS_NOSTRETCH_ENABLED                 I2C_CR1_NOSTRETCH
 262
 263 #define IS_SMBUS_NO_STRETCH(STRETCH)            (((STRETCH) == SMBUS_NOSTRETCH_DISABLED) || \
 264                                                  ((STRETCH) == SMBUS_NOSTRETCH_ENABLED))
 265 /**
 266   * @}
 267   */
 268
 269 /** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
 270   * @{
 271   */
 272 #define SMBUS_PEC_DISABLED                      ((uint32_t)0x00000000)
 273 #define SMBUS_PEC_ENABLED                       I2C_CR1_PECEN
 274
 275 #define IS_SMBUS_PEC(PEC)                       (((PEC) == SMBUS_PEC_DISABLED) || \
 276                                                  ((PEC) == SMBUS_PEC_ENABLED))
 277 /**
 278   * @}
 279   */
 280
 281 /** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
 282   * @{
 283   */
 284 #define SMBUS_PERIPHERAL_MODE_SMBUS_HOST        (uint32_t)(I2C_CR1_SMBHEN)
 285 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE       (uint32_t)(0x00000000)
 286 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP   (uint32_t)(I2C_CR1_SMBDEN)
 287
 288 #define IS_SMBUS_PERIPHERAL_MODE(MODE)          (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST)   || \
 289                                                  ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE)  || \
 290                                                  ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
 291 /**
 292   * @}
 293   */
 294
 295 /** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
 296   * @{
 297   */
 298
 299 #define  SMBUS_SOFTEND_MODE                     ((uint32_t)0x00000000)
 300 #define  SMBUS_RELOAD_MODE                      I2C_CR2_RELOAD
 301 #define  SMBUS_AUTOEND_MODE                     I2C_CR2_AUTOEND
 302 #define  SMBUS_SENDPEC_MODE                     I2C_CR2_PECBYTE
 303
 304 #define IS_SMBUS_TRANSFER_MODE(MODE)            (((MODE) == SMBUS_RELOAD_MODE)                          || \
 305                                                  ((MODE) == SMBUS_AUTOEND_MODE)                         || \
 306                                                  ((MODE) == SMBUS_SOFTEND_MODE)                         || \
 307                                                  ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE))   || \
 308                                                  ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))  || \
 309                                                  ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE))   || \
 310                                                  ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
 311
 312 /**
 313   * @}
 314   */
 315
 316 /** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
 317   * @{
 318   */
 319
 320 #define  SMBUS_NO_STARTSTOP                     ((uint32_t)0x00000000)
 321 #define  SMBUS_GENERATE_STOP                    I2C_CR2_STOP
 322 #define  SMBUS_GENERATE_START_READ              (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
 323 #define  SMBUS_GENERATE_START_WRITE             I2C_CR2_START
 324
 325 #define IS_SMBUS_TRANSFER_REQUEST(REQUEST)      (((REQUEST) == SMBUS_GENERATE_STOP)             || \
 326                                                  ((REQUEST) == SMBUS_GENERATE_START_READ)       || \
 327                                                  ((REQUEST) == SMBUS_GENERATE_START_WRITE)      || \
 328                                                  ((REQUEST) == SMBUS_NO_STARTSTOP))
 329
 330 /**
 331   * @}
 332   */
 333
 334 /** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
 335   * @{
 336   */
 337
 338 #define  SMBUS_FIRST_FRAME                      ((uint32_t)(SMBUS_SOFTEND_MODE))
 339 #define  SMBUS_NEXT_FRAME                       ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
 340 #define  SMBUS_FIRST_AND_LAST_FRAME_NO_PEC      SMBUS_AUTOEND_MODE
 341 #define  SMBUS_LAST_FRAME_NO_PEC                SMBUS_AUTOEND_MODE
 342 #define  SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC    ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
 343 #define  SMBUS_LAST_FRAME_WITH_PEC              ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
 344
 345 #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)    (((REQUEST) == SMBUS_FIRST_FRAME)                       || \
 346                                                        ((REQUEST) == SMBUS_NEXT_FRAME)                        || \
 347                                                        ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC)       || \
 348                                                        ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC)                 || \
 349                                                        ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)     || \
 350                                                        ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
 351
 352 /**
 353   * @}
 354   */
 355
 356 /** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
 357   * @brief SMBUS Interrupt definition
 358   *        Elements values convention: 0xXXXXXXXX
 359   *           - XXXXXXXX  : Interrupt control mask
 360   * @{
 361   */
 362 #define SMBUS_IT_ERRI                     I2C_CR1_ERRIE
 363 #define SMBUS_IT_TCI                      I2C_CR1_TCIE
 364 #define SMBUS_IT_STOPI                    I2C_CR1_STOPIE
 365 #define SMBUS_IT_NACKI                    I2C_CR1_NACKIE
 366 #define SMBUS_IT_ADDRI                    I2C_CR1_ADDRIE
 367 #define SMBUS_IT_RXI                      I2C_CR1_RXIE
 368 #define SMBUS_IT_TXI                      I2C_CR1_TXIE
 369 #define SMBUS_IT_TX                       (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
 370 #define SMBUS_IT_RX                       (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
 371 #define SMBUS_IT_ALERT                    (SMBUS_IT_ERRI)
 372 #define SMBUS_IT_ADDR                     (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
 373 /**
 374   * @}
 375   */
 376
 377 /** @defgroup SMBUS_Flag_definition SMBUS Flag definition
 378   * @brief Flag definition
 379   *        Elements values convention: 0xXXXXYYYY
 380   *           - XXXXXXXX  : Flag mask
 381   * @{
 382   */
 383
 384 #define  SMBUS_FLAG_TXE                   I2C_ISR_TXE
 385 #define  SMBUS_FLAG_TXIS                  I2C_ISR_TXIS
 386 #define  SMBUS_FLAG_RXNE                  I2C_ISR_RXNE
 387 #define  SMBUS_FLAG_ADDR                  I2C_ISR_ADDR
 388 #define  SMBUS_FLAG_AF                    I2C_ISR_NACKF
 389 #define  SMBUS_FLAG_STOPF                 I2C_ISR_STOPF
 390 #define  SMBUS_FLAG_TC                    I2C_ISR_TC
 391 #define  SMBUS_FLAG_TCR                   I2C_ISR_TCR
 392 #define  SMBUS_FLAG_BERR                  I2C_ISR_BERR
 393 #define  SMBUS_FLAG_ARLO                  I2C_ISR_ARLO
 394 #define  SMBUS_FLAG_OVR                   I2C_ISR_OVR
 395 #define  SMBUS_FLAG_PECERR                I2C_ISR_PECERR
 396 #define  SMBUS_FLAG_TIMEOUT               I2C_ISR_TIMEOUT
 397 #define  SMBUS_FLAG_ALERT                 I2C_ISR_ALERT
 398 #define  SMBUS_FLAG_BUSY                  I2C_ISR_BUSY
 399 #define  SMBUS_FLAG_DIR                   I2C_ISR_DIR
 400 /**
 401   * @}
 402   */
 403
 404 /**
 405   * @}
 406   */
 407
 408 /* Exported macros ------------------------------------------------------------*/
 409 /** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
 410   * @{
 411   */
 412
 413 /** @brief  Reset SMBUS handle state
 414   * @param  __HANDLE__: SMBUS handle.
 415   * @retval None
 416   */
 417 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
 418
 419 /** @brief  Enable or disable the specified SMBUS interrupts.
 420   * @param  __HANDLE__: specifies the SMBUS Handle.
 421   *         This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral.
 422   * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
 423   *        This parameter can be one of the following values:
 424   *            @arg SMBUS_IT_ERRI: Errors interrupt enable
 425   *            @arg SMBUS_IT_TCI: Transfer complete interrupt enable
 426   *            @arg SMBUS_IT_STOPI: STOP detection interrupt enable
 427   *            @arg SMBUS_IT_NACKI: NACK received interrupt enable
 428   *            @arg SMBUS_IT_ADDRI: Address match interrupt enable
 429   *            @arg SMBUS_IT_RXI: RX interrupt enable
 430   *            @arg SMBUS_IT_TXI: TX interrupt enable
 431   *
 432   * @retval None
 433   */
 434
 435 #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
 436 #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
 437
 438 /** @brief  Checks if the specified SMBUS interrupt source is enabled or disabled.
 439   * @param  __HANDLE__: specifies the SMBUS Handle.
 440   *         This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral.
 441   * @param  __INTERRUPT__: specifies the SMBUS interrupt source to check.
 442   *          This parameter can be one of the following values:
 443   *            @arg SMBUS_IT_ERRI: Errors interrupt enable
 444   *            @arg SMBUS_IT_TCI: Transfer complete interrupt enable
 445   *            @arg SMBUS_IT_STOPI: STOP detection interrupt enable
 446   *            @arg SMBUS_IT_NACKI: NACK received interrupt enable
 447   *            @arg SMBUS_IT_ADDRI: Address match interrupt enable
 448   *            @arg SMBUS_IT_RXI: RX interrupt enable
 449   *            @arg SMBUS_IT_TXI: TX interrupt enable
 450   *
 451   * @retval The new state of __IT__ (TRUE or FALSE).
 452   */
 453 #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 454
 455 /** @brief  Checks whether the specified SMBUS flag is set or not.
 456   * @param  __HANDLE__: specifies the SMBUS Handle.
 457   *         This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral.
 458   * @param  __FLAG__: specifies the flag to check.
 459   *        This parameter can be one of the following values:
 460   *            @arg SMBUS_FLAG_TXE:             Transmit data register empty
 461   *            @arg SMBUS_FLAG_TXIS:            Transmit interrupt status
 462   *            @arg SMBUS_FLAG_RXNE:            Receive data register not empty
 463   *            @arg SMBUS_FLAG_ADDR:            Address matched (slave mode)
 464   *            @arg SMBUS_FLAG_AF:              NACK received flag
 465   *            @arg SMBUS_FLAG_STOPF:           STOP detection flag
 466   *            @arg SMBUS_FLAG_TC:              Transfer complete (master mode)
 467   *            @arg SMBUS_FLAG_TCR:             Transfer complete reload
 468   *            @arg SMBUS_FLAG_BERR:            Bus error
 469   *            @arg SMBUS_FLAG_ARLO:            Arbitration lost
 470   *            @arg SMBUS_FLAG_OVR:             Overrun/Underrun
 471   *            @arg SMBUS_FLAG_PECERR:          PEC error in reception
 472   *            @arg SMBUS_FLAG_TIMEOUT:         Timeout or Tlow detection flag
 473   *            @arg SMBUS_FLAG_ALERT:           SMBus alert
 474   *            @arg SMBUS_FLAG_BUSY:            Bus busy
 475   *            @arg SMBUS_FLAG_DIR:             Transfer direction (slave mode)
 476   *
 477   * @retval The new state of __FLAG__ (TRUE or FALSE).
 478   */
 479 #define SMBUS_FLAG_MASK  ((uint32_t)0x0001FFFF)
 480 #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
 481
 482 /** @brief  Clears the SMBUS pending flags which are cleared by writing 1 in a specific bit.
 483   * @param  __HANDLE__: specifies the SMBUS Handle.
 484   *         This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral.
 485   * @param  __FLAG__: specifies the flag to clear.
 486   *          This parameter can be any combination of the following values:
 487   *            @arg SMBUS_FLAG_ADDR:            Address matched (slave mode)
 488   *            @arg SMBUS_FLAG_AF:              NACK received flag
 489   *            @arg SMBUS_FLAG_STOPF:           STOP detection flag
 490   *            @arg SMBUS_FLAG_BERR:            Bus error
 491   *            @arg SMBUS_FLAG_ARLO:            Arbitration lost
 492   *            @arg SMBUS_FLAG_OVR:             Overrun/Underrun
 493   *            @arg SMBUS_FLAG_PECERR:          PEC error in reception
 494   *            @arg SMBUS_FLAG_TIMEOUT:         Timeout or Tlow detection flag
 495   *            @arg SMBUS_FLAG_ALERT:           SMBus alert
 496   *
 497   * @retval None
 498   */
 499 #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
 500
 501
 502 #define __HAL_SMBUS_ENABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR1 |=  I2C_CR1_PE)
 503 #define __HAL_SMBUS_DISABLE(__HANDLE__)                         ((__HANDLE__)->Instance->CR1 &=  ~I2C_CR1_PE)
 504
 505 #define __HAL_SMBUS_RESET_CR1(__HANDLE__)                       ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
 506 #define __HAL_SMBUS_RESET_CR2(__HANDLE__)                       ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
 507
 508 #define __HAL_SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__)     (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
 509                                                                   (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
 510
 511 #define __HAL_SMBUS_GET_ADDR_MATCH(__HANDLE__)                  (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17)
 512 #define __HAL_SMBUS_GET_DIR(__HANDLE__)                         (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16)
 513 #define __HAL_SMBUS_GET_STOP_MODE(__HANDLE__)                   ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
 514 #define __HAL_SMBUS_GET_PEC_MODE(__HANDLE__)                    ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
 515 #define __HAL_SMBUS_GET_ALERT_ENABLED(__HANDLE__)                ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
 516 #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__)                   ((__HANDLE__)->Instance->CR2 |= I2C_CR2_NACK)
 517
 518 #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1)                         ((ADDRESS1) <= (uint32_t)0x000003FF)
 519 #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2)                         ((ADDRESS2) <= (uint16_t)0x00FF)
 520 /**
 521   * @}
 522   */
 523
 524 /* Exported functions --------------------------------------------------------*/
 525 /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
 526   * @{
 527   */
 528
 529 /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
 530  * @{
 531  */
 532
 533 /* Initialization and de-initialization functions  **********************************/
 534 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
 535 HAL_StatusTypeDef HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus);
 536 void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
 537 void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
 538
 539 /**
 540   * @}
 541   */
 542
 543 /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
 544  * @{
 545  */
 546
 547 /* IO operation functions  *****************************************************/
 548 /******* Blocking mode: Polling */
 549 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
 550
 551 /******* Non-Blocking mode: Interrupt */
 552 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
 553 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
 554 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
 555 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
 556 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
 557
 558 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
 559 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
 560 HAL_StatusTypeDef HAL_SMBUS_Slave_Listen_IT(SMBUS_HandleTypeDef *hsmbus);
 561 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
 562
 563 /* Aliases for new API and to insure inter STM32 series compatibility */
 564 #define HAL_SMBUS_EnableListen_IT   HAL_SMBUS_Slave_Listen_IT
 565
 566 /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
 567 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
 568 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
 569 void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
 570 void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
 571 void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
 572 void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
 573 void HAL_SMBUS_SlaveAddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
 574 void HAL_SMBUS_SlaveListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
 575
 576 /* Aliases for new API and to insure inter STM32 series compatibility */
 577 #define HAL_SMBUS_AddrCallback         HAL_SMBUS_SlaveAddrCallback
 578 #define HAL_SMBUS_ListenCpltCallback   HAL_SMBUS_SlaveListenCpltCallback
 579
 580 void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
 581
 582 /**
 583   * @}
 584   */
 585
 586 /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
 587  *  @{
 588  */
 589
 590 /* Peripheral State and Errors functions  **************************************************/
 591 uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
 592 uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
 593
 594 /**
 595   * @}
 596   */
 597
 598 /**
 599   * @}
 600   */
 601
 602 /**
 603   * @}
 604   */
 605
 606 /**
 607   * @}
 608   */
 609 #ifdef __cplusplus
 610 }
 611 #endif
 612
 613
 614 #endif /* __STM32F0xx_HAL_SMBUS_H */
 615
 616 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 617