tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc_ex.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f4xx_hal_rcc_ex.c
   4   * @author  MCD Application Team
   5   * @version V1.1.0
   6   * @date    19-June-2014
   7   * @brief   Extension RCC HAL module driver.
   8   *          This file provides firmware functions to manage the following
   9   *          functionalities RCC extension peripheral:
  10   *           + Extended Peripheral Control functions
  11   *
  12   ******************************************************************************
  13   * @attention
  14   *
  15   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  16   *
  17   * Redistribution and use in source and binary forms, with or without modification,
  18   * are permitted provided that the following conditions are met:
  19   *   1. Redistributions of source code must retain the above copyright notice,
  20   *      this list of conditions and the following disclaimer.
  21   *   2. Redistributions in binary form must reproduce the above copyright notice,
  22   *      this list of conditions and the following disclaimer in the documentation
  23   *      and/or other materials provided with the distribution.
  24   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  25   *      may be used to endorse or promote products derived from this software
  26   *      without specific prior written permission.
  27   *
  28   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  29   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  30   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  31   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  32   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  34   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  35   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  36   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  37   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38   *
  39   ******************************************************************************
  40   */
  41
  42 /* Includes ------------------------------------------------------------------*/
  43 #include "stm32f4xx_hal.h"
  44
  45 /** @addtogroup STM32F4xx_HAL_Driver
  46   * @{
  47   */
  48
  49 /** @defgroup RCC
  50   * @brief RCC HAL module driver
  51   * @{
  52   */
  53
  54 #ifdef HAL_RCC_MODULE_ENABLED
  55
  56 /* Private typedef -----------------------------------------------------------*/
  57 /* Private define ------------------------------------------------------------*/
  58 #define PLLI2S_TIMEOUT_VALUE    100 /* Timeout value fixed to 100 ms  */
  59 #define PLLSAI_TIMEOUT_VALUE    100 /* Timeout value fixed to 100 ms  */
  60 /* Private macro -------------------------------------------------------------*/
  61 /* Private variables ---------------------------------------------------------*/
  62 /* Private function prototypes -----------------------------------------------*/
  63 /* Private functions ---------------------------------------------------------*/
  64
  65 /** @defgroup RCCEx_Private_Functions
  66   * @{
  67   */
  68
  69 /** @defgroup RCCEx_Group1 Extended Peripheral Control functions
  70  *  @brief  Extended Peripheral Control functions
  71  *
  72 @verbatim
  73  ===============================================================================
  74                 ##### Extended Peripheral Control functions  #####
  75  ===============================================================================
  76     [..]
  77     This subsection provides a set of functions allowing to control the RCC Clocks
  78     frequencies.
  79     [..]
  80     (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
  81         select the RTC clock source; in this case the Backup domain will be reset in
  82         order to modify the RTC Clock source, as consequence RTC registers (including
  83         the backup registers) and RCC_BDCR register are set to their reset values.
  84
  85 @endverbatim
  86   * @{
  87   */
  88 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
  89 /**
  90   * @brief  Initializes the RCC extended peripherals clocks according to the specified
  91   *         parameters in the RCC_PeriphCLKInitTypeDef.
  92   * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
  93   *         contains the configuration information for the Extended Peripherals
  94   *         clocks(I2S, SAI, LTDC RTC and TIM).
  95   *
  96   * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
  97   *         the RTC clock source; in this case the Backup domain will be reset in
  98   *         order to modify the RTC Clock source, as consequence RTC registers (including
  99   *         the backup registers) and RCC_BDCR register are set to their reset values.
 100   *
 101   * @retval HAL status
 102   */
 103 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
 104 {
 105   uint32_t tickstart = 0;
 106   uint32_t tmpreg = 0;
 107
 108   /* Check the parameters */
 109   assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
 110
 111   /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------------*/
 112
 113   /*----------------------- Common configuration SAI/I2S ---------------------------*/
 114   /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
 115      factor is common parameters for both peripherals */
 116   if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
 117      (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S))
 118   {
 119     /* check for Parameters */
 120     assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
 121
 122     /* Disable the PLLI2S */
 123     __HAL_RCC_PLLI2S_DISABLE();
 124     /* Get tick */
 125     tickstart = HAL_GetTick();
 126     /* Wait till PLLI2S is disabled */
 127     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
 128     {
 129       if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
 130       {
 131         /* return in case of Timeout detected */
 132         return HAL_TIMEOUT;
 133       }
 134     }
 135
 136     /*---------------------------- I2S configuration -------------------------------*/
 137     /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
 138       only for I2S configuration */
 139     if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
 140     {
 141       /* check for Parameters */
 142       assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
 143       /* Configure the PLLI2S division factors */
 144       /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */
 145       /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
 146       __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
 147     }
 148
 149     /*---------------------------- SAI configuration -------------------------------*/
 150     /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
 151        be added only for SAI configuration */
 152     if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
 153     {
 154       /* Check the PLLI2S division factors */
 155       assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
 156       assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
 157
 158       /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
 159       tmpreg = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
 160       /* Configure the PLLI2S division factors */
 161       /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
 162       /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
 163       /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
 164       __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg);
 165       /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
 166       __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
 167     }
 168
 169     /* Enable the PLLI2S */
 170     __HAL_RCC_PLLI2S_ENABLE();
 171     /* Get tick */
 172     tickstart = HAL_GetTick();
 173     /* Wait till PLLI2S is ready */
 174     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
 175     {
 176       if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
 177       {
 178         /* return in case of Timeout detected */
 179         return HAL_TIMEOUT;
 180       }
 181     }
 182   }
 183
 184   /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/
 185
 186   /*----------------------- Common configuration SAI/LTDC --------------------*/
 187   /* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division
 188      factor is common parameters for both peripherals */
 189   if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
 190      (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC))
 191   {
 192     /* Check the PLLSAI division factors */
 193     assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
 194
 195     /* Disable PLLSAI Clock */
 196     __HAL_RCC_PLLSAI_DISABLE();
 197     /* Get tick */
 198     tickstart = HAL_GetTick();
 199     /* Wait till PLLSAI is disabled */
 200     while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
 201     {
 202       if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
 203       {
 204         /* return in case of Timeout detected */
 205         return HAL_TIMEOUT;
 206       }
 207     }
 208
 209     /*---------------------------- SAI configuration -------------------------*/
 210     /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
 211        be added only for SAI configuration */
 212     if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
 213     {
 214       assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
 215       assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
 216
 217       /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
 218       tmpreg = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
 219       /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
 220       /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
 221       /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
 222       __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg);
 223       /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
 224       __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
 225     }
 226
 227     /*---------------------------- LTDC configuration ------------------------*/
 228     if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
 229     {
 230       assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
 231       assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
 232
 233       /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
 234       tmpreg = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
 235       /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
 236       /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
 237       /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
 238       __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg, PeriphClkInit->PLLSAI.PLLSAIR);
 239       /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
 240       __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
 241     }
 242     /* Enable PLLSAI Clock */
 243     __HAL_RCC_PLLSAI_ENABLE();
 244     /* Get tick */
 245     tickstart = HAL_GetTick();
 246     /* Wait till PLLSAI is ready */
 247     while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
 248     {
 249       if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
 250       {
 251         /* return in case of Timeout detected */
 252         return HAL_TIMEOUT;
 253       }
 254     }
 255   }
 256
 257
 258   /*---------------------------- RTC configuration ---------------------------*/
 259   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
 260   {
 261     /* Enable Power Clock*/
 262     __PWR_CLK_ENABLE();
 263
 264     /* Enable write access to Backup domain */
 265     PWR->CR |= PWR_CR_DBP;
 266
 267     /* Get tick */
 268     tickstart = HAL_GetTick();
 269
 270     while((PWR->CR & PWR_CR_DBP) == RESET)
 271     {
 272       if((HAL_GetTick() - tickstart ) > DBP_TIMEOUT_VALUE)
 273       {
 274         return HAL_TIMEOUT;
 275       }
 276     }
 277
 278     /* Reset the Backup domain only if the RTC Clock source selction is modified */
 279     if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
 280     {
 281       /* Store the content of BDCR register before the reset of Backup Domain */
 282       tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
 283       /* RTC Clock selection can be changed only if the Backup Domain is reset */
 284       __HAL_RCC_BACKUPRESET_FORCE();
 285       __HAL_RCC_BACKUPRESET_RELEASE();
 286       /* Restore the Content of BDCR register */
 287       RCC->BDCR = tmpreg;
 288     }
 289
 290     /* If LSE is selected as RTC clock source, wait for LSE reactivation */
 291     if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
 292     {
 293       /* Get tick */
 294       tickstart = HAL_GetTick();
 295
 296       /* Wait till LSE is ready */
 297       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 298       {
 299         if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
 300         {
 301           return HAL_TIMEOUT;
 302         }
 303       }
 304     }
 305     __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
 306   }
 307
 308   /*---------------------------- TIM configuration ---------------------------*/
 309   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
 310   {
 311     __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
 312   }
 313   return HAL_OK;
 314 }
 315
 316 /**
 317   * @brief  Configures the RCC_OscInitStruct according to the internal
 318   * RCC configuration registers.
 319   * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
 320   *         will be configured.
 321   * @retval None
 322   */
 323 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
 324 {
 325   uint32_t tempreg;
 326
 327   /* Set all possible values for the extended clock type parameter------------*/
 328   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI | RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC;
 329
 330   /* Get the PLLI2S Clock configuration -----------------------------------------------*/
 331   PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
 332   PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
 333   PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
 334   /* Get the PLLSAI Clock configuration -----------------------------------------------*/
 335   PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
 336   PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
 337   PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
 338   /* Get the PLLSAI/PLLI2S division factors -----------------------------------------------*/
 339   PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
 340   PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
 341   PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
 342   /* Get the RTC Clock configuration -----------------------------------------------*/
 343   tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
 344   PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
 345
 346   if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
 347   {
 348     PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
 349   }
 350   else
 351   {
 352     PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
 353   }
 354 }
 355 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
 356
 357 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
 358     defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
 359 /**
 360   * @brief  Initializes the RCC extended peripherals clocks according to the specified parameters in the
 361   *         RCC_PeriphCLKInitTypeDef.
 362   * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
 363   *         contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
 364   *
 365   * @note   A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
 366   *         the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
 367   *        domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
 368   *
 369   * @retval HAL status
 370   */
 371 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
 372 {
 373   uint32_t tickstart = 0;
 374   uint32_t tmpreg = 0;
 375
 376   /* Check the parameters */
 377   assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
 378
 379   /*---------------------------- I2S configuration ---------------------------*/
 380   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
 381   {
 382     /* check for Parameters */
 383     assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
 384     assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
 385 #if defined(STM32F411xE)
 386     assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
 387 #endif /* STM32F411xE */
 388     /* Disable the PLLI2S */
 389     __HAL_RCC_PLLI2S_DISABLE();
 390     /* Get tick */
 391     tickstart = HAL_GetTick();
 392     /* Wait till PLLI2S is disabled */
 393     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
 394     {
 395       if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
 396       {
 397         /* return in case of Timeout detected */
 398         return HAL_TIMEOUT;
 399       }
 400     }
 401
 402 #if defined(STM32F411xE)
 403     /* Configure the PLLI2S division factors */
 404     /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLI2SM) */
 405     /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
 406     __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR);
 407 #else
 408     /* Configure the PLLI2S division factors */
 409     /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */
 410     /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
 411     __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
 412 #endif /* STM32F411xE */
 413
 414     /* Enable the PLLI2S */
 415     __HAL_RCC_PLLI2S_ENABLE();
 416     /* Get tick */
 417     tickstart = HAL_GetTick();
 418     /* Wait till PLLI2S is ready */
 419     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
 420     {
 421       if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
 422       {
 423         /* return in case of Timeout detected */
 424         return HAL_TIMEOUT;
 425       }
 426     }
 427   }
 428
 429   /*---------------------------- RTC configuration ---------------------------*/
 430   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
 431   {
 432     /* Enable Power Clock*/
 433     __PWR_CLK_ENABLE();
 434
 435     /* Enable write access to Backup domain */
 436     PWR->CR |= PWR_CR_DBP;
 437
 438     /* Get tick */
 439     tickstart = HAL_GetTick();
 440
 441     while((PWR->CR & PWR_CR_DBP) == RESET)
 442     {
 443       if((HAL_GetTick() - tickstart ) > DBP_TIMEOUT_VALUE)
 444       {
 445         return HAL_TIMEOUT;
 446       }
 447     }
 448
 449     /* Reset the Backup domain only if the RTC Clock source selction is modified */
 450     if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
 451     {
 452       /* Store the content of BDCR register before the reset of Backup Domain */
 453       tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
 454       /* RTC Clock selection can be changed only if the Backup Domain is reset */
 455       __HAL_RCC_BACKUPRESET_FORCE();
 456       __HAL_RCC_BACKUPRESET_RELEASE();
 457       /* Restore the Content of BDCR register */
 458       RCC->BDCR = tmpreg;
 459     }
 460
 461     /* If LSE is selected as RTC clock source, wait for LSE reactivation */
 462     if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
 463     {
 464       /* Get tick */
 465       tickstart = HAL_GetTick();
 466
 467       /* Wait till LSE is ready */
 468       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 469       {
 470         if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
 471         {
 472           return HAL_TIMEOUT;
 473         }
 474       }
 475     }
 476     __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
 477   }
 478
 479   return HAL_OK;
 480 }
 481
 482 /**
 483   * @brief  Configures the RCC_OscInitStruct according to the internal
 484   * RCC configuration registers.
 485   * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
 486   * will be configured.
 487   * @retval None
 488   */
 489 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
 490 {
 491   uint32_t tempreg;
 492
 493   /* Set all possible values for the extended clock type parameter------------*/
 494   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_RTC;
 495
 496   /* Get the PLLI2S Clock configuration -----------------------------------------------*/
 497   PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
 498   PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
 499 #if defined(STM32F411xE)
 500   PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM);
 501 #endif /* STM32F411xE */
 502   /* Get the RTC Clock configuration -----------------------------------------------*/
 503   tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
 504   PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
 505
 506 }
 507 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
 508
 509 #if defined(STM32F411xE)
 510 /**
 511   * @brief  Select LSE mode
 512   *
 513   * @note   This mode is only available for STM32F411xx devices.
 514   *
 515   * @param  Mode: specifies the LSE mode.
 516   *          This parameter can be one of the following values:
 517   *            @arg RCC_LSE_LOWPOWER_MODE:  LSE oscillator in low power mode selection
 518   *            @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode selection
 519   * @retval None
 520   */
 521 void HAL_RCCEx_SelectLSEMode(uint8_t Mode)
 522 {
 523   /* Check the parameters */
 524   assert_param(IS_RCC_LSE_MODE(Mode));
 525   if(Mode == RCC_LSE_HIGHDRIVE_MODE)
 526   {
 527     SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
 528   }
 529   else
 530   {
 531     CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
 532   }
 533 }
 534
 535 #endif /* STM32F411xE */
 536
 537 /**
 538   * @}
 539   */
 540
 541 /**
 542   * @}
 543   */
 544
 545 #endif /* HAL_RCC_MODULE_ENABLED */
 546 /**
 547   * @}
 548   */
 549
 550 /**
 551   * @}
 552   */
 553
 554 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/