1 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
2 ;* File Name : startup_stm32f072xb.s
3 ;* Author : MCD Application Team
6 ;* Description : STM32F072x8/STM32F072xB devices vector table for EWARM toolchain.
7 ;* This module performs:
8 ;* - Set the initial SP
9 ;* - Set the initial PC == __iar_program_start,
10 ;* - Set the vector table entries with the exceptions ISR
12 ;* - Branches to main in the C library (which eventually
14 ;* After Reset the Cortex-M0 processor is in Thread mode,
15 ;* priority is Privileged, and the Stack is set to Main.
16 ;*******************************************************************************
18 ;* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
20 ;* Redistribution and use in source and binary forms, with or without modification,
21 ;* are permitted provided that the following conditions are met:
22 ;* 1. Redistributions of source code must retain the above copyright notice,
23 ;* this list of conditions and the following disclaimer.
24 ;* 2. Redistributions in binary form must reproduce the above copyright notice,
25 ;* this list of conditions and the following disclaimer in the documentation
26 ;* and/or other materials provided with the distribution.
27 ;* 3. Neither the name of STMicroelectronics nor the names of its contributors
28 ;* may be used to endorse or promote products derived from this software
29 ;* without specific prior written permission.
31 ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
32 ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
33 ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
34 ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
35 ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
36 ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
37 ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
38 ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
39 ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 ;*******************************************************************************
45 ; The modules in this file are included in the libraries, and may be replaced
46 ; by any user-defined modules that define the PUBLIC symbol _program_start or
47 ; a user defined start symbol.
48 ; To override the cstartup defined in the library, simply add your modified
49 ; version to the workbench project.
51 ; The vector table is normally located at address 0.
52 ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
53 ; The name "__vector_table" has special meaning for C-SPY:
54 ; it is where the SP start value is found, and the NVIC vector
55 ; table register (VTOR) is initialized to this address if != 0.
62 ;; Forward declaration of sections.
63 SECTION CSTACK:DATA:NOROOT(3)
65 SECTION .intvec:CODE:NOROOT(2)
67 EXTERN __iar_program_start
74 DCD Reset_Handler ; Reset Handler
76 DCD NMI_Handler ; NMI Handler
77 DCD HardFault_Handler ; Hard Fault Handler
85 DCD SVC_Handler ; SVCall Handler
88 DCD PendSV_Handler ; PendSV Handler
89 DCD SysTick_Handler ; SysTick Handler
92 DCD WWDG_IRQHandler ; Window Watchdog
93 DCD PVD_VDDIO2_IRQHandler ; PVD and VDDIO2 through EXTI Line detect
94 DCD RTC_IRQHandler ; RTC through EXTI Line
95 DCD FLASH_IRQHandler ; FLASH
96 DCD RCC_CRS_IRQHandler ; RCC and CRS
97 DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
98 DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
99 DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
100 DCD TSC_IRQHandler ; TSC
101 DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
102 DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
103 DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4 to Channel 7
104 DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
105 DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
106 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
107 DCD TIM2_IRQHandler ; TIM2
108 DCD TIM3_IRQHandler ; TIM3
109 DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
110 DCD TIM7_IRQHandler ; TIM7
111 DCD TIM14_IRQHandler ; TIM14
112 DCD TIM15_IRQHandler ; TIM15
113 DCD TIM16_IRQHandler ; TIM16
114 DCD TIM17_IRQHandler ; TIM17
115 DCD I2C1_IRQHandler ; I2C1
116 DCD I2C2_IRQHandler ; I2C2
117 DCD SPI1_IRQHandler ; SPI1
118 DCD SPI2_IRQHandler ; SPI2
119 DCD USART1_IRQHandler ; USART1
120 DCD USART2_IRQHandler ; USART2
121 DCD USART3_4_IRQHandler ; USART3 and USART4
122 DCD CEC_CAN_IRQHandler ; CEC and CAN
123 DCD USB_IRQHandler ; USB
125 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
127 ;; Default interrupt handlers.
131 PUBWEAK Reset_Handler
132 SECTION .text:CODE:NOROOT:REORDER(2)
136 LDR R0, =__iar_program_start
140 SECTION .text:CODE:NOROOT:REORDER(1)
144 PUBWEAK HardFault_Handler
145 SECTION .text:CODE:NOROOT:REORDER(1)
150 SECTION .text:CODE:NOROOT:REORDER(1)
154 PUBWEAK PendSV_Handler
155 SECTION .text:CODE:NOROOT:REORDER(1)
159 PUBWEAK SysTick_Handler
160 SECTION .text:CODE:NOROOT:REORDER(1)
164 PUBWEAK WWDG_IRQHandler
165 SECTION .text:CODE:NOROOT:REORDER(1)
169 PUBWEAK PVD_VDDIO2_IRQHandler
170 SECTION .text:CODE:NOROOT:REORDER(1)
171 PVD_VDDIO2_IRQHandler
172 B PVD_VDDIO2_IRQHandler
174 PUBWEAK RTC_IRQHandler
175 SECTION .text:CODE:NOROOT:REORDER(1)
179 PUBWEAK FLASH_IRQHandler
180 SECTION .text:CODE:NOROOT:REORDER(1)
184 PUBWEAK RCC_CRS_IRQHandler
185 SECTION .text:CODE:NOROOT:REORDER(1)
189 PUBWEAK EXTI0_1_IRQHandler
190 SECTION .text:CODE:NOROOT:REORDER(1)
194 PUBWEAK EXTI2_3_IRQHandler
195 SECTION .text:CODE:NOROOT:REORDER(1)
199 PUBWEAK EXTI4_15_IRQHandler
200 SECTION .text:CODE:NOROOT:REORDER(1)
202 B EXTI4_15_IRQHandler
204 PUBWEAK TSC_IRQHandler
205 SECTION .text:CODE:NOROOT:REORDER(1)
209 PUBWEAK DMA1_Channel1_IRQHandler
210 SECTION .text:CODE:NOROOT:REORDER(1)
211 DMA1_Channel1_IRQHandler
212 B DMA1_Channel1_IRQHandler
214 PUBWEAK DMA1_Channel2_3_IRQHandler
215 SECTION .text:CODE:NOROOT:REORDER(1)
216 DMA1_Channel2_3_IRQHandler
217 B DMA1_Channel2_3_IRQHandler
219 PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
220 SECTION .text:CODE:NOROOT:REORDER(1)
221 DMA1_Channel4_5_6_7_IRQHandler
222 B DMA1_Channel4_5_6_7_IRQHandler
224 PUBWEAK ADC1_COMP_IRQHandler
225 SECTION .text:CODE:NOROOT:REORDER(1)
227 B ADC1_COMP_IRQHandler
229 PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
230 SECTION .text:CODE:NOROOT:REORDER(1)
231 TIM1_BRK_UP_TRG_COM_IRQHandler
232 B TIM1_BRK_UP_TRG_COM_IRQHandler
234 PUBWEAK TIM1_CC_IRQHandler
235 SECTION .text:CODE:NOROOT:REORDER(1)
239 PUBWEAK TIM2_IRQHandler
240 SECTION .text:CODE:NOROOT:REORDER(1)
244 PUBWEAK TIM3_IRQHandler
245 SECTION .text:CODE:NOROOT:REORDER(1)
249 PUBWEAK TIM6_DAC_IRQHandler
250 SECTION .text:CODE:NOROOT:REORDER(1)
252 B TIM6_DAC_IRQHandler
254 PUBWEAK TIM7_IRQHandler
255 SECTION .text:CODE:NOROOT:REORDER(1)
259 PUBWEAK TIM14_IRQHandler
260 SECTION .text:CODE:NOROOT:REORDER(1)
264 PUBWEAK TIM15_IRQHandler
265 SECTION .text:CODE:NOROOT:REORDER(1)
269 PUBWEAK TIM16_IRQHandler
270 SECTION .text:CODE:NOROOT:REORDER(1)
274 PUBWEAK TIM17_IRQHandler
275 SECTION .text:CODE:NOROOT:REORDER(1)
279 PUBWEAK I2C1_IRQHandler
280 SECTION .text:CODE:NOROOT:REORDER(1)
284 PUBWEAK I2C2_IRQHandler
285 SECTION .text:CODE:NOROOT:REORDER(1)
289 PUBWEAK SPI1_IRQHandler
290 SECTION .text:CODE:NOROOT:REORDER(1)
294 PUBWEAK SPI2_IRQHandler
295 SECTION .text:CODE:NOROOT:REORDER(1)
299 PUBWEAK USART1_IRQHandler
300 SECTION .text:CODE:NOROOT:REORDER(1)
304 PUBWEAK USART2_IRQHandler
305 SECTION .text:CODE:NOROOT:REORDER(1)
309 PUBWEAK USART3_4_IRQHandler
310 SECTION .text:CODE:NOROOT:REORDER(1)
312 B USART3_4_IRQHandler
314 PUBWEAK CEC_CAN_IRQHandler
315 SECTION .text:CODE:NOROOT:REORDER(1)
319 PUBWEAK USB_IRQHandler
320 SECTION .text:CODE:NOROOT:REORDER(1)
325 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****