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[tmk_keyboard.git] / tmk_core / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_STM / TARGET_STM32F3XX / stm32f30x_tim.h
1 /**
2 ******************************************************************************
3 * @file stm32f30x_tim.h
4 * @author MCD Application Team
5 * @version V1.1.0
6 * @date 27-February-2014
7 * @brief This file contains all the functions prototypes for the TIM firmware
8 * library.
9 ******************************************************************************
10 * @attention
11 *
12 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
13 *
14 * Redistribution and use in source and binary forms, with or without modification,
15 * are permitted provided that the following conditions are met:
16 * 1. Redistributions of source code must retain the above copyright notice,
17 * this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 ******************************************************************************
37 */
38
39 /* Define to prevent recursive inclusion -------------------------------------*/
40 #ifndef __STM32F30x_TIM_H
41 #define __STM32F30x_TIM_H
42
43 #ifdef __cplusplus
44 extern "C" {
45 #endif
46
47 /* Includes ------------------------------------------------------------------*/
48 #include "stm32f30x.h"
49
50 /** @addtogroup stm32f30x_StdPeriph_Driver
51 * @{
52 */
53
54 /** @addtogroup TIM
55 * @{
56 */
57
58 /* Exported types ------------------------------------------------------------*/
59
60 /**
61 * @brief TIM Time Base Init structure definition
62 * @note This structure is used with all TIMx except for TIM6 and TIM7.
63 */
64
65 typedef struct
66 {
67 uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
68 This parameter can be a number between 0x0000 and 0xFFFF */
69
70 uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
71 This parameter can be a value of @ref TIM_Counter_Mode */
72
73 uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active
74 Auto-Reload Register at the next update event.
75 This parameter must be a number between 0x0000 and 0xFFFF. */
76
77 uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
78 This parameter can be a value of @ref TIM_Clock_Division_CKD */
79
80 uint16_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
81 reaches zero, an update event is generated and counting restarts
82 from the RCR value (N).
83 This means in PWM mode that (N+1) corresponds to:
84 - the number of PWM periods in edge-aligned mode
85 - the number of half PWM period in center-aligned mode
86 This parameter must be a number between 0x00 and 0xFF.
87 @note This parameter is valid only for TIM1 and TIM8. */
88 } TIM_TimeBaseInitTypeDef;
89
90 /**
91 * @brief TIM Output Compare Init structure definition
92 */
93
94 typedef struct
95 {
96 uint32_t TIM_OCMode; /*!< Specifies the TIM mode.
97 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
98
99 uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
100 This parameter can be a value of @ref TIM_Output_Compare_State */
101
102 uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.
103 This parameter can be a value of @ref TIM_Output_Compare_N_State
104 @note This parameter is valid only for TIM1 and TIM8. */
105
106 uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
107 This parameter can be a number between 0x0000 and 0xFFFF */
108
109 uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
110 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
111
112 uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.
113 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
114 @note This parameter is valid only for TIM1 and TIM8. */
115
116 uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
117 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
118 @note This parameter is valid only for TIM1 and TIM8. */
119
120 uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
121 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
122 @note This parameter is valid only for TIM1 and TIM8. */
123 } TIM_OCInitTypeDef;
124
125 /**
126 * @brief TIM Input Capture Init structure definition
127 */
128
129 typedef struct
130 {
131
132 uint16_t TIM_Channel; /*!< Specifies the TIM channel.
133 This parameter can be a value of @ref TIM_Channel */
134
135 uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
136 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
137
138 uint16_t TIM_ICSelection; /*!< Specifies the input.
139 This parameter can be a value of @ref TIM_Input_Capture_Selection */
140
141 uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
142 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
143
144 uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
145 This parameter can be a number between 0x0 and 0xF */
146 } TIM_ICInitTypeDef;
147
148 /**
149 * @brief BDTR structure definition
150 * @note This structure is used only with TIM1 and TIM8.
151 */
152
153 typedef struct
154 {
155
156 uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.
157 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
158
159 uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.
160 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
161
162 uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.
163 This parameter can be a value of @ref TIM_Lock_level */
164
165 uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the
166 switching-on of the outputs.
167 This parameter can be a number between 0x00 and 0xFF */
168
169 uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not.
170 This parameter can be a value of @ref TIM_Break_Input_enable_disable */
171
172 uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
173 This parameter can be a value of @ref TIM_Break_Polarity */
174
175 uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
176 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
177 } TIM_BDTRInitTypeDef;
178
179 /* Exported constants --------------------------------------------------------*/
180
181 /** @defgroup TIM_Exported_constants
182 * @{
183 */
184
185 #define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
186 ((PERIPH) == TIM2) || \
187 ((PERIPH) == TIM3) || \
188 ((PERIPH) == TIM4) || \
189 ((PERIPH) == TIM6) || \
190 ((PERIPH) == TIM7) || \
191 ((PERIPH) == TIM8) || \
192 ((PERIPH) == TIM15) || \
193 ((PERIPH) == TIM16) || \
194 ((PERIPH) == TIM17))
195 /* LIST1: TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16 and TIM17 */
196 #define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
197 ((PERIPH) == TIM2) || \
198 ((PERIPH) == TIM3) || \
199 ((PERIPH) == TIM4) || \
200 ((PERIPH) == TIM8) || \
201 ((PERIPH) == TIM15) || \
202 ((PERIPH) == TIM16) || \
203 ((PERIPH) == TIM17))
204
205 /* LIST2: TIM1, TIM2, TIM3, TIM4, TIM8 and TIM15 */
206 #define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
207 ((PERIPH) == TIM2) || \
208 ((PERIPH) == TIM3) || \
209 ((PERIPH) == TIM4) || \
210 ((PERIPH) == TIM8) || \
211 ((PERIPH) == TIM15))
212 /* LIST3: TIM1, TIM2, TIM3, TIM4 and TIM8 */
213 #define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
214 ((PERIPH) == TIM2) || \
215 ((PERIPH) == TIM3) || \
216 ((PERIPH) == TIM4) || \
217 ((PERIPH) == TIM8))
218 /* LIST4: TIM1 and TIM8 */
219 #define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) ||\
220 ((PERIPH) == TIM8))
221 /* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */
222 #define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
223 ((PERIPH) == TIM2) || \
224 ((PERIPH) == TIM3) || \
225 ((PERIPH) == TIM4) || \
226 ((PERIPH) == TIM6) || \
227 ((PERIPH) == TIM7) || \
228 ((PERIPH) == TIM8))
229 /* LIST6: TIM1, TIM8, TIM15, TIM16 and TIM17 */
230 #define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
231 ((PERIPH) == TIM8) || \
232 ((PERIPH) == TIM15) || \
233 ((PERIPH) == TIM16) || \
234 ((PERIPH) == TIM17))
235
236 /* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */
237 #define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
238 ((PERIPH) == TIM2) || \
239 ((PERIPH) == TIM3) || \
240 ((PERIPH) == TIM4) || \
241 ((PERIPH) == TIM6) || \
242 ((PERIPH) == TIM7) || \
243 ((PERIPH) == TIM8) || \
244 ((PERIPH) == TIM15))
245 /* LIST8: TIM16 (option register) */
246 #define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM16)|| \
247 ((PERIPH) == TIM1)||\
248 ((PERIPH) == TIM8))
249
250 /** @defgroup TIM_Output_Compare_and_PWM_modes
251 * @{
252 */
253
254 #define TIM_OCMode_Timing ((uint32_t)0x00000)
255 #define TIM_OCMode_Active ((uint32_t)0x00010)
256 #define TIM_OCMode_Inactive ((uint32_t)0x00020)
257 #define TIM_OCMode_Toggle ((uint32_t)0x00030)
258 #define TIM_OCMode_PWM1 ((uint32_t)0x00060)
259 #define TIM_OCMode_PWM2 ((uint32_t)0x00070)
260
261 #define TIM_OCMode_Retrigerrable_OPM1 ((uint32_t)0x10000)
262 #define TIM_OCMode_Retrigerrable_OPM2 ((uint32_t)0x10010)
263 #define TIM_OCMode_Combined_PWM1 ((uint32_t)0x10040)
264 #define TIM_OCMode_Combined_PWM2 ((uint32_t)0x10050)
265 #define TIM_OCMode_Asymmetric_PWM1 ((uint32_t)0x10060)
266 #define TIM_OCMode_Asymmetric_PWM2 ((uint32_t)0x10070)
267
268 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
269 ((MODE) == TIM_OCMode_Active) || \
270 ((MODE) == TIM_OCMode_Inactive) || \
271 ((MODE) == TIM_OCMode_Toggle)|| \
272 ((MODE) == TIM_OCMode_PWM1) || \
273 ((MODE) == TIM_OCMode_PWM2) || \
274 ((MODE) == TIM_OCMode_Retrigerrable_OPM1) || \
275 ((MODE) == TIM_OCMode_Retrigerrable_OPM2) || \
276 ((MODE) == TIM_OCMode_Combined_PWM1) || \
277 ((MODE) == TIM_OCMode_Combined_PWM2) || \
278 ((MODE) == TIM_OCMode_Asymmetric_PWM1) || \
279 ((MODE) == TIM_OCMode_Asymmetric_PWM2))
280
281 #define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
282 ((MODE) == TIM_OCMode_Active) || \
283 ((MODE) == TIM_OCMode_Inactive) || \
284 ((MODE) == TIM_OCMode_Toggle)|| \
285 ((MODE) == TIM_OCMode_PWM1) || \
286 ((MODE) == TIM_OCMode_PWM2) || \
287 ((MODE) == TIM_ForcedAction_Active) || \
288 ((MODE) == TIM_ForcedAction_InActive) || \
289 ((MODE) == TIM_OCMode_Retrigerrable_OPM1) || \
290 ((MODE) == TIM_OCMode_Retrigerrable_OPM2) || \
291 ((MODE) == TIM_OCMode_Combined_PWM1) || \
292 ((MODE) == TIM_OCMode_Combined_PWM2) || \
293 ((MODE) == TIM_OCMode_Asymmetric_PWM1) || \
294 ((MODE) == TIM_OCMode_Asymmetric_PWM2))
295 /**
296 * @}
297 */
298
299 /** @defgroup TIM_One_Pulse_Mode
300 * @{
301 */
302
303 #define TIM_OPMode_Single ((uint16_t)0x0008)
304 #define TIM_OPMode_Repetitive ((uint16_t)0x0000)
305 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
306 ((MODE) == TIM_OPMode_Repetitive))
307 /**
308 * @}
309 */
310
311 /** @defgroup TIM_Channel
312 * @{
313 */
314
315 #define TIM_Channel_1 ((uint16_t)0x0000)
316 #define TIM_Channel_2 ((uint16_t)0x0004)
317 #define TIM_Channel_3 ((uint16_t)0x0008)
318 #define TIM_Channel_4 ((uint16_t)0x000C)
319 #define TIM_Channel_5 ((uint16_t)0x0010)
320 #define TIM_Channel_6 ((uint16_t)0x0014)
321
322 #define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
323 ((CHANNEL) == TIM_Channel_2) || \
324 ((CHANNEL) == TIM_Channel_3) || \
325 ((CHANNEL) == TIM_Channel_4))
326
327 #define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
328 ((CHANNEL) == TIM_Channel_2))
329 #define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
330 ((CHANNEL) == TIM_Channel_2) || \
331 ((CHANNEL) == TIM_Channel_3))
332 /**
333 * @}
334 */
335
336 /** @defgroup TIM_Clock_Division_CKD
337 * @{
338 */
339
340 #define TIM_CKD_DIV1 ((uint16_t)0x0000)
341 #define TIM_CKD_DIV2 ((uint16_t)0x0100)
342 #define TIM_CKD_DIV4 ((uint16_t)0x0200)
343 #define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
344 ((DIV) == TIM_CKD_DIV2) || \
345 ((DIV) == TIM_CKD_DIV4))
346 /**
347 * @}
348 */
349
350 /** @defgroup TIM_Counter_Mode
351 * @{
352 */
353
354 #define TIM_CounterMode_Up ((uint16_t)0x0000)
355 #define TIM_CounterMode_Down ((uint16_t)0x0010)
356 #define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
357 #define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
358 #define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
359 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
360 ((MODE) == TIM_CounterMode_Down) || \
361 ((MODE) == TIM_CounterMode_CenterAligned1) || \
362 ((MODE) == TIM_CounterMode_CenterAligned2) || \
363 ((MODE) == TIM_CounterMode_CenterAligned3))
364 /**
365 * @}
366 */
367
368 /** @defgroup TIM_Output_Compare_Polarity
369 * @{
370 */
371
372 #define TIM_OCPolarity_High ((uint16_t)0x0000)
373 #define TIM_OCPolarity_Low ((uint16_t)0x0002)
374 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
375 ((POLARITY) == TIM_OCPolarity_Low))
376 /**
377 * @}
378 */
379
380 /** @defgroup TIM_Output_Compare_N_Polarity
381 * @{
382 */
383
384 #define TIM_OCNPolarity_High ((uint16_t)0x0000)
385 #define TIM_OCNPolarity_Low ((uint16_t)0x0008)
386 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
387 ((POLARITY) == TIM_OCNPolarity_Low))
388 /**
389 * @}
390 */
391
392 /** @defgroup TIM_Output_Compare_State
393 * @{
394 */
395
396 #define TIM_OutputState_Disable ((uint16_t)0x0000)
397 #define TIM_OutputState_Enable ((uint16_t)0x0001)
398 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
399 ((STATE) == TIM_OutputState_Enable))
400 /**
401 * @}
402 */
403
404 /** @defgroup TIM_Output_Compare_N_State
405 * @{
406 */
407
408 #define TIM_OutputNState_Disable ((uint16_t)0x0000)
409 #define TIM_OutputNState_Enable ((uint16_t)0x0004)
410 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
411 ((STATE) == TIM_OutputNState_Enable))
412 /**
413 * @}
414 */
415
416 /** @defgroup TIM_Capture_Compare_State
417 * @{
418 */
419
420 #define TIM_CCx_Enable ((uint16_t)0x0001)
421 #define TIM_CCx_Disable ((uint16_t)0x0000)
422 #define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
423 ((CCX) == TIM_CCx_Disable))
424 /**
425 * @}
426 */
427
428 /** @defgroup TIM_Capture_Compare_N_State
429 * @{
430 */
431
432 #define TIM_CCxN_Enable ((uint16_t)0x0004)
433 #define TIM_CCxN_Disable ((uint16_t)0x0000)
434 #define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
435 ((CCXN) == TIM_CCxN_Disable))
436 /**
437 * @}
438 */
439
440 /** @defgroup TIM_Break_Input_enable_disable
441 * @{
442 */
443
444 #define TIM_Break_Enable ((uint16_t)0x1000)
445 #define TIM_Break_Disable ((uint16_t)0x0000)
446 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
447 ((STATE) == TIM_Break_Disable))
448 /**
449 * @}
450 */
451
452 /** @defgroup TIM_Break1_Input_enable_disable
453 * @{
454 */
455
456 #define TIM_Break1_Enable ((uint32_t)0x00001000)
457 #define TIM_Break1_Disable ((uint32_t)0x00000000)
458 #define IS_TIM_BREAK1_STATE(STATE) (((STATE) == TIM_Break1_Enable) || \
459 ((STATE) == TIM_Break1_Disable))
460 /**
461 * @}
462 */
463
464 /** @defgroup TIM_Break2_Input_enable_disable
465 * @{
466 */
467
468 #define TIM_Break2_Enable ((uint32_t)0x01000000)
469 #define TIM_Break2_Disable ((uint32_t)0x00000000)
470 #define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_Break2_Enable) || \
471 ((STATE) == TIM_Break2_Disable))
472 /**
473 * @}
474 */
475
476 /** @defgroup TIM_Break_Polarity
477 * @{
478 */
479
480 #define TIM_BreakPolarity_Low ((uint16_t)0x0000)
481 #define TIM_BreakPolarity_High ((uint16_t)0x2000)
482 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
483 ((POLARITY) == TIM_BreakPolarity_High))
484 /**
485 * @}
486 */
487
488 /** @defgroup TIM_Break1_Polarity
489 * @{
490 */
491
492 #define TIM_Break1Polarity_Low ((uint32_t)0x00000000)
493 #define TIM_Break1Polarity_High ((uint32_t)0x00002000)
494 #define IS_TIM_BREAK1_POLARITY(POLARITY) (((POLARITY) == TIM_Break1Polarity_Low) || \
495 ((POLARITY) == TIM_Break1Polarity_High))
496 /**
497 * @}
498 */
499
500 /** @defgroup TIM_Break2_Polarity
501 * @{
502 */
503
504 #define TIM_Break2Polarity_Low ((uint32_t)0x00000000)
505 #define TIM_Break2Polarity_High ((uint32_t)0x02000000)
506 #define IS_TIM_BREAK2_POLARITY(POLARITY) (((POLARITY) == TIM_Break2Polarity_Low) || \
507 ((POLARITY) == TIM_Break2Polarity_High))
508 /**
509 * @}
510 */
511
512 /** @defgroup TIM_Break1_Filter
513 * @{
514 */
515
516 #define IS_TIM_BREAK1_FILTER(FILTER) ((FILTER) <= 0xF)
517 /**
518 * @}
519 */
520
521 /** @defgroup TIM_Break2_Filter
522 * @{
523 */
524
525 #define IS_TIM_BREAK2_FILTER(FILTER) ((FILTER) <= 0xF)
526 /**
527 * @}
528 */
529
530 /** @defgroup TIM_AOE_Bit_Set_Reset
531 * @{
532 */
533
534 #define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
535 #define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
536 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
537 ((STATE) == TIM_AutomaticOutput_Disable))
538 /**
539 * @}
540 */
541
542 /** @defgroup TIM_Lock_level
543 * @{
544 */
545
546 #define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
547 #define TIM_LOCKLevel_1 ((uint16_t)0x0100)
548 #define TIM_LOCKLevel_2 ((uint16_t)0x0200)
549 #define TIM_LOCKLevel_3 ((uint16_t)0x0300)
550 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
551 ((LEVEL) == TIM_LOCKLevel_1) || \
552 ((LEVEL) == TIM_LOCKLevel_2) || \
553 ((LEVEL) == TIM_LOCKLevel_3))
554 /**
555 * @}
556 */
557
558 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state
559 * @{
560 */
561
562 #define TIM_OSSIState_Enable ((uint16_t)0x0400)
563 #define TIM_OSSIState_Disable ((uint16_t)0x0000)
564 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
565 ((STATE) == TIM_OSSIState_Disable))
566 /**
567 * @}
568 */
569
570 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
571 * @{
572 */
573
574 #define TIM_OSSRState_Enable ((uint16_t)0x0800)
575 #define TIM_OSSRState_Disable ((uint16_t)0x0000)
576 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
577 ((STATE) == TIM_OSSRState_Disable))
578 /**
579 * @}
580 */
581
582 /** @defgroup TIM_Output_Compare_Idle_State
583 * @{
584 */
585
586 #define TIM_OCIdleState_Set ((uint16_t)0x0100)
587 #define TIM_OCIdleState_Reset ((uint16_t)0x0000)
588 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
589 ((STATE) == TIM_OCIdleState_Reset))
590 /**
591 * @}
592 */
593
594 /** @defgroup TIM_Output_Compare_N_Idle_State
595 * @{
596 */
597
598 #define TIM_OCNIdleState_Set ((uint16_t)0x0200)
599 #define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
600 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
601 ((STATE) == TIM_OCNIdleState_Reset))
602 /**
603 * @}
604 */
605
606 /** @defgroup TIM_Input_Capture_Polarity
607 * @{
608 */
609
610 #define TIM_ICPolarity_Rising ((uint16_t)0x0000)
611 #define TIM_ICPolarity_Falling ((uint16_t)0x0002)
612 #define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
613 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
614 ((POLARITY) == TIM_ICPolarity_Falling)|| \
615 ((POLARITY) == TIM_ICPolarity_BothEdge))
616 /**
617 * @}
618 */
619
620 /** @defgroup TIM_Input_Capture_Selection
621 * @{
622 */
623
624 #define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
625 connected to IC1, IC2, IC3 or IC4, respectively */
626 #define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
627 connected to IC2, IC1, IC4 or IC3, respectively. */
628 #define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
629 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
630 ((SELECTION) == TIM_ICSelection_IndirectTI) || \
631 ((SELECTION) == TIM_ICSelection_TRC))
632 /**
633 * @}
634 */
635
636 /** @defgroup TIM_Input_Capture_Prescaler
637 * @{
638 */
639
640 #define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
641 #define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
642 #define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
643 #define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
644 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
645 ((PRESCALER) == TIM_ICPSC_DIV2) || \
646 ((PRESCALER) == TIM_ICPSC_DIV4) || \
647 ((PRESCALER) == TIM_ICPSC_DIV8))
648 /**
649 * @}
650 */
651
652 /** @defgroup TIM_interrupt_sources
653 * @{
654 */
655
656 #define TIM_IT_Update ((uint16_t)0x0001)
657 #define TIM_IT_CC1 ((uint16_t)0x0002)
658 #define TIM_IT_CC2 ((uint16_t)0x0004)
659 #define TIM_IT_CC3 ((uint16_t)0x0008)
660 #define TIM_IT_CC4 ((uint16_t)0x0010)
661 #define TIM_IT_COM ((uint16_t)0x0020)
662 #define TIM_IT_Trigger ((uint16_t)0x0040)
663 #define TIM_IT_Break ((uint16_t)0x0080)
664 #define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
665
666 #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
667 ((IT) == TIM_IT_CC1) || \
668 ((IT) == TIM_IT_CC2) || \
669 ((IT) == TIM_IT_CC3) || \
670 ((IT) == TIM_IT_CC4) || \
671 ((IT) == TIM_IT_COM) || \
672 ((IT) == TIM_IT_Trigger) || \
673 ((IT) == TIM_IT_Break))
674 /**
675 * @}
676 */
677
678 /** @defgroup TIM_DMA_Base_address
679 * @{
680 */
681
682 #define TIM_DMABase_CR1 ((uint16_t)0x0000)
683 #define TIM_DMABase_CR2 ((uint16_t)0x0001)
684 #define TIM_DMABase_SMCR ((uint16_t)0x0002)
685 #define TIM_DMABase_DIER ((uint16_t)0x0003)
686 #define TIM_DMABase_SR ((uint16_t)0x0004)
687 #define TIM_DMABase_EGR ((uint16_t)0x0005)
688 #define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
689 #define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
690 #define TIM_DMABase_CCER ((uint16_t)0x0008)
691 #define TIM_DMABase_CNT ((uint16_t)0x0009)
692 #define TIM_DMABase_PSC ((uint16_t)0x000A)
693 #define TIM_DMABase_ARR ((uint16_t)0x000B)
694 #define TIM_DMABase_RCR ((uint16_t)0x000C)
695 #define TIM_DMABase_CCR1 ((uint16_t)0x000D)
696 #define TIM_DMABase_CCR2 ((uint16_t)0x000E)
697 #define TIM_DMABase_CCR3 ((uint16_t)0x000F)
698 #define TIM_DMABase_CCR4 ((uint16_t)0x0010)
699 #define TIM_DMABase_BDTR ((uint16_t)0x0011)
700 #define TIM_DMABase_DCR ((uint16_t)0x0012)
701 #define TIM_DMABase_OR ((uint16_t)0x0013)
702 #define TIM_DMABase_CCMR3 ((uint16_t)0x0014)
703 #define TIM_DMABase_CCR5 ((uint16_t)0x0015)
704 #define TIM_DMABase_CCR6 ((uint16_t)0x0016)
705 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
706 ((BASE) == TIM_DMABase_CR2) || \
707 ((BASE) == TIM_DMABase_SMCR) || \
708 ((BASE) == TIM_DMABase_DIER) || \
709 ((BASE) == TIM_DMABase_SR) || \
710 ((BASE) == TIM_DMABase_EGR) || \
711 ((BASE) == TIM_DMABase_CCMR1) || \
712 ((BASE) == TIM_DMABase_CCMR2) || \
713 ((BASE) == TIM_DMABase_CCER) || \
714 ((BASE) == TIM_DMABase_CNT) || \
715 ((BASE) == TIM_DMABase_PSC) || \
716 ((BASE) == TIM_DMABase_ARR) || \
717 ((BASE) == TIM_DMABase_RCR) || \
718 ((BASE) == TIM_DMABase_CCR1) || \
719 ((BASE) == TIM_DMABase_CCR2) || \
720 ((BASE) == TIM_DMABase_CCR3) || \
721 ((BASE) == TIM_DMABase_CCR4) || \
722 ((BASE) == TIM_DMABase_BDTR) || \
723 ((BASE) == TIM_DMABase_DCR) || \
724 ((BASE) == TIM_DMABase_OR) || \
725 ((BASE) == TIM_DMABase_CCMR3) || \
726 ((BASE) == TIM_DMABase_CCR5) || \
727 ((BASE) == TIM_DMABase_CCR6))
728 /**
729 * @}
730 */
731
732 /** @defgroup TIM_DMA_Burst_Length
733 * @{
734 */
735
736 #define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
737 #define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
738 #define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
739 #define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
740 #define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
741 #define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
742 #define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
743 #define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
744 #define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
745 #define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
746 #define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
747 #define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
748 #define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
749 #define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
750 #define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
751 #define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
752 #define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
753 #define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
754 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
755 ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
756 ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
757 ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
758 ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
759 ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
760 ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
761 ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
762 ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
763 ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
764 ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
765 ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
766 ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
767 ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
768 ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
769 ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
770 ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
771 ((LENGTH) == TIM_DMABurstLength_18Transfers))
772 /**
773 * @}
774 */
775
776 /** @defgroup TIM_DMA_sources
777 * @{
778 */
779
780 #define TIM_DMA_Update ((uint16_t)0x0100)
781 #define TIM_DMA_CC1 ((uint16_t)0x0200)
782 #define TIM_DMA_CC2 ((uint16_t)0x0400)
783 #define TIM_DMA_CC3 ((uint16_t)0x0800)
784 #define TIM_DMA_CC4 ((uint16_t)0x1000)
785 #define TIM_DMA_COM ((uint16_t)0x2000)
786 #define TIM_DMA_Trigger ((uint16_t)0x4000)
787 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
788
789 /**
790 * @}
791 */
792
793 /** @defgroup TIM_External_Trigger_Prescaler
794 * @{
795 */
796
797 #define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
798 #define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
799 #define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
800 #define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
801 #define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
802 ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
803 ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
804 ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
805 /**
806 * @}
807 */
808
809 /** @defgroup TIM_Internal_Trigger_Selection
810 * @{
811 */
812
813 #define TIM_TS_ITR0 ((uint16_t)0x0000)
814 #define TIM_TS_ITR1 ((uint16_t)0x0010)
815 #define TIM_TS_ITR2 ((uint16_t)0x0020)
816 #define TIM_TS_ITR3 ((uint16_t)0x0030)
817 #define TIM_TS_TI1F_ED ((uint16_t)0x0040)
818 #define TIM_TS_TI1FP1 ((uint16_t)0x0050)
819 #define TIM_TS_TI2FP2 ((uint16_t)0x0060)
820 #define TIM_TS_ETRF ((uint16_t)0x0070)
821 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
822 ((SELECTION) == TIM_TS_ITR1) || \
823 ((SELECTION) == TIM_TS_ITR2) || \
824 ((SELECTION) == TIM_TS_ITR3) || \
825 ((SELECTION) == TIM_TS_TI1F_ED) || \
826 ((SELECTION) == TIM_TS_TI1FP1) || \
827 ((SELECTION) == TIM_TS_TI2FP2) || \
828 ((SELECTION) == TIM_TS_ETRF))
829 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
830 ((SELECTION) == TIM_TS_ITR1) || \
831 ((SELECTION) == TIM_TS_ITR2) || \
832 ((SELECTION) == TIM_TS_ITR3))
833 /**
834 * @}
835 */
836
837 /** @defgroup TIM_TIx_External_Clock_Source
838 * @{
839 */
840
841 #define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
842 #define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
843 #define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
844
845 /**
846 * @}
847 */
848
849 /** @defgroup TIM_External_Trigger_Polarity
850 * @{
851 */
852 #define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
853 #define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
854 #define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
855 ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
856 /**
857 * @}
858 */
859
860 /** @defgroup TIM_Prescaler_Reload_Mode
861 * @{
862 */
863
864 #define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
865 #define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
866 #define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
867 ((RELOAD) == TIM_PSCReloadMode_Immediate))
868 /**
869 * @}
870 */
871
872 /** @defgroup TIM_Forced_Action
873 * @{
874 */
875
876 #define TIM_ForcedAction_Active ((uint16_t)0x0050)
877 #define TIM_ForcedAction_InActive ((uint16_t)0x0040)
878 #define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
879 ((ACTION) == TIM_ForcedAction_InActive))
880 /**
881 * @}
882 */
883
884 /** @defgroup TIM_Encoder_Mode
885 * @{
886 */
887
888 #define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
889 #define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
890 #define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
891 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
892 ((MODE) == TIM_EncoderMode_TI2) || \
893 ((MODE) == TIM_EncoderMode_TI12))
894 /**
895 * @}
896 */
897
898
899 /** @defgroup TIM_Event_Source
900 * @{
901 */
902
903 #define TIM_EventSource_Update ((uint16_t)0x0001)
904 #define TIM_EventSource_CC1 ((uint16_t)0x0002)
905 #define TIM_EventSource_CC2 ((uint16_t)0x0004)
906 #define TIM_EventSource_CC3 ((uint16_t)0x0008)
907 #define TIM_EventSource_CC4 ((uint16_t)0x0010)
908 #define TIM_EventSource_COM ((uint16_t)0x0020)
909 #define TIM_EventSource_Trigger ((uint16_t)0x0040)
910 #define TIM_EventSource_Break ((uint16_t)0x0080)
911 #define TIM_EventSource_Break2 ((uint16_t)0x0100)
912 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFE00) == 0x0000) && ((SOURCE) != 0x0000))
913
914 /**
915 * @}
916 */
917
918 /** @defgroup TIM_Update_Source
919 * @{
920 */
921
922 #define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
923 or the setting of UG bit, or an update generation
924 through the slave mode controller. */
925 #define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
926 #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
927 ((SOURCE) == TIM_UpdateSource_Regular))
928 /**
929 * @}
930 */
931
932 /** @defgroup TIM_Output_Compare_Preload_State
933 * @{
934 */
935
936 #define TIM_OCPreload_Enable ((uint16_t)0x0008)
937 #define TIM_OCPreload_Disable ((uint16_t)0x0000)
938 #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
939 ((STATE) == TIM_OCPreload_Disable))
940 /**
941 * @}
942 */
943
944 /** @defgroup TIM_Output_Compare_Fast_State
945 * @{
946 */
947
948 #define TIM_OCFast_Enable ((uint16_t)0x0004)
949 #define TIM_OCFast_Disable ((uint16_t)0x0000)
950 #define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
951 ((STATE) == TIM_OCFast_Disable))
952
953 /**
954 * @}
955 */
956
957 /** @defgroup TIM_Output_Compare_Clear_State
958 * @{
959 */
960
961 #define TIM_OCClear_Enable ((uint16_t)0x0080)
962 #define TIM_OCClear_Disable ((uint16_t)0x0000)
963 #define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
964 ((STATE) == TIM_OCClear_Disable))
965 /**
966 * @}
967 */
968
969 /** @defgroup TIM_Trigger_Output_Source
970 * @{
971 */
972
973 #define TIM_TRGOSource_Reset ((uint16_t)0x0000)
974 #define TIM_TRGOSource_Enable ((uint16_t)0x0010)
975 #define TIM_TRGOSource_Update ((uint16_t)0x0020)
976 #define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
977 #define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
978 #define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
979 #define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
980 #define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
981 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
982 ((SOURCE) == TIM_TRGOSource_Enable) || \
983 ((SOURCE) == TIM_TRGOSource_Update) || \
984 ((SOURCE) == TIM_TRGOSource_OC1) || \
985 ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
986 ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
987 ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
988 ((SOURCE) == TIM_TRGOSource_OC4Ref))
989
990
991 #define TIM_TRGO2Source_Reset ((uint32_t)0x00000000)
992 #define TIM_TRGO2Source_Enable ((uint32_t)0x00100000)
993 #define TIM_TRGO2Source_Update ((uint32_t)0x00200000)
994 #define TIM_TRGO2Source_OC1 ((uint32_t)0x00300000)
995 #define TIM_TRGO2Source_OC1Ref ((uint32_t)0x00400000)
996 #define TIM_TRGO2Source_OC2Ref ((uint32_t)0x00500000)
997 #define TIM_TRGO2Source_OC3Ref ((uint32_t)0x00600000)
998 #define TIM_TRGO2Source_OC4Ref ((uint32_t)0x00700000)
999 #define TIM_TRGO2Source_OC5Ref ((uint32_t)0x00800000)
1000 #define TIM_TRGO2Source_OC6Ref ((uint32_t)0x00900000)
1001 #define TIM_TRGO2Source_OC4Ref_RisingFalling ((uint32_t)0x00A00000)
1002 #define TIM_TRGO2Source_OC6Ref_RisingFalling ((uint32_t)0x00B00000)
1003 #define TIM_TRGO2Source_OC4RefRising_OC6RefRising ((uint32_t)0x00C00000)
1004 #define TIM_TRGO2Source_OC4RefRising_OC6RefFalling ((uint32_t)0x00D00000)
1005 #define TIM_TRGO2Source_OC5RefRising_OC6RefRising ((uint32_t)0x00E00000)
1006 #define TIM_TRGO2Source_OC5RefRising_OC6RefFalling ((uint32_t)0x00F00000)
1007 #define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2Source_Reset) || \
1008 ((SOURCE) == TIM_TRGO2Source_Enable) || \
1009 ((SOURCE) == TIM_TRGO2Source_Update) || \
1010 ((SOURCE) == TIM_TRGO2Source_OC1) || \
1011 ((SOURCE) == TIM_TRGO2Source_OC1Ref) || \
1012 ((SOURCE) == TIM_TRGO2Source_OC2Ref) || \
1013 ((SOURCE) == TIM_TRGO2Source_OC3Ref) || \
1014 ((SOURCE) == TIM_TRGO2Source_OC4Ref) || \
1015 ((SOURCE) == TIM_TRGO2Source_OC5Ref) || \
1016 ((SOURCE) == TIM_TRGO2Source_OC6Ref) || \
1017 ((SOURCE) == TIM_TRGO2Source_OC4Ref_RisingFalling) || \
1018 ((SOURCE) == TIM_TRGO2Source_OC6Ref_RisingFalling) || \
1019 ((SOURCE) == TIM_TRGO2Source_OC4RefRising_OC6RefRising) || \
1020 ((SOURCE) == TIM_TRGO2Source_OC4RefRising_OC6RefFalling) || \
1021 ((SOURCE) == TIM_TRGO2Source_OC5RefRising_OC6RefRising) || \
1022 ((SOURCE) == TIM_TRGO2Source_OC5RefRising_OC6RefFalling))
1023 /**
1024 * @}
1025 */
1026
1027 /** @defgroup TIM_Slave_Mode
1028 * @{
1029 */
1030
1031 #define TIM_SlaveMode_Reset ((uint32_t)0x00004)
1032 #define TIM_SlaveMode_Gated ((uint32_t)0x00005)
1033 #define TIM_SlaveMode_Trigger ((uint32_t)0x00006)
1034 #define TIM_SlaveMode_External1 ((uint32_t)0x00007)
1035 #define TIM_SlaveMode_Combined_ResetTrigger ((uint32_t)0x10000)
1036 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
1037 ((MODE) == TIM_SlaveMode_Gated) || \
1038 ((MODE) == TIM_SlaveMode_Trigger) || \
1039 ((MODE) == TIM_SlaveMode_External1) || \
1040 ((MODE) == TIM_SlaveMode_Combined_ResetTrigger))
1041 /**
1042 * @}
1043 */
1044
1045 /** @defgroup TIM_Master_Slave_Mode
1046 * @{
1047 */
1048
1049 #define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
1050 #define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
1051 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
1052 ((STATE) == TIM_MasterSlaveMode_Disable))
1053 /**
1054 * @}
1055 */
1056 /** @defgroup TIM_Remap
1057 * @{
1058 */
1059 #define TIM16_GPIO ((uint16_t)0x0000)
1060 #define TIM16_RTC_CLK ((uint16_t)0x0001)
1061 #define TIM16_HSEDiv32 ((uint16_t)0x0002)
1062 #define TIM16_MCO ((uint16_t)0x0003)
1063
1064 #define TIM1_ADC1_AWDG1 ((uint16_t)0x0001)
1065 #define TIM1_ADC1_AWDG2 ((uint16_t)0x0002)
1066 #define TIM1_ADC1_AWDG3 ((uint16_t)0x0003)
1067 #define TIM1_ADC4_AWDG1 ((uint16_t)0x0004)
1068 #define TIM1_ADC4_AWDG2 ((uint16_t)0x0008)
1069 #define TIM1_ADC4_AWDG3 ((uint16_t)0x000C)
1070
1071 #define TIM8_ADC2_AWDG1 ((uint16_t)0x0001)
1072 #define TIM8_ADC2_AWDG2 ((uint16_t)0x0002)
1073 #define TIM8_ADC2_AWDG3 ((uint16_t)0x0003)
1074 #define TIM8_ADC3_AWDG1 ((uint16_t)0x0004)
1075 #define TIM8_ADC3_AWDG2 ((uint16_t)0x0008)
1076 #define TIM8_ADC3_AWDG3 ((uint16_t)0x000C)
1077
1078 #define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM16_GPIO)|| \
1079 ((TIM_REMAP) == TIM16_RTC_CLK) || \
1080 ((TIM_REMAP) == TIM16_HSEDiv32) || \
1081 ((TIM_REMAP) == TIM16_MCO) ||\
1082 ((TIM_REMAP) == TIM1_ADC1_AWDG1) ||\
1083 ((TIM_REMAP) == TIM1_ADC1_AWDG2) ||\
1084 ((TIM_REMAP) == TIM1_ADC1_AWDG3) ||\
1085 ((TIM_REMAP) == TIM1_ADC4_AWDG1) ||\
1086 ((TIM_REMAP) == TIM1_ADC4_AWDG2) ||\
1087 ((TIM_REMAP) == TIM1_ADC4_AWDG3) ||\
1088 ((TIM_REMAP) == TIM8_ADC2_AWDG1) ||\
1089 ((TIM_REMAP) == TIM8_ADC2_AWDG2) ||\
1090 ((TIM_REMAP) == TIM8_ADC2_AWDG3) ||\
1091 ((TIM_REMAP) == TIM8_ADC3_AWDG1) ||\
1092 ((TIM_REMAP) == TIM8_ADC3_AWDG2) ||\
1093 ((TIM_REMAP) == TIM8_ADC3_AWDG3))
1094
1095 /**
1096 * @}
1097 */
1098 /** @defgroup TIM_Flags
1099 * @{
1100 */
1101
1102 #define TIM_FLAG_Update ((uint32_t)0x00001)
1103 #define TIM_FLAG_CC1 ((uint32_t)0x00002)
1104 #define TIM_FLAG_CC2 ((uint32_t)0x00004)
1105 #define TIM_FLAG_CC3 ((uint32_t)0x00008)
1106 #define TIM_FLAG_CC4 ((uint32_t)0x00010)
1107 #define TIM_FLAG_COM ((uint32_t)0x00020)
1108 #define TIM_FLAG_Trigger ((uint32_t)0x00040)
1109 #define TIM_FLAG_Break ((uint32_t)0x00080)
1110 #define TIM_FLAG_Break2 ((uint32_t)0x00100)
1111 #define TIM_FLAG_CC1OF ((uint32_t)0x00200)
1112 #define TIM_FLAG_CC2OF ((uint32_t)0x00400)
1113 #define TIM_FLAG_CC3OF ((uint32_t)0x00800)
1114 #define TIM_FLAG_CC4OF ((uint32_t)0x01000)
1115 #define TIM_FLAG_CC5 ((uint32_t)0x10000)
1116 #define TIM_FLAG_CC6 ((uint32_t)0x20000)
1117 #define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
1118 ((FLAG) == TIM_FLAG_CC1) || \
1119 ((FLAG) == TIM_FLAG_CC2) || \
1120 ((FLAG) == TIM_FLAG_CC3) || \
1121 ((FLAG) == TIM_FLAG_CC4) || \
1122 ((FLAG) == TIM_FLAG_COM) || \
1123 ((FLAG) == TIM_FLAG_Trigger) || \
1124 ((FLAG) == TIM_FLAG_Break) || \
1125 ((FLAG) == TIM_FLAG_Break2) || \
1126 ((FLAG) == TIM_FLAG_CC1OF) || \
1127 ((FLAG) == TIM_FLAG_CC2OF) || \
1128 ((FLAG) == TIM_FLAG_CC3OF) || \
1129 ((FLAG) == TIM_FLAG_CC4OF) ||\
1130 ((FLAG) == TIM_FLAG_CC5) ||\
1131 ((FLAG) == TIM_FLAG_CC6))
1132
1133 #define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint32_t)0xE000) == 0x0000) && ((TIM_FLAG) != 0x0000))
1134 /**
1135 * @}
1136 */
1137
1138 /** @defgroup TIM_OCReferenceClear
1139 * @{
1140 */
1141 #define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008)
1142 #define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000)
1143 #define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \
1144 ((SOURCE) == TIM_OCReferenceClear_OCREFCLR))
1145
1146 /** @defgroup TIM_Input_Capture_Filer_Value
1147 * @{
1148 */
1149
1150 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
1151 /**
1152 * @}
1153 */
1154
1155 /** @defgroup TIM_External_Trigger_Filter
1156 * @{
1157 */
1158
1159 #define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
1160 /**
1161 * @}
1162 */
1163
1164 /** @defgroup TIM_Legacy
1165 * @{
1166 */
1167
1168 #define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
1169 #define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
1170 #define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
1171 #define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
1172 #define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
1173 #define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
1174 #define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
1175 #define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
1176 #define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
1177 #define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
1178 #define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
1179 #define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
1180 #define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
1181 #define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
1182 #define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
1183 #define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
1184 #define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
1185 #define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
1186 /**
1187 * @}
1188 */
1189
1190 /**
1191 * @}
1192 */
1193
1194 /* Exported macro ------------------------------------------------------------*/
1195 /* Exported functions --------------------------------------------------------*/
1196
1197 /* TimeBase management ********************************************************/
1198 void TIM_DeInit(TIM_TypeDef* TIMx);
1199 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
1200 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
1201 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
1202 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
1203 void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
1204 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
1205 uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
1206 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
1207 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
1208 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
1209 void TIM_UIFRemap(TIM_TypeDef* TIMx, FunctionalState NewState);
1210 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
1211 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
1212 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
1213 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
1214
1215 /* Output Compare management **************************************************/
1216 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
1217 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
1218 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
1219 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
1220 void TIM_OC5Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
1221 void TIM_OC6Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
1222 void TIM_SelectGC5C1(TIM_TypeDef* TIMx, FunctionalState NewState);
1223 void TIM_SelectGC5C2(TIM_TypeDef* TIMx, FunctionalState NewState);
1224 void TIM_SelectGC5C3(TIM_TypeDef* TIMx, FunctionalState NewState);
1225 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
1226 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint32_t TIM_OCMode);
1227 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
1228 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
1229 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
1230 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
1231 void TIM_SetCompare5(TIM_TypeDef* TIMx, uint32_t Compare5);
1232 void TIM_SetCompare6(TIM_TypeDef* TIMx, uint32_t Compare6);
1233 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
1234 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
1235 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
1236 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
1237 void TIM_ForcedOC5Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
1238 void TIM_ForcedOC6Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
1239 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
1240 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
1241 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
1242 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
1243 void TIM_OC5PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
1244 void TIM_OC6PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
1245 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
1246 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
1247 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
1248 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
1249 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
1250 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
1251 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
1252 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
1253 void TIM_ClearOC5Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
1254 void TIM_ClearOC6Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
1255 void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear);
1256 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
1257 void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
1258 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
1259 void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
1260 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
1261 void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
1262 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
1263 void TIM_OC5PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
1264 void TIM_OC6PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
1265 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
1266 void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
1267
1268 /* Input Capture management ***************************************************/
1269 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
1270 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
1271 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
1272 uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
1273 uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
1274 uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
1275 uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
1276 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
1277 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
1278 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
1279 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
1280
1281 /* Advanced-control timers (TIM1 and TIM8) specific features ******************/
1282 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
1283 void TIM_Break1Config(TIM_TypeDef* TIMx, uint32_t TIM_Break1Polarity, uint8_t TIM_Break1Filter);
1284 void TIM_Break2Config(TIM_TypeDef* TIMx, uint32_t TIM_Break2Polarity, uint8_t TIM_Break2Filter);
1285 void TIM_Break1Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
1286 void TIM_Break2Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
1287 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
1288 void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
1289 void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
1290 void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
1291
1292 /* Interrupts, DMA and flags management ***************************************/
1293 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
1294 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
1295 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint32_t TIM_FLAG);
1296 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
1297 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
1298 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
1299 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
1300 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
1301 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
1302
1303 /* Clocks management **********************************************************/
1304 void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
1305 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
1306 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
1307 uint16_t TIM_ICPolarity, uint16_t ICFilter);
1308 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
1309 uint16_t ExtTRGFilter);
1310 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
1311 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
1312
1313 /* Synchronization management *************************************************/
1314 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
1315 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
1316 void TIM_SelectOutputTrigger2(TIM_TypeDef* TIMx, uint32_t TIM_TRGO2Source);
1317 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint32_t TIM_SlaveMode);
1318 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
1319 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
1320 uint16_t ExtTRGFilter);
1321
1322 /* Specific interface management **********************************************/
1323 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
1324 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
1325 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
1326
1327 /* Specific remapping management **********************************************/
1328 void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);
1329
1330 #ifdef __cplusplus
1331 }
1332 #endif
1333
1334 #endif /*__STM32F30x_TIM_H */
1335
1336 /**
1337 * @}
1338 */
1339
1340 /**
1341 * @}
1342 */
1343
1344 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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